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@cryptix cryptix/runner.go
Created Aug 13, 2014

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runnableSim
package main
import (
"bufio"
"fmt"
"log"
"os"
"runtime"
)
func main() {
sim := NewSimpleAluGenerator()
fmt.Println("#Ready")
scanner := bufio.NewScanner(os.Stdin)
var (
idx, offset int
value int64
)
for scanner.Scan() {
line := scanner.Text()
switch line[0] {
case '#':
continue
case 'a': // assert
switch line[1] {
case 'n':
fmt.Sscanf(line[2:], "%d %x", &idx, &value)
assert(value == sim.GetOutput(idx))
fmt.Println(">an")
case 'a':
fmt.Sscanf(line[2:], "%d %d %x", &idx, &offset, &value)
assert(value == sim.GetOutput(idx, offset))
fmt.Println(">aa")
}
case 'd':
switch line[1] {
case 'j':
fmt.Println(">dj", sim.GetJsonDesc())
case 'c':
fmt.Printf(">dc %d\n", sim.GetDeltaCycle())
case 'e':
fmt.Sscanf(line[2:], "%d", &idx)
sim.SetDisableEdge(idx > 0)
fmt.Printf("#set disabled edges to %v\n", idx > 0)
fmt.Println(">de")
case 'r':
fmt.Sscanf(line[2:], "%d", &idx)
sim.SetDisableRegOutputLogic(idx > 0)
fmt.Printf("#setdisabled register output logic to %v\n", idx > 0)
fmt.Println(">dr")
}
case 'g': // get
switch line[1] {
case 'n':
fmt.Sscanf(line[2:], "%d", &idx)
fmt.Printf(">gn %d %x\n", idx, sim.GetOutput(idx))
case 'a':
fmt.Sscanf(line[2:], "%d %d", &idx, &offset)
fmt.Printf(">ga %d %d %x\n", idx, offset, sim.GetOutput(idx, offset))
}
case 'i': // init
switch line[1] {
case 'c':
sim.InitConstants()
fmt.Println(">ic")
}
case 'r': // run
switch line[1] {
case 'r':
sim.Run()
fmt.Println(">rr")
}
case 's': // set
switch line[1] {
case 'n':
fmt.Sscanf(line[2:], "%d %x", &idx, &value)
fmt.Printf("#Setting %d to %x\n", idx, value)
sim.SetInput(idx, value)
fmt.Println(">sn")
case 'a':
fmt.Sscanf(line[2:], "%d %d %x", &idx, &offset, &value)
fmt.Printf("#Setting %d[%d] to %x\n", idx, offset, value)
sim.SetInput(idx, value, offset)
fmt.Println(">sa")
}
case 'x':
switch line[1] {
case 'n':
fmt.Println(">xn")
os.Exit(0)
case 'e':
fmt.Println(">xe")
os.Exit(1)
}
}
}
if err := scanner.Err(); err != nil {
fmt.Fprintf(os.Stderr, "Error during Scan(): %s\n", err)
os.Exit(-1)
}
os.Exit(2)
}
func assert(expr bool) {
if !expr {
_, file, line, _ := runtime.Caller(1)
log.Fatalf("assert failed on <%s:%d>\n", file, line)
}
}
package main
type regUpdate struct {
internal, offset int
}
type SimpleAluGenerator struct {
varIdx map[string]int
regUpdates []regUpdate
regUpdatePos int
disableEdge bool
disableRegOutputLogic bool
epsCycle int64
deltaCycle int64
timeStamp int64
_Pred_alu_if0_fresh bool
_Pred_alu_switch0_case0_fresh bool
_Pred_alu_switch0_case1_fresh bool
_Pred_alu_switch0_case2_fresh bool
_Pred_alu_rst_fresh bool
_Pred_alu_if0 bool
_Pred_alu_switch0_case0 bool
_Pred_alu_switch0_case1 bool
_Pred_alu_switch0_case2 bool
_Pred_alu_rst bool
_Pred_alu_if0_update int64
_Pred_alu_switch0_case0_update int64
_Pred_alu_switch0_case1_update int64
_Pred_alu_switch0_case2_update int64
_Pred_alu_rst_update int64
alu_clk_pos_active bool
alu_clk_pos_handled bool
alu_tmp_res_1_OutRead__reg int64
alu_tmp_res_1_OutRead int64
alu_switch0 int64
alu_clk_prev int64
alu_clk_update int64
alu_clk int64
alu_instr int64
alu_isZero int64
alu_op1 int64
alu_op2 int64
alu_res int64
alu_rst int64
}
func NewSimpleAluGenerator() *SimpleAluGenerator {
return NewSimpleAluGeneratorWithArgs(false, false)
}
func NewSimpleAluGeneratorWithArgs(disableEdge, disableRegOutputLogic bool) *SimpleAluGenerator {
var s = SimpleAluGenerator{
disableEdge: disableEdge,
disableRegOutputLogic: disableRegOutputLogic,
}
s.varIdx = make(map[string]int, 14)
s.varIdx["$Pred_alu.@if0"] = 1
s.varIdx["$Pred_alu.@switch0.@case0"] = 2
s.varIdx["$Pred_alu.@switch0.@case1"] = 3
s.varIdx["$Pred_alu.@switch0.@case2"] = 4
s.varIdx["$Pred_alu.rst"] = 5
s.varIdx["alu.$tmp_res_1_OutRead"] = 6
s.varIdx["alu.@switch0"] = 7
s.varIdx["alu.clk"] = 8
s.varIdx["alu.instr"] = 9
s.varIdx["alu.isZero"] = 10
s.varIdx["alu.op1"] = 11
s.varIdx["alu.op2"] = 12
s.varIdx["alu.res"] = 13
s.varIdx["alu.rst"] = 14
return &s
}
func (s *SimpleAluGenerator) skipEdge(local int64) bool {
var dc = local >> 16 // zero-extended shift
if dc < s.deltaCycle {
return false
}
if (dc == s.deltaCycle) && ((local & 0xFFFF) == s.epsCycle) {
return false
}
return true
}
func (s *SimpleAluGenerator) updateRegs() {
for _, r := range s.regUpdates {
switch r.internal {
case 6:
s.alu_tmp_res_1_OutRead = s.alu_tmp_res_1_OutRead__reg
}
}
}
func (s *SimpleAluGenerator) s000_frame_0004() {
var t0, t1 int64
t0 = 0 //const0
t1 = (t0) & 1 //cast_uint[targetSize=1,currentSize=32]
s.alu_isZero = t1 //Assign value
}
func (s *SimpleAluGenerator) s001_frame_0002() {
var t0 int64
t0 = s.alu_tmp_res_1_OutRead //loadInternal[alu.$tmp_res_1_OutRead]
s.alu_res = t0 //Assign value
}
func (s *SimpleAluGenerator) s001_frame_001E() {
var t0 int64 = s.alu_tmp_res_1_OutRead //loadInternal[alu.$tmp_res_1_OutRead]
var t1 int64 = 0 //const0
var t2 int64 = (t1) & 0x0000001F //cast_uint[targetSize=5,currentSize=32]
var t3 bool = t0 == t2 //eq
s._Pred_alu_if0 = t3 //Assign value
s._Pred_alu_if0_update = s.timeStamp //update timestamp
}
func (s *SimpleAluGenerator) s001_frame_000D() {
var t0, t1 int64
t0 = s.alu_instr //loadInternal[alu.instr]
t1 = (t0 >> 0) & 0x0000000F //bitAccessSingleRange[from=3,to=0]
s.alu_switch0 = t1 //Assign value
}
func (s *SimpleAluGenerator) s001_frame_0025() {
var t0, t1 int64
var t2 bool
t0 = s.alu_rst //loadInternal[alu.rst]
t1 = 0 //const0
t2 = t0 != t1 //not_eq
s._Pred_alu_rst = t2 //Assign value
s._Pred_alu_rst_update = s.timeStamp //update timestamp
}
func (s *SimpleAluGenerator) s003_frame_0021() {
var t1, t2 int64
//posPredicate[$Pred_alu.@if0]
t1 = 0 //const0
t2 = (t1) & 1 //cast_uint[targetSize=1,currentSize=32]
s.alu_isZero = t2 //Assign value
}
func (s *SimpleAluGenerator) s003_frame_000E() {
var t0, t1 int64
var t2 bool
t0 = s.alu_switch0 //loadInternal[alu.@switch0]
t1 = 0 //loadConstant[constantIdx=0]
t2 = t0 == t1 //eq
s._Pred_alu_switch0_case0 = t2 //Assign value
s._Pred_alu_switch0_case0_update = s.timeStamp //update timestamp
}
func (s *SimpleAluGenerator) s003_frame_0013() {
var t0, t1 int64
var t2 bool
t0 = s.alu_switch0 //loadInternal[alu.@switch0]
t1 = 1 //loadConstant[constantIdx=0]
t2 = t0 == t1 //eq
s._Pred_alu_switch0_case1 = t2 //Assign value
s._Pred_alu_switch0_case1_update = s.timeStamp //update timestamp
}
func (s *SimpleAluGenerator) s004_frame_0023() {
var t1, t2 int64
//negPredicate[$Pred_alu.@if0]
t1 = 1 //const1
t2 = (t1) & 1 //cast_uint[targetSize=1,currentSize=32]
s.alu_isZero = t2 //Assign value
}
func (s *SimpleAluGenerator) s005_frame_000F() {
var t3, t4, t5, t5_cpy int64
//posPredicate[$Pred_alu.@switch0.@case0]
s.alu_clk_update = s.timeStamp //isRisingEdge[internalIdx=11]
//negPredicate[$Pred_alu.rst]
t3 = s.alu_op1 //loadInternal[alu.op1]
t4 = s.alu_op2 //loadInternal[alu.op2]
t5 = (t3 + t4) & 0x0000001F //plus[targetSizeWithType=10]
t5_cpy = s.alu_tmp_res_1_OutRead //Backup of current value
s.alu_tmp_res_1_OutRead__reg = t5 //Assign value
if t5_cpy != s.alu_tmp_res_1_OutRead__reg {
s.regUpdates[s.regUpdatePos] = regUpdate{6, 0}
s.regUpdatePos++
}
}
func (s *SimpleAluGenerator) s005_frame_0018() {
var t2, t3 int64
var t4 bool
//negPredicate[$Pred_alu.@switch0.@case0]
//negPredicate[$Pred_alu.@switch0.@case1]
t2 = 1 //const1
t3 = 1 //const1
t4 = t2 == t3 //eq
s._Pred_alu_switch0_case2 = t4 //Assign value
s._Pred_alu_switch0_case2_update = s.timeStamp //update timestamp
}
func (s *SimpleAluGenerator) s006_frame_0014() {
var t3, t4, t5, t5_cpy int64
//posPredicate[$Pred_alu.@switch0.@case1]
s.alu_clk_update = s.timeStamp //isRisingEdge[internalIdx=11]
//negPredicate[$Pred_alu.rst]
t3 = s.alu_op1 //loadInternal[alu.op1]
t4 = s.alu_op2 //loadInternal[alu.op2]
t5 = (t3 - t4) & 0x0000001F //minus[targetSizeWithType=10]
t5_cpy = s.alu_tmp_res_1_OutRead //Backup of current value
s.alu_tmp_res_1_OutRead__reg = t5 //Assign value
if t5_cpy != s.alu_tmp_res_1_OutRead__reg {
s.regUpdates[s.regUpdatePos] = regUpdate{6, 0}
s.regUpdatePos++
}
}
func (s *SimpleAluGenerator) s007_frame_0019() {
var t3, t4, t5, t6, t6_cpy int64
//posPredicate[$Pred_alu.@switch0.@case2]
s.alu_clk_update = s.timeStamp //isRisingEdge[internalIdx=11]
//negPredicate[$Pred_alu.rst]
t3 = s.alu_op1 //loadInternal[alu.op1]
t4 = s.alu_op2 //loadInternal[alu.op2]
t5 = (t3 * t4) & 0x000003FF //mul[targetSizeWithType=20]
t6 = (t5) & 0x0000001F //cast_uint[targetSize=5,currentSize=10]
t6_cpy = s.alu_tmp_res_1_OutRead //Backup of current value
s.alu_tmp_res_1_OutRead__reg = t6 //Assign value
if t6_cpy != s.alu_tmp_res_1_OutRead__reg {
s.regUpdates[s.regUpdatePos] = regUpdate{6, 0}
s.regUpdatePos++
}
}
func (s *SimpleAluGenerator) s009_frame_000A() {
var t2, t3, t3_cpy int64
//posPredicate[$Pred_alu.rst]
s.alu_clk_update = s.timeStamp //isRisingEdge[internalIdx=11]
t2 = 0 //const0
t3 = (t2) & 0x0000001F //cast_uint[targetSize=5,currentSize=32]
t3_cpy = s.alu_tmp_res_1_OutRead //Backup of current value
s.alu_tmp_res_1_OutRead__reg = t3 //Assign value
if t3_cpy != s.alu_tmp_res_1_OutRead__reg {
s.regUpdates[s.regUpdatePos] = regUpdate{6, 0} //writeInternal[internal=6]
s.regUpdatePos++
}
// t5 = 0 //const0
//Write to #null
}
func (s *SimpleAluGenerator) initConstants() {
s.epsCycle = 0
s.timeStamp = (s.deltaCycle << 16) | s.epsCycle
}
func (s *SimpleAluGenerator) Run() {
s.epsCycle = 0
s.deltaCycle += 1
for len(s.regUpdates) > 0 && !s.disableRegOutputLogic {
s.regUpdates = make([]regUpdate, 4)
s.timeStamp = (s.deltaCycle << 16) | s.epsCycle
s.stage0000()
s.stage0001()
s.stage0003()
s.stage0004()
s.stage0005()
s.stage0006()
s.stage0007()
s.stage0009()
s.updateRegs()
s.epsCycle += 1
}
s.alu_clk_prev = s.alu_clk
}
func (s *SimpleAluGenerator) stage0000() {
s.s000_frame_0004()
}
func (s *SimpleAluGenerator) stage0001() {
s.s001_frame_0002()
s.s001_frame_001E()
s.s001_frame_000D()
s.s001_frame_0025()
}
func (s *SimpleAluGenerator) stage0003() {
s._Pred_alu_if0_fresh = s._Pred_alu_if0_update == s.timeStamp
if s._Pred_alu_if0 &&
s._Pred_alu_if0_fresh {
s.s003_frame_0021()
}
s.s003_frame_000E()
s.s003_frame_0013()
}
func (s *SimpleAluGenerator) stage0004() {
if !s._Pred_alu_if0 &&
s._Pred_alu_if0_fresh {
s.s004_frame_0023()
}
}
func (s *SimpleAluGenerator) stage0005() {
s.alu_clk_pos_active = ((s.alu_clk_prev == 0) || s.disableEdge) && (s.alu_clk == 1)
s.alu_clk_pos_handled = s.skipEdge(s.alu_clk_update)
s._Pred_alu_rst_fresh = s._Pred_alu_rst_update == s.timeStamp
s._Pred_alu_switch0_case0_fresh = s._Pred_alu_switch0_case0_update == s.timeStamp
s._Pred_alu_switch0_case1_fresh = s._Pred_alu_switch0_case1_update == s.timeStamp
if s.alu_clk_pos_active &&
!s.alu_clk_pos_handled &&
!s._Pred_alu_rst &&
s._Pred_alu_rst_fresh &&
s._Pred_alu_switch0_case0 &&
s._Pred_alu_switch0_case0_fresh {
s.s005_frame_000F()
}
if !s._Pred_alu_switch0_case0 &&
s._Pred_alu_switch0_case0_fresh &&
!s._Pred_alu_switch0_case1 &&
s._Pred_alu_switch0_case1_fresh {
s.s005_frame_0018()
}
}
func (s *SimpleAluGenerator) stage0006() {
if s.alu_clk_pos_active &&
!s.alu_clk_pos_handled &&
!s._Pred_alu_rst &&
s._Pred_alu_rst_fresh &&
s._Pred_alu_switch0_case1 &&
s._Pred_alu_switch0_case1_fresh {
s.s006_frame_0014()
}
}
func (s *SimpleAluGenerator) stage0007() {
s._Pred_alu_switch0_case2_fresh = s._Pred_alu_switch0_case2_update == s.timeStamp
if s.alu_clk_pos_active &&
!s.alu_clk_pos_handled &&
!s._Pred_alu_rst &&
s._Pred_alu_rst_fresh &&
s._Pred_alu_switch0_case2 &&
s._Pred_alu_switch0_case2_fresh {
s.s007_frame_0019()
}
}
func (s *SimpleAluGenerator) stage0009() {
if s.alu_clk_pos_active &&
!s.alu_clk_pos_handled &&
s._Pred_alu_rst &&
s._Pred_alu_rst_fresh {
s.s009_frame_000A()
}
}
// go hat kein overloading
func (s *SimpleAluGenerator) SetInputWithName(name string, value int64, arrayIdx ...int) {
s.SetInput(s.getIndex(name), value, arrayIdx...)
}
func (s *SimpleAluGenerator) SetInput(idx int, value int64, arrayIdx ...int) {
switch idx {
case 1:
s._Pred_alu_if0 = value != 0
break
case 2:
s._Pred_alu_switch0_case0 = value != 0
break
case 3:
s._Pred_alu_switch0_case1 = value != 0
break
case 4:
s._Pred_alu_switch0_case2 = value != 0
break
case 5:
s._Pred_alu_rst = value != 0
break
case 6:
s.alu_tmp_res_1_OutRead = value
break
case 7:
s.alu_switch0 = value
break
case 8:
s.alu_clk = value
break
case 9:
s.alu_instr = value
break
case 10:
s.alu_isZero = value
break
case 11:
s.alu_op1 = value
break
case 12:
s.alu_op2 = value
break
case 13:
s.alu_res = value
break
case 14:
s.alu_rst = value
break
default:
panic("Not a valid index")
}
}
func (s *SimpleAluGenerator) getIndex(name string) int {
idx, ok := s.varIdx[name]
if !ok {
panic("The name:" + name + " is not a valid index")
}
return idx
}
func (s *SimpleAluGenerator) getName(idx int) string {
switch idx {
case 1:
return "$Pred_alu.@if0"
case 2:
return "$Pred_alu.@switch0.@case0"
case 3:
return "$Pred_alu.@switch0.@case1"
case 4:
return "$Pred_alu.@switch0.@case2"
case 5:
return "$Pred_alu.rst"
case 6:
return "alu.$tmp_res_1_OutRead"
case 7:
return "alu.@switch0"
case 8:
return "alu.clk"
case 9:
return "alu.instr"
case 10:
return "alu.isZero"
case 11:
return "alu.op1"
case 12:
return "alu.op2"
case 13:
return "alu.res"
case 14:
return "alu.rst"
default:
panic("Not a valid index:")
}
}
func (s *SimpleAluGenerator) GetOutputWithName(name string, arrayIdx ...int) int64 {
return s.GetOutput(s.getIndex(name), arrayIdx...)
}
func (s *SimpleAluGenerator) GetOutput(idx int, arrayIdx ...int) int64 {
switch idx {
case 1:
if s._Pred_alu_if0 {
return 1
} else {
return 0
}
case 2:
if s._Pred_alu_switch0_case0 {
return 1
} else {
return 0
}
case 3:
if s._Pred_alu_switch0_case1 {
return 1
} else {
return 0
}
case 4:
if s._Pred_alu_switch0_case2 {
return 1
} else {
return 0
}
case 5:
if s._Pred_alu_rst {
return 1
} else {
return 0
}
case 6:
return s.alu_tmp_res_1_OutRead & 0x0000001F
case 7:
return s.alu_switch0 & 0x0000000F
case 8:
return s.alu_clk & 1
case 9:
return s.alu_instr & 0x0000000F
case 10:
return s.alu_isZero & 1
case 11:
return s.alu_op1 & 0x0000001F
case 12:
return s.alu_op2 & 0x0000001F
case 13:
return s.alu_res & 0x0000001F
case 14:
return s.alu_rst & 1
default:
panic("Not a valid index:")
}
}
func (s *SimpleAluGenerator) GetDeltaCycle() int64 {
return s.deltaCycle
}
func (s SimpleAluGenerator) GetJsonDesc() string {
return "{\"moduleName\":\"alu\",\"inPorts\":[{\"idx\":8,\"name\":\"alu.clk\",\"width\":1,\"clock\": true,\"reset\":false,\"type\":0},{\"idx\":9,\"name\":\"alu.instr\",\"width\":4,\"clock\": false,\"reset\":false,\"type\":0},{\"idx\":11,\"name\":\"alu.op1\",\"width\":5,\"clock\": false,\"reset\":false,\"type\":2},{\"idx\":12,\"name\":\"alu.op2\",\"width\":5,\"clock\": false,\"reset\":false,\"type\":2},{\"idx\":14,\"name\":\"alu.rst\",\"width\":1,\"clock\": false,\"reset\":true,\"type\":0}],\"inOutPorts\":[],\"outPorts\":[{\"idx\":10,\"name\":\"alu.isZero\",\"width\":1,\"clock\": false,\"reset\":false,\"type\":0},{\"idx\":13,\"name\":\"alu.res\",\"width\":5,\"clock\": false,\"reset\":false,\"type\":2}],\"internalPorts\":[{\"idx\":0,\"name\":\"#null\",\"width\":1,\"clock\": false,\"reset\":false,\"type\":0},{\"idx\":1,\"name\":\"$Pred_alu.@if0\",\"width\":1,\"clock\": false,\"reset\":false,\"type\":0},{\"idx\":2,\"name\":\"$Pred_alu.@switch0.@case0\",\"width\":1,\"clock\": false,\"reset\":false,\"type\":0},{\"idx\":3,\"name\":\"$Pred_alu.@switch0.@case1\",\"width\":1,\"clock\": false,\"reset\":false,\"type\":0},{\"idx\":4,\"name\":\"$Pred_alu.@switch0.@case2\",\"width\":1,\"clock\": false,\"reset\":false,\"type\":0},{\"idx\":5,\"name\":\"$Pred_alu.rst\",\"width\":1,\"clock\": false,\"reset\":false,\"type\":0},{\"idx\":6,\"name\":\"alu.$tmp_res_1_OutRead\",\"width\":5,\"clock\": false,\"reset\":false,\"type\":2},{\"idx\":7,\"name\":\"alu.@switch0\",\"width\":4,\"clock\": false,\"reset\":false,\"type\":0}],\"nameIdx\":{\"alu.rst\":14,\"alu.op2\":12,\"alu.op1\":11,\"alu.instr\":9,\"$Pred_alu.rst\":5,\"#null\":0,\"alu.@switch0\":7,\"$Pred_alu.@switch0.@case1\":3,\"alu.clk\":8,\"alu.isZero\":10,\"$Pred_alu.@switch0.@case0\":2,\"alu.$tmp_res_1_OutRead\":6,\"$Pred_alu.@switch0.@case2\":4,\"alu.res\":13,\"$Pred_alu.@if0\":1}}"
}
func (s *SimpleAluGenerator) SetDisableEdge(enable bool) {
s.disableEdge = enable
}
func (s *SimpleAluGenerator) SetDisableRegOutputLogic(enable bool) {
s.disableRegOutputLogic = enable
}
func (s *SimpleAluGenerator) InitConstants() {
panic("not yet implemented")
}
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