Skip to content

Instantly share code, notes, and snippets.

@cyring

cyring/gist:d0ff0cdd89fc37b0ec2ed6037e218b79

Created January 20, 2023 15:09
Star
Embed
What would you like to do?
Learn more about clone URLs
Download ZIP
i9-13900K
Raw
gistfile1.txt
13th Gen Intel(R) Core(TM) i9-13900K
@cyring
Copy link
Author

cyring commented Jan 20, 2023 •
edited 

Processor                                 [13th Gen Intel(R) Core(TM) i9-13900K]
|- Architecture                                                    [Raptor Lake]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x0000010f]
|- Signature                                                           [  06_B7]
|- Stepping                                                            [      1]
|- Online CPU                                                          [ 32/ 32]
|- Base Clock                                                          [ 99.836]
|- Frequency            (MHz)                      Ratio                        
                 Min    798.70                    <   8 >                       
                 Max   2995.11                    <  30 >                       
|- Factory                                                             [100.000]
                       3000                       [  30 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT   6988.59                    <  70 >                       
   |- HWP                                                                       
                 Min   6988.59                    <  70 >                       
                 Max   6988.59                    <  70 >                       
                 TGT      AUTO                    <   0 >                       
|- Turbo Boost                                                         [ UNLOCK]
                  1C   5790.55                    <  58 >                       
                  2C   5790.55                    <  58 >                       
                  3C   5491.04                    <  55 >                       
                  4C   5491.04                    <  55 >                       
                  5C   5491.04                    <  55 >                       
                  6C   5491.04                    <  55 >                       
                  7C   5491.04                    <  55 >                       
                  8C   5491.04                    <  55 >                       
|- Hybrid                                                              [ UNLOCK]
                  1C   4292.97                    <  43 >                       
|- Uncore                                                              [ UNLOCK]
                 Min    798.69                    <   8 >                       
                 Max   4991.82                    <  50 >                       
|- TDP                                                           Level [  0:3  ]
   |- Programmable                                                     [ UNLOCK]
   |- Configuration                                                    [   LOCK]
   |- Turbo Activation                                                 [ UNLOCK]
             Nominal   2995.11                    [  30 ]                       
               Turbo      AUTO                    <   0 >                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNNI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N] AVX-VNNI-VEX [Y]      MOVDIRI [Y]   MOVDIR64B [Y] 
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- ENQCMD       [N]         GFNI [Y]        OSPKE [Y]     WAITPKG [Y] 
|- MMX/Ext    [Y/N] MON/MWAITX [Y/N]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/N]      SSE4.2 [Y] 
|- SERIALIZE    [Y]      SYSCALL [Y]        RDPID [Y]         SGX [N] 
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Capable]
|- CPL Qualified Debug Store                                  DS-CPL   [Capable]
|- 64-Bit Debug Store                                         DTES64   [Capable]
|- Fast Short REP CMPSB                                         FSRC   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast Short REP STOSB                                         FSRS   [Capable]
|- Fast Zero-length REP MOVSB                                   FZRM   [Missing]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                     FMA | FMA4   [Capable]
|- Hardware Feedback Interface                                   HFI   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- History Reset                                              HRESET   [Capable]
|- Hybrid part processor                                      HYBRID   [Capable]
|- Instruction Based Sampling                                    IBS   [Missing]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- Linear Address Masking                                        LAM   [Missing]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Memory Protection Extensions                                  MPX   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Capable]
|- Platform Configuration                                    PCONFIG   [Capable]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Capable]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Write Data to a Processor Trace Packet                    PTWRITE   [Capable]
|- Resource Director Technology/PQE                            RDT-A   [Missing]
|- Resource Director Technology/PQM                            RDT-M   [Missing]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Capable]
|- Self-Snoop                                                     SS   [Capable]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Thread Director                                                TD   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Capable]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Capable]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Missing]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- Execution Disable Bit Support                              XD-Bit   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Capable]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
|- Writeback & invalidate the L1 data cache                L1D-FLUSH   [Capable]
|- Hypervisor - No flush L1D on VM entry            L1DFL_VMENTRY_NO   [ Enable]
|- Arch - Buffer Overwriting                                MD-CLEAR   [Capable]
|- Arch - No Rogue Data Cache Load                           RDCL_NO   [ Enable]
|- Arch - Enhanced IBRS                                     IBRS_ALL   [ Enable]
|- Arch - Return Stack Buffer Alternate                         RSBA   [Capable]
|- Arch - No Speculative Store Bypass                         SSB_NO   [Capable]
|- Arch - No Microarchitectural Data Sampling                 MDS_NO   [ Enable]
|- Arch - No TSX Asynchronous Abort                           TAA_NO   [ Enable]
|- Arch - No Page Size Change MCE                     PSCHANGE_MC_NO   [ Enable]
|- Arch - STLB QoS                                              STLB   [ Enable]
|- Arch - Functional Safety Island                              FuSa   [ Enable]
|- Arch - RSM in CPL0 only                                       RSM   [ Enable]
|- Arch - Split Locked Access Exception                         SPLA   [ Enable]
|- Arch - Snoop Filter QoS Mask                         SNOOP_FILTER   [ Enable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Data Operand Independent Timing Mode                 DOITM   [Capable]
|- Arch - Not affected by SBDR or SSDP                  SBDR_SSDP_NO   [ Enable]
|- Arch - No Fill Buffer Stale Data Propagator              FBSDP_NO   [ Enable]
|- Arch - No Primary Stale Data Propagator                   PSDP_NO   [ Enable]
|- Arch - Overwrite Fill Buffer values                      FB_CLEAR   [Capable]
|- Arch - Special Register Buffer Data Sampling                SRBDS   [ Unable]
   |- RDRAND and RDSEED mitigation                             RNGDS   [ Unable]
   |- Restricted Transactional Memory                            RTM   [ Unable]
   |- Verify Segment for Writing instruction                    VERW   [ Unable]
|- Arch - Restricted RSB Alternate                             RRSBA   [ Enable]
|- Arch - No Branch Target Injection                          BHI_NO   [Capable]
|- Arch - Legacy xAPIC Disable                             XAPIC_DIS   [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer               PBRSB_NO   [Capable]
|- Arch - IPRED disabled for CPL3                        IPRED_DIS_U   [Capable]
|- Arch - IPRED disabled for CPL0/1/2                    IPRED_DIS_S   [Capable]
|- Arch - RRSBA disabled for CPL3                        RRSBA_DIS_U   [Capable]
|- Arch - RRSBA disabled for CPL0/1/2                    RRSBA_DIS_S   [Capable]
|- Arch - BHI disabled for CPL0/1/2                        BHI_DIS_S   [Capable]
|- No MXCSR Configuration Dependent Timing                   MCDT_NO   [ Unable]
Security Features                                                               
|- CPUID Key Locker                                               KL   [Capable]
|- AES Key Locker instructions                                AESKLE   [Missing]
|- AES Wide Key Locker instructions                          WIDE_KL   [Capable]
|- Software Guard SGX1 Extensions                               SGX1   [Missing]
|- Software Guard SGX2 Extensions                               SGX2   [Missing]
                                                                                
Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   <OFF>
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L2 Line Prefetcher                                        L2 HW CL   < ON>
|- System Management Mode                                       SMM-Dual   [ ON]
|- Hyper-Threading                                                   HTT   [ ON]
|- SpeedStep                                                        EIST   < ON>
|- Dynamic Acceleration                                              IDA   [ ON]
|- Turbo Boost Max 3.0                                             TURBO   < ON>
|- Energy Efficiency Optimization                                    EEO   <OFF>
|- Race To Halt Optimization                                         R2H   <OFF>
|- Watchdog Timer                                                    TCO   <OFF>
|- Virtualization                                                    VMX   [ ON]
   |- I/O MMU                                                       VT-d   [ ON]
   |- Version                                                     [         4.0]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  5]
|- Counters:          General                   Fixed                           
|           {  6,  0,  0 } x 48 bits            3 x 48 bits                     
|- Enhanced Halt State                                           C1E       < ON>
|- C1 Auto Demotion                                              C1A       < ON>
|- C3 Auto Demotion                                              C3A       <OFF>
|- C1 UnDemotion                                                 C1U       < ON>
|- C3 UnDemotion                                                 C3U       <OFF>
|- C6 Core Demotion                                              CC6       <OFF>
|- C6 Module Demotion                                            MC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware Duty Cycling                                         HDC       [OFF]
|- Package C-States                                                             
   |- Configuration Control                                   CONFIG   [ UNLOCK]
   |- Lowest C-State                                           LIMIT   <     C0>
   |- I/O MWAIT Redirection                                  IOMWAIT   <Disable>
   |- Max C-State Inclusion                                    RANGE   <     C8>
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x1814]
|- ACPI Processor C-States                                      _CST   [      3]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     0     2     0     1     0     1              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Last Level Cache Misses                                             [Capable]
|- Branch Instructions Retired                                         [Capable]
|- Branch Mispredicts Retired                                          [Capable]
|- Top-down slots Counter                                              [Capable]
|- Processor Performance Control                                _PCT   [ Enable]
|- Performance Supported States                                 _PSS   [      0]
|- Performance Present Capabilities                             _PPC   [      0]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax <  0:100 C>
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [  0.00%]
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   [      0]
   |- Energy Policy                                          HWP EPP   <      0>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Capable]
|- Package Thermal Management                                    PTM   [Capable]
|- Thermal Monitor 1                                             TM1   [ Enable]
|- Thermal Monitor 2                                             TM2   [Capable]
|- Thermal Design Power                                          TDP   [  125 W]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   < 4095 W>
   |- Time Window                                                TW1   <    8 s>
   |- Power Limit                                                PL2   < 4095 W>
   |- Time Window                                                TW2   <   2 ms>
|- Thermal Design Power                                         Core   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   < 976 us>
|- Thermal Design Power                                       Uncore   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   < 976 us>
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                     Platform   <Disable>
   |- Power Limit                                                PL1   <  125 W>
   |- Time Window                                                TW1   <    1 s>
   |- Power Limit                                                PL2   <    0 W>
   |- Time Window                                                TW2   < 976 us>
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Package Thermal Point                                                        
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000061035]
   |- Window                                            second   [  0.000976562]

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID  Hybrid ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0  P   1   0  0   32768  8     49152 12   2097152 16  37748736 12  
001:  0    1  P   1   0  1   32768  8     49152 12   2097152 16  37748736 12  
002:  0    8  P   1   4  0   32768  8     49152 12   2097152 16  37748736 12  
003:  0    9  P   1   4  1   32768  8     49152 12   2097152 16  37748736 12  
004:  0   16  P   1   8  0   32768  8     49152 12   2097152 16  37748736 12  
005:  0   17  P   1   8  1   32768  8     49152 12   2097152 16  37748736 12  
006:  0   24  P   1  12  0   32768  8     49152 12   2097152 16  37748736 12  
007:  0   25  P   1  12  1   32768  8     49152 12   2097152 16  37748736 12  
008:  0   32  P   1  16  0   32768  8     49152 12   2097152 16  37748736 12  
009:  0   33  P   1  16  1   32768  8     49152 12   2097152 16  37748736 12  
010:  0   40  P   1  20  0   32768  8     49152 12   2097152 16  37748736 12  
011:  0   41  P   1  20  1   32768  8     49152 12   2097152 16  37748736 12  
012:  0   48  P   1  24  0   32768  8     49152 12   2097152 16  37748736 12  
013:  0   49  P   1  24  1   32768  8     49152 12   2097152 16  37748736 12  
014:  0   56  P   1  28  0   32768  8     49152 12   2097152 16  37748736 12  
015:  0   57  P   1  28  1   32768  8     49152 12   2097152 16  37748736 12  
016:  0   64  E   1  32  0   65536  8     32768  8   4194304 16  37748736 12  
017:  0   66  E   1  33  0   65536  8     32768  8   4194304 16  37748736 12  
018:  0   68  E   1  34  0   65536  8     32768  8   4194304 16  37748736 12  
019:  0   70  E   1  35  0   65536  8     32768  8   4194304 16  37748736 12  
020:  0   72  E   1  36  0   65536  8     32768  8   4194304 16  37748736 12  
021:  0   74  E   1  37  0   65536  8     32768  8   4194304 16  37748736 12  
022:  0   76  E   1  38  0   65536  8     32768  8   4194304 16  37748736 12  
023:  0   78  E   1  39  0   65536  8     32768  8   4194304 16  37748736 12  
024:  0   80  E   1  40  0   65536  8     32768  8   4194304 16  37748736 12  
025:  0   82  E   1  41  0   65536  8     32768  8   4194304 16  37748736 12  
026:  0   84  E   1  42  0   65536  8     32768  8   4194304 16  37748736 12  
027:  0   86  E   1  43  0   65536  8     32768  8   4194304 16  37748736 12  
028:  0   88  E   1  44  0   65536  8     32768  8   4194304 16  37748736 12  
029:  0   90  E   1  45  0   65536  8     32768  8   4194304 16  37748736 12  
030:  0   92  E   1  46  0   65536  8     32768  8   4194304 16  37748736 12  
031:  0   94  E   1  47  0   65536  8     32768  8   4194304 16  37748736 12  

[ 0] American Megatrends International, LLC.                                    
[ 1] F23a                                                                       
[ 2] 01/04/2023                                                                 
[ 3] Gigabyte Technology Co., Ltd.                                              
[ 4] Z690 AORUS XTREME                                                          
[ 5] -CF                                                                        
[ 6] D---u---s---n-                                                             
[ 7] Default string                                                             
[ 8] Z690 MB                                                                    
[ 9] Gigabyte Technology Co., Ltd.                                              
[10] Z690 AORUS XTREME                                                          
[11] x.x                                                                        
[12] D---u---s---n-                                                             
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes                   
[14]                                                                            
[15] Controller0-ChannelA-DIMM1\BANK 0                                          
[16]                                                                            
[17] Controller1-ChannelA-DIMM1\BANK 0                                          
[18]                                                                            
[19] G Skill Intl                                                               
[20]                                                                            
[21] G Skill Intl                                                               
[22]                                                                            
[23] F5-7800J3646H16G                                                           
[24]                                                                            
[25] F5-7800J3646H16G                                                           

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000   19.01     0  0.0000   30  000000000000000000    0.000000000   0.000000000
001    1.03     0  0.0000   30  000000000000000000    0.000000000   0.000000000
002    2.16     0  0.0000   28  000000000000000000    0.000000000   0.000000000
003    1.01     0  0.0000   28  000000000000000000    0.000000000   0.000000000
004    1.86     0  0.0000   28  000000000000000000    0.000000000   0.000000000
005    1.25     0  0.0000   28  000000000000000000    0.000000000   0.000000000
006    7.45     0  0.0000   27  000000000000000000    0.000000000   0.000000000
007    0.94     0  0.0000   27  000000000000000000    0.000000000   0.000000000
008    6.00     0  0.0000   30  000000000000000000    0.000000000   0.000000000
009    0.56     0  0.0000   30  000000000000000000    0.000000000   0.000000000
010   13.55 10944  1.3359   28  000000000000000000    0.000000000   0.000000000
011    0.65     0  0.0000   28  000000000000000000    0.000000000   0.000000000
012    8.84     0  0.0000   30  000000000000000000    0.000000000   0.000000000
013    0.54     0  0.0000   30  000000000000000000    0.000000000   0.000000000
014   18.13     0  0.0000   27  000000000000000000    0.000000000   0.000000000
015    1.93     0  0.0000   27  000000000000000000    0.000000000   0.000000000
016    3.43     0  0.0000   30  000000000000000000    0.000000000   0.000000000
017    2.23     0  0.0000   30  000000000000000000    0.000000000   0.000000000
018    0.92     0  0.0000   30  000000000000000000    0.000000000   0.000000000
019    0.76     0  0.0000   30  000000000000000000    0.000000000   0.000000000
020    1.08     0  0.0000   30  000000000000000000    0.000000000   0.000000000
021    1.34     0  0.0000   30  000000000000000000    0.000000000   0.000000000
022    0.67     0  0.0000   30  000000000000000000    0.000000000   0.000000000
023    0.43     0  0.0000   30  000000000000000000    0.000000000   0.000000000
024    1.04     0  0.0000   31  000000000000000000    0.000000000   0.000000000
025   14.86     0  0.0000   31  000000000000000000    0.000000000   0.000000000
026   87.28     0  0.0000   31  000000000000000000    0.000000000   0.000000000
027    0.62     0  0.0000   31  000000000000000000    0.000000000   0.000000000
028    0.48     0  0.0000   32  000000000000000000    0.000000000   0.000000000
029    2.01     0  0.0000   32  000000000000000000    0.000000000   0.000000000
030    0.66     0  0.0000   32  000000000000000000    0.000000000   0.000000000
031    1.54 10780  0.0000   32  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J):   8.445556641   6.971984863   0.000000000   0.000000000   0.000000000
Power(W) :   8.445556641   6.971984863   0.000000000   0.000000000   0.000000000

@cyring
Copy link
Author

cyring commented Jan 20, 2023 •
edited

Memory Controller

Z690

@cyring
Copy link
Author

cyring commented Jan 22, 2023

Voltage Core

Vcore_RPL

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment