Instantly share code, notes, and snippets.

Embed
What would you like to do?
****** START compiling Program:Intrinsics(int):int (MethodHash=7ba20f7c)
Generating code for Unix x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 7e 03 00 00 04 ldsfld 0x4000003
IL_0005 20 00 04 00 00 ldc.i4 0x400
IL_000a 02 ldarg.0
IL_000b 28 13 00 00 0a call 0xA000013
IL_0010 2a ret
Arg #0 passed in register(s) rdi
lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
*************** In compInitDebuggingInfo() for Program:Intrinsics(int):int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 011h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:Intrinsics(int):int
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [000..011)
IL Code Size,Instr 17, 5, Basic Block count 1, Local Variable Num,Ref count 2, 1 for method Program:Intrinsics(int):int
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program:Intrinsics(int):int'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Program:Intrinsics(int):int
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program:Intrinsics(int):int'
[ 0] 0 (0x000) ldsfld 04000003
[ 1] 5 (0x005) ldc.i4 1024
[ 2] 10 (0x00a) ldarg.0
[ 3] 11 (0x00b) call 0A000013 (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT)
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
info.compCompHnd->canTailCall returned false for call [000004]
[000008] ------------ * STMT void (IL 0x000... ???)
[000004] I-C-G------- \--* CALL int GetNthBitOffset.Intrinsics (exactContextHnd=0x00007FA5D4E17599)
[000001] ----G------- arg0 +--* FIELD long _bits
[000002] ------------ arg1 +--* CNS_INT int 0x400
[000003] ------------ arg2 \--* LCL_VAR int V00 arg0
[ 1] 16 (0x010) ret
[000011] ------------ * STMT void (IL ???... ???)
[000010] --C--------- \--* RETURN int
[000009] --C--------- \--* RET_EXPR int (inl return from call [000004])
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** In fgInline()
Expanding INLINE_CANDIDATE in statement [000008] in BB01:
[000008] ------------ * STMT void (IL 0x000...0x010)
[000004] I-C-G------- \--* CALL int GetNthBitOffset.Intrinsics (exactContextHnd=0x00007FA5D4E17599)
[000001] ----G------- arg0 +--* FIELD long _bits
[000002] ------------ arg1 +--* CNS_INT int 0x400
[000003] ------------ arg2 \--* LCL_VAR int V00 arg0
Argument #0: has global refs
[000001] ----G------- * FIELD long _bits
Argument #1: is a constant
[000002] ------------ * CNS_INT int 0x400
Argument #2: is a local var
[000003] ------------ * LCL_VAR int V00 arg0
INLINER: inlineInfo.tokenLookupContextHandle for GetNthBitOffset:Intrinsics(long,int,int):int set to 0x00007FA5D4E17599:
Invoking compiler for the inlinee method GetNthBitOffset:Intrinsics(long,int,int):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 0a stloc.0
IL_0002 04 ldarg.2
IL_0003 0b stloc.1
IL_0004 04 ldarg.2
IL_0005 06 ldloc.0
IL_0006 4c ldind.i8
IL_0007 28 0d 00 00 0a call 0xA00000D
IL_000c 69 conv.i4
IL_000d 59 sub
IL_000e 10 02 starg.s 0x2
IL_0010 06 ldloc.0
IL_0011 1e ldc.i4.8
IL_0012 58 add
IL_0013 0a stloc.0
IL_0014 04 ldarg.2
IL_0015 16 ldc.i4.0
IL_0016 30 ea bgt.s -22 (IL_0002)
IL_0018 06 ldloc.0
IL_0019 1e ldc.i4.8
IL_001a 59 sub
IL_001b 0a stloc.0
IL_001c 17 ldc.i4.1
IL_001d 6a conv.i8
IL_001e 07 ldloc.1
IL_001f 17 ldc.i4.1
IL_0020 59 sub
IL_0021 1f 3f ldc.i4.s 0x3F
IL_0023 5f and
IL_0024 62 shl
IL_0025 06 ldloc.0
IL_0026 4c ldind.i8
IL_0027 28 0f 00 00 0a call 0xA00000F
IL_002c 28 10 00 00 0a call 0xA000010
IL_0031 69 conv.i4
IL_0032 0c stloc.2
IL_0033 06 ldloc.0
IL_0034 02 ldarg.0
IL_0035 59 sub
IL_0036 1e ldc.i4.8
IL_0037 5b div
IL_0038 6a conv.i8
IL_0039 1c ldc.i4.6
IL_003a 62 shl
IL_003b 69 conv.i4
IL_003c 08 ldloc.2
IL_003d 58 add
IL_003e 2a ret
INLINER impTokenLookupContextHandle for GetNthBitOffset:Intrinsics(long,int,int):int is 0x00007FA5D4E17599.
*************** In fgFindBasicBlocks() for GetNthBitOffset:Intrinsics(long,int,int):int
Jump targets:
IL_0002
New Basic Block BB02 [0001] created.
BB02 [000..002)
New Basic Block BB03 [0002] created.
BB03 [002..018)
New Basic Block BB04 [0003] created.
BB04 [018..03F)
Basic block list for 'GetNthBitOffset:Intrinsics(long,int,int):int'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001] 1 1 [000..002)
BB03 [0002] 2 1 [002..018)-> BB03 ( cond ) bwd
BB04 [0003] 1 1 [018..03F) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for GetNthBitOffset:Intrinsics(long,int,int):int
impImportBlockPending for BB02
Importing BB02 (PC=000) of 'GetNthBitOffset:Intrinsics(long,int,int):int'
[ 0] 0 (0x000) ldarg.0
lvaGrabTemp returning 2 (V02 tmp1) called for Inlining Arg.
[ 1] 1 (0x001) stloc.0
lvaGrabTemp returning 3 (V03 tmp2) (a long lifetime temp) called for Inline stloc first use temp.
[000016] ------------ * STMT void
[000013] ------------ | /--* LCL_VAR long V02 tmp1
[000015] -A---------- \--* ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
impImportBlockPending for BB03
Importing BB03 (PC=002) of 'GetNthBitOffset:Intrinsics(long,int,int):int'
[ 0] 2 (0x002) ldarg.2
lvaGrabTemp returning 4 (V04 tmp3) called for Inlining Arg.
[ 1] 3 (0x003) stloc.1
lvaGrabTemp returning 5 (V05 tmp4) (a long lifetime temp) called for Inline stloc first use temp.
[000021] ------------ * STMT void
[000018] ------------ | /--* LCL_VAR int V04 tmp3
[000020] -A---------- \--* ASG int
[000019] D------N---- \--* LCL_VAR int V05 tmp4
[ 0] 4 (0x004) ldarg.2
[ 1] 5 (0x005) ldloc.0
[ 2] 6 (0x006) ldind.i8
[ 2] 7 (0x007) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 2] 12 (0x00c) conv.i4
[ 2] 13 (0x00d) sub
[ 1] 14 (0x00e) starg.s 2
[000031] ------------ * STMT void
[000026] ---XG------- | /--* CAST int <- long
[000025] ---XG------- | | \--* HWIntrinsic long PopCount
[000024] *--XG------- | | \--* IND long
[000023] ------------ | | \--* LCL_VAR long V03 tmp2
[000027] ---XG------- | /--* SUB int
[000022] ------------ | | \--* LCL_VAR int V04 tmp3
[000030] -A-XG------- \--* ASG int
[000029] D------N---- \--* LCL_VAR int V04 tmp3
[ 0] 16 (0x010) ldloc.0
[ 1] 17 (0x011) ldc.i4.8 8
[ 2] 18 (0x012) add
[ 1] 19 (0x013) stloc.0
[000038] ------------ * STMT void
[000034] ------------ | /--* CAST long <- int
[000033] ------------ | | \--* CNS_INT int 8
[000035] ------------ | /--* ADD long
[000032] ------------ | | \--* LCL_VAR long V03 tmp2
[000037] -A---------- \--* ASG long
[000036] D------N---- \--* LCL_VAR long V03 tmp2
[ 0] 20 (0x014) ldarg.2
[ 1] 21 (0x015) ldc.i4.0 0
[ 2] 22 (0x016) bgt.s
[000043] ------------ * STMT void
[000042] ------------ \--* JTRUE void
[000040] ------------ | /--* CNS_INT int 0
[000041] ------------ \--* GT int
[000039] ------------ \--* LCL_VAR int V04 tmp3
impImportBlockPending for BB04
impImportBlockPending for BB03
Importing BB04 (PC=024) of 'GetNthBitOffset:Intrinsics(long,int,int):int'
[ 0] 24 (0x018) ldloc.0
[ 1] 25 (0x019) ldc.i4.8 8
[ 2] 26 (0x01a) sub
[ 1] 27 (0x01b) stloc.0
[000051] ------------ * STMT void
[000047] ------------ | /--* CAST long <- int
[000046] ------------ | | \--* CNS_INT int 8
[000048] ------------ | /--* SUB long
[000045] ------------ | | \--* LCL_VAR long V03 tmp2
[000050] -A---------- \--* ASG long
[000049] D------N---- \--* LCL_VAR long V03 tmp2
[ 0] 28 (0x01c) ldc.i4.1 1
[ 1] 29 (0x01d) conv.i8
[ 1] 30 (0x01e) ldloc.1
[ 2] 31 (0x01f) ldc.i4.1 1
[ 3] 32 (0x020) sub
[ 2] 33 (0x021) ldc.i4.s 63
[ 3] 35 (0x023) and
[ 2] 36 (0x024) shl
[ 1] 37 (0x025) ldloc.0
[ 2] 38 (0x026) ldind.i8
[ 2] 39 (0x027) call 0A00000F
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 1] 44 (0x02c) call 0A000010
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 1] 49 (0x031) conv.i4
[ 1] 50 (0x032) stloc.2
lvaGrabTemp returning 6 (V06 tmp5) (a long lifetime temp) called for Inline stloc first use temp.
[000067] ------------ * STMT void
[000064] ---XG------- | /--* CAST int <- long
[000063] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
[000061] *--XG------- | | | /--* IND long
[000060] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000062] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
[000057] ------------ | | | /--* CNS_INT int 63
[000058] ------------ | | | /--* AND int
[000055] ------------ | | | | | /--* CNS_INT int 1
[000056] ------------ | | | | \--* SUB int
[000054] ------------ | | | | \--* LCL_VAR int V05 tmp4
[000059] ------------ | | \--* LSH long
[000053] ------------ | | \--* CAST long <- int
[000052] ------------ | | \--* CNS_INT int 1
[000066] -A-XG------- \--* ASG int
[000065] D------N---- \--* LCL_VAR int V06 tmp5
[ 0] 51 (0x033) ldloc.0
[ 1] 52 (0x034) ldarg.0
[ 2] 53 (0x035) sub
[ 1] 54 (0x036) ldc.i4.8 8
[ 2] 55 (0x037) div
[ 1] 56 (0x038) conv.i8
[ 1] 57 (0x039) ldc.i4.6 6
[ 2] 58 (0x03a) shl
[ 1] 59 (0x03b) conv.i4
[ 1] 60 (0x03c) ldloc.2
[ 2] 61 (0x03d) add
[ 1] 62 (0x03e) ret
Inlinee Return expression (before normalization) =>
[000077] ------------ /--* LCL_VAR int V06 tmp5
[000078] ---X-------- * ADD int
[000076] ---X-------- \--* CAST int <- long
[000074] ------------ | /--* CNS_INT int 6
[000075] ---X-------- \--* LSH long
[000072] ------------ | /--* CAST long <- int
[000071] ------------ | | \--* CNS_INT int 8
[000073] ---X-------- \--* DIV long
[000069] ------------ | /--* LCL_VAR long V02 tmp1
[000070] ------------ \--* SUB long
[000068] ------------ \--* LCL_VAR long V03 tmp2
Inlinee Return expression (after normalization) =>
[000077] ------------ /--* LCL_VAR int V06 tmp5
[000078] ---X-------- * ADD int
[000076] ---X-------- \--* CAST int <- long
[000074] ------------ | /--* CNS_INT int 6
[000075] ---X-------- \--* LSH long
[000072] ------------ | /--* CAST long <- int
[000071] ------------ | | \--* CNS_INT int 8
[000073] ---X-------- \--* DIV long
[000069] ------------ | /--* LCL_VAR long V02 tmp1
[000070] ------------ \--* SUB long
[000068] ------------ \--* LCL_VAR long V03 tmp2
----------- Statements (and blocks) added due to the inlining of call [000004] -----------
Arguments setup:
[000081] ------------ * STMT void (IL 0x000... ???)
[000001] ----G------- | /--* FIELD long _bits
[000080] -A--G------- \--* ASG long
[000079] D------N---- \--* LCL_VAR long V02 tmp1
[000084] ------------ * STMT void (IL 0x000... ???)
[000003] ------------ | /--* LCL_VAR int V00 arg0
[000083] -A---------- \--* ASG int
[000082] D------N---- \--* LCL_VAR int V04 tmp3
Zero init inlinee locals:
[000088] ------------ * STMT void (IL 0x000... ???)
[000085] ------------ | /--* CNS_INT long 0
[000087] -A---------- \--* ASG long
[000086] D------N---- \--* LCL_VAR long V03 tmp2
[000092] ------------ * STMT void (IL 0x000... ???)
[000089] ------------ | /--* CNS_INT int 0
[000091] -A---------- \--* ASG int
[000090] D------N---- \--* LCL_VAR int V05 tmp4
[000096] ------------ * STMT void (IL 0x000... ???)
[000093] ------------ | /--* CNS_INT int 0
[000095] -A---------- \--* ASG int
[000094] D------N---- \--* LCL_VAR int V06 tmp5
Inlinee method body:New Basic Block BB05 [0004] created.
Convert bbJumpKind of BB04 to BBJ_NONE
fgInlineAppendStatements: no gc ref inline locals.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001] 1 1 [000..001) i
BB03 [0002] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB04 [0003] 1 1 [000..001) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB02 [000..001), preds={} succs={BB03}
***** BB02, stmt 1
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] ------------ | /--* LCL_VAR long V02 tmp1
[000015] -A---------- \--* ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
------------ BB03 [000..001) -> BB03 (cond), preds={} succs={BB04,BB03}
***** BB03, stmt 2
[000021] ------------ * STMT void (IL 0x000... ???)
[000018] ------------ | /--* LCL_VAR int V04 tmp3
[000020] -A---------- \--* ASG int
[000019] D------N---- \--* LCL_VAR int V05 tmp4
***** BB03, stmt 3
[000031] ------------ * STMT void (IL 0x000... ???)
[000026] ---XG------- | /--* CAST int <- long
[000025] ---XG------- | | \--* HWIntrinsic long PopCount
[000024] *--XG------- | | \--* IND long
[000023] ------------ | | \--* LCL_VAR long V03 tmp2
[000027] ---XG------- | /--* SUB int
[000022] ------------ | | \--* LCL_VAR int V04 tmp3
[000030] -A-XG------- \--* ASG int
[000029] D------N---- \--* LCL_VAR int V04 tmp3
***** BB03, stmt 4
[000038] ------------ * STMT void (IL 0x000... ???)
[000034] ------------ | /--* CAST long <- int
[000033] ------------ | | \--* CNS_INT int 8
[000035] ------------ | /--* ADD long
[000032] ------------ | | \--* LCL_VAR long V03 tmp2
[000037] -A---------- \--* ASG long
[000036] D------N---- \--* LCL_VAR long V03 tmp2
***** BB03, stmt 5
[000043] ------------ * STMT void (IL 0x000... ???)
[000042] ------------ \--* JTRUE void
[000040] ------------ | /--* CNS_INT int 0
[000041] ------------ \--* GT int
[000039] ------------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001), preds={} succs={BB05}
***** BB04, stmt 6
[000051] ------------ * STMT void (IL 0x000... ???)
[000047] ------------ | /--* CAST long <- int
[000046] ------------ | | \--* CNS_INT int 8
[000048] ------------ | /--* SUB long
[000045] ------------ | | \--* LCL_VAR long V03 tmp2
[000050] -A---------- \--* ASG long
[000049] D------N---- \--* LCL_VAR long V03 tmp2
***** BB04, stmt 7
[000067] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG------- | /--* CAST int <- long
[000063] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
[000061] *--XG------- | | | /--* IND long
[000060] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000062] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
[000057] ------------ | | | /--* CNS_INT int 63
[000058] ------------ | | | /--* AND int
[000055] ------------ | | | | | /--* CNS_INT int 1
[000056] ------------ | | | | \--* SUB int
[000054] ------------ | | | | \--* LCL_VAR int V05 tmp4
[000059] ------------ | | \--* LSH long
[000053] ------------ | | \--* CAST long <- int
[000052] ------------ | | \--* CNS_INT int 1
[000066] -A-XG------- \--* ASG int
[000065] D------N---- \--* LCL_VAR int V06 tmp5
-------------------------------------------------------------------------------------------------------------------
Return expression for call at [000004] is
[000077] ------------ /--* LCL_VAR int V06 tmp5
[000078] ---X-------- * ADD int
[000076] ---X-------- \--* CAST int <- long
[000074] ------------ | /--* CNS_INT int 6
[000075] ---X-------- \--* LSH long
[000072] ------------ | /--* CAST long <- int
[000071] ------------ | | \--* CNS_INT int 8
[000073] ---X-------- \--* DIV long
[000069] ------------ | /--* LCL_VAR long V02 tmp1
[000070] ------------ \--* SUB long
[000068] ------------ \--* LCL_VAR long V03 tmp2
Successfully inlined GetNthBitOffset:Intrinsics(long,int,int):int (63 IL bytes) (depth 1) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Program:Intrinsics(int):int' calling 'GetNthBitOffset:Intrinsics(long,int,int):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Replacing the return expression placeholder [000009] with [000078]
[000009] --C--------- * RET_EXPR int (inl return from call [000078])
Inserting the inline return expression
[000077] ------------ /--* LCL_VAR int V06 tmp5
[000078] ---X-------- * ADD int
[000076] ---X-------- \--* CAST int <- long
[000074] ------------ | /--* CNS_INT int 6
[000075] ---X-------- \--* LSH long
[000072] ------------ | /--* CAST long <- int
[000071] ------------ | | \--* CNS_INT int 8
[000073] ---X-------- \--* DIV long
[000069] ------------ | /--* LCL_VAR long V02 tmp1
[000070] ------------ \--* SUB long
[000068] ------------ \--* LCL_VAR long V03 tmp2
*************** After fgInline()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001) i
BB03 [0002] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB04 [0003] 1 1 [000..001) i
BB05 [0004] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
[000081] ------------ * STMT void (IL 0x000... ???)
[000001] ----G------- | /--* FIELD long _bits
[000080] -A--G------- \--* ASG long
[000079] D------N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000084] ------------ * STMT void (IL 0x000... ???)
[000003] ------------ | /--* LCL_VAR int V00 arg0
[000083] -A---------- \--* ASG int
[000082] D------N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000088] ------------ * STMT void (IL 0x000... ???)
[000085] ------------ | /--* CNS_INT long 0
[000087] -A---------- \--* ASG long
[000086] D------N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000092] ------------ * STMT void (IL 0x000... ???)
[000089] ------------ | /--* CNS_INT int 0
[000091] -A---------- \--* ASG int
[000090] D------N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000096] ------------ * STMT void (IL 0x000... ???)
[000093] ------------ | /--* CNS_INT int 0
[000095] -A---------- \--* ASG int
[000094] D------N---- \--* LCL_VAR int V06 tmp5
------------ BB02 [000..001), preds={} succs={BB03}
***** BB02, stmt 6
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] ------------ | /--* LCL_VAR long V02 tmp1
[000015] -A---------- \--* ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
------------ BB03 [000..001) -> BB03 (cond), preds={} succs={BB04,BB03}
***** BB03, stmt 7
[000021] ------------ * STMT void (IL 0x000... ???)
[000018] ------------ | /--* LCL_VAR int V04 tmp3
[000020] -A---------- \--* ASG int
[000019] D------N---- \--* LCL_VAR int V05 tmp4
***** BB03, stmt 8
[000031] ------------ * STMT void (IL 0x000... ???)
[000026] ---XG------- | /--* CAST int <- long
[000025] ---XG------- | | \--* HWIntrinsic long PopCount
[000024] *--XG------- | | \--* IND long
[000023] ------------ | | \--* LCL_VAR long V03 tmp2
[000027] ---XG------- | /--* SUB int
[000022] ------------ | | \--* LCL_VAR int V04 tmp3
[000030] -A-XG------- \--* ASG int
[000029] D------N---- \--* LCL_VAR int V04 tmp3
***** BB03, stmt 9
[000038] ------------ * STMT void (IL 0x000... ???)
[000034] ------------ | /--* CAST long <- int
[000033] ------------ | | \--* CNS_INT int 8
[000035] ------------ | /--* ADD long
[000032] ------------ | | \--* LCL_VAR long V03 tmp2
[000037] -A---------- \--* ASG long
[000036] D------N---- \--* LCL_VAR long V03 tmp2
***** BB03, stmt 10
[000043] ------------ * STMT void (IL 0x000... ???)
[000042] ------------ \--* JTRUE void
[000040] ------------ | /--* CNS_INT int 0
[000041] ------------ \--* GT int
[000039] ------------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001), preds={} succs={BB05}
***** BB04, stmt 11
[000051] ------------ * STMT void (IL 0x000... ???)
[000047] ------------ | /--* CAST long <- int
[000046] ------------ | | \--* CNS_INT int 8
[000048] ------------ | /--* SUB long
[000045] ------------ | | \--* LCL_VAR long V03 tmp2
[000050] -A---------- \--* ASG long
[000049] D------N---- \--* LCL_VAR long V03 tmp2
***** BB04, stmt 12
[000067] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG------- | /--* CAST int <- long
[000063] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
[000061] *--XG------- | | | /--* IND long
[000060] ------------ | | | | \--* LCL_VAR long V03 tmp2
[000062] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
[000057] ------------ | | | /--* CNS_INT int 63
[000058] ------------ | | | /--* AND int
[000055] ------------ | | | | | /--* CNS_INT int 1
[000056] ------------ | | | | \--* SUB int
[000054] ------------ | | | | \--* LCL_VAR int V05 tmp4
[000059] ------------ | | \--* LSH long
[000053] ------------ | | \--* CAST long <- int
[000052] ------------ | | \--* CNS_INT int 1
[000066] -A-XG------- \--* ASG int
[000065] D------N---- \--* LCL_VAR int V06 tmp5
------------ BB05 [???..???) (return), preds={} succs={}
***** BB05, stmt 13
[000011] ------------ * STMT void (IL ???... ???)
[000010] --C--------- \--* RETURN int
[000077] ------------ | /--* LCL_VAR int V06 tmp5
[000078] ---X-------- \--* ADD int
[000076] ---X-------- \--* CAST int <- long
[000074] ------------ | /--* CNS_INT int 6
[000075] ---X-------- \--* LSH long
[000072] ------------ | /--* CAST long <- int
[000071] ------------ | | \--* CNS_INT int 8
[000073] ---X-------- \--* DIV long
[000069] ------------ | /--* LCL_VAR long V02 tmp1
[000070] ------------ \--* SUB long
[000068] ------------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 06000006 Program:Intrinsics(int):int
[1 IL=0011 TR=000004 06000007] [aggressive inline attribute] GetNthBitOffset:Intrinsics(long,int,int):int
Budget: initialTime=111, finalTime=223, initialBudget=1110, currentBudget=1222
Budget: increased by 112 because of force inlines
Budget: initialSize=518, finalSize=518
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001) i
BB03 [0002] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB04 [0003] 1 1 [000..001) i
BB05 [0004] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
; V02 tmp1 long
; V03 tmp2 long
; V04 tmp3 int
; V05 tmp4 int
; V06 tmp5 int
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
; V02 tmp1 long
; V03 tmp2 long
; V04 tmp3 int
; V05 tmp4 int
; V06 tmp5 int
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'Program:Intrinsics(int):int'
fgMorphTree BB01, stmt 1 (before)
[000001] ----G------- /--* FIELD long _bits
[000080] -A--G------- * ASG long
[000079] D------N---- \--* LCL_VAR long V02 tmp1
fgMorphTree BB01, stmt 1 (after)
[000001] x---G+------ /--* IND long
[000098] -----+------ | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits]
[000080] -A--G+------ * ASG long
[000079] D----+-N---- \--* LCL_VAR long V02 tmp1
fgMorphTree BB01, stmt 2 (before)
[000003] ------------ /--* LCL_VAR int V00 arg0
[000083] -A---------- * ASG int
[000082] D------N---- \--* LCL_VAR int V04 tmp3
GenTreeNode creates assertion:
[000083] -A---------- * ASG int
In BB01 New Local Copy Assertion: V04 == V00 index=#01, mask=0000000000000001
fgMorphTree BB01, stmt 3 (before)
[000085] ------------ /--* CNS_INT long 0
[000087] -A---------- * ASG long
[000086] D------N---- \--* LCL_VAR long V03 tmp2
GenTreeNode creates assertion:
[000087] -A---------- * ASG long
In BB01 New Local Constant Assertion: V03 == 0 index=#02, mask=0000000000000002
fgMorphTree BB01, stmt 4 (before)
[000089] ------------ /--* CNS_INT int 0
[000091] -A---------- * ASG int
[000090] D------N---- \--* LCL_VAR int V05 tmp4
GenTreeNode creates assertion:
[000091] -A---------- * ASG int
In BB01 New Local Constant Assertion: V05 == 0 index=#03, mask=0000000000000004
fgMorphTree BB01, stmt 5 (before)
[000093] ------------ /--* CNS_INT int 0
[000095] -A---------- * ASG int
[000094] D------N---- \--* LCL_VAR int V06 tmp5
GenTreeNode creates assertion:
[000095] -A---------- * ASG int
In BB01 New Local Constant Assertion: V06 == 0 index=#04, mask=0000000000000008
Morphing BB02 of 'Program:Intrinsics(int):int'
fgMorphTree BB02, stmt 6 (before)
[000013] ------------ /--* LCL_VAR long V02 tmp1
[000015] -A---------- * ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
GenTreeNode creates assertion:
[000015] -A---------- * ASG long
In BB02 New Local Copy Assertion: V03 == V02 index=#01, mask=0000000000000001
Morphing BB03 of 'Program:Intrinsics(int):int'
fgMorphTree BB03, stmt 7 (before)
[000018] ------------ /--* LCL_VAR int V04 tmp3
[000020] -A---------- * ASG int
[000019] D------N---- \--* LCL_VAR int V05 tmp4
GenTreeNode creates assertion:
[000020] -A---------- * ASG int
In BB03 New Local Copy Assertion: V05 == V04 index=#01, mask=0000000000000001
fgMorphTree BB03, stmt 8 (before)
[000026] ---XG------- /--* CAST int <- long
[000025] ---XG------- | \--* HWIntrinsic long PopCount
[000024] *--XG------- | \--* IND long
[000023] ------------ | \--* LCL_VAR long V03 tmp2
[000027] ---XG------- /--* SUB int
[000022] ------------ | \--* LCL_VAR int V04 tmp3
[000030] -A-XG------- * ASG int
[000029] D------N---- \--* LCL_VAR int V04 tmp3
The assignment [000030] using V05 removes: Copy Assertion: V05 == V04
fgMorphTree BB03, stmt 9 (before)
[000034] ------------ /--* CAST long <- int
[000033] ------------ | \--* CNS_INT int 8
[000035] ------------ /--* ADD long
[000032] ------------ | \--* LCL_VAR long V03 tmp2
[000037] -A---------- * ASG long
[000036] D------N---- \--* LCL_VAR long V03 tmp2
Folding long operator with constant nodes into a constant:
[000034] ------------ * CAST long <- int
[000033] -----+------ \--* CNS_INT int 8
Bashed to long constant:
[000034] ------------ * CNS_INT long 8
fgMorphTree BB03, stmt 9 (after)
[000034] -----+------ /--* CNS_INT long 8
[000035] -----+------ /--* ADD long
[000032] -----+------ | \--* LCL_VAR long V03 tmp2
[000037] -A---+------ * ASG long
[000036] D----+-N---- \--* LCL_VAR long V03 tmp2
fgMorphTree BB03, stmt 10 (before)
[000042] ------------ * JTRUE void
[000040] ------------ | /--* CNS_INT int 0
[000041] ------------ \--* GT int
[000039] ------------ \--* LCL_VAR int V04 tmp3
Morphing BB04 of 'Program:Intrinsics(int):int'
fgMorphTree BB04, stmt 11 (before)
[000047] ------------ /--* CAST long <- int
[000046] ------------ | \--* CNS_INT int 8
[000048] ------------ /--* SUB long
[000045] ------------ | \--* LCL_VAR long V03 tmp2
[000050] -A---------- * ASG long
[000049] D------N---- \--* LCL_VAR long V03 tmp2
Folding long operator with constant nodes into a constant:
[000047] ------------ * CAST long <- int
[000046] -----+------ \--* CNS_INT int 8
Bashed to long constant:
[000047] ------------ * CNS_INT long 8
fgMorphTree BB04, stmt 11 (after)
[000047] -----+------ /--* CNS_INT long -8
[000048] -----+------ /--* ADD long
[000045] -----+------ | \--* LCL_VAR long V03 tmp2
[000050] -A---+------ * ASG long
[000049] D----+-N---- \--* LCL_VAR long V03 tmp2
fgMorphTree BB04, stmt 12 (before)
[000064] ---XG------- /--* CAST int <- long
[000063] ---XG------- | \--* HWIntrinsic long TrailingZeroCount
[000061] *--XG------- | | /--* IND long
[000060] ------------ | | | \--* LCL_VAR long V03 tmp2
[000062] ---XG------- | \--* HWIntrinsic long ParallelBitDeposit
[000057] ------------ | | /--* CNS_INT int 63
[000058] ------------ | | /--* AND int
[000055] ------------ | | | | /--* CNS_INT int 1
[000056] ------------ | | | \--* SUB int
[000054] ------------ | | | \--* LCL_VAR int V05 tmp4
[000059] ------------ | \--* LSH long
[000053] ------------ | \--* CAST long <- int
[000052] ------------ | \--* CNS_INT int 1
[000066] -A-XG------- * ASG int
[000065] D------N---- \--* LCL_VAR int V06 tmp5
Folding long operator with constant nodes into a constant:
[000053] ------------ * CAST long <- int
[000052] -----+------ \--* CNS_INT int 1
Bashed to long constant:
[000053] ------------ * CNS_INT long 1
GenTreeNode creates assertion:
[000066] -A-XG------- * ASG int
In BB04 New Local Subrange Assertion: V06 in [-2147483648..2147483647] index=#01, mask=0000000000000001
fgMorphTree BB04, stmt 12 (after)
[000064] ---XG+------ /--* CAST int <- long
[000063] ---XG+------ | \--* HWIntrinsic long TrailingZeroCount
[000061] *--XG+------ | | /--* IND long
[000060] -----+------ | | | \--* LCL_VAR long V03 tmp2
[000062] ---XG+------ | \--* HWIntrinsic long ParallelBitDeposit
[000057] -----+------ | | /--* CNS_INT int 63
[000058] -----+------ | | /--* AND int
[000055] -----+------ | | | | /--* CNS_INT int -1
[000056] -----+------ | | | \--* ADD int
[000054] -----+------ | | | \--* LCL_VAR int V05 tmp4
[000059] -----+------ | \--* LSH long
[000053] -----+------ | \--* CNS_INT long 1
[000066] -A-XG+------ * ASG int
[000065] D----+-N---- \--* LCL_VAR int V06 tmp5
Morphing BB05 of 'Program:Intrinsics(int):int'
fgMorphTree BB05, stmt 13 (before)
[000010] --C--------- * RETURN int
[000077] ------------ | /--* LCL_VAR int V06 tmp5
[000078] ---X-------- \--* ADD int
[000076] ---X-------- \--* CAST int <- long
[000074] ------------ | /--* CNS_INT int 6
[000075] ---X-------- \--* LSH long
[000072] ------------ | /--* CAST long <- int
[000071] ------------ | | \--* CNS_INT int 8
[000073] ---X-------- \--* DIV long
[000069] ------------ | /--* LCL_VAR long V02 tmp1
[000070] ------------ \--* SUB long
[000068] ------------ \--* LCL_VAR long V03 tmp2
Folding long operator with constant nodes into a constant:
[000072] ------------ * CAST long <- int
[000071] ------------ \--* CNS_INT int 8
Bashed to long constant:
[000072] ------------ * CNS_INT long 8
fgMorphTree BB05, stmt 13 (after)
[000010] -----+------ * RETURN int
[000077] -----+------ | /--* LCL_VAR int V06 tmp5
[000078] -----+------ \--* ADD int
[000074] -----+------ | /--* CNS_INT int 6
[000075] -----+------ \--* LSH int
[000099] -----+------ \--* CAST int <- long
[000072] -----+------ | /--* CNS_INT long 8
[000073] -----+------ \--* DIV long
[000069] -----+------ | /--* LCL_VAR long V02 tmp1
[000070] -----+------ \--* SUB long
[000068] -----+------ \--* LCL_VAR long V03 tmp2
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001) i
BB03 [0002] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB04 [0003] 1 1 [000..001) i
BB05 [0004] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001) i
BB03 [0002] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB04 [0003] 1 1 [000..001) i
BB05 [0004] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001) i
BB03 [0002] 2 BB02,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [000..001) i
BB05 [0004] 1 BB04 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeEdgeWeights()
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001) i
BB03 [0002] 2 BB02,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [000..001) i
BB05 [0004] 1 BB04 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights
*************** In fgCreateFunclets()
After fgCreateFunclets()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001) i
BB03 [0002] 2 BB02,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [000..001) i
BB05 [0004] 1 BB04 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001) i
BB03 [0002] 2 BB02,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [000..001) i
BB05 [0004] 1 BB04 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB01 and BB02:
*************** In fgDebugCheckBBlist
Compacting blocks BB04 and BB05:
*************** In fgDebugCheckBBlist
After updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()
Initial BasicBlocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB04 to BB03
*************** After renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 3, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB01 BB02
BB03 : BB01 BB02 BB03
After computing reachability:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
BB02: BB02 BB01
BB03: BB03 BB02 BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB02
BB02 : BB03
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
[000081] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000098] -----+------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits]
[000080] -A--G+------ \--* ASG long
[000079] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000084] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000083] -A---+------ \--* ASG int
[000082] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000088] ------------ * STMT void (IL 0x000... ???)
[000085] -----+------ | /--* CNS_INT long 0
[000087] -A---+------ \--* ASG long
[000086] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000092] ------------ * STMT void (IL 0x000... ???)
[000089] -----+------ | /--* CNS_INT int 0
[000091] -A---+------ \--* ASG int
[000090] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000096] ------------ * STMT void (IL 0x000... ???)
[000093] -----+------ | /--* CNS_INT int 0
[000095] -A---+------ \--* ASG int
[000094] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB01, stmt 6
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 7
[000021] ------------ * STMT void (IL 0x000... ???)
[000018] -----+------ | /--* LCL_VAR int V04 tmp3
[000020] -A---+------ \--* ASG int
[000019] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB02, stmt 8
[000031] ------------ * STMT void (IL 0x000... ???)
[000026] ---XG+------ | /--* CAST int <- long
[000025] ---XG+------ | | \--* HWIntrinsic long PopCount
[000024] *--XG+------ | | \--* IND long
[000023] -----+------ | | \--* LCL_VAR long V03 tmp2
[000027] ---XG+------ | /--* SUB int
[000022] -----+------ | | \--* LCL_VAR int V04 tmp3
[000030] -A-XG+------ \--* ASG int
[000029] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 9
[000038] ------------ * STMT void (IL 0x000... ???)
[000034] -----+------ | /--* CNS_INT long 8
[000035] -----+------ | /--* ADD long
[000032] -----+------ | | \--* LCL_VAR long V03 tmp2
[000037] -A---+------ \--* ASG long
[000036] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
[000043] ------------ * STMT void (IL 0x000... ???)
[000042] -----+------ \--* JTRUE void
[000040] -----+------ | /--* CNS_INT int 0
[000041] J----+-N---- \--* GT int
[000039] -----+------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 11
[000051] ------------ * STMT void (IL 0x000... ???)
[000047] -----+------ | /--* CNS_INT long -8
[000048] -----+------ | /--* ADD long
[000045] -----+------ | | \--* LCL_VAR long V03 tmp2
[000050] -A---+------ \--* ASG long
[000049] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB03, stmt 12
[000067] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG+------ | /--* CAST int <- long
[000063] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000061] *--XG+------ | | | /--* IND long
[000060] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000062] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000057] -----+------ | | | /--* CNS_INT int 63
[000058] -----+------ | | | /--* AND int
[000055] -----+------ | | | | | /--* CNS_INT int -1
[000056] -----+------ | | | | \--* ADD int
[000054] -----+------ | | | | \--* LCL_VAR int V05 tmp4
[000059] -----+------ | | \--* LSH long
[000053] -----+------ | | \--* CNS_INT long 1
[000066] -A-XG+------ \--* ASG int
[000065] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB03, stmt 13
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000077] -----+------ | /--* LCL_VAR int V06 tmp5
[000078] -----+------ \--* ADD int
[000074] -----+------ | /--* CNS_INT int 6
[000075] -----+------ \--* LSH int
[000099] -----+------ \--* CAST int <- long
[000072] -----+------ | /--* CNS_INT long 8
[000073] -----+------ \--* DIV long
[000069] -----+------ | /--* LCL_VAR long V02 tmp1
[000070] -----+------ \--* SUB long
[000068] -----+------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
[000081] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000098] -----+------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits]
[000080] -A--G+------ \--* ASG long
[000079] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000084] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000083] -A---+------ \--* ASG int
[000082] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000088] ------------ * STMT void (IL 0x000... ???)
[000085] -----+------ | /--* CNS_INT long 0
[000087] -A---+------ \--* ASG long
[000086] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000092] ------------ * STMT void (IL 0x000... ???)
[000089] -----+------ | /--* CNS_INT int 0
[000091] -A---+------ \--* ASG int
[000090] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000096] ------------ * STMT void (IL 0x000... ???)
[000093] -----+------ | /--* CNS_INT int 0
[000095] -A---+------ \--* ASG int
[000094] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB01, stmt 6
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 7
[000021] ------------ * STMT void (IL 0x000... ???)
[000018] -----+------ | /--* LCL_VAR int V04 tmp3
[000020] -A---+------ \--* ASG int
[000019] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB02, stmt 8
[000031] ------------ * STMT void (IL 0x000... ???)
[000026] ---XG+------ | /--* CAST int <- long
[000025] ---XG+------ | | \--* HWIntrinsic long PopCount
[000024] *--XG+------ | | \--* IND long
[000023] -----+------ | | \--* LCL_VAR long V03 tmp2
[000027] ---XG+------ | /--* SUB int
[000022] -----+------ | | \--* LCL_VAR int V04 tmp3
[000030] -A-XG+------ \--* ASG int
[000029] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 9
[000038] ------------ * STMT void (IL 0x000... ???)
[000034] -----+------ | /--* CNS_INT long 8
[000035] -----+------ | /--* ADD long
[000032] -----+------ | | \--* LCL_VAR long V03 tmp2
[000037] -A---+------ \--* ASG long
[000036] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
[000043] ------------ * STMT void (IL 0x000... ???)
[000042] -----+------ \--* JTRUE void
[000040] -----+------ | /--* CNS_INT int 0
[000041] J----+-N---- \--* GT int
[000039] -----+------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 11
[000051] ------------ * STMT void (IL 0x000... ???)
[000047] -----+------ | /--* CNS_INT long -8
[000048] -----+------ | /--* ADD long
[000045] -----+------ | | \--* LCL_VAR long V03 tmp2
[000050] -A---+------ \--* ASG long
[000049] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB03, stmt 12
[000067] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG+------ | /--* CAST int <- long
[000063] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000061] *--XG+------ | | | /--* IND long
[000060] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000062] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000057] -----+------ | | | /--* CNS_INT int 63
[000058] -----+------ | | | /--* AND int
[000055] -----+------ | | | | | /--* CNS_INT int -1
[000056] -----+------ | | | | \--* ADD int
[000054] -----+------ | | | | \--* LCL_VAR int V05 tmp4
[000059] -----+------ | | \--* LSH long
[000053] -----+------ | | \--* CNS_INT long 1
[000066] -A-XG+------ \--* ASG int
[000065] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB03, stmt 13
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000077] -----+------ | /--* LCL_VAR int V06 tmp5
[000078] -----+------ \--* ADD int
[000074] -----+------ | /--* CNS_INT int 6
[000075] -----+------ \--* LSH int
[000099] -----+------ \--* CAST int <- long
[000072] -----+------ | /--* CNS_INT long 8
[000073] -----+------ \--* DIV long
[000069] -----+------ | /--* LCL_VAR long V02 tmp1
[000070] -----+------ \--* SUB long
[000068] -----+------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optOptimizeLoops()
*************** In fgDebugCheckBBlist
*************** In optFindNaturalLoops()
Recorded loop L00, from BB02 to BB02 (Head=BB01, Entry=BB02, ExitCnt=1 at BB02)
Final natural loop table:
L00, from BB02 to BB02 (Head=BB01, Entry=BB02, ExitCnt=1 at BB02)
Marking loop L01
BB02(wt=4 )
Found a total of 1 loops.
After loop weight marking:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** In optCloneLoops()
Blocks/Trees at start of phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
[000081] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000098] -----+------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits]
[000080] -A--G+------ \--* ASG long
[000079] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000084] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000083] -A---+------ \--* ASG int
[000082] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000088] ------------ * STMT void (IL 0x000... ???)
[000085] -----+------ | /--* CNS_INT long 0
[000087] -A---+------ \--* ASG long
[000086] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000092] ------------ * STMT void (IL 0x000... ???)
[000089] -----+------ | /--* CNS_INT int 0
[000091] -A---+------ \--* ASG int
[000090] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000096] ------------ * STMT void (IL 0x000... ???)
[000093] -----+------ | /--* CNS_INT int 0
[000095] -A---+------ \--* ASG int
[000094] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB01, stmt 6
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 7
[000021] ------------ * STMT void (IL 0x000... ???)
[000018] -----+------ | /--* LCL_VAR int V04 tmp3
[000020] -A---+------ \--* ASG int
[000019] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB02, stmt 8
[000031] ------------ * STMT void (IL 0x000... ???)
[000026] ---XG+------ | /--* CAST int <- long
[000025] ---XG+------ | | \--* HWIntrinsic long PopCount
[000024] *--XG+------ | | \--* IND long
[000023] -----+------ | | \--* LCL_VAR long V03 tmp2
[000027] ---XG+------ | /--* SUB int
[000022] -----+------ | | \--* LCL_VAR int V04 tmp3
[000030] -A-XG+------ \--* ASG int
[000029] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 9
[000038] ------------ * STMT void (IL 0x000... ???)
[000034] -----+------ | /--* CNS_INT long 8
[000035] -----+------ | /--* ADD long
[000032] -----+------ | | \--* LCL_VAR long V03 tmp2
[000037] -A---+------ \--* ASG long
[000036] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
[000043] ------------ * STMT void (IL 0x000... ???)
[000042] -----+------ \--* JTRUE void
[000040] -----+------ | /--* CNS_INT int 0
[000041] J----+-N---- \--* GT int
[000039] -----+------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 11
[000051] ------------ * STMT void (IL 0x000... ???)
[000047] -----+------ | /--* CNS_INT long -8
[000048] -----+------ | /--* ADD long
[000045] -----+------ | | \--* LCL_VAR long V03 tmp2
[000050] -A---+------ \--* ASG long
[000049] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB03, stmt 12
[000067] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG+------ | /--* CAST int <- long
[000063] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000061] *--XG+------ | | | /--* IND long
[000060] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000062] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000057] -----+------ | | | /--* CNS_INT int 63
[000058] -----+------ | | | /--* AND int
[000055] -----+------ | | | | | /--* CNS_INT int -1
[000056] -----+------ | | | | \--* ADD int
[000054] -----+------ | | | | \--* LCL_VAR int V05 tmp4
[000059] -----+------ | | \--* LSH long
[000053] -----+------ | | \--* CNS_INT long 1
[000066] -A-XG+------ \--* ASG int
[000065] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB03, stmt 13
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000077] -----+------ | /--* LCL_VAR int V06 tmp5
[000078] -----+------ \--* ADD int
[000074] -----+------ | /--* CNS_INT int 6
[000075] -----+------ \--* LSH int
[000099] -----+------ \--* CAST int <- long
[000072] -----+------ | /--* CNS_INT long 8
[000073] -----+------ \--* DIV long
[000069] -----+------ | /--* LCL_VAR long V02 tmp1
[000070] -----+------ \--* SUB long
[000068] -----+------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
Considering loop 0 to clone for optimizations.
> No iter flag on loop 0.
------------------------------------------------------------
After loop cloning:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
[000081] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000098] -----+------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits]
[000080] -A--G+------ \--* ASG long
[000079] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000084] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000083] -A---+------ \--* ASG int
[000082] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000088] ------------ * STMT void (IL 0x000... ???)
[000085] -----+------ | /--* CNS_INT long 0
[000087] -A---+------ \--* ASG long
[000086] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000092] ------------ * STMT void (IL 0x000... ???)
[000089] -----+------ | /--* CNS_INT int 0
[000091] -A---+------ \--* ASG int
[000090] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000096] ------------ * STMT void (IL 0x000... ???)
[000093] -----+------ | /--* CNS_INT int 0
[000095] -A---+------ \--* ASG int
[000094] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB01, stmt 6
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 7
[000021] ------------ * STMT void (IL 0x000... ???)
[000018] -----+------ | /--* LCL_VAR int V04 tmp3
[000020] -A---+------ \--* ASG int
[000019] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB02, stmt 8
[000031] ------------ * STMT void (IL 0x000... ???)
[000026] ---XG+------ | /--* CAST int <- long
[000025] ---XG+------ | | \--* HWIntrinsic long PopCount
[000024] *--XG+------ | | \--* IND long
[000023] -----+------ | | \--* LCL_VAR long V03 tmp2
[000027] ---XG+------ | /--* SUB int
[000022] -----+------ | | \--* LCL_VAR int V04 tmp3
[000030] -A-XG+------ \--* ASG int
[000029] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 9
[000038] ------------ * STMT void (IL 0x000... ???)
[000034] -----+------ | /--* CNS_INT long 8
[000035] -----+------ | /--* ADD long
[000032] -----+------ | | \--* LCL_VAR long V03 tmp2
[000037] -A---+------ \--* ASG long
[000036] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
[000043] ------------ * STMT void (IL 0x000... ???)
[000042] -----+------ \--* JTRUE void
[000040] -----+------ | /--* CNS_INT int 0
[000041] J----+-N---- \--* GT int
[000039] -----+------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 11
[000051] ------------ * STMT void (IL 0x000... ???)
[000047] -----+------ | /--* CNS_INT long -8
[000048] -----+------ | /--* ADD long
[000045] -----+------ | | \--* LCL_VAR long V03 tmp2
[000050] -A---+------ \--* ASG long
[000049] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB03, stmt 12
[000067] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG+------ | /--* CAST int <- long
[000063] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000061] *--XG+------ | | | /--* IND long
[000060] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000062] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000057] -----+------ | | | /--* CNS_INT int 63
[000058] -----+------ | | | /--* AND int
[000055] -----+------ | | | | | /--* CNS_INT int -1
[000056] -----+------ | | | | \--* ADD int
[000054] -----+------ | | | | \--* LCL_VAR int V05 tmp4
[000059] -----+------ | | \--* LSH long
[000053] -----+------ | | \--* CNS_INT long 1
[000066] -A-XG+------ \--* ASG int
[000065] D----+-N---- \--* LCL_VAR int V06 tmp5
***** BB03, stmt 13
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000077] -----+------ | /--* LCL_VAR int V06 tmp5
[000078] -----+------ \--* ADD int
[000074] -----+------ | /--* CNS_INT int 6
[000075] -----+------ \--* LSH int
[000099] -----+------ \--* CAST int <- long
[000072] -----+------ | /--* CNS_INT long 8
[000073] -----+------ \--* DIV long
[000069] -----+------ | /--* LCL_VAR long V02 tmp1
[000070] -----+------ \--* SUB long
[000068] -----+------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** In optUnrollLoops()
*************** In fgDebugCheckBBlist
*************** In lvaMarkLocalVars()
*** marking local variables in block BB01 (weight=1 )
[000081] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000098] -----+------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits]
[000080] -A--G+------ \--* ASG long
[000079] D----+-N---- \--* LCL_VAR long V02 tmp1
New refCnts for V02: refCnt = 1, refCntWtd = 2
[000084] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000083] -A---+------ \--* ASG int
[000082] D----+-N---- \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 1, refCntWtd = 1
[000088] ------------ * STMT void (IL 0x000... ???)
[000085] -----+------ | /--* CNS_INT long 0
[000087] -A---+------ \--* ASG long
[000086] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 1, refCntWtd = 1
[000092] ------------ * STMT void (IL 0x000... ???)
[000089] -----+------ | /--* CNS_INT int 0
[000091] -A---+------ \--* ASG int
[000090] D----+-N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 1, refCntWtd = 1
[000096] ------------ * STMT void (IL 0x000... ???)
[000093] -----+------ | /--* CNS_INT int 0
[000095] -A---+------ \--* ASG int
[000094] D----+-N---- \--* LCL_VAR int V06 tmp5
New refCnts for V06: refCnt = 1, refCntWtd = 1
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 2, refCntWtd = 4
*** marking local variables in block BB02 (weight=4 )
[000021] ------------ * STMT void (IL 0x000... ???)
[000018] -----+------ | /--* LCL_VAR int V04 tmp3
[000020] -A---+------ \--* ASG int
[000019] D----+-N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 2, refCntWtd = 5
New refCnts for V04: refCnt = 2, refCntWtd = 10
[000031] ------------ * STMT void (IL 0x000... ???)
[000026] ---XG+------ | /--* CAST int <- long
[000025] ---XG+------ | | \--* HWIntrinsic long PopCount
[000024] *--XG+------ | | \--* IND long
[000023] -----+------ | | \--* LCL_VAR long V03 tmp2
[000027] ---XG+------ | /--* SUB int
[000022] -----+------ | | \--* LCL_VAR int V04 tmp3
[000030] -A-XG+------ \--* ASG int
[000029] D----+-N---- \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 3, refCntWtd = 18
New refCnts for V04: refCnt = 4, refCntWtd = 26
New refCnts for V03: refCnt = 3, refCntWtd = 6
[000038] ------------ * STMT void (IL 0x000... ???)
[000034] -----+------ | /--* CNS_INT long 8
[000035] -----+------ | /--* ADD long
[000032] -----+------ | | \--* LCL_VAR long V03 tmp2
[000037] -A---+------ \--* ASG long
[000036] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 4, refCntWtd = 10
New refCnts for V03: refCnt = 5, refCntWtd = 14
[000043] ------------ * STMT void (IL 0x000... ???)
[000042] -----+------ \--* JTRUE void
[000040] -----+------ | /--* CNS_INT int 0
[000041] J----+-N---- \--* GT int
[000039] -----+------ \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 5, refCntWtd = 34
*** marking local variables in block BB03 (weight=1 )
[000051] ------------ * STMT void (IL 0x000... ???)
[000047] -----+------ | /--* CNS_INT long -8
[000048] -----+------ | /--* ADD long
[000045] -----+------ | | \--* LCL_VAR long V03 tmp2
[000050] -A---+------ \--* ASG long
[000049] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 6, refCntWtd = 15
New refCnts for V03: refCnt = 7, refCntWtd = 16
[000067] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG+------ | /--* CAST int <- long
[000063] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000061] *--XG+------ | | | /--* IND long
[000060] -----+------ | | | | \--* LCL_VAR long V03 tmp2
[000062] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000057] -----+------ | | | /--* CNS_INT int 63
[000058] -----+------ | | | /--* AND int
[000055] -----+------ | | | | | /--* CNS_INT int -1
[000056] -----+------ | | | | \--* ADD int
[000054] -----+------ | | | | \--* LCL_VAR int V05 tmp4
[000059] -----+------ | | \--* LSH long
[000053] -----+------ | | \--* CNS_INT long 1
[000066] -A-XG+------ \--* ASG int
[000065] D----+-N---- \--* LCL_VAR int V06 tmp5
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 3, refCntWtd = 6
New refCnts for V03: refCnt = 8, refCntWtd = 17
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000077] -----+------ | /--* LCL_VAR int V06 tmp5
[000078] -----+------ \--* ADD int
[000074] -----+------ | /--* CNS_INT int 6
[000075] -----+------ \--* LSH int
[000099] -----+------ \--* CAST int <- long
[000072] -----+------ | /--* CNS_INT long 8
[000073] -----+------ \--* DIV long
[000069] -----+------ | /--* LCL_VAR long V02 tmp1
[000070] -----+------ \--* SUB long
[000068] -----+------ \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 9, refCntWtd = 18
New refCnts for V02: refCnt = 3, refCntWtd = 6
New refCnts for V06: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
*************** In optAddCopies()
refCnt table for 'Intrinsics':
V04 tmp3 [ int]: refCnt = 5, refCntWtd = 34
V03 tmp2 [ long]: refCnt = 9, refCntWtd = 18
V02 tmp1 [ long]: refCnt = 3, refCntWtd = 6
V05 tmp4 [ int]: refCnt = 3, refCntWtd = 6
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3
V06 tmp5 [ int]: refCnt = 3, refCntWtd = 3
V01 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
fgMarkLoopHead: Checking loop head block BB02: no guaranteed callsite exits, marking method as fully interruptible
The biggest BB has 14 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
( 5, 12) [000081] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long
N001 ( 3, 10) [000098] ------------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits]
N004 ( 5, 12) [000080] -A--G---R--- \--* ASG long
N003 ( 1, 1) [000079] D------N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
( 1, 3) [000084] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0
N003 ( 1, 3) [000083] -A------R--- \--* ASG int
N002 ( 1, 1) [000082] D------N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
( 1, 3) [000088] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000085] ------------ | /--* CNS_INT long 0
N003 ( 1, 3) [000087] -A------R--- \--* ASG long
N002 ( 1, 1) [000086] D------N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
( 1, 3) [000092] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000089] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000091] -A------R--- \--* ASG int
N002 ( 1, 1) [000090] D------N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
( 1, 3) [000096] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000093] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000095] -A------R--- \--* ASG int
N002 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V06 tmp5
***** BB01, stmt 6
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1
N003 ( 1, 3) [000015] -A------R--- \--* ASG long
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 7
( 1, 3) [000021] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000018] ------------ | /--* LCL_VAR int V04 tmp3
N003 ( 1, 3) [000020] -A------R--- \--* ASG int
N002 ( 1, 1) [000019] D------N---- \--* LCL_VAR int V05 tmp4
***** BB02, stmt 8
( 7, 7) [000031] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000026] ---XG------- | /--* CAST int <- long
N004 ( 4, 3) [000025] ---XG------- | | \--* HWIntrinsic long PopCount
N003 ( 3, 2) [000024] *--XG------- | | \--* IND long
N002 ( 1, 1) [000023] ------------ | | \--* LCL_VAR long V03 tmp2
N006 ( 7, 7) [000027] ---XG------- | /--* SUB int
N001 ( 1, 1) [000022] ------------ | | \--* LCL_VAR int V04 tmp3
N008 ( 7, 7) [000030] -A-XG---R--- \--* ASG int
N007 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 9
( 3, 3) [000038] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8
N003 ( 3, 3) [000035] ------------ | /--* ADD long
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR long V03 tmp2
N005 ( 3, 3) [000037] -A------R--- \--* ASG long
N004 ( 1, 1) [000036] D------N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
( 5, 5) [000043] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000042] ------------ \--* JTRUE void
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000041] J------N---- \--* GT int
N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 11
( 3, 3) [000051] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000047] ------------ | /--* CNS_INT long -8
N003 ( 3, 3) [000048] ------------ | /--* ADD long
N001 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2
N005 ( 3, 3) [000050] -A------R--- \--* ASG long
N004 ( 1, 1) [000049] D------N---- \--* LCL_VAR long V03 tmp2
***** BB03, stmt 12
( 16, 13) [000067] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000064] ---XG------- | /--* CAST int <- long
N011 ( 15, 11) [000063] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
N009 ( 3, 2) [000061] *--XG------- | | | /--* IND long
N008 ( 1, 1) [000060] ------------ | | | | \--* LCL_VAR long V03 tmp2
N010 ( 14, 10) [000062] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
N004 ( 1, 1) [000057] ------------ | | | /--* CNS_INT int 63
N005 ( 5, 5) [000058] ------------ | | | /--* AND int
N002 ( 1, 1) [000055] ------------ | | | | | /--* CNS_INT int -1
N003 ( 3, 3) [000056] ------------ | | | | \--* ADD int
N001 ( 1, 1) [000054] ------------ | | | | \--* LCL_VAR int V05 tmp4
N007 ( 10, 7) [000059] --------R--- | | \--* LSH long
N006 ( 1, 1) [000053] ------------ | | \--* CNS_INT long 1
N014 ( 16, 13) [000066] -A-XG---R--- \--* ASG int
N013 ( 1, 1) [000065] D------N---- \--* LCL_VAR int V06 tmp5
***** BB03, stmt 13
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int
N009 ( 1, 1) [000077] ------------ | /--* LCL_VAR int V06 tmp5
N010 ( 29, 13) [000078] ------------ \--* ADD int
N007 ( 1, 1) [000074] ------------ | /--* CNS_INT int 6
N008 ( 27, 11) [000075] ------------ \--* LSH int
N006 ( 25, 9) [000099] ------------ \--* CAST int <- long
N004 ( 1, 1) [000072] ------------ | /--* CNS_INT long 8
N005 ( 24, 7) [000073] ------------ \--* DIV long
N002 ( 1, 1) [000069] ------------ | /--* LCL_VAR long V02 tmp1
N003 ( 3, 3) [000070] ------------ \--* SUB long
N001 ( 1, 1) [000068] ------------ \--* LCL_VAR long V03 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 4.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
*************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...)
*************** In SsaBuilder::InsertPhiFunctions()
*************** In fgLocalVarLiveness()
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={ V00 } + ByrefExposed + GcHeap
DEF(5)={V04 V03 V02 V05 V06}
BB02 USE(2)={V04 V03 } + ByrefExposed + GcHeap
DEF(3)={V04 V03 V05}
BB03 USE(3)={V03 V02 V05 } + ByrefExposed + GcHeap
DEF(2)={V03 V06}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={ V00} + ByrefExposed + GcHeap
OUT(3)={V04 V03 V02 } + ByrefExposed + GcHeap
BB02 IN (3)={V04 V03 V02 } + ByrefExposed + GcHeap
OUT(4)={V04 V03 V02 V05} + ByrefExposed + GcHeap
BB03 IN (3)={V03 V02 V05} + ByrefExposed + GcHeap
OUT(0)={ }
top level assign
removing stmt with no side effects
Removing statement [000096] in BB01 as useless:
( 1, 3) [000096] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000093] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000095] -A------R--- \--* ASG int
N002 ( 1, 1) [000094] D------N---- \--* LCL_VAR int V06 tmp5
New refCnts for V06: refCnt = 2, refCntWtd = 2
top level assign
removing stmt with no side effects
Removing statement [000092] in BB01 as useless:
( 1, 3) [000092] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000089] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000091] -A------R--- \--* ASG int
N002 ( 1, 1) [000090] D------N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 2, refCntWtd = 5
top level assign
removing stmt with no side effects
Removing statement [000088] in BB01 as useless:
( 1, 3) [000088] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000085] ------------ | /--* CNS_INT long 0
N003 ( 1, 3) [000087] -A------R--- \--* ASG long
N002 ( 1, 1) [000086] D------N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 8, refCntWtd = 17
In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal)
Inserting phi functions:
Inserting phi definition for V04 at start of BB02.
Inserting phi definition for V03 at start of BB02.
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
( 5, 12) [000081] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long
N001 ( 3, 10) [000098] ------------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits]
N004 ( 5, 12) [000080] -A--G---R--- \--* ASG long
N003 ( 1, 1) [000079] D------N---- \--* LCL_VAR long V02 tmp1 d:2
***** BB01, stmt 2
( 1, 3) [000084] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use)
N003 ( 1, 3) [000083] -A------R--- \--* ASG int
N002 ( 1, 1) [000082] D------N---- \--* LCL_VAR int V04 tmp3 d:2
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2
N003 ( 1, 3) [000015] -A------R--- \--* ASG long
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 4
( 2, 3) [000108] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000106] ------------ | * PHI long
N001 ( 0, 0) [000113] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000109] ------------ | \--* PHI_ARG long V03 tmp2 u:2
N007 ( 2, 3) [000107] -A------R--- \--* ASG long
N006 ( 1, 1) [000105] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 5
( 2, 3) [000104] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000102] ------------ | * PHI int
N001 ( 0, 0) [000115] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000111] ------------ | \--* PHI_ARG int V04 tmp3 u:2
N007 ( 2, 3) [000103] -A------R--- \--* ASG int
N006 ( 1, 1) [000101] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 6
( 1, 3) [000021] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000018] ------------ | /--* LCL_VAR int V04 tmp3 u:3
N003 ( 1, 3) [000020] -A------R--- \--* ASG int
N002 ( 1, 1) [000019] D------N---- \--* LCL_VAR int V05 tmp4 d:2
***** BB02, stmt 7
( 7, 7) [000031] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000026] ---XG------- | /--* CAST int <- long
N004 ( 4, 3) [000025] ---XG------- | | \--* HWIntrinsic long PopCount
N003 ( 3, 2) [000024] *--XG------- | | \--* IND long
N002 ( 1, 1) [000023] ------------ | | \--* LCL_VAR long V03 tmp2 u:3
N006 ( 7, 7) [000027] ---XG------- | /--* SUB int
N001 ( 1, 1) [000022] ------------ | | \--* LCL_VAR int V04 tmp3 u:3 (last use)
N008 ( 7, 7) [000030] -A-XG---R--- \--* ASG int
N007 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V04 tmp3 d:4
***** BB02, stmt 8
( 3, 3) [000038] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8
N003 ( 3, 3) [000035] ------------ | /--* ADD long
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use)
N005 ( 3, 3) [000037] -A------R--- \--* ASG long
N004 ( 1, 1) [000036] D------N---- \--* LCL_VAR long V03 tmp2 d:4
***** BB02, stmt 9
( 5, 5) [000043] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000042] ------------ \--* JTRUE void
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000041] J------N---- \--* GT int
N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V04 tmp3 u:4
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 10
( 3, 3) [000051] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000047] ------------ | /--* CNS_INT long -8
N003 ( 3, 3) [000048] ------------ | /--* ADD long
N001 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:4 (last use)
N005 ( 3, 3) [000050] -A------R--- \--* ASG long
N004 ( 1, 1) [000049] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 11
( 16, 13) [000067] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000064] ---XG------- | /--* CAST int <- long
N011 ( 15, 11) [000063] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
N009 ( 3, 2) [000061] *--XG------- | | | /--* IND long
N008 ( 1, 1) [000060] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:5
N010 ( 14, 10) [000062] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
N004 ( 1, 1) [000057] ------------ | | | /--* CNS_INT int 63
N005 ( 5, 5) [000058] ------------ | | | /--* AND int
N002 ( 1, 1) [000055] ------------ | | | | | /--* CNS_INT int -1
N003 ( 3, 3) [000056] ------------ | | | | \--* ADD int
N001 ( 1, 1) [000054] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:2 (last use)
N007 ( 10, 7) [000059] --------R--- | | \--* LSH long
N006 ( 1, 1) [000053] ------------ | | \--* CNS_INT long 1
N014 ( 16, 13) [000066] -A-XG---R--- \--* ASG int
N013 ( 1, 1) [000065] D------N---- \--* LCL_VAR int V06 tmp5 d:2
***** BB03, stmt 12
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int
N009 ( 1, 1) [000077] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use)
N010 ( 29, 13) [000078] ------------ \--* ADD int
N007 ( 1, 1) [000074] ------------ | /--* CNS_INT int 6
N008 ( 27, 11) [000075] ------------ \--* LSH int
N006 ( 25, 9) [000099] ------------ \--* CAST int <- long
N004 ( 1, 1) [000072] ------------ | /--* CNS_INT long 8
N005 ( 24, 7) [000073] ------------ \--* DIV long
N002 ( 1, 1) [000069] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use)
N003 ( 3, 3) [000070] ------------ \--* SUB long
N001 ( 1, 1) [000068] ------------ \--* LCL_VAR long V03 tmp2 u:5 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In optEarlyProp()
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $c0
The SSA definition for ByrefExposed (#2) at start of BB01 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB01 is $c0 {InitVal($41)}
***** BB01, stmt 1 (before)
N002 ( 5, 12) [000001] x---G------- /--* IND long
N001 ( 3, 10) [000098] ------------ | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits]
N004 ( 5, 12) [000080] -A--G---R--- * ASG long
N003 ( 1, 1) [000079] D------N---- \--* LCL_VAR long V02 tmp1 d:2
N001 [000098] CNS_INT(h) 0x7fa5d4e14498 static Fseq[_bits] => $100 {Hnd const: 0x00007FA5D4E14498}
N002 [000001] IND => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N003 [000079] LCL_VAR V02 tmp1 d:2 => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N004 [000080] ASG => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
***** BB01, stmt 1 (after)
N002 ( 5, 12) [000001] x---G------- /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000098] ------------ | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits] $100
N004 ( 5, 12) [000080] -A--G---R--- * ASG long <l:$140, c:$180>
N003 ( 1, 1) [000079] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
---------
***** BB01, stmt 2 (before)
N001 ( 1, 1) [000003] ------------ /--* LCL_VAR int V00 arg0 u:2 (last use)
N003 ( 1, 3) [000083] -A------R--- * ASG int
N002 ( 1, 1) [000082] D------N---- \--* LCL_VAR int V04 tmp3 d:2
N001 [000003] LCL_VAR V00 arg0 u:2 (last use) => $80 {InitVal($40)}
N002 [000082] LCL_VAR V04 tmp3 d:2 => $80 {InitVal($40)}
N003 [000083] ASG => $80 {InitVal($40)}
***** BB01, stmt 2 (after)
N001 ( 1, 1) [000003] ------------ /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000083] -A------R--- * ASG int $80
N002 ( 1, 1) [000082] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
---------
***** BB01, stmt 3 (before)
N001 ( 1, 1) [000013] ------------ /--* LCL_VAR long V02 tmp1 u:2
N003 ( 1, 3) [000015] -A------R--- * ASG long
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2
N001 [000013] LCL_VAR V02 tmp1 u:2 => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N002 [000014] LCL_VAR V03 tmp2 d:2 => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N003 [000015] ASG => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
***** BB01, stmt 3 (after)
N001 ( 1, 1) [000013] ------------ /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- * ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
finish(BB01).
Succ(BB02).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
SSA definition: set VN of local 3/3 to $141 {PhiDef($3, $3, $200)}.
SSA definition: set VN of local 4/3 to $240 {PhiDef($4, $3, $200)}.
The SSA definition for ByrefExposed (#2) at start of BB02 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB02 is $c0 {InitVal($41)}
***** BB02, stmt 4 (before)
N001 ( 1, 1) [000018] ------------ /--* LCL_VAR int V04 tmp3 u:3
N003 ( 1, 3) [000020] -A------R--- * ASG int
N002 ( 1, 1) [000019] D------N---- \--* LCL_VAR int V05 tmp4 d:2
N001 [000018] LCL_VAR V04 tmp3 u:3 => $240 {PhiDef($4, $3, $200)}
N002 [000019] LCL_VAR V05 tmp4 d:2 => $240 {PhiDef($4, $3, $200)}
N003 [000020] ASG => $240 {PhiDef($4, $3, $200)}
***** BB02, stmt 4 (after)
N001 ( 1, 1) [000018] ------------ /--* LCL_VAR int V04 tmp3 u:3 $240
N003 ( 1, 3) [000020] -A------R--- * ASG int $240
N002 ( 1, 1) [000019] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $240
---------
***** BB02, stmt 5 (before)
N005 ( 5, 5) [000026] ---XG------- /--* CAST int <- long
N004 ( 4, 3) [000025] ---XG------- | \--* HWIntrinsic long PopCount
N003 ( 3, 2) [000024] *--XG------- | \--* IND long
N002 ( 1, 1) [000023] ------------ | \--* LCL_VAR long V03 tmp2 u:3
N006 ( 7, 7) [000027] ---XG------- /--* SUB int
N001 ( 1, 1) [000022] ------------ | \--* LCL_VAR int V04 tmp3 u:3 (last use)
N008 ( 7, 7) [000030] -A-XG---R--- * ASG int
N007 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V04 tmp3 d:4
N001 [000022] LCL_VAR V04 tmp3 u:3 (last use) => $240 {PhiDef($4, $3, $200)}
N002 [000023] LCL_VAR V03 tmp2 u:3 => $141 {PhiDef($3, $3, $200)}
N003 [000024] IND => <l:$142 {ByrefExposedLoad($42, $141, $c0)}, c:$2c0 {2c0}>
VNForCastOper(int) is $45
N005 [000026] CAST => $340 {Cast($300, $45)}
N006 [000027] SUB => $341 {SUB($240, $340)}
N007 [000029] LCL_VAR V04 tmp3 d:4 => $341 {SUB($240, $340)}
N008 [000030] ASG => $341 {SUB($240, $340)}
***** BB02, stmt 5 (after)
N005 ( 5, 5) [000026] ---XG------- /--* CAST int <- long $340
N004 ( 4, 3) [000025] ---XG------- | \--* HWIntrinsic long PopCount $300
N003 ( 3, 2) [000024] *--XG------- | \--* IND long <l:$142, c:$2c0>
N002 ( 1, 1) [000023] ------------ | \--* LCL_VAR long V03 tmp2 u:3 $141
N006 ( 7, 7) [000027] ---XG------- /--* SUB int $341
N001 ( 1, 1) [000022] ------------ | \--* LCL_VAR int V04 tmp3 u:3 (last use) $240
N008 ( 7, 7) [000030] -A-XG---R--- * ASG int $341
N007 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $341
---------
***** BB02, stmt 6 (before)
N002 ( 1, 1) [000034] ------------ /--* CNS_INT long 8
N003 ( 3, 3) [000035] ------------ /--* ADD long
N001 ( 1, 1) [000032] ------------ | \--* LCL_VAR long V03 tmp2 u:3 (last use)
N005 ( 3, 3) [000037] -A------R--- * ASG long
N004 ( 1, 1) [000036] D------N---- \--* LCL_VAR long V03 tmp2 d:4
N001 [000032] LCL_VAR V03 tmp2 u:3 (last use) => $141 {PhiDef($3, $3, $200)}
N002 [000034] CNS_INT 8 => $380 {LngCns: 8}
N003 [000035] ADD => $201 {ADD($141, $380)}
N004 [000036] LCL_VAR V03 tmp2 d:4 => $201 {ADD($141, $380)}
N005 [000037] ASG => $201 {ADD($141, $380)}
***** BB02, stmt 6 (after)
N002 ( 1, 1) [000034] ------------ /--* CNS_INT long 8 $380
N003 ( 3, 3) [000035] ------------ /--* ADD long $201
N001 ( 1, 1) [000032] ------------ | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000037] -A------R--- * ASG long $201
N004 ( 1, 1) [000036] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $201
---------
***** BB02, stmt 7 (before)
N004 ( 5, 5) [000042] ------------ * JTRUE void
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000041] J------N---- \--* GT int
N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V04 tmp3 u:4
N001 [000039] LCL_VAR V04 tmp3 u:4 => $341 {SUB($240, $340)}
N002 [000040] CNS_INT 0 => $40 {IntCns 0}
N003 [000041] GT => $342 {GT($341, $40)}
***** BB02, stmt 7 (after)
N004 ( 5, 5) [000042] ------------ * JTRUE void
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000041] J------N---- \--* GT int $342
N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V04 tmp3 u:4 $341
finish(BB02).
Succ(BB03).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB02).
The SSA definition for ByrefExposed (#2) at start of BB03 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB03 is $c0 {InitVal($41)}
***** BB03, stmt 10 (before)
N002 ( 1, 1) [000047] ------------ /--* CNS_INT long -8
N003 ( 3, 3) [000048] ------------ /--* ADD long
N001 ( 1, 1) [000045] ------------ | \--* LCL_VAR long V03 tmp2 u:4 (last use)
N005 ( 3, 3) [000050] -A------R--- * ASG long
N004 ( 1, 1) [000049] D------N---- \--* LCL_VAR long V03 tmp2 d:5
N001 [000045] LCL_VAR V03 tmp2 u:4 (last use) => $201 {ADD($141, $380)}
N002 [000047] CNS_INT -8 => $382 {LngCns: -8}
N003 [000048] ADD => $202 {ADD($201, $382)}
N004 [000049] LCL_VAR V03 tmp2 d:5 => $202 {ADD($201, $382)}
N005 [000050] ASG => $202 {ADD($201, $382)}
***** BB03, stmt 10 (after)
N002 ( 1, 1) [000047] ------------ /--* CNS_INT long -8 $382
N003 ( 3, 3) [000048] ------------ /--* ADD long $202
N001 ( 1, 1) [000045] ------------ | \--* LCL_VAR long V03 tmp2 u:4 (last use) $201
N005 ( 3, 3) [000050] -A------R--- * ASG long $202
N004 ( 1, 1) [000049] D------N---- \--* LCL_VAR long V03 tmp2 d:5 $202
---------
***** BB03, stmt 11 (before)
N012 ( 16, 13) [000064] ---XG------- /--* CAST int <- long
N011 ( 15, 11) [000063] ---XG------- | \--* HWIntrinsic long TrailingZeroCount
N009 ( 3, 2) [000061] *--XG------- | | /--* IND long
N008 ( 1, 1) [000060] ------------ | | | \--* LCL_VAR long V03 tmp2 u:5
N010 ( 14, 10) [000062] ---XG------- | \--* HWIntrinsic long ParallelBitDeposit
N004 ( 1, 1) [000057] ------------ | | /--* CNS_INT int 63
N005 ( 5, 5) [000058] ------------ | | /--* AND int
N002 ( 1, 1) [000055] ------------ | | | | /--* CNS_INT int -1
N003 ( 3, 3) [000056] ------------ | | | \--* ADD int
N001 ( 1, 1) [000054] ------------ | | | \--* LCL_VAR int V05 tmp4 u:2 (last use)
N007 ( 10, 7) [000059] --------R--- | \--* LSH long
N006 ( 1, 1) [000053] ------------ | \--* CNS_INT long 1
N014 ( 16, 13) [000066] -A-XG---R--- * ASG int
N013 ( 1, 1) [000065] D------N---- \--* LCL_VAR int V06 tmp5 d:2
N001 [000054] LCL_VAR V05 tmp4 u:2 (last use) => $240 {PhiDef($4, $3, $200)}
N002 [000055] CNS_INT -1 => $41 {IntCns -1}
N003 [000056] ADD => $343 {ADD($41, $240)}
N004 [000057] CNS_INT 63 => $46 {IntCns 63}
N005 [000058] AND => $344 {AND($46, $343)}
N006 [000053] CNS_INT 1 => $383 {LngCns: 1}
N007 [000059] LSH => $203 {LSH($383, $344)}
N008 [000060] LCL_VAR V03 tmp2 u:5 => $202 {ADD($201, $382)}
N009 [000061] IND => <l:$143 {ByrefExposedLoad($42, $202, $c0)}, c:$184 {184}>
VNForCastOper(int) is $45
N012 [000064] CAST => $345 {Cast($3c1, $45)}
N013 [000065] LCL_VAR V06 tmp5 d:2 => $345 {Cast($3c1, $45)}
N014 [000066] ASG => $345 {Cast($3c1, $45)}
***** BB03, stmt 11 (after)
N012 ( 16, 13) [000064] ---XG------- /--* CAST int <- long $345
N011 ( 15, 11) [000063] ---XG------- | \--* HWIntrinsic long TrailingZeroCount $3c1
N009 ( 3, 2) [000061] *--XG------- | | /--* IND long <l:$143, c:$184>
N008 ( 1, 1) [000060] ------------ | | | \--* LCL_VAR long V03 tmp2 u:5 $202
N010 ( 14, 10) [000062] ---XG------- | \--* HWIntrinsic long ParallelBitDeposit $3c0
N004 ( 1, 1) [000057] ------------ | | /--* CNS_INT int 63 $46
N005 ( 5, 5) [000058] ------------ | | /--* AND int $344
N002 ( 1, 1) [000055] ------------ | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000056] ------------ | | | \--* ADD int $343
N001 ( 1, 1) [000054] ------------ | | | \--* LCL_VAR int V05 tmp4 u:2 (last use) $240
N007 ( 10, 7) [000059] --------R--- | \--* LSH long $203
N006 ( 1, 1) [000053] ------------ | \--* CNS_INT long 1 $383
N014 ( 16, 13) [000066] -A-XG---R--- * ASG int $345
N013 ( 1, 1) [000065] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $345
---------
***** BB03, stmt 12 (before)
N011 ( 30, 14) [000010] ------------ * RETURN int
N009 ( 1, 1) [000077] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use)
N010 ( 29, 13) [000078] ------------ \--* ADD int
N007 ( 1, 1) [000074] ------------ | /--* CNS_INT int 6
N008 ( 27, 11) [000075] ------------ \--* LSH int
N006 ( 25, 9) [000099] ------------ \--* CAST int <- long
N004 ( 1, 1) [000072] ------------ | /--* CNS_INT long 8
N005 ( 24, 7) [000073] ------------ \--* DIV long
N002 ( 1, 1) [000069] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use)
N003 ( 3, 3) [000070] ------------ \--* SUB long
N001 ( 1, 1) [000068] ------------ \--* LCL_VAR long V03 tmp2 u:5 (last use)
N001 [000068] LCL_VAR V03 tmp2 u:5 (last use) => $202 {ADD($201, $382)}
N002 [000069] LCL_VAR V02 tmp1 u:2 (last use) => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N003 [000070] SUB => <l:$204 {SUB($202, $140)}, c:$205 {SUB($202, $180)}>
N004 [000072] CNS_INT 8 => $380 {LngCns: 8}
N005 [000073] DIV => <l:$206 {DIV($204, $380)}, c:$207 {DIV($205, $380)}>
VNForCastOper(int) is $45
N006 [000099] CAST => <l:$346 {Cast($206, $45)}, c:$347 {Cast($207, $45)}>
N007 [000074] CNS_INT 6 => $47 {IntCns 6}
N008 [000075] LSH => <l:$348 {LSH($346, $47)}, c:$349 {LSH($347, $47)}>
N009 [000077] LCL_VAR V06 tmp5 u:2 (last use) => $345 {Cast($3c1, $45)}
N010 [000078] ADD => <l:$34a {ADD($345, $348)}, c:$34b {ADD($345, $349)}>
N011 [000010] RETURN => $1c2 {1c2}
***** BB03, stmt 12 (after)
N011 ( 30, 14) [000010] ------------ * RETURN int $1c2
N009 ( 1, 1) [000077] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $345
N010 ( 29, 13) [000078] ------------ \--* ADD int <l:$34a, c:$34b>
N007 ( 1, 1) [000074] ------------ | /--* CNS_INT int 6 $47
N008 ( 27, 11) [000075] ------------ \--* LSH int <l:$348, c:$349>
N006 ( 25, 9) [000099] ------------ \--* CAST int <- long <l:$346, c:$347>
N004 ( 1, 1) [000072] ------------ | /--* CNS_INT long 8 $380
N005 ( 24, 7) [000073] ------------ \--* DIV long <l:$206, c:$207>
N002 ( 1, 1) [000069] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000070] ------------ \--* SUB long <l:$204, c:$205>
N001 ( 1, 1) [000068] ------------ \--* LCL_VAR long V03 tmp2 u:5 (last use) $202
finish(BB03).
*************** In optHoistLoopCode()
Blocks/Trees before phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
( 5, 12) [000081] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000098] ------------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits] $100
N004 ( 5, 12) [000080] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000079] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000084] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000083] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000082] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 4
( 2, 3) [000108] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000106] ------------ | * PHI long
N001 ( 0, 0) [000113] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000109] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000107] -A------R--- \--* ASG long
N006 ( 1, 1) [000105] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 5
( 2, 3) [000104] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000102] ------------ | * PHI int
N001 ( 0, 0) [000115] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000111] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000103] -A------R--- \--* ASG int
N006 ( 1, 1) [000101] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 6
( 1, 3) [000021] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000018] ------------ | /--* LCL_VAR int V04 tmp3 u:3 $240
N003 ( 1, 3) [000020] -A------R--- \--* ASG int $240
N002 ( 1, 1) [000019] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $240
***** BB02, stmt 7
( 7, 7) [000031] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000026] ---XG------- | /--* CAST int <- long $340
N004 ( 4, 3) [000025] ---XG------- | | \--* HWIntrinsic long PopCount $300
N003 ( 3, 2) [000024] *--XG------- | | \--* IND long <l:$142, c:$2c0>
N002 ( 1, 1) [000023] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N006 ( 7, 7) [000027] ---XG------- | /--* SUB int $341
N001 ( 1, 1) [000022] ------------ | | \--* LCL_VAR int V04 tmp3 u:3 (last use) $240
N008 ( 7, 7) [000030] -A-XG---R--- \--* ASG int $341
N007 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $341
***** BB02, stmt 8
( 3, 3) [000038] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 $380
N003 ( 3, 3) [000035] ------------ | /--* ADD long $201
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000037] -A------R--- \--* ASG long $201
N004 ( 1, 1) [000036] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $201
***** BB02, stmt 9
( 5, 5) [000043] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000042] ------------ \--* JTRUE void
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000041] J------N---- \--* GT int $342
N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V04 tmp3 u:4 $341
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 10
( 3, 3) [000051] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000047] ------------ | /--* CNS_INT long -8 $382
N003 ( 3, 3) [000048] ------------ | /--* ADD long $202
N001 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:4 (last use) $201
N005 ( 3, 3) [000050] -A------R--- \--* ASG long $202
N004 ( 1, 1) [000049] D------N---- \--* LCL_VAR long V03 tmp2 d:5 $202
***** BB03, stmt 11
( 16, 13) [000067] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000064] ---XG------- | /--* CAST int <- long $345
N011 ( 15, 11) [000063] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount $3c1
N009 ( 3, 2) [000061] *--XG------- | | | /--* IND long <l:$143, c:$184>
N008 ( 1, 1) [000060] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:5 $202
N010 ( 14, 10) [000062] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit $3c0
N004 ( 1, 1) [000057] ------------ | | | /--* CNS_INT int 63 $46
N005 ( 5, 5) [000058] ------------ | | | /--* AND int $344
N002 ( 1, 1) [000055] ------------ | | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000056] ------------ | | | | \--* ADD int $343
N001 ( 1, 1) [000054] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:2 (last use) $240
N007 ( 10, 7) [000059] --------R--- | | \--* LSH long $203
N006 ( 1, 1) [000053] ------------ | | \--* CNS_INT long 1 $383
N014 ( 16, 13) [000066] -A-XG---R--- \--* ASG int $345
N013 ( 1, 1) [000065] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $345
***** BB03, stmt 12
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int $1c2
N009 ( 1, 1) [000077] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $345
N010 ( 29, 13) [000078] ------------ \--* ADD int <l:$34a, c:$34b>
N007 ( 1, 1) [000074] ------------ | /--* CNS_INT int 6 $47
N008 ( 27, 11) [000075] ------------ \--* LSH int <l:$348, c:$349>
N006 ( 25, 9) [000099] ------------ \--* CAST int <- long <l:$346, c:$347>
N004 ( 1, 1) [000072] ------------ | /--* CNS_INT long 8 $380
N005 ( 24, 7) [000073] ------------ \--* DIV long <l:$206, c:$207>
N002 ( 1, 1) [000069] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000070] ------------ \--* SUB long <l:$204, c:$205>
N001 ( 1, 1) [000068] ------------ \--* LCL_VAR long V03 tmp2 u:5 (last use) $202
-------------------------------------------------------------------------------------------------------------------
optHoistLoopCode for loop L00 <BB02..BB02>:
Loop body does not contain a call
USEDEF (3)={V04 V03 V05}
INOUT (4)={V04 V03 V02 V05}
LOOPVARS(3)={V04 V03 V05}
optHoistLoopExprsForBlock BB02 (weight= 4 ) of loop L00 <BB02..BB02>, firstBlock is true
*************** In optVnCopyProp()
*************** In SsaBuilder::ComputeDominators(Compiler*, ...)
Copy Assertion for BB01
curSsaName stack: { }
Live vars: {V00} => {V00 V02}
Live vars: {V00 V02} => {V02}
Live vars: {V02} => {V02 V04}
Live vars: {V02 V04} => {V02 V03 V04}
Copy Assertion for BB02
curSsaName stack: { 0-[000003]:V00 2-[000079]:V02 3-[000014]:V03 4-[000082]:V04 }
Live vars: {V02 V03 V04} => {V02 V03 V04 V05}
Live vars: {V02 V03 V04 V05} => {V02 V03 V05}
VN based copy assertion for [000022] V04 @00000240 by [000019] V05 @00000240.
N001 ( 1, 1) [000022] ------------ * LCL_VAR int V04 tmp3 u:3 (last use) $240
New refCnts for V04: refCnt = 4, refCntWtd = 26
New refCnts for V05: refCnt = 3, refCntWtd = 9
copy propagated to:
N001 ( 1, 1) [000022] ------------ * LCL_VAR int V05 tmp4 u:2 (last use) $240
Live vars: {V02 V03 V05} => {V02 V03 V04 V05}
Live vars: {V02 V03 V04 V05} => {V02 V04 V05}
Live vars: {V02 V04 V05} => {V02 V03 V04 V05}
Copy Assertion for BB03
curSsaName stack: { 0-[000003]:V00 2-[000079]:V02 3-[000036]:V03 4-[000029]:V04 5-[000019]:V05 }
Live vars: {V02 V03 V05} => {V02 V05}
Live vars: {V02 V05} => {V02 V03 V05}
Live vars: {V02 V03 V05} => {V02 V03}
Live vars: {V02 V03} => {V02 V03 V06}
Live vars: {V02 V03 V06} => {V02 V06}
Live vars: {V02 V06} => {V06}
Live vars: {V06} => {}
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
( 5, 12) [000081] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000098] ------------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits] $100
N004 ( 5, 12) [000080] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000079] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000084] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000083] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000082] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 4
( 2, 3) [000108] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000106] ------------ | * PHI long
N001 ( 0, 0) [000113] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000109] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000107] -A------R--- \--* ASG long
N006 ( 1, 1) [000105] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 5
( 2, 3) [000104] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000102] ------------ | * PHI int
N001 ( 0, 0) [000115] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000111] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000103] -A------R--- \--* ASG int
N006 ( 1, 1) [000101] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 6
( 1, 3) [000021] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000018] ------------ | /--* LCL_VAR int V04 tmp3 u:3 $240
N003 ( 1, 3) [000020] -A------R--- \--* ASG int $240
N002 ( 1, 1) [000019] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $240
***** BB02, stmt 7
( 7, 7) [000031] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000026] ---XG------- | /--* CAST int <- long $340
N004 ( 4, 3) [000025] ---XG------- | | \--* HWIntrinsic long PopCount $300
N003 ( 3, 2) [000024] *--XG------- | | \--* IND long <l:$142, c:$2c0>
N002 ( 1, 1) [000023] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N006 ( 7, 7) [000027] ---XG------- | /--* SUB int $341
N001 ( 1, 1) [000022] ------------ | | \--* LCL_VAR int V05 tmp4 u:2 (last use) $240
N008 ( 7, 7) [000030] -A-XG---R--- \--* ASG int $341
N007 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $341
***** BB02, stmt 8
( 3, 3) [000038] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 $380
N003 ( 3, 3) [000035] ------------ | /--* ADD long $201
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000037] -A------R--- \--* ASG long $201
N004 ( 1, 1) [000036] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $201
***** BB02, stmt 9
( 5, 5) [000043] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000042] ------------ \--* JTRUE void
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000041] J------N---- \--* GT int $342
N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V04 tmp3 u:4 $341
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 10
( 3, 3) [000051] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000047] ------------ | /--* CNS_INT long -8 $382
N003 ( 3, 3) [000048] ------------ | /--* ADD long $202
N001 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:4 (last use) $201
N005 ( 3, 3) [000050] -A------R--- \--* ASG long $202
N004 ( 1, 1) [000049] D------N---- \--* LCL_VAR long V03 tmp2 d:5 $202
***** BB03, stmt 11
( 16, 13) [000067] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000064] ---XG------- | /--* CAST int <- long $345
N011 ( 15, 11) [000063] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount $3c1
N009 ( 3, 2) [000061] *--XG------- | | | /--* IND long <l:$143, c:$184>
N008 ( 1, 1) [000060] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:5 $202
N010 ( 14, 10) [000062] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit $3c0
N004 ( 1, 1) [000057] ------------ | | | /--* CNS_INT int 63 $46
N005 ( 5, 5) [000058] ------------ | | | /--* AND int $344
N002 ( 1, 1) [000055] ------------ | | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000056] ------------ | | | | \--* ADD int $343
N001 ( 1, 1) [000054] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:2 (last use) $240
N007 ( 10, 7) [000059] --------R--- | | \--* LSH long $203
N006 ( 1, 1) [000053] ------------ | | \--* CNS_INT long 1 $383
N014 ( 16, 13) [000066] -A-XG---R--- \--* ASG int $345
N013 ( 1, 1) [000065] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $345
***** BB03, stmt 12
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int $1c2
N009 ( 1, 1) [000077] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $345
N010 ( 29, 13) [000078] ------------ \--* ADD int <l:$34a, c:$34b>
N007 ( 1, 1) [000074] ------------ | /--* CNS_INT int 6 $47
N008 ( 27, 11) [000075] ------------ \--* LSH int <l:$348, c:$349>
N006 ( 25, 9) [000099] ------------ \--* CAST int <- long <l:$346, c:$347>
N004 ( 1, 1) [000072] ------------ | /--* CNS_INT long 8 $380
N005 ( 24, 7) [000073] ------------ \--* DIV long <l:$206, c:$207>
N002 ( 1, 1) [000069] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000070] ------------ \--* SUB long <l:$204, c:$205>
N001 ( 1, 1) [000068] ------------ \--* LCL_VAR long V03 tmp2 u:5 (last use) $202
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
( 5, 12) [000081] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000098] ------------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits] $100
N004 ( 5, 12) [000080] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000079] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000084] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000083] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000082] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 4
( 2, 3) [000108] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000106] ------------ | * PHI long
N001 ( 0, 0) [000113] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000109] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000107] -A------R--- \--* ASG long
N006 ( 1, 1) [000105] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 5
( 2, 3) [000104] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000102] ------------ | * PHI int
N001 ( 0, 0) [000115] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000111] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000103] -A------R--- \--* ASG int
N006 ( 1, 1) [000101] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 6
( 1, 3) [000021] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000018] ------------ | /--* LCL_VAR int V04 tmp3 u:3 $240
N003 ( 1, 3) [000020] -A------R--- \--* ASG int $240
N002 ( 1, 1) [000019] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $240
***** BB02, stmt 7
( 7, 7) [000031] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000026] ---XG------- | /--* CAST int <- long $340
N004 ( 4, 3) [000025] ---XG------- | | \--* HWIntrinsic long PopCount $300
N003 ( 3, 2) [000024] *--XG------- | | \--* IND long <l:$142, c:$2c0>
N002 ( 1, 1) [000023] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N006 ( 7, 7) [000027] ---XG------- | /--* SUB int $341
N001 ( 1, 1) [000022] ------------ | | \--* LCL_VAR int V05 tmp4 u:2 (last use) $240
N008 ( 7, 7) [000030] -A-XG---R--- \--* ASG int $341
N007 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $341
***** BB02, stmt 8
( 3, 3) [000038] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 $380
N003 ( 3, 3) [000035] ------------ | /--* ADD long $201
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000037] -A------R--- \--* ASG long $201
N004 ( 1, 1) [000036] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $201
***** BB02, stmt 9
( 5, 5) [000043] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000042] ------------ \--* JTRUE void
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000041] J------N---- \--* GT int $342
N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V04 tmp3 u:4 $341
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 10
( 3, 3) [000051] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000047] ------------ | /--* CNS_INT long -8 $382
N003 ( 3, 3) [000048] ------------ | /--* ADD long $202
N001 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:4 (last use) $201
N005 ( 3, 3) [000050] -A------R--- \--* ASG long $202
N004 ( 1, 1) [000049] D------N---- \--* LCL_VAR long V03 tmp2 d:5 $202
***** BB03, stmt 11
( 16, 13) [000067] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000064] ---XG------- | /--* CAST int <- long $345
N011 ( 15, 11) [000063] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount $3c1
N009 ( 3, 2) [000061] *--XG------- | | | /--* IND long <l:$143, c:$184>
N008 ( 1, 1) [000060] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:5 $202
N010 ( 14, 10) [000062] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit $3c0
N004 ( 1, 1) [000057] ------------ | | | /--* CNS_INT int 63 $46
N005 ( 5, 5) [000058] ------------ | | | /--* AND int $344
N002 ( 1, 1) [000055] ------------ | | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000056] ------------ | | | | \--* ADD int $343
N001 ( 1, 1) [000054] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:2 (last use) $240
N007 ( 10, 7) [000059] --------R--- | | \--* LSH long $203
N006 ( 1, 1) [000053] ------------ | | \--* CNS_INT long 1 $383
N014 ( 16, 13) [000066] -A-XG---R--- \--* ASG int $345
N013 ( 1, 1) [000065] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $345
***** BB03, stmt 12
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int $1c2
N009 ( 1, 1) [000077] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $345
N010 ( 29, 13) [000078] ------------ \--* ADD int <l:$34a, c:$34b>
N007 ( 1, 1) [000074] ------------ | /--* CNS_INT int 6 $47
N008 ( 27, 11) [000075] ------------ \--* LSH int <l:$348, c:$349>
N006 ( 25, 9) [000099] ------------ \--* CAST int <- long <l:$346, c:$347>
N004 ( 1, 1) [000072] ------------ | /--* CNS_INT long 8 $380
N005 ( 24, 7) [000073] ------------ \--* DIV long <l:$206, c:$207>
N002 ( 1, 1) [000069] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000070] ------------ \--* SUB long <l:$204, c:$205>
N001 ( 1, 1) [000068] ------------ \--* LCL_VAR long V03 tmp2 u:5 (last use) $202
-------------------------------------------------------------------------------------------------------------------
GenTreeNode creates assertion:
N004 ( 5, 5) [000042] ------------ * JTRUE void
In BB02 New Global Constant Assertion: (834, 64) ($342,$40) Loop_Bnd {GT($341, $40)} is not {IntCns 0} index=#01, mask=0000000000000001
GenTreeNode creates assertion:
N004 ( 5, 5) [000042] ------------ * JTRUE void
In BB02 New Global Constant Assertion: (834, 64) ($342,$40) Loop_Bnd {GT($341, $40)} is {IntCns 0} index=#02, mask=0000000000000002
BB01 valueGen = 0000000000000000
BB02 valueGen = 0000000000000002 => BB02 valueGen = 0000000000000001,
BB03 valueGen = 0000000000000000AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000
AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000
AssertionPropCallback::Changed : BB01 before out -> 0000000000000003; after out -> 0000000000000000;
jumpDest before out -> 0000000000000003; jumpDest after out -> 0000000000000000;
AssertionPropCallback::StartMerge: BB02 in -> 0000000000000003
AssertionPropCallback::Merge : BB02 in -> 0000000000000003, predBlock BB01 out -> 0000000000000000
AssertionPropCallback::Merge : BB02 in -> 0000000000000000, predBlock BB02 out -> 0000000000000003
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000000
AssertionPropCallback::Changed : BB02 before out -> 0000000000000003; after out -> 0000000000000002;
jumpDest before out -> 0000000000000003; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB03 in -> 0000000000000003
AssertionPropCallback::Merge : BB03 in -> 0000000000000003, predBlock BB02 out -> 0000000000000002
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000002
AssertionPropCallback::Changed : BB03 before out -> 0000000000000003; after out -> 0000000000000002;
jumpDest before out -> 0000000000000003; jumpDest after out -> 0000000000000002;
AssertionPropCallback::StartMerge: BB02 in -> 0000000000000000
AssertionPropCallback::Merge : BB02 in -> 0000000000000000, predBlock BB01 out -> 0000000000000000
AssertionPropCallback::Merge : BB02 in -> 0000000000000000, predBlock BB02 out -> 0000000000000002
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000000
AssertionPropCallback::Unchanged : BB02 out -> 0000000000000002; jumpDest out -> 0000000000000001
BB01 valueIn = 0000000000000000 valueOut = 0000000000000000
BB02 valueIn = 0000000000000000 valueOut = 0000000000000002 => BB02 valueOut= 0000000000000001
BB03 valueIn = 0000000000000002 valueOut = 0000000000000002
Propagating 0000000000000000 assertions for BB01, stmt [000081], tree [000098], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000081], tree [000001], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000081], tree [000079], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000081], tree [000080], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000084], tree [000003], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000084], tree [000082], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000084], tree [000083], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000016], tree [000013], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000016], tree [000014], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000016], tree [000015], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000021], tree [000018], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000021], tree [000019], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000021], tree [000020], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000031], tree [000022], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000031], tree [000023], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000031], tree [000024], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000031], tree [000025], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000031], tree [000026], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000031], tree [000027], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000031], tree [000029], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000031], tree [000030], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000038], tree [000032], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000038], tree [000034], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000038], tree [000035], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000038], tree [000036], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000038], tree [000037], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000043], tree [000039], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000043], tree [000040], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000043], tree [000041], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000051], tree [000045], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000051], tree [000047], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000051], tree [000048], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000051], tree [000049], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000051], tree [000050], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000054], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000055], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000056], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000057], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000058], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000053], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000059], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000060], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000061], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000062], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000063], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000064], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000065], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000067], tree [000066], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000068], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000069], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000070], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000072], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000073], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000099], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000074], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000075], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000077], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000078], tree -> 0
Propagating 0000000000000002 assertions for BB03, stmt [000011], tree [000010], tree -> 0
*************** In fgDebugCheckBBlist
*************** In OptimizeRangeChecks()
Blocks/trees before phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
( 5, 12) [000081] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000098] ------------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits] $100
N004 ( 5, 12) [000080] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000079] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000084] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000083] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000082] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 4
( 2, 3) [000108] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000106] ------------ | * PHI long
N001 ( 0, 0) [000113] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000109] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000107] -A------R--- \--* ASG long
N006 ( 1, 1) [000105] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 5
( 2, 3) [000104] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000102] ------------ | * PHI int
N001 ( 0, 0) [000115] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000111] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000103] -A------R--- \--* ASG int
N006 ( 1, 1) [000101] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 6
( 1, 3) [000021] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000018] ------------ | /--* LCL_VAR int V04 tmp3 u:3 $240
N003 ( 1, 3) [000020] -A------R--- \--* ASG int $240
N002 ( 1, 1) [000019] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $240
***** BB02, stmt 7
( 7, 7) [000031] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000026] ---XG------- | /--* CAST int <- long $340
N004 ( 4, 3) [000025] ---XG------- | | \--* HWIntrinsic long PopCount $300
N003 ( 3, 2) [000024] *--XG------- | | \--* IND long <l:$142, c:$2c0>
N002 ( 1, 1) [000023] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N006 ( 7, 7) [000027] ---XG------- | /--* SUB int $341
N001 ( 1, 1) [000022] ------------ | | \--* LCL_VAR int V05 tmp4 u:2 (last use) $240
N008 ( 7, 7) [000030] -A-XG---R--- \--* ASG int $341
N007 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $341
***** BB02, stmt 8
( 3, 3) [000038] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 $380
N003 ( 3, 3) [000035] ------------ | /--* ADD long $201
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000037] -A------R--- \--* ASG long $201
N004 ( 1, 1) [000036] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $201
***** BB02, stmt 9
( 5, 5) [000043] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000042] ------------ \--* JTRUE void
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000041] J------N---- \--* GT int $342
N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V04 tmp3 u:4 $341
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 10
( 3, 3) [000051] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000047] ------------ | /--* CNS_INT long -8 $382
N003 ( 3, 3) [000048] ------------ | /--* ADD long $202
N001 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:4 (last use) $201
N005 ( 3, 3) [000050] -A------R--- \--* ASG long $202
N004 ( 1, 1) [000049] D------N---- \--* LCL_VAR long V03 tmp2 d:5 $202
***** BB03, stmt 11
( 16, 13) [000067] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000064] ---XG------- | /--* CAST int <- long $345
N011 ( 15, 11) [000063] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount $3c1
N009 ( 3, 2) [000061] *--XG------- | | | /--* IND long <l:$143, c:$184>
N008 ( 1, 1) [000060] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:5 $202
N010 ( 14, 10) [000062] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit $3c0
N004 ( 1, 1) [000057] ------------ | | | /--* CNS_INT int 63 $46
N005 ( 5, 5) [000058] ------------ | | | /--* AND int $344
N002 ( 1, 1) [000055] ------------ | | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000056] ------------ | | | | \--* ADD int $343
N001 ( 1, 1) [000054] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:2 (last use) $240
N007 ( 10, 7) [000059] --------R--- | | \--* LSH long $203
N006 ( 1, 1) [000053] ------------ | | \--* CNS_INT long 1 $383
N014 ( 16, 13) [000066] -A-XG---R--- \--* ASG int $345
N013 ( 1, 1) [000065] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $345
***** BB03, stmt 12
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int $1c2
N009 ( 1, 1) [000077] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $345
N010 ( 29, 13) [000078] ------------ \--* ADD int <l:$34a, c:$34b>
N007 ( 1, 1) [000074] ------------ | /--* CNS_INT int 6 $47
N008 ( 27, 11) [000075] ------------ \--* LSH int <l:$348, c:$349>
N006 ( 25, 9) [000099] ------------ \--* CAST int <- long <l:$346, c:$347>
N004 ( 1, 1) [000072] ------------ | /--* CNS_INT long 8 $380
N005 ( 24, 7) [000073] ------------ \--* DIV long <l:$206, c:$207>
N002 ( 1, 1) [000069] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000070] ------------ \--* SUB long <l:$204, c:$205>
N001 ( 1, 1) [000068] ------------ \--* LCL_VAR long V03 tmp2 u:5 (last use) $202
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0003] 1 BB02 1 [000..001) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
( 5, 12) [000081] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000098] ------------ | | \--* CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits] $100
N004 ( 5, 12) [000080] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000079] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000084] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000083] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000082] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 4
( 2, 3) [000108] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000106] ------------ | * PHI long
N001 ( 0, 0) [000113] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000109] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000107] -A------R--- \--* ASG long
N006 ( 1, 1) [000105] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 5
( 2, 3) [000104] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000102] ------------ | * PHI int
N001 ( 0, 0) [000115] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000111] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000103] -A------R--- \--* ASG int
N006 ( 1, 1) [000101] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 6
( 1, 3) [000021] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000018] ------------ | /--* LCL_VAR int V04 tmp3 u:3 $240
N003 ( 1, 3) [000020] -A------R--- \--* ASG int $240
N002 ( 1, 1) [000019] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $240
***** BB02, stmt 7
( 7, 7) [000031] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000026] ---XG------- | /--* CAST int <- long $340
N004 ( 4, 3) [000025] ---XG------- | | \--* HWIntrinsic long PopCount $300
N003 ( 3, 2) [000024] *--XG------- | | \--* IND long <l:$142, c:$2c0>
N002 ( 1, 1) [000023] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 $141
N006 ( 7, 7) [000027] ---XG------- | /--* SUB int $341
N001 ( 1, 1) [000022] ------------ | | \--* LCL_VAR int V05 tmp4 u:2 (last use) $240
N008 ( 7, 7) [000030] -A-XG---R--- \--* ASG int $341
N007 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $341
***** BB02, stmt 8
( 3, 3) [000038] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000034] ------------ | /--* CNS_INT long 8 $380
N003 ( 3, 3) [000035] ------------ | /--* ADD long $201
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000037] -A------R--- \--* ASG long $201
N004 ( 1, 1) [000036] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $201
***** BB02, stmt 9
( 5, 5) [000043] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000042] ------------ \--* JTRUE void
N002 ( 1, 1) [000040] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000041] J------N---- \--* GT int $342
N001 ( 1, 1) [000039] ------------ \--* LCL_VAR int V04 tmp3 u:4 $341
------------ BB03 [000..001) (return), preds={BB02} succs={}
***** BB03, stmt 10
( 3, 3) [000051] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000047] ------------ | /--* CNS_INT long -8 $382
N003 ( 3, 3) [000048] ------------ | /--* ADD long $202
N001 ( 1, 1) [000045] ------------ | | \--* LCL_VAR long V03 tmp2 u:4 (last use) $201
N005 ( 3, 3) [000050] -A------R--- \--* ASG long $202
N004 ( 1, 1) [000049] D------N---- \--* LCL_VAR long V03 tmp2 d:5 $202
***** BB03, stmt 11
( 16, 13) [000067] ------------ * STMT void (IL 0x000... ???)
N012 ( 16, 13) [000064] ---XG------- | /--* CAST int <- long $345
N011 ( 15, 11) [000063] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount $3c1
N009 ( 3, 2) [000061] *--XG------- | | | /--* IND long <l:$143, c:$184>
N008 ( 1, 1) [000060] ------------ | | | | \--* LCL_VAR long V03 tmp2 u:5 $202
N010 ( 14, 10) [000062] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit $3c0
N004 ( 1, 1) [000057] ------------ | | | /--* CNS_INT int 63 $46
N005 ( 5, 5) [000058] ------------ | | | /--* AND int $344
N002 ( 1, 1) [000055] ------------ | | | | | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000056] ------------ | | | | \--* ADD int $343
N001 ( 1, 1) [000054] ------------ | | | | \--* LCL_VAR int V05 tmp4 u:2 (last use) $240
N007 ( 10, 7) [000059] --------R--- | | \--* LSH long $203
N006 ( 1, 1) [000053] ------------ | | \--* CNS_INT long 1 $383
N014 ( 16, 13) [000066] -A-XG---R--- \--* ASG int $345
N013 ( 1, 1) [000065] D------N---- \--* LCL_VAR int V06 tmp5 d:2 $345
***** BB03, stmt 12
( 30, 14) [000011] ------------ * STMT void (IL ???... ???)
N011 ( 30, 14) [000010] ------------ \--* RETURN int $1c2
N009 ( 1, 1) [000077] ------------ | /--* LCL_VAR int V06 tmp5 u:2 (last use) $345
N010 ( 29, 13) [000078] ------------ \--* ADD int <l:$34a, c:$34b>
N007 ( 1, 1) [000074] ------------ | /--* CNS_INT int 6 $47
N008 ( 27, 11) [000075] ------------ \--* LSH int <l:$348, c:$349>
N006 ( 25, 9) [000099] ------------ \--* CAST int <- long <l:$346, c:$347>
N004 ( 1, 1) [000072] ------------ | /--* CNS_INT long 8 $380
N005 ( 24, 7) [000073] ------------ \--* DIV long <l:$206, c:$207>
N002 ( 1, 1) [000069] ------------ | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000070] ------------ \--* SUB long <l:$204, c:$205>
N001 ( 1, 1) [000068] ------------ \--* LCL_VAR long V03 tmp2 u:5 (last use) $202
-------------------------------------------------------------------------------------------------------------------
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 5, 12) [000080] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000083] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000107] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000103] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000020] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N008 ( 7, 7) [000030] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000037] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000050] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N014 ( 16, 13) [000066] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target LIR
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0003] 1 BB02 1 [000..001) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
( 5, 12) [000081] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits] $100
/--* t98 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000080] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000084] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000083] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000113] ------------ t113 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000109] ------------ t109 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t113 long
+--* t109 long
N005 ( 2, 2) [000106] ------------ t106 = * PHI long
/--* t106 long
N007 ( 2, 3) [000107] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000115] ------------ t115 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000111] ------------ t111 = PHI_ARG int V04 tmp3 u:2 $80
/--* t115 int
+--* t111 int
N005 ( 2, 2) [000102] ------------ t102 = * PHI int
/--* t102 int
N007 ( 2, 3) [000103] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 1, 3) [000021] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:3 $240
/--* t18 int
N003 ( 1, 3) [000020] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 7, 7) [000031] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V05 tmp4 u:2 (last use) $240
N002 ( 1, 1) [000023] ------------ t23 = LCL_VAR long V03 tmp2 u:3 $141
/--* t23 long
N003 ( 3, 2) [000024] *--XG------- t24 = * IND long <l:$142, c:$2c0>
/--* t24 long
N004 ( 4, 3) [000025] ---XG------- t25 = * HWIntrinsic long PopCount $300
/--* t25 long
N005 ( 5, 5) [000026] ---XG------- t26 = * CAST int <- long $340
/--* t22 int
+--* t26 int
N006 ( 7, 7) [000027] ---XG------- t27 = * SUB int $341
/--* t27 int
N008 ( 7, 7) [000030] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 3, 3) [000038] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000032] ------------ t32 = LCL_VAR long V03 tmp2 u:3 (last use) $141
N002 ( 1, 1) [000034] ------------ t34 = CNS_INT long 8 $380
/--* t32 long
+--* t34 long
N003 ( 3, 3) [000035] ------------ t35 = * ADD long $201
/--* t35 long
N005 ( 3, 3) [000037] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 5, 5) [000043] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000039] ------------ t39 = LCL_VAR int V04 tmp3 u:4 $341
N002 ( 1, 1) [000040] ------------ t40 = CNS_INT int 0 $40
/--* t39 int
+--* t40 int
N003 ( 3, 3) [000041] J------N---- t41 = * GT int $342
/--* t41 int
N004 ( 5, 5) [000042] ------------ * JTRUE void
------------ BB03 [000..001) (return), preds={BB02} succs={}
( 3, 3) [000051] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V03 tmp2 u:4 (last use) $201
N002 ( 1, 1) [000047] ------------ t47 = CNS_INT long -8 $382
/--* t45 long
+--* t47 long
N003 ( 3, 3) [000048] ------------ t48 = * ADD long $202
/--* t48 long
N005 ( 3, 3) [000050] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
( 16, 13) [000067] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000054] ------------ t54 = LCL_VAR int V05 tmp4 u:2 (last use) $240
N002 ( 1, 1) [000055] ------------ t55 = CNS_INT int -1 $41
/--* t54 int
+--* t55 int
N003 ( 3, 3) [000056] ------------ t56 = * ADD int $343
N004 ( 1, 1) [000057] ------------ t57 = CNS_INT int 63 $46
/--* t56 int
+--* t57 int
N005 ( 5, 5) [000058] ------------ t58 = * AND int $344
N006 ( 1, 1) [000053] ------------ t53 = CNS_INT long 1 $383
/--* t53 long
+--* t58 int
N007 ( 10, 7) [000059] ------------ t59 = * LSH long $203
N008 ( 1, 1) [000060] ------------ t60 = LCL_VAR long V03 tmp2 u:5 $202
/--* t60 long
N009 ( 3, 2) [000061] *--XG------- t61 = * IND long <l:$143, c:$184>
/--* t59 long
+--* t61 long
N010 ( 14, 10) [000062] ---XG------- t62 = * HWIntrinsic long ParallelBitDeposit $3c0
/--* t62 long
N011 ( 15, 11) [000063] ---XG------- t63 = * HWIntrinsic long TrailingZeroCount $3c1
/--* t63 long
N012 ( 16, 13) [000064] ---XG------- t64 = * CAST int <- long $345
/--* t64 int
N014 ( 16, 13) [000066] DA-XG------- * STORE_LCL_VAR int V06 tmp5 d:2
N001 ( 1, 1) [000068] ------------ t68 = LCL_VAR long V03 tmp2 u:5 (last use) $202
N002 ( 1, 1) [000069] ------------ t69 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t68 long
+--* t69 long
N003 ( 3, 3) [000070] ------------ t70 = * SUB long <l:$204, c:$205>
N004 ( 1, 1) [000072] ------------ t72 = CNS_INT long 8 $380
/--* t70 long
+--* t72 long
N005 ( 24, 7) [000073] ------------ t73 = * DIV long <l:$206, c:$207>
/--* t73 long
N006 ( 25, 9) [000099] ------------ t99 = * CAST int <- long <l:$346, c:$347>
N007 ( 1, 1) [000074] ------------ t74 = CNS_INT int 6 $47
/--* t99 int
+--* t74 int
N008 ( 27, 11) [000075] ------------ t75 = * LSH int <l:$348, c:$349>
N009 ( 1, 1) [000077] ------------ t77 = LCL_VAR int V06 tmp5 u:2 (last use) $345
/--* t75 int
+--* t77 int
N010 ( 29, 13) [000078] ------------ t78 = * ADD int <l:$34a, c:$34b>
/--* t78 int
N011 ( 30, 14) [000010] ------------ * RETURN int $1c2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target LIR
BB02 [0002] 2 BB01,BB02 4 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0003] 1 BB02 1 [000..001) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
( 5, 12) [000081] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x7fa5d4e14498 static Fseq[_bits] $100
/--* t98 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000080] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000084] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000083] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000113] ------------ t113 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000109] ------------ t109 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t113 long
+--* t109 long
N005 ( 2, 2) [000106] ------------ t106 = * PHI long
/--* t106 long
N007 ( 2, 3) [000107] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000115] ------------ t115 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000111] ------------ t111 = PHI_ARG int V04 tmp3 u:2 $80
/--* t115 int
+--* t111 int
N005 ( 2, 2) [000102] ------------ t102 = * PHI int
/--* t102 int
N007 ( 2, 3) [000103] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 1, 3) [000021] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR int V04 tmp3 u:3 $240
/--* t18 int
N003 ( 1, 3) [000020] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 7, 7) [000031] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V05 tmp4 u:2 (last use) $240
N002 ( 1, 1) [000023] ------------ t23 = LCL_VAR long V03 tmp2 u:3 $141
/--* t23 long
N003 ( 3, 2) [000024] *--XG------- t24 = * IND long <l:$142, c:$2c0>
/--* t24 long
N004 ( 4, 3) [000025] ---XG------- t25 = * HWIntrinsic long PopCount $300
/--* t25 long
N005 ( 5, 5) [000026] ---XG------- t26 = * CAST int <- long $340
/--* t22 int
+--* t26 int
N006 ( 7, 7) [000027] ---XG------- t27 = * SUB int $341
/--* t27 int
N008 ( 7, 7) [000030] DA-XG------- * STORE_LCL_VAR int V