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@daniestevez /hl2-bandscope-16384.patch
Created Jan 7, 2018

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Hermes-Lite 2 firmware patch for 16384 samples in bandscope FIFO
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hl2-bandscope-16384.patch
diff --git a/firmware/Polyphase_FIR/firram36.qip b/firmware/Polyphase_FIR/firram36.qip
index 06157a7..017ba13 100644
--- a/firmware/Polyphase_FIR/firram36.qip
+++ b/firmware/Polyphase_FIR/firram36.qip
@@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "14.0"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "firram36.v"]
diff --git a/firmware/Polyphase_FIR/firram36.v b/firmware/Polyphase_FIR/firram36.v
index 11e6b0b..cd6ac09 100644
--- a/firmware/Polyphase_FIR/firram36.v
+++ b/firmware/Polyphase_FIR/firram36.v
@@ -14,22 +14,22 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 14.0.1 Build 205 08/13/2014 SJ Web Edition
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
-//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
-//Your use of Altera Corporation's design tools, logic functions
+//Copyright (C) 2016 Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, the Altera Quartus II License Agreement,
-//the Altera MegaCore Function License Agreement, or other
+//to the terms and conditions of the Intel Program License
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
-//devices manufactured by Altera and sold by Altera or its
+//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
diff --git a/firmware/Polyphase_FIR/firram36I_1024.qip b/firmware/Polyphase_FIR/firram36I_1024.qip
index db53dc8..24c096f 100644
--- a/firmware/Polyphase_FIR/firram36I_1024.qip
+++ b/firmware/Polyphase_FIR/firram36I_1024.qip
@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "14.0"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "firram36I_1024.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "firram36I_1024_bb.v"]
diff --git a/firmware/Polyphase_FIR/firram36I_1024.v b/firmware/Polyphase_FIR/firram36I_1024.v
index 962b225..a0ab116 100644
--- a/firmware/Polyphase_FIR/firram36I_1024.v
+++ b/firmware/Polyphase_FIR/firram36I_1024.v
@@ -14,22 +14,22 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 14.0.1 Build 205 08/13/2014 SJ Web Edition
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
-//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
-//Your use of Altera Corporation's design tools, logic functions
+//Copyright (C) 2016 Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, the Altera Quartus II License Agreement,
-//the Altera MegaCore Function License Agreement, or other
+//to the terms and conditions of the Intel Program License
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
-//devices manufactured by Altera and sold by Altera or its
+//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
diff --git a/firmware/Polyphase_FIR/firromI_1024.qip b/firmware/Polyphase_FIR/firromI_1024.qip
index 8e11a57..bdc5c39 100644
--- a/firmware/Polyphase_FIR/firromI_1024.qip
+++ b/firmware/Polyphase_FIR/firromI_1024.qip
@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "14.0"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "firromI_1024.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "firromI_1024_bb.v"]
diff --git a/firmware/Polyphase_FIR/firromI_1024.v b/firmware/Polyphase_FIR/firromI_1024.v
index 8b3697c..46540c2 100644
--- a/firmware/Polyphase_FIR/firromI_1024.v
+++ b/firmware/Polyphase_FIR/firromI_1024.v
@@ -14,22 +14,22 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 14.0.1 Build 205 08/13/2014 SJ Web Edition
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
-//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
-//Your use of Altera Corporation's design tools, logic functions
+//Copyright (C) 2016 Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, the Altera Quartus II License Agreement,
-//the Altera MegaCore Function License Agreement, or other
+//to the terms and conditions of the Intel Program License
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
-//devices manufactured by Altera and sold by Altera or its
+//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
diff --git a/firmware/beta2.qsf b/firmware/beta2.qsf
index 5ff1bd3..040f48e 100755
--- a/firmware/beta2.qsf
+++ b/firmware/beta2.qsf
@@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EP4CE22E22C8
set_global_assignment -name TOP_LEVEL_ENTITY hermeslite
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:38:59 JUNE 27, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -216,12 +216,14 @@ set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name VERILOG_MACRO "BETA2=1"
+set_location_assignment CLKCTRL_G17 -to clock_ethrxint~clkctrl
+set_location_assignment CLKCTRL_G19 -to ethtxext_clkmux_i|auto_generated|clkctrl1
+set_location_assignment CLKCTRL_G15 -to ethtxint_clkmux_i|auto_generated|clkctrl1
set_global_assignment -name SDC_FILE hermeslite.sdc
set_global_assignment -name VERILOG_FILE rtl/hermeslite.v
set_global_assignment -name VERILOG_FILE rtl/ad9866.v
set_global_assignment -name VERILOG_FILE Polyphase_FIR/firfilt.v
set_global_assignment -name VERILOG_FILE Polyphase_FIR/CicInterpM5.v
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/firromI_1024.v
set_global_assignment -name QIP_FILE Polyphase_FIR/firromI_1024.qip
set_global_assignment -name VERILOG_FILE Polyphase_FIR/firram36I_1024.v
set_global_assignment -name QIP_FILE Polyphase_FIR/firram36I_1024.qip
@@ -294,7 +296,4 @@ set_global_assignment -name QIP_FILE cycloneip/SP_fifo.qip
set_global_assignment -name QIP_FILE cycloneip/PHY_fifo.qip
set_global_assignment -name QIP_FILE cycloneip/Tx_fifo.qip
set_global_assignment -name QIP_FILE cycloneip/PHY_Rx_fifo.qip
-set_location_assignment CLKCTRL_G17 -to clock_ethrxint~clkctrl
-set_location_assignment CLKCTRL_G19 -to ethtxext_clkmux_i|auto_generated|clkctrl1
-set_location_assignment CLKCTRL_G15 -to ethtxint_clkmux_i|auto_generated|clkctrl1
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/firmware/beta3.qsf b/firmware/beta3.qsf
index 4ff884c..dc88c84 100755
--- a/firmware/beta3.qsf
+++ b/firmware/beta3.qsf
@@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EP4CE22E22C8
set_global_assignment -name TOP_LEVEL_ENTITY hermeslite
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:54:43 JUNE 26, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -221,7 +221,6 @@ set_global_assignment -name VERILOG_FILE rtl/hermeslite.v
set_global_assignment -name VERILOG_FILE rtl/ad9866.v
set_global_assignment -name VERILOG_FILE Polyphase_FIR/firfilt.v
set_global_assignment -name VERILOG_FILE Polyphase_FIR/CicInterpM5.v
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/firromI_1024.v
set_global_assignment -name QIP_FILE Polyphase_FIR/firromI_1024.qip
set_global_assignment -name VERILOG_FILE Polyphase_FIR/firram36I_1024.v
set_global_assignment -name QIP_FILE Polyphase_FIR/firram36I_1024.qip
diff --git a/firmware/beta3_halfduplex.qsf b/firmware/beta3_halfduplex.qsf
index 5457390..3ce7b61 100755
--- a/firmware/beta3_halfduplex.qsf
+++ b/firmware/beta3_halfduplex.qsf
@@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EP4CE22E22C8
set_global_assignment -name TOP_LEVEL_ENTITY hermeslite
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:42:50 SEPTEMBER 09, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -192,7 +192,6 @@ set_global_assignment -name VERILOG_FILE rtl/hermeslite.v
set_global_assignment -name VERILOG_FILE rtl/ad9866.v
set_global_assignment -name VERILOG_FILE Polyphase_FIR/firfilt.v
set_global_assignment -name VERILOG_FILE Polyphase_FIR/CicInterpM5.v
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/firromI_1024.v
set_global_assignment -name QIP_FILE Polyphase_FIR/firromI_1024.qip
set_global_assignment -name VERILOG_FILE Polyphase_FIR/firram36I_1024.v
set_global_assignment -name QIP_FILE Polyphase_FIR/firram36I_1024.qip
diff --git a/firmware/beta5.qsf b/firmware/beta5.qsf
index 0ff03f3..b3295b0 100755
--- a/firmware/beta5.qsf
+++ b/firmware/beta5.qsf
@@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EP4CE22E22C8
set_global_assignment -name TOP_LEVEL_ENTITY hermeslite
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:06:31 NOVEMBER 30, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -221,7 +221,6 @@ set_global_assignment -name VERILOG_FILE rtl/hermeslite.v
set_global_assignment -name VERILOG_FILE rtl/ad9866.v
set_global_assignment -name VERILOG_FILE Polyphase_FIR/firfilt.v
set_global_assignment -name VERILOG_FILE Polyphase_FIR/CicInterpM5.v
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/firromI_1024.v
set_global_assignment -name QIP_FILE Polyphase_FIR/firromI_1024.qip
set_global_assignment -name VERILOG_FILE Polyphase_FIR/firram36I_1024.v
set_global_assignment -name QIP_FILE Polyphase_FIR/firram36I_1024.qip
diff --git a/firmware/cycloneip/PHY_Rx_fifo.qip b/firmware/cycloneip/PHY_Rx_fifo.qip
index bcf6c69..a7b6f56 100644
--- a/firmware/cycloneip/PHY_Rx_fifo.qip
+++ b/firmware/cycloneip/PHY_Rx_fifo.qip
@@ -1,4 +1,9 @@
-set_global_assignment -name IP_TOOL_NAME "FIFO"
-set_global_assignment -name IP_TOOL_VERSION "16.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PHY_Rx_fifo.v"]
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PHY_Rx_fifo.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PHY_Rx_fifo.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PHY_Rx_fifo_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PHY_Rx_fifo_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PHY_Rx_fifo.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PHY_Rx_fifo.cmp"]
diff --git a/firmware/cycloneip/PHY_Rx_fifo.v b/firmware/cycloneip/PHY_Rx_fifo.v
index eb42093..faef3b8 100644
--- a/firmware/cycloneip/PHY_Rx_fifo.v
+++ b/firmware/cycloneip/PHY_Rx_fifo.v
@@ -1,202 +1,203 @@
-// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: dcfifo_mixed_widths
-
-// ============================================================
-// File Name: PHY_Rx_fifo.v
-// Megafunction Name(s):
-// dcfifo_mixed_widths
-//
-// Simulation Library Files(s):
-//
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 16.1.2 Build 203 01/18/2017 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2017 Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Intel Program License
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel MegaCore Function License Agreement, or other
-//applicable license agreement, including, without limitation,
-//that your use is for the sole purpose of programming logic
-//devices manufactured by Intel and sold by Intel or its
-//authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module PHY_Rx_fifo (
- aclr,
- data,
- rdclk,
- rdreq,
- wrclk,
- wrreq,
- q,
- rdempty,
- rdfull,
- rdusedw,
- wrfull,
- wrusedw);
-
- input aclr;
- input [7:0] data;
- input rdclk;
- input rdreq;
- input wrclk;
- input wrreq;
- output [15:0] q;
- output rdempty;
- output rdfull;
- output [12:0] rdusedw;
- output wrfull;
- output [13:0] wrusedw;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri0 aclr;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
- wire [15:0] sub_wire0;
- wire sub_wire1;
- wire sub_wire2;
- wire [12:0] sub_wire3;
- wire sub_wire4;
- wire [13:0] sub_wire5;
- wire [15:0] q = sub_wire0[15:0];
- wire rdempty = sub_wire1;
- wire rdfull = sub_wire2;
- wire [12:0] rdusedw = sub_wire3[12:0];
- wire wrfull = sub_wire4;
- wire [13:0] wrusedw = sub_wire5[13:0];
-
- dcfifo_mixed_widths dcfifo_mixed_widths_component (
- .aclr (aclr),
- .data (data),
- .rdclk (rdclk),
- .rdreq (rdreq),
- .wrclk (wrclk),
- .wrreq (wrreq),
- .q (sub_wire0),
- .rdempty (sub_wire1),
- .rdfull (sub_wire2),
- .rdusedw (sub_wire3),
- .wrfull (sub_wire4),
- .wrusedw (sub_wire5),
- .eccstatus (),
- .wrempty ());
- defparam
- dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
- dcfifo_mixed_widths_component.lpm_numwords = 16384,
- dcfifo_mixed_widths_component.lpm_showahead = "OFF",
- dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
- dcfifo_mixed_widths_component.lpm_width = 8,
- dcfifo_mixed_widths_component.lpm_widthu = 14,
- dcfifo_mixed_widths_component.lpm_widthu_r = 13,
- dcfifo_mixed_widths_component.lpm_width_r = 16,
- dcfifo_mixed_widths_component.overflow_checking = "ON",
- dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
- dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
- dcfifo_mixed_widths_component.underflow_checking = "ON",
- dcfifo_mixed_widths_component.use_eab = "ON",
- dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
- dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "16384"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "8"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "16"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "1"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16384"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "14"
-// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "13"
-// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-// Retrieval info: USED_PORT: rdusedw 0 0 13 0 OUTPUT NODEFVAL "rdusedw[12..0]"
-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-// Retrieval info: USED_PORT: wrusedw 0 0 14 0 OUTPUT NODEFVAL "wrusedw[13..0]"
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 13 0 @rdusedw 0 0 13 0
-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 14 0 @wrusedw 0 0 14 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo_bb.v FALSE
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo_mixed_widths
+
+// ============================================================
+// File Name: PHY_Rx_fifo.v
+// Megafunction Name(s):
+// dcfifo_mixed_widths
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2016 Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Intel Program License
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other
+//applicable license agreement, including, without limitation,
+//that your use is for the sole purpose of programming logic
+//devices manufactured by Intel and sold by Intel or its
+//authorized distributors. Please refer to the applicable
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module PHY_Rx_fifo (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ rdfull,
+ rdusedw,
+ wrfull,
+ wrusedw);
+
+ input aclr;
+ input [7:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [15:0] q;
+ output rdempty;
+ output rdfull;
+ output [8:0] rdusedw;
+ output wrfull;
+ output [9:0] wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [15:0] sub_wire0;
+ wire sub_wire1;
+ wire sub_wire2;
+ wire [8:0] sub_wire3;
+ wire sub_wire4;
+ wire [9:0] sub_wire5;
+ wire [15:0] q = sub_wire0[15:0];
+ wire rdempty = sub_wire1;
+ wire rdfull = sub_wire2;
+ wire [8:0] rdusedw = sub_wire3[8:0];
+ wire wrfull = sub_wire4;
+ wire [9:0] wrusedw = sub_wire5[9:0];
+
+ dcfifo_mixed_widths dcfifo_mixed_widths_component (
+ .aclr (aclr),
+ .data (data),
+ .rdclk (rdclk),
+ .rdreq (rdreq),
+ .wrclk (wrclk),
+ .wrreq (wrreq),
+ .q (sub_wire0),
+ .rdempty (sub_wire1),
+ .rdfull (sub_wire2),
+ .rdusedw (sub_wire3),
+ .wrfull (sub_wire4),
+ .wrusedw (sub_wire5),
+ .eccstatus (),
+ .wrempty ());
+ defparam
+ dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
+ dcfifo_mixed_widths_component.lpm_numwords = 1024,
+ dcfifo_mixed_widths_component.lpm_showahead = "OFF",
+ dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
+ dcfifo_mixed_widths_component.lpm_width = 8,
+ dcfifo_mixed_widths_component.lpm_widthu = 10,
+ dcfifo_mixed_widths_component.lpm_widthu_r = 9,
+ dcfifo_mixed_widths_component.lpm_width_r = 16,
+ dcfifo_mixed_widths_component.overflow_checking = "ON",
+ dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
+ dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
+ dcfifo_mixed_widths_component.underflow_checking = "ON",
+ dcfifo_mixed_widths_component.use_eab = "ON",
+ dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
+ dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "8"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_Rx_fifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/firmware/cycloneip/PHY_fifo.qip b/firmware/cycloneip/PHY_fifo.qip
index d887eff..9bc86b4 100644
--- a/firmware/cycloneip/PHY_fifo.qip
+++ b/firmware/cycloneip/PHY_fifo.qip
@@ -1,4 +1,4 @@
-set_global_assignment -name IP_TOOL_NAME "FIFO"
-set_global_assignment -name IP_TOOL_VERSION "16.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone III}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PHY_fifo.v"]
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PHY_fifo.v"]
diff --git a/firmware/cycloneip/PHY_fifo.v b/firmware/cycloneip/PHY_fifo.v
index 5bc2d05..51bfc05 100644
--- a/firmware/cycloneip/PHY_fifo.v
+++ b/firmware/cycloneip/PHY_fifo.v
@@ -1,176 +1,177 @@
-// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: dcfifo
-
-// ============================================================
-// File Name: PHY_fifo.v
-// Megafunction Name(s):
-// dcfifo
-//
-// Simulation Library Files(s):
-//
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 16.1.2 Build 203 01/18/2017 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2017 Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Intel Program License
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel MegaCore Function License Agreement, or other
-//applicable license agreement, including, without limitation,
-//that your use is for the sole purpose of programming logic
-//devices manufactured by Intel and sold by Intel or its
-//authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module PHY_fifo (
- aclr,
- data,
- rdclk,
- rdreq,
- wrclk,
- wrreq,
- q,
- rdempty);
-
- input aclr;
- input [7:0] data;
- input rdclk;
- input rdreq;
- input wrclk;
- input wrreq;
- output [7:0] q;
- output rdempty;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri0 aclr;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
- wire [7:0] sub_wire0;
- wire sub_wire1;
- wire [7:0] q = sub_wire0[7:0];
- wire rdempty = sub_wire1;
-
- dcfifo dcfifo_component (
- .aclr (aclr),
- .data (data),
- .rdclk (rdclk),
- .rdreq (rdreq),
- .wrclk (wrclk),
- .wrreq (wrreq),
- .q (sub_wire0),
- .rdempty (sub_wire1),
- .eccstatus (),
- .rdfull (),
- .rdusedw (),
- .wrempty (),
- .wrfull (),
- .wrusedw ());
- defparam
- dcfifo_component.intended_device_family = "Cyclone III",
- dcfifo_component.lpm_numwords = 32,
- dcfifo_component.lpm_showahead = "OFF",
- dcfifo_component.lpm_type = "dcfifo",
- dcfifo_component.lpm_width = 8,
- dcfifo_component.lpm_widthu = 5,
- dcfifo_component.overflow_checking = "ON",
- dcfifo_component.rdsync_delaypipe = 4,
- dcfifo_component.read_aclr_synch = "OFF",
- dcfifo_component.underflow_checking = "ON",
- dcfifo_component.use_eab = "ON",
- dcfifo_component.write_aclr_synch = "OFF",
- dcfifo_component.wrsync_delaypipe = 4;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "32"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "8"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "8"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsFull NUMERIC "0"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo_bb.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo_waveforms.html FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo_wave*.jpg FALSE
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: PHY_fifo.v
+// Megafunction Name(s):
+// dcfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2016 Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Intel Program License
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other
+//applicable license agreement, including, without limitation,
+//that your use is for the sole purpose of programming logic
+//devices manufactured by Intel and sold by Intel or its
+//authorized distributors. Please refer to the applicable
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module PHY_fifo (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty);
+
+ input aclr;
+ input [7:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [7:0] q;
+ output rdempty;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [7:0] sub_wire0;
+ wire sub_wire1;
+ wire [7:0] q = sub_wire0[7:0];
+ wire rdempty = sub_wire1;
+
+ dcfifo dcfifo_component (
+ .aclr (aclr),
+ .data (data),
+ .rdclk (rdclk),
+ .rdreq (rdreq),
+ .wrclk (wrclk),
+ .wrreq (wrreq),
+ .q (sub_wire0),
+ .rdempty (sub_wire1),
+ .eccstatus (),
+ .rdfull (),
+ .rdusedw (),
+ .wrempty (),
+ .wrfull (),
+ .wrusedw ());
+ defparam
+ dcfifo_component.intended_device_family = "Cyclone IV E",
+ dcfifo_component.lpm_numwords = 32,
+ dcfifo_component.lpm_showahead = "OFF",
+ dcfifo_component.lpm_type = "dcfifo",
+ dcfifo_component.lpm_width = 8,
+ dcfifo_component.lpm_widthu = 5,
+ dcfifo_component.overflow_checking = "ON",
+ dcfifo_component.rdsync_delaypipe = 4,
+ dcfifo_component.read_aclr_synch = "OFF",
+ dcfifo_component.underflow_checking = "ON",
+ dcfifo_component.use_eab = "ON",
+ dcfifo_component.write_aclr_synch = "OFF",
+ dcfifo_component.wrsync_delaypipe = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "32"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "8"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "8"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL PHY_fifo_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/firmware/cycloneip/SP_fifo.qip b/firmware/cycloneip/SP_fifo.qip
index d75a3af..9c0dec1 100644
--- a/firmware/cycloneip/SP_fifo.qip
+++ b/firmware/cycloneip/SP_fifo.qip
@@ -1,4 +1,9 @@
-set_global_assignment -name IP_TOOL_NAME "FIFO"
-set_global_assignment -name IP_TOOL_VERSION "16.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone III}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "SP_fifo.v"]
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "SP_fifo.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SP_fifo.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SP_fifo_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SP_fifo_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SP_fifo.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SP_fifo.cmp"]
diff --git a/firmware/cycloneip/SP_fifo.v b/firmware/cycloneip/SP_fifo.v
index d106dc6..e7b6be3 100644
--- a/firmware/cycloneip/SP_fifo.v
+++ b/firmware/cycloneip/SP_fifo.v
@@ -1,196 +1,197 @@
-// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: dcfifo_mixed_widths
-
-// ============================================================
-// File Name: SP_fifo.v
-// Megafunction Name(s):
-// dcfifo_mixed_widths
-//
-// Simulation Library Files(s):
-//
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 16.1.2 Build 203 01/18/2017 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2017 Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Intel Program License
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel MegaCore Function License Agreement, or other
-//applicable license agreement, including, without limitation,
-//that your use is for the sole purpose of programming logic
-//devices manufactured by Intel and sold by Intel or its
-//authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module SP_fifo (
- aclr,
- data,
- rdclk,
- rdreq,
- wrclk,
- wrreq,
- q,
- rdempty,
- wrempty,
- wrfull,
- wrusedw);
-
- input aclr;
- input [15:0] data;
- input rdclk;
- input rdreq;
- input wrclk;
- input wrreq;
- output [7:0] q;
- output rdempty;
- output wrempty;
- output wrfull;
- output [10:0] wrusedw;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri0 aclr;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
- wire [7:0] sub_wire0;
- wire sub_wire1;
- wire sub_wire2;
- wire sub_wire3;
- wire [10:0] sub_wire4;
- wire [7:0] q = sub_wire0[7:0];
- wire rdempty = sub_wire1;
- wire wrempty = sub_wire2;
- wire wrfull = sub_wire3;
- wire [10:0] wrusedw = sub_wire4[10:0];
-
- dcfifo_mixed_widths dcfifo_mixed_widths_component (
- .aclr (aclr),
- .data (data),
- .rdclk (rdclk),
- .rdreq (rdreq),
- .wrclk (wrclk),
- .wrreq (wrreq),
- .q (sub_wire0),
- .rdempty (sub_wire1),
- .wrempty (sub_wire2),
- .wrfull (sub_wire3),
- .wrusedw (sub_wire4),
- .eccstatus (),
- .rdfull (),
- .rdusedw ());
- defparam
- dcfifo_mixed_widths_component.intended_device_family = "Cyclone III",
- dcfifo_mixed_widths_component.lpm_numwords = 2048,
- dcfifo_mixed_widths_component.lpm_showahead = "OFF",
- dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
- dcfifo_mixed_widths_component.lpm_width = 16,
- dcfifo_mixed_widths_component.lpm_widthu = 11,
- dcfifo_mixed_widths_component.lpm_widthu_r = 12,
- dcfifo_mixed_widths_component.lpm_width_r = 8,
- dcfifo_mixed_widths_component.overflow_checking = "ON",
- dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
- dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
- dcfifo_mixed_widths_component.underflow_checking = "ON",
- dcfifo_mixed_widths_component.use_eab = "ON",
- dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
- dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "2048"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "16"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "8"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "12"
-// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL "wrusedw[10..0]"
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo_bb.v FALSE
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo_mixed_widths
+
+// ============================================================
+// File Name: SP_fifo.v
+// Megafunction Name(s):
+// dcfifo_mixed_widths
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2016 Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Intel Program License
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other
+//applicable license agreement, including, without limitation,
+//that your use is for the sole purpose of programming logic
+//devices manufactured by Intel and sold by Intel or its
+//authorized distributors. Please refer to the applicable
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module SP_fifo (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ wrempty,
+ wrfull,
+ wrusedw);
+
+ input aclr;
+ input [15:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [7:0] q;
+ output rdempty;
+ output wrempty;
+ output wrfull;
+ output [13:0] wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [7:0] sub_wire0;
+ wire sub_wire1;
+ wire sub_wire2;
+ wire sub_wire3;
+ wire [13:0] sub_wire4;
+ wire [7:0] q = sub_wire0[7:0];
+ wire rdempty = sub_wire1;
+ wire wrempty = sub_wire2;
+ wire wrfull = sub_wire3;
+ wire [13:0] wrusedw = sub_wire4[13:0];
+
+ dcfifo_mixed_widths dcfifo_mixed_widths_component (
+ .aclr (aclr),
+ .data (data),
+ .rdclk (rdclk),
+ .rdreq (rdreq),
+ .wrclk (wrclk),
+ .wrreq (wrreq),
+ .q (sub_wire0),
+ .rdempty (sub_wire1),
+ .wrempty (sub_wire2),
+ .wrfull (sub_wire3),
+ .wrusedw (sub_wire4),
+ .eccstatus (),
+ .rdfull (),
+ .rdusedw ());
+ defparam
+ dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
+ dcfifo_mixed_widths_component.lpm_numwords = 16384,
+ dcfifo_mixed_widths_component.lpm_showahead = "OFF",
+ dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
+ dcfifo_mixed_widths_component.lpm_width = 16,
+ dcfifo_mixed_widths_component.lpm_widthu = 14,
+ dcfifo_mixed_widths_component.lpm_widthu_r = 15,
+ dcfifo_mixed_widths_component.lpm_width_r = 8,
+ dcfifo_mixed_widths_component.overflow_checking = "ON",
+ dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
+ dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
+ dcfifo_mixed_widths_component.underflow_checking = "ON",
+ dcfifo_mixed_widths_component.use_eab = "ON",
+ dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
+ dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "16384"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "8"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16384"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "14"
+// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "15"
+// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 14 0 OUTPUT NODEFVAL "wrusedw[13..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 14 0 @wrusedw 0 0 14 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL SP_fifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/firmware/hermeslite.qpf b/firmware/hermeslite.qpf
index 68dd4cf..6ec103f 100755
--- a/firmware/hermeslite.qpf
+++ b/firmware/hermeslite.qpf
@@ -1,35 +1,35 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2017 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other
-# applicable license agreement, including, without limitation,
-# that your use is for the sole purpose of programming logic
-# devices manufactured by Intel and sold by Intel or its
-# authorized distributors. Please refer to the applicable
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 16.1.2 Build 203 01/18/2017 SJ Lite Edition
-# Date created = 21:35:48 December 14, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "16.1"
-DATE = "21:35:48 December 14, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "beta5"
-PROJECT_REVISION = "beta2"
-PROJECT_REVISION = "beta3"
-PROJECT_REVISION = "beta3_halfduplex"
-PROJECT_REVISION = "hermeslite"
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2016 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Intel and sold by Intel or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+# Date created = 19:27:02 December 29, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.1"
+DATE = "19:27:02 December 29, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "beta2"
+PROJECT_REVISION = "beta5"
+PROJECT_REVISION = "beta3"
+PROJECT_REVISION = "beta3_halfduplex"
+PROJECT_REVISION = "hermeslite"
diff --git a/firmware/hermeslite.qsf b/firmware/hermeslite.qsf
index 1702001..6a794f7 100755
--- a/firmware/hermeslite.qsf
+++ b/firmware/hermeslite.qsf
@@ -37,232 +37,231 @@
# -------------------------------------------------------------------------- #
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE22E22C8
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE22E22C8
set_global_assignment -name TOP_LEVEL_ENTITY hermeslite
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:00 DECEMBER 21, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name ENABLE_OCT_DONE OFF
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_location_assignment PIN_72 -to clk_recovered
-set_location_assignment PIN_104 -to clk_scl1
-set_location_assignment PIN_103 -to clk_sda1
-set_location_assignment PIN_33 -to io_adc_scl
-set_location_assignment PIN_32 -to io_adc_sda
-set_location_assignment PIN_77 -to io_cn4_2
-set_location_assignment PIN_80 -to io_cn4_3
-set_location_assignment PIN_83 -to io_cn4_6
-set_location_assignment PIN_85 -to io_cn4_7
-set_location_assignment PIN_86 -to io_cn5_2
-set_location_assignment PIN_87 -to io_cn5_3
-set_location_assignment PIN_88 -to io_cn5_6
-set_location_assignment PIN_89 -to io_cn5_7
-set_location_assignment PIN_25 -to io_cn8
-set_location_assignment PIN_24 -to io_cn9
-set_location_assignment PIN_23 -to io_cn10
-set_location_assignment PIN_91 -to io_db22_2
-set_location_assignment PIN_90 -to io_db22_3
-set_location_assignment PIN_76 -to io_db24
-set_location_assignment PIN_98 -to io_led_d2
-set_location_assignment PIN_99 -to io_led_d3
-set_location_assignment PIN_100 -to io_led_d4
-set_location_assignment PIN_101 -to io_led_d5
-set_location_assignment PIN_31 -to io_scl2
-set_location_assignment PIN_30 -to io_sda2
-set_location_assignment PIN_55 -to io_tp2
-set_location_assignment PIN_52 -to phy_clk125
-set_location_assignment PIN_51 -to phy_mdc
-set_location_assignment PIN_50 -to phy_mdio
-set_location_assignment PIN_49 -to phy_rst_n
-set_location_assignment PIN_64 -to phy_rx[3]
-set_location_assignment PIN_60 -to phy_rx[2]
-set_location_assignment PIN_59 -to phy_rx[1]
-set_location_assignment PIN_58 -to phy_rx[0]
-set_location_assignment PIN_53 -to phy_rx_clk
-set_location_assignment PIN_54 -to phy_rx_dv
-set_location_assignment PIN_67 -to phy_tx[3]
-set_location_assignment PIN_68 -to phy_tx[2]
-set_location_assignment PIN_69 -to phy_tx[1]
-set_location_assignment PIN_71 -to phy_tx[0]
-set_location_assignment PIN_66 -to phy_tx_clk
-set_location_assignment PIN_65 -to phy_tx_en
-set_location_assignment PIN_46 -to pwr_clk1p2
-set_location_assignment PIN_44 -to pwr_clk3p3
-set_location_assignment PIN_43 -to pwr_clkvpa
-set_location_assignment PIN_42 -to pwr_envpa
-set_location_assignment PIN_126 -to rffe_ad9866_clk76p8
-set_location_assignment PIN_114 -to rffe_ad9866_pga[5]
-set_location_assignment PIN_113 -to rffe_ad9866_pga[4]
-set_location_assignment PIN_112 -to rffe_ad9866_pga[3]
-set_location_assignment PIN_111 -to rffe_ad9866_pga[2]
-set_location_assignment PIN_110 -to rffe_ad9866_pga[1]
-set_location_assignment PIN_106 -to rffe_ad9866_pga[0]
-set_location_assignment PIN_105 -to rffe_ad9866_rst_n
-set_location_assignment PIN_137 -to rffe_ad9866_rx[5]
-set_location_assignment PIN_136 -to rffe_ad9866_rx[4]
-set_location_assignment PIN_135 -to rffe_ad9866_rx[3]
-set_location_assignment PIN_133 -to rffe_ad9866_rx[2]
-set_location_assignment PIN_132 -to rffe_ad9866_rx[1]
-set_location_assignment PIN_129 -to rffe_ad9866_rx[0]
-set_location_assignment PIN_127 -to rffe_ad9866_rxclk
-set_location_assignment PIN_128 -to rffe_ad9866_rxsync
-set_location_assignment PIN_119 -to rffe_ad9866_sclk
-set_location_assignment PIN_120 -to rffe_ad9866_sdio
-set_location_assignment PIN_115 -to rffe_ad9866_sen_n
-set_location_assignment PIN_10 -to rffe_ad9866_tx[5]
-set_location_assignment PIN_7 -to rffe_ad9866_tx[4]
-set_location_assignment PIN_144 -to rffe_ad9866_tx[3]
-set_location_assignment PIN_143 -to rffe_ad9866_tx[2]
-set_location_assignment PIN_142 -to rffe_ad9866_tx[1]
-set_location_assignment PIN_141 -to rffe_ad9866_tx[0]
-set_location_assignment PIN_121 -to rffe_ad9866_txquiet_n
-set_location_assignment PIN_125 -to rffe_ad9866_txsync
-set_location_assignment PIN_11 -to rffe_rfsw_sel
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to pwr_envpa
-set_instance_assignment -name IO_STANDARD "2.5 V" -to pwr_clkvpa
-set_instance_assignment -name IO_STANDARD "2.5 V" -to pwr_clk3p3
-set_instance_assignment -name IO_STANDARD "2.5 V" -to pwr_clk1p2
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx_clk
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rst_n
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_mdio
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_mdc
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_clk125
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx_en
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx_clk
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx_dv
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx
-set_instance_assignment -name IO_STANDARD "2.5 V" -to io_tp2
-set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_recovered
-set_instance_assignment -name IO_STANDARD "2.5 V" -to io_db24
-set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn5_7
-set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn5_6
-set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn5_3
-set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn5_2
-set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn4_7
-set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn4_6
-set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn4_3
-set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn4_2
-set_location_assignment PIN_39 -to pa_en
-set_location_assignment PIN_28 -to pa_tr
-set_instance_assignment -name IO_STANDARD "2.5 V" -to pa_en
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:00 DECEMBER 21, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_location_assignment PIN_72 -to clk_recovered
+set_location_assignment PIN_104 -to clk_scl1
+set_location_assignment PIN_103 -to clk_sda1
+set_location_assignment PIN_33 -to io_adc_scl
+set_location_assignment PIN_32 -to io_adc_sda
+set_location_assignment PIN_77 -to io_cn4_2
+set_location_assignment PIN_80 -to io_cn4_3
+set_location_assignment PIN_83 -to io_cn4_6
+set_location_assignment PIN_85 -to io_cn4_7
+set_location_assignment PIN_86 -to io_cn5_2
+set_location_assignment PIN_87 -to io_cn5_3
+set_location_assignment PIN_88 -to io_cn5_6
+set_location_assignment PIN_89 -to io_cn5_7
+set_location_assignment PIN_25 -to io_cn8
+set_location_assignment PIN_24 -to io_cn9
+set_location_assignment PIN_23 -to io_cn10
+set_location_assignment PIN_91 -to io_db22_2
+set_location_assignment PIN_90 -to io_db22_3
+set_location_assignment PIN_76 -to io_db24
+set_location_assignment PIN_98 -to io_led_d2
+set_location_assignment PIN_99 -to io_led_d3
+set_location_assignment PIN_100 -to io_led_d4
+set_location_assignment PIN_101 -to io_led_d5
+set_location_assignment PIN_31 -to io_scl2
+set_location_assignment PIN_30 -to io_sda2
+set_location_assignment PIN_55 -to io_tp2
+set_location_assignment PIN_52 -to phy_clk125
+set_location_assignment PIN_51 -to phy_mdc
+set_location_assignment PIN_50 -to phy_mdio
+set_location_assignment PIN_49 -to phy_rst_n
+set_location_assignment PIN_64 -to phy_rx[3]
+set_location_assignment PIN_60 -to phy_rx[2]
+set_location_assignment PIN_59 -to phy_rx[1]
+set_location_assignment PIN_58 -to phy_rx[0]
+set_location_assignment PIN_53 -to phy_rx_clk
+set_location_assignment PIN_54 -to phy_rx_dv
+set_location_assignment PIN_67 -to phy_tx[3]
+set_location_assignment PIN_68 -to phy_tx[2]
+set_location_assignment PIN_69 -to phy_tx[1]
+set_location_assignment PIN_71 -to phy_tx[0]
+set_location_assignment PIN_66 -to phy_tx_clk
+set_location_assignment PIN_65 -to phy_tx_en
+set_location_assignment PIN_46 -to pwr_clk1p2
+set_location_assignment PIN_44 -to pwr_clk3p3
+set_location_assignment PIN_43 -to pwr_clkvpa
+set_location_assignment PIN_42 -to pwr_envpa
+set_location_assignment PIN_126 -to rffe_ad9866_clk76p8
+set_location_assignment PIN_114 -to rffe_ad9866_pga[5]
+set_location_assignment PIN_113 -to rffe_ad9866_pga[4]
+set_location_assignment PIN_112 -to rffe_ad9866_pga[3]
+set_location_assignment PIN_111 -to rffe_ad9866_pga[2]
+set_location_assignment PIN_110 -to rffe_ad9866_pga[1]
+set_location_assignment PIN_106 -to rffe_ad9866_pga[0]
+set_location_assignment PIN_105 -to rffe_ad9866_rst_n
+set_location_assignment PIN_137 -to rffe_ad9866_rx[5]
+set_location_assignment PIN_136 -to rffe_ad9866_rx[4]
+set_location_assignment PIN_135 -to rffe_ad9866_rx[3]
+set_location_assignment PIN_133 -to rffe_ad9866_rx[2]
+set_location_assignment PIN_132 -to rffe_ad9866_rx[1]
+set_location_assignment PIN_129 -to rffe_ad9866_rx[0]
+set_location_assignment PIN_127 -to rffe_ad9866_rxclk
+set_location_assignment PIN_128 -to rffe_ad9866_rxsync
+set_location_assignment PIN_119 -to rffe_ad9866_sclk
+set_location_assignment PIN_120 -to rffe_ad9866_sdio
+set_location_assignment PIN_115 -to rffe_ad9866_sen_n
+set_location_assignment PIN_10 -to rffe_ad9866_tx[5]
+set_location_assignment PIN_7 -to rffe_ad9866_tx[4]
+set_location_assignment PIN_144 -to rffe_ad9866_tx[3]
+set_location_assignment PIN_143 -to rffe_ad9866_tx[2]
+set_location_assignment PIN_142 -to rffe_ad9866_tx[1]
+set_location_assignment PIN_141 -to rffe_ad9866_tx[0]
+set_location_assignment PIN_121 -to rffe_ad9866_txquiet_n
+set_location_assignment PIN_125 -to rffe_ad9866_txsync
+set_location_assignment PIN_11 -to rffe_rfsw_sel
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pwr_envpa
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pwr_clkvpa
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pwr_clk3p3
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pwr_clk1p2
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx_clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rst_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_mdio
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_mdc
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_clk125
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx_en
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx_clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx_dv
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx
+set_instance_assignment -name IO_STANDARD "2.5 V" -to io_tp2
+set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_recovered
+set_instance_assignment -name IO_STANDARD "2.5 V" -to io_db24
+set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn5_7
+set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn5_6
+set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn5_3
+set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn5_2
+set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn4_7
+set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn4_6
+set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn4_3
+set_instance_assignment -name IO_STANDARD "2.5 V" -to io_cn4_2
+set_location_assignment PIN_39 -to pa_en
+set_location_assignment PIN_28 -to pa_tr
+set_instance_assignment -name IO_STANDARD "2.5 V" -to pa_en
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_location_assignment M9K_X33_Y5_N0 -to "ethernet:ethernet_inst|network:network_inst|icmp:icmp_inst|icmp_fifo:icmp_fifo_inst|scfifo:scfifo_component|scfifo_gf31:auto_generated|a_dpfifo_3731:dpfifo|altsyncram_dgh1:FIFOram"
+set_location_assignment M9K_X33_Y5_N0 -to "ethernet:ethernet_inst|network:network_inst|icmp:icmp_inst|icmp_fifo:icmp_fifo_inst|scfifo:scfifo_component|scfifo_gf31:auto_generated|a_dpfifo_3731:dpfifo|altsyncram_dgh1:FIFOram"
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-set_global_assignment -name SDC_FILE hermeslite.sdc
-set_global_assignment -name VERILOG_FILE rtl/hermeslite.v
-set_global_assignment -name VERILOG_FILE rtl/ad9866.v
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/firfilt.v
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/CicInterpM5.v
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/firromI_1024.v
-set_global_assignment -name QIP_FILE Polyphase_FIR/firromI_1024.qip
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/firram36I_1024.v
-set_global_assignment -name QIP_FILE Polyphase_FIR/firram36I_1024.qip
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/FirInterp8_1024.v
-set_global_assignment -name MIF_FILE Polyphase_FIR/coefI8_1024.mif
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/firram36.v
-set_global_assignment -name QIP_FILE Polyphase_FIR/firram36.qip
-set_global_assignment -name VERILOG_FILE Polyphase_FIR/firromH.v
-set_global_assignment -name QIP_FILE Polyphase_FIR/firromH.qip
-set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8H.mif
-set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8G.mif
-set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8F.mif
-set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8E.mif
-set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8D.mif
-set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8C.mif
-set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8B.mif
-set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8A.mif
-set_global_assignment -name TEXT_FILE Polyphase_FIR/coefL8.txt
-set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8.mif
-set_global_assignment -name LICENSE_FILE Polyphase_FIR/coefL8.dat
-set_global_assignment -name VERILOG_FILE rtl/sp_rcv_ctrl.v
-set_global_assignment -name VERILOG_FILE rtl/Led_flash.v
-set_global_assignment -name VERILOG_FILE rtl/varcic.v
-set_global_assignment -name VERILOG_FILE rtl/cdc_mcp.v
-set_global_assignment -name VERILOG_FILE rtl/cdc_sync.v
-set_global_assignment -name VERILOG_FILE rtl/cic.v
-set_global_assignment -name VERILOG_FILE rtl/cic_comb.v
-set_global_assignment -name VERILOG_FILE rtl/cic_integrator.v
-set_global_assignment -name VERILOG_FILE rtl/cordic.v
-set_global_assignment -name VERILOG_FILE rtl/cpl_cordic.v
-set_global_assignment -name VERILOG_FILE rtl/debounce.v
-set_global_assignment -name VERILOG_FILE rtl/FIFO.v
-set_global_assignment -name VERILOG_FILE rtl/Hermes_clk_lrclk_gen.v
-set_global_assignment -name VERILOG_FILE rtl/Hermes_Tx_fifo_ctrl.v
-set_global_assignment -name VERILOG_FILE rtl/pulsegen.v
-set_global_assignment -name VERILOG_FILE rtl/receiver.v
-set_global_assignment -name VERILOG_FILE rtl/i2c_master.v
-set_global_assignment -name VERILOG_FILE rtl/i2c_init.v
-set_global_assignment -name VERILOG_FILE rtl/i2c2_init.v
-set_global_assignment -name VERILOG_FILE rtl/i2c.v
-set_global_assignment -name VERILOG_FILE rtl/slow_adc.v
-set_global_assignment -name VERILOG_FILE rtl/cmd_wbm.v
-set_global_assignment -name VERILOG_FILE ethernet/cdc_sync.v
-set_global_assignment -name VERILOG_FILE ethernet/udp_send.v
-set_global_assignment -name VERILOG_FILE ethernet/udp_recv.v
-set_global_assignment -name VERILOG_FILE ethernet/sync.v
-set_global_assignment -name VERILOG_FILE ethernet/rgmii_send.v
-set_global_assignment -name VERILOG_FILE ethernet/rgmii_recv.v
-set_global_assignment -name VERILOG_FILE ethernet/phy_cfg.v
-set_global_assignment -name VERILOG_FILE ethernet/ethernet.v
-set_global_assignment -name VERILOG_FILE ethernet/network.v
-set_global_assignment -name VERILOG_FILE ethernet/mdio.v
-set_global_assignment -name VERILOG_FILE ethernet/mac_send.v
-set_global_assignment -name VERILOG_FILE ethernet/mac_recv.v
-set_global_assignment -name VERILOG_FILE ethernet/ip_send.v
-set_global_assignment -name VERILOG_FILE ethernet/ip_recv.v
-set_global_assignment -name QIP_FILE cycloneip/icmp_fifo.qip
-set_global_assignment -name VERILOG_FILE ethernet/icmp.v
-set_global_assignment -name VERILOG_FILE ethernet/dhcp.v
-set_global_assignment -name VERILOG_FILE cycloneip/ddio_out.v
-set_global_assignment -name VERILOG_FILE cycloneip/ddio_in.v
-set_global_assignment -name VERILOG_FILE ethernet/crc32.v
-set_global_assignment -name VERILOG_FILE ethernet/arp.v
-set_global_assignment -name VERILOG_FILE ethernet/Rx_recv.v
-set_global_assignment -name VERILOG_FILE ethernet/Tx_send.v
-set_global_assignment -name VERILOG_FILE rtl/axis_fifo.v
-set_global_assignment -name QIP_FILE cycloneip/ethpll.qip
-set_global_assignment -name QIP_FILE cycloneip/ad9866pll.qip
-set_global_assignment -name QIP_FILE cycloneip/SP_fifo.qip
-set_global_assignment -name QIP_FILE cycloneip/PHY_fifo.qip
-set_global_assignment -name QIP_FILE cycloneip/Tx_fifo.qip
-set_global_assignment -name QIP_FILE cycloneip/PHY_Rx_fifo.qip
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+set_global_assignment -name SDC_FILE hermeslite.sdc
+set_global_assignment -name VERILOG_FILE rtl/hermeslite.v
+set_global_assignment -name VERILOG_FILE rtl/ad9866.v
+set_global_assignment -name VERILOG_FILE Polyphase_FIR/firfilt.v
+set_global_assignment -name VERILOG_FILE Polyphase_FIR/CicInterpM5.v
+set_global_assignment -name QIP_FILE Polyphase_FIR/firromI_1024.qip
+set_global_assignment -name VERILOG_FILE Polyphase_FIR/firram36I_1024.v
+set_global_assignment -name QIP_FILE Polyphase_FIR/firram36I_1024.qip
+set_global_assignment -name VERILOG_FILE Polyphase_FIR/FirInterp8_1024.v
+set_global_assignment -name MIF_FILE Polyphase_FIR/coefI8_1024.mif
+set_global_assignment -name VERILOG_FILE Polyphase_FIR/firram36.v
+set_global_assignment -name QIP_FILE Polyphase_FIR/firram36.qip
+set_global_assignment -name VERILOG_FILE Polyphase_FIR/firromH.v
+set_global_assignment -name QIP_FILE Polyphase_FIR/firromH.qip
+set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8H.mif
+set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8G.mif
+set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8F.mif
+set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8E.mif
+set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8D.mif
+set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8C.mif
+set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8B.mif
+set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8A.mif
+set_global_assignment -name TEXT_FILE Polyphase_FIR/coefL8.txt
+set_global_assignment -name MIF_FILE Polyphase_FIR/coefL8.mif
+set_global_assignment -name LICENSE_FILE Polyphase_FIR/coefL8.dat
+set_global_assignment -name VERILOG_FILE rtl/sp_rcv_ctrl.v
+set_global_assignment -name VERILOG_FILE rtl/Led_flash.v
+set_global_assignment -name VERILOG_FILE rtl/varcic.v
+set_global_assignment -name VERILOG_FILE rtl/cdc_mcp.v
+set_global_assignment -name VERILOG_FILE rtl/cdc_sync.v
+set_global_assignment -name VERILOG_FILE rtl/cic.v
+set_global_assignment -name VERILOG_FILE rtl/cic_comb.v
+set_global_assignment -name VERILOG_FILE rtl/cic_integrator.v
+set_global_assignment -name VERILOG_FILE rtl/cordic.v
+set_global_assignment -name VERILOG_FILE rtl/cpl_cordic.v
+set_global_assignment -name VERILOG_FILE rtl/debounce.v
+set_global_assignment -name VERILOG_FILE rtl/FIFO.v
+set_global_assignment -name VERILOG_FILE rtl/Hermes_clk_lrclk_gen.v
+set_global_assignment -name VERILOG_FILE rtl/Hermes_Tx_fifo_ctrl.v
+set_global_assignment -name VERILOG_FILE rtl/pulsegen.v
+set_global_assignment -name VERILOG_FILE rtl/receiver.v
+set_global_assignment -name VERILOG_FILE rtl/i2c_master.v
+set_global_assignment -name VERILOG_FILE rtl/i2c_init.v
+set_global_assignment -name VERILOG_FILE rtl/i2c2_init.v
+set_global_assignment -name VERILOG_FILE rtl/i2c.v
+set_global_assignment -name VERILOG_FILE rtl/slow_adc.v
+set_global_assignment -name VERILOG_FILE rtl/cmd_wbm.v
+set_global_assignment -name VERILOG_FILE ethernet/cdc_sync.v
+set_global_assignment -name VERILOG_FILE ethernet/udp_send.v
+set_global_assignment -name VERILOG_FILE ethernet/udp_recv.v
+set_global_assignment -name VERILOG_FILE ethernet/sync.v
+set_global_assignment -name VERILOG_FILE ethernet/rgmii_send.v
+set_global_assignment -name VERILOG_FILE ethernet/rgmii_recv.v
+set_global_assignment -name VERILOG_FILE ethernet/phy_cfg.v
+set_global_assignment -name VERILOG_FILE ethernet/ethernet.v
+set_global_assignment -name VERILOG_FILE ethernet/network.v
+set_global_assignment -name VERILOG_FILE ethernet/mdio.v
+set_global_assignment -name VERILOG_FILE ethernet/mac_send.v
+set_global_assignment -name VERILOG_FILE ethernet/mac_recv.v
+set_global_assignment -name VERILOG_FILE ethernet/ip_send.v
+set_global_assignment -name VERILOG_FILE ethernet/ip_recv.v
+set_global_assignment -name QIP_FILE cycloneip/icmp_fifo.qip
+set_global_assignment -name VERILOG_FILE ethernet/icmp.v
+set_global_assignment -name VERILOG_FILE ethernet/dhcp.v
+set_global_assignment -name VERILOG_FILE cycloneip/ddio_out.v
+set_global_assignment -name VERILOG_FILE cycloneip/ddio_in.v
+set_global_assignment -name VERILOG_FILE ethernet/crc32.v
+set_global_assignment -name VERILOG_FILE ethernet/arp.v
+set_global_assignment -name VERILOG_FILE ethernet/Rx_recv.v
+set_global_assignment -name VERILOG_FILE ethernet/Tx_send.v
+set_global_assignment -name VERILOG_FILE rtl/axis_fifo.v
+set_global_assignment -name QIP_FILE cycloneip/ethpll.qip
+set_global_assignment -name QIP_FILE cycloneip/ad9866pll.qip
+set_global_assignment -name QIP_FILE cycloneip/SP_fifo.qip
+set_global_assignment -name QIP_FILE cycloneip/PHY_fifo.qip
+set_global_assignment -name QIP_FILE cycloneip/Tx_fifo.qip
+set_global_assignment -name QIP_FILE cycloneip/PHY_Rx_fifo.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/firmware/rtl/hermeslite.v b/firmware/rtl/hermeslite.v
index dccf249..c0e6b36 100755
--- a/firmware/rtl/hermeslite.v
+++ b/firmware/rtl/hermeslite.v
@@ -162,7 +162,7 @@ localparam RRRR = (CLK_FREQ == 61440000) ? 160 : (CLK_FREQ == 79872000) ? 208 :
// Number of Receivers
-localparam NR = 3; // number of receivers to implement
+localparam NR = 1; // number of receivers to implement
// Number of transmitters Be very careful when using more than 1 transmitter!
@@ -182,7 +182,7 @@ localparam Merc_serialno = 8'd00; // Use same value as equivalent Mercury
localparam RX_FIFO_SZ = 4096; // 16 by 4096 deep RX FIFO
localparam TX_FIFO_SZ = 1024; // 16 by 1024 deep TX FIFO
-localparam SP_FIFO_SZ = 2048; // 16 by 8192 deep SP FIFO, was 16384 but wouldn't fit
+localparam SP_FIFO_SZ = 16384;//2048; // 16 by 8192 deep SP FIFO, was 16384 but wouldn't fit
// Wishbone interconnect
localparam WB_DATA_WIDTH = 32;
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