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fc0012 for rtl-sdr (updated for saner reg values, GPIO handling and gain control)

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rtlsdr-fc0012.diff
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diff --git a/src/Makefile b/src/Makefile
index 4f66cf6..5cc3414 100644
--- a/src/Makefile
+++ b/src/Makefile
@@ -1,9 +1,9 @@
LDFLAGS=`pkg-config --libs libusb-1.0`
-CFLAGS=-Wall -O2 `pkg-config --cflags libusb-1.0`
+CFLAGS=-Wall -DDEBUG -O2 `pkg-config --cflags libusb-1.0`
all: rtl-sdr
-rtl-sdr: main.o tuner_e4000.o tuner_fc0013.c
+rtl-sdr: main.o tuner_e4000.o tuner_fc0013.o tuner_fc0012.o
$(CC) -o $@ $^ $(LDFLAGS)
clean:
diff --git a/src/main.c b/src/main.c
index 2643303..5dce454 100644
--- a/src/main.c
+++ b/src/main.c
@@ -27,6 +27,7 @@
#include <libusb.h>
#include "tuner_e4000.h"
+#include "tuner_fc0012.h"
#include "tuner_fc0013.h"
#define READLEN (16 * 16384)
@@ -41,14 +42,26 @@
#define NOXON_VID 0x0ccd
#define NOXON_PID 0x00b3
+/* GTek T803) */
+#define GTEK_VID 0x1f4d
+#define GTEK_T803_PID 0xb803
+
#define CRYSTAL_FREQ 28800000
+
+#ifdef DEBUG
+#define DEBUGF printf
+#else
+#define DEBUGF(...) ()
+#endif
+
static struct libusb_device_handle *devh = NULL;
static int do_exit = 0;
enum TUNER_TYPE {
TUNER_E4000,
- TUNER_FC0013
+ TUNER_FC0013,
+ TUNER_FC0012
} tuner_type;
static int find_device(void)
@@ -66,6 +79,12 @@ static int find_device(void)
printf("Found Terratec NOXON stick with FC0013 tuner\n");
return 0;
}
+ devh = libusb_open_device_with_vid_pid(NULL, GTEK_VID, GTEK_T803_PID);
+ if (devh > 0) {
+ tuner_type = TUNER_FC0012;
+ printf("Found GTEK T803 stick with FC0012 tuner\n");
+ return 0;
+ }
return -EIO;
}
@@ -244,9 +263,39 @@ void set_i2c_repeater(int on)
demod_write_reg(1, 0x01, on ? 0x18 : 0x10, 1);
}
+void dump_rtl_regs(void)
+{
+#ifdef DEBUG
+ unsigned char regBuf;
+ int i;
+
+ DEBUGF("\nRTL SYSB registers:\nreg 00 01 02 03 04 05 06 07 08 09 0a 0b 0c\nval");
+ for (i=0; i<=0xc; ++i)
+ {
+ regBuf = rtl_read_reg(SYSB, 0x3000+i, 1);
+ DEBUGF(" %02x",regBuf);
+ }
+ DEBUGF("\n");
+#endif
+}
+
+
+void rtl_set_gpio_bit(uint8_t bit, int val) {
+ uint8_t r;
+ bit = 1<<(bit-1);
+ r = rtl_read_reg(SYSB, GPO, 1);
+ if (val) {
+ r |= bit;
+ } else {
+ r &= (~bit);
+ }
+ rtl_write_reg(SYSB, GPO, r, 1);
+}
+
void rtl_init(void)
{
unsigned int i;
+ uint16_t r;
/* default FIR coefficients used for DAB/FM by the Windows driver,
* the DVB driver uses different ones */
@@ -260,10 +309,34 @@ void rtl_init(void)
rtl_write_reg(USBB, USB_EPA_MAXPKT, 0x0002, 2);
rtl_write_reg(USBB, USB_EPA_CTL, 0x1002, 2);
+ dump_rtl_regs();
+
/* poweron demod */
rtl_write_reg(SYSB, DEMOD_CTL_1, 0x22, 1);
rtl_write_reg(SYSB, DEMOD_CTL, 0xe8, 1);
+ if (tuner_type == TUNER_FC0012) {
+ dump_rtl_regs();
+ DEBUGF("reset fs0012 tuner... ");
+ /* the fs0012 has it's RESET line hooked up to GPIO5
+ *
+ * If we don't set GPIO5 to an output and leave it floating,
+ * the tuner never comes up (just stays in RESET state)
+ *
+ * GPIO6 controls the V/U band filter, so we should set that
+ * to an output too
+ */
+ r = rtl_read_reg(SYSB, GPD, 1);
+ r &= (~(0x30)); rtl_write_reg(SYSB, GPO, r, 1);
+ r = rtl_read_reg(SYSB, GPOE, 1);
+ r |= 0x30; rtl_write_reg(SYSB, GPOE, r, 1);
+
+ /* Do reset */
+ rtl_set_gpio_bit(5,1);
+ rtl_set_gpio_bit(5,0);
+ dump_rtl_regs();
+ }
+
/* reset demod (bit 3, soft_rst) */
demod_write_reg(1, 0x01, 0x14, 1);
demod_write_reg(1, 0x01, 0x10, 1);
@@ -300,6 +373,7 @@ void rtl_init(void)
void tuner_init(int frequency)
{
+ int ret;
set_i2c_repeater(1);
switch (tuner_type) {
@@ -309,8 +383,17 @@ void tuner_init(int frequency)
e4000_SetRfFreqHz(1, frequency);
break;
case TUNER_FC0013:
- FC0013_Open();
- FC0013_SetFrequency(frequency/1000, 8);
+ ret = FC0013_Open();
+ if (ret != FC0013_FUNCTION_SUCCESS) { printf("Couldn't open tuner!\n"); exit(1); }
+ ret = FC0013_SetFrequency(frequency/1000, 8);
+ if (ret != FC0013_FUNCTION_SUCCESS) { printf("Couldn't set frequency!\n"); exit(1); }
+ break;
+ case TUNER_FC0012:
+ ret = FC0012_Open();
+ if (ret != FC0012_OK) { printf("Couldn't open tuner!\n"); exit(1); }
+ //rtl_set_gpio_bit(6, (frequency > 300000000)); // Set U/V filters through gpio6
+ ret = FC0012_SetFrequency(frequency/1000, FC0012_BANDWIDTH_8MHZ);
+ if (ret != FC0012_OK) { printf("Couldn't set frequency!\n"); exit(1); }
break;
default:
printf("No valid tuner available!");
@@ -397,7 +480,7 @@ int main(int argc, char **argv)
/* Initialize tuner & set frequency */
tuner_init(frequency);
- file = fopen(filename, "wb");
+ file = fopen(filename, "wb+");
if (!file) {
printf("Failed to open %s\n", filename);
diff --git a/src/tuner_fc0012.c b/src/tuner_fc0012.c
new file mode 100644
index 0000000..c2df78b
--- /dev/null
+++ b/src/tuner_fc0012.c
@@ -0,0 +1,309 @@
+/*
+ * fc0012 tuner support for rtl-sdr
+ *
+ * Based on tuner_fc0012.c found as part of the (seemingly GPLed)
+ * rtl2832u Linux DVB driver.
+ *
+ * Rewritten and hacked into rtl-sdr by David Basden <davidb-sdr@rcpt.to>
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+
+#include "tuner_fc0012.h"
+#include "i2c.h"
+
+#define FC0012_I2C_ADDR 0xc6
+#define CRYSTAL_FREQ 28800000
+
+#define FC0012_LNAGAIN FC0012_LNA_GAIN_HI
+
+/* Incomplete list of register settings:
+ *
+ * Name Reg Bits Desc
+ * LNA_POWER_DOWN 0x06 0 Set to 1 to switch off low noise amp
+ * VCO_SPEED 0x06 3 Set the speed of the VCO. example
+ * driver hardcodes to 1 for some reason
+ * BANDWIDTH 0x06 6-7 Set bandwidth. 6MHz = 0x80, 7MHz=0x40
+ * 8MHz=0x00
+ * XTAL_SPEED 0x07 5 Set to 1 for 28.8MHz Crystal input
+ * or 0 for 36MHz
+ * EN_CAL_RSSI 0x09 4 Enable calibrate RSSI
+ * (Receive Signal Strength Indicator)
+ * LNA_FORCE 0x0d 0
+ * AGC_FORCE 0x0d ?
+ * LNA_GAIN 0x13 0-4 Low noise amp gain
+ * LNA_COMPS 0x15 3 ?
+ * VCO_CALIB 0x0e 7 Set high then low to calibrate VCO
+ *
+ */
+
+/* glue functions to rtl-sdr code */
+int FC0012_Write(unsigned char RegAddr, unsigned char Byte)
+{
+ uint8_t data[2];
+
+ data[0] = RegAddr;
+ data[1] = Byte;
+
+ if (rtl_i2c_write(FC0012_I2C_ADDR, data, 2) < 0)
+ return FC0012_ERROR;
+
+ return FC0012_OK;
+}
+
+int FC0012_Read(unsigned char RegAddr, unsigned char *pByte)
+{
+ uint8_t data = RegAddr;
+
+ if (rtl_i2c_write(FC0012_I2C_ADDR, &data, 1) < 0)
+ return FC0012_ERROR;
+ if (rtl_i2c_read(FC0012_I2C_ADDR, &data, 1) < 0)
+ return FC0012_ERROR;
+
+ *pByte = data;
+
+ return FC0012_OK;
+}
+
+#ifdef DEBUG
+#define DEBUGF printf
+#else
+#define DEBUGF(...) ()
+#endif
+
+void FC0012_Dump_Registers()
+{
+#ifdef DEBUG
+ unsigned char regBuf;
+ int ret;
+ int i;
+
+ DEBUGF("\nFC0012 registers:\n");
+ for (i=0; i<=0x15; ++i)
+ {
+ ret = FC0012_Read(i, &regBuf);
+ if (ret) DEBUGF("\nCouldn't read register %02x\n", i);
+ DEBUGF("R%x=%02x ",i,regBuf);
+ }
+ DEBUGF("\n");
+ FC0012_Read(0x06, &regBuf);
+ DEBUGF("LNA_POWER_DOWN:\t%s\n", regBuf & 1 ? "Powered down" : "Not Powered Down");
+ DEBUGF("VCO_SPEED:\t%s\n", regBuf & 0x8 ? "High speed" : "Slow speed");
+ DEBUGF("Bandwidth:\t%s\n", (regBuf & 0xC) ? "8MHz" : "less than 8MHz");
+ FC0012_Read(0x07, &regBuf);
+ DEBUGF("Crystal Speed:\t%s\n", (regBuf & 0x20) ? "28.8MHz" : "36MHZ<!>");
+ FC0012_Read(0x09, &regBuf);
+ DEBUGF("RSSI calibration mode:\t%s\n", (regBuf & 0x10) ? "RSSI CALIBRATION IN PROGRESS<!>" : "Disabled");
+ FC0012_Read(0x0d, &regBuf);
+ DEBUGF("LNA Force:\t%s\n", (regBuf & 0x1) ? "Forced" : "Not Forced");
+ FC0012_Read(0x13, &regBuf);
+ DEBUGF("LNA Gain:\t");
+ switch (regBuf) {
+ case (0x10): DEBUGF("19.7dB\n"); break;
+ case (0x17): DEBUGF("17.9dB\n"); break;
+ case (0x08): DEBUGF("7.1dB\n"); break;
+ case (0x02): DEBUGF("-9.9dB\n"); break;
+ default: DEBUGF("unknown gain value 0x02x\n");
+ }
+#endif
+}
+
+
+int FC0012_Open()
+{
+ DEBUGF("FC0012_Open start");
+ if (FC0012_Write(0x01, 0x05)) return -1;
+ if (FC0012_Write(0x02, 0x10)) return -1;
+ if (FC0012_Write(0x03, 0x00)) return -1;
+ if (FC0012_Write(0x04, 0x00)) return -1;
+ if (FC0012_Write(0x05, 0x0F)) return -1;
+ if (FC0012_Write(0x06, 0x00)) return -1; // divider 2, VCO slow
+ if (FC0012_Write(0x07, 0x20)) return -1; // change to 0x00 for a 36MHz crystal
+ if (FC0012_Write(0x08, 0xFF)) return -1; // AGC Clock divide by 254, AGC gain 1/256, Loop Bw 1/8
+ if (FC0012_Write(0x09, 0x6E)) return -1; // Disable LoopThrough
+ if (FC0012_Write(0x0A, 0xB8)) return -1; // Disable LO Test Buffer
+ if (FC0012_Write(0x0B, 0x82)) return -1; // Output Clock is same as clock frequency
+ //if (FC0012_Write(0x0C, 0xF8)) return -1;
+ if (FC0012_Write(0x0C, 0xFC)) return -1; // AGC up-down mode
+ if (FC0012_Write(0x0D, 0x02)) return -1; // AGC Not Forcing & LNA Forcing
+ if (FC0012_Write(0x0E, 0x00)) return -1;
+ if (FC0012_Write(0x0F, 0x00)) return -1;
+ if (FC0012_Write(0x10, 0x00)) return -1;
+ if (FC0012_Write(0x11, 0x00)) return -1;
+ if (FC0012_Write(0x12, 0x1F)) return -1; // Set to maximum gain
+ if (FC0012_Write(0x13, FC0012_LNAGAIN)) return -1;
+ if (FC0012_Write(0x14, 0x00)) return -1;
+ if (FC0012_Write(0x15, 0x04)) return -1; // Enable LNA COMPS
+
+ /* Black magic from nim_rtl2832_fc0012.c in DVB driver.
+ Even though we've set 0x11 to 0x00 above, this needs to happen to have
+ it go back
+ */
+ if (FC0012_Write(0x0d, 0x02)) return -1;
+ if (FC0012_Write(0x11, 0x00)) return -1;
+ if (FC0012_Write(0x15, 0x04)) return -1;
+
+ DEBUGF("FC0012_Open SUCCESS");
+ return FC0012_OK;
+}
+
+# if 0
+// Frequency is in kHz. Bandwidth is in MHz
+// This is pseudocode to set GPIO6 for VHF/UHF filter switching.
+// Trying to do this in reality leads to fail currently. I'm probably doing it wrong.
+void FC0012_Frequency_Control(unsigned int Frequency, unsigned short Bandwidth)
+{
+ if( Frequency < 260000 && Frequency > 150000 )
+ {
+ // set GPIO6 = low
+
+ // 1. Set tuner frequency
+ // 2. if the program quality is not good enough, switch to frequency + 500kHz
+ // 3. if the program quality is still no good, switch to frequency - 500kHz
+ }
+ else
+ {
+ // set GPIO6 = high
+
+ // set tuner frequency
+ }
+}
+#endif
+
+int FC0012_SetFrequency(unsigned long Frequency, unsigned short Bandwidth)
+{
+ int VCO1 = 0;
+ unsigned long doubleVCO;
+ unsigned short xin, xdiv;
+ unsigned char reg[21], am, pm, multi;
+ unsigned char read_byte;
+
+ unsigned long CrystalFreqKhz;
+
+ DEBUGF("FC0012_SetFrequency start");
+
+ CrystalFreqKhz = (CRYSTAL_FREQ + 500) / 1000;
+
+ //===================================== Select frequency divider and the frequency of VCO
+ if (Frequency * 96 < 3560000)
+ {
+ multi = 96; reg[5] = 0x82; reg[6] = 0x00;
+ }
+ else if (Frequency * 64 < 3560000)
+ {
+ multi = 64; reg[5] = 0x82; reg[6] = 0x02;
+ }
+ else if (Frequency * 48 < 3560000)
+ {
+ multi = 48; reg[5] = 0x42; reg[6] = 0x00;
+ }
+ else if (Frequency * 32 < 3560000)
+ {
+ multi = 32; reg[5] = 0x42; reg[6] = 0x02;
+ }
+ else if (Frequency * 24 < 3560000)
+ {
+ multi = 24; reg[5] = 0x22; reg[6] = 0x00;
+ }
+ else if (Frequency * 16 < 3560000)
+ {
+ multi = 16; reg[5] = 0x22; reg[6] = 0x02;
+ }
+ else if (Frequency * 12 < 3560000)
+ {
+ multi = 12; reg[5] = 0x12; reg[6] = 0x00;
+ }
+ else if (Frequency * 8 < 3560000)
+ {
+ multi = 8; reg[5] = 0x12; reg[6] = 0x02;
+ }
+ else if (Frequency * 6 < 3560000)
+ {
+ multi = 6; reg[5] = 0x0A; reg[6] = 0x00;
+ }
+ else
+ {
+ multi = 4; reg[5] = 0x0A; reg[6] = 0x02;
+ }
+
+ doubleVCO = Frequency * multi;
+
+ reg[6] = reg[6] | 0x08;
+ VCO1 = 1;
+ xdiv = (unsigned short)(doubleVCO / (CrystalFreqKhz / 2));
+ if( (doubleVCO - xdiv * (CrystalFreqKhz / 2)) >= (CrystalFreqKhz / 4) )
+ xdiv = xdiv + 1;
+
+ pm = (unsigned char)( xdiv / 8 );
+ am = (unsigned char)( xdiv - (8 * pm));
+
+ if (am < 2) {
+ reg[1] = am + 8;
+ reg[2] = pm - 1;
+ } else {
+ reg[1] = am;
+ reg[2] = pm;
+ }
+
+ // From VCO frequency determines the XIN ( fractional part of Delta Sigma PLL) and divided value (XDIV).
+ xin = (unsigned short)(doubleVCO - ((unsigned short)(doubleVCO / (CrystalFreqKhz / 2))) * (CrystalFreqKhz / 2));
+ xin = ((xin << 15)/(unsigned short)(CrystalFreqKhz / 2));
+ if( xin >= (unsigned short) 16384 )
+ xin = xin + (unsigned short) 32768;
+
+ reg[3] = (unsigned char)(xin >> 8);
+ reg[4] = (unsigned char)(xin & 0x00FF);
+
+ DEBUGF("Frequency: %lu, Fa: %d, Fp: %d, Xin:%d \n", Frequency, am, pm, xin);
+
+ switch(Bandwidth)
+ {
+ case 6: reg[6] = 0x80 | reg[6]; break;
+ case 7: reg[6] = (~0x80 & reg[6]) | 0x40; break;
+ case 8: default: reg[6] = ~0xC0 & reg[6]; break;
+ }
+
+ if (FC0012_Write(0x01, reg[1])) return -1;
+ if (FC0012_Write(0x02, reg[2])) return -1;
+ if (FC0012_Write(0x03, reg[3])) return -1;
+ if (FC0012_Write(0x04, reg[4])) return -1;
+ //reg[5] = reg[5] | 0x07; // This is really not cool. Why is it there?
+ // Same with hardcoding VCO=1
+ if (FC0012_Write(0x05, reg[5])) return -1;
+ if (FC0012_Write(0x06, reg[6])) return -1;
+
+ // VCO Calibration
+ if (FC0012_Write(0x0E, 0x80)) return -1;
+ if (FC0012_Write(0x0E, 0x00)) return -1;
+
+ // VCO Re-Calibration if needed
+ if (FC0012_Write(0x0E, 0x00)) return -1;
+ if (FC0012_Read(0x0E, &read_byte)) return -1;
+ reg[14] = 0x3F & read_byte;
+
+ if (VCO1)
+ {
+ if (reg[14] > 0x3C)
+ {
+ reg[6] = 0x08 | reg[6];
+
+ if (FC0012_Write(0x06, reg[6])) return -1;
+ if (FC0012_Write(0x0E, 0x80)) return -1;
+ if (FC0012_Write(0x0E, 0x00)) return -1;
+ }
+ }
+ else
+ {
+ if (reg[14] < 0x02) {
+ reg[6] = 0x08 | reg[6];
+
+ if (FC0012_Write(0x06, reg[6])) return -1;
+ if (FC0012_Write(0x0E, 0x80)) return -1;
+ if (FC0012_Write(0x0E, 0x00)) return -1;
+ }
+ }
+
+ DEBUGF("FC0012_SetFrequency SUCCESS"); FC0012_Dump_Registers();
+ return FC0012_OK;
+}
diff --git a/src/tuner_fc0012.h b/src/tuner_fc0012.h
new file mode 100644
index 0000000..85c04e6
--- /dev/null
+++ b/src/tuner_fc0012.h
@@ -0,0 +1,21 @@
+#ifndef __TUNER_FC0012_H
+#define __TUNER_FC0012_H
+
+#define FC0012_OK 0
+#define FC0012_ERROR 1
+
+#define FC0012_BANDWIDTH_6MHZ 6
+#define FC0012_BANDWIDTH_7MHZ 7
+#define FC0012_BANDWIDTH_8MHZ 8
+
+#define FC0012_LNA_GAIN_LOW 0x00
+#define FC0012_LNA_GAIN_MID 0x08
+#define FC0012_LNA_GAIN_HI 0x17
+#define FC0012_LNA_GAIN_MAX 0x10
+
+int FC0012_Open();
+int FC0012_Read(unsigned char RegAddr, unsigned char *pByte);
+int FC0012_Write(unsigned char RegAddr, unsigned char Byte);
+int FC0012_SetFrequency(unsigned long Frequency, unsigned short Bandwidth);
+
+#endif
diff --git a/src/tuner_fc0013.c b/src/tuner_fc0013.c
index 73b1ed9..8537ff9 100644
--- a/src/tuner_fc0013.c
+++ b/src/tuner_fc0013.c
@@ -7,6 +7,7 @@
*/
#include <stdint.h>
+#include "i2c.h"
#include "tuner_fc0013.h"
#define CRYSTAL_FREQ 28800000

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