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Last active October 6, 2024 17:34
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TC358743 Radxa Zero 3W Notes

Audio

tc358743-audio.dts overlay allows audio to be captured. I2S audio is a 48kHz sampling rate at 32 bit/sample.

Audio Formats

According to gstreamer, the following caps are supported. This seems to indicate that up to 8-channel audio (likely 7.1) capture is supported by the tc35874x driver. I haven't tested more than stereo, and haven't made sure it isn't just mono.

audio/x-raw, format={ (string)S32LE, (string)S24_32LE, (string)S16LE, (string)S8 }, layout=interleaved, rate=[ 8000, 192000 ], channels=2, channel-mask=0x0000000000000003
audio/x-raw, format={ (string)S32LE, (string)S24_32LE, (string)S16LE, (string)S8 }, layout=interleaved, rate=[ 8000, 192000 ], channels=3, channel-mask=0x000000000000000b
audio/x-raw, format={ (string)S32LE, (string)S24_32LE, (string)S16LE, (string)S8 }, layout=interleaved, rate=[ 8000, 192000 ], channels=4, channel-mask=0x0000000000000033
audio/x-raw, format={ (string)S32LE, (string)S24_32LE, (string)S16LE, (string)S8 }, layout=interleaved, rate=[ 8000, 192000 ], channels=6, channel-mask=0x000000000000003f
audio/x-raw, format={ (string)S32LE, (string)S24_32LE, (string)S16LE, (string)S8 }, layout=interleaved, rate=[ 8000, 192000 ], channels=8, channel-mask=0x0000000000000c3f

Video

Data path seems like it should be: sensor -> csi2_dphy -> mipi_csi -> rkcif_mipi_lvds

Despite creating the expected devices, etc, this doesn't seem to actually produce any video (revision #2 of the dts). The only way I could get something working was to link in the ISP. This doesn't seem like it'd be required. The docs aren't particularly clear on this, but they make it appear that the ISP is optional (or maybe only optional for non-bayer data).

It may be that the VICAP block only supports YCbCr 8-bit 4:2:2). But the TC358743XBG also claims to support output of RGB, YCbCr 4:4:4 and 4:2:2 both @ 8-bit. Maybe this is where exact pixel format becomes important. Potentially one in NV16 (4:2:2) and the other is YUYV. This would explain needing to involve the ISP in conversion, I guess...

pixel format mismatch?

Input that the driver detects is (via media-ctl) listed as:

fmt:UYVY8_2X8/1920x1080@10000/600000 field:none colorspace:smpte170m

And the output appears to be:

fmt:YUYV8_2X8/1920x1080 field:none colorspace:smpte170m

This seems to suggest the detected pixel format from the TC358743 is 8-bit UYVY, and it's converted to 8-bit YUYV for downstream consumption (into the vicap block). The difference appears to be ordering of data, while it's the same data:

format pixel 0 pixel 1 pixel 2 pixel 3
UYVY Cb Y Cr Y
YUYV Y Cb Y Cr

In order to do this, the ISP seems to be needed to do the conversion before it gets to the vicap, which makes the data available to v4l2, etc.

/dts-v1/;
/plugin/;
/ {
metadata {
title = "TC358743 HDMI RX Audio";
compatible = "radxa,zero3";
description = "Allow use of TC358743 HDMI -> CSI2 input I2S audio.";
category = "audio";
exclusive = "i2s3_2ch";
};
fragment@0 {
target-path = "/";
__overlay__ {
i2s_hdmi_in: tc358743-i2s {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,name = "tc358743-hdmiin";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
cpu_dai: simple-audio-card,cpu {
sound-dai = <&i2s3_2ch>;
};
codec_dai: simple-audio-card,codec {
sound-dai = <&tc358743_codec>;
};
};
};
};
fragment@1 {
target-path = "/";
__overlay__ {
tc358743_codec: tc358743-codec {
#sound-dai-cells = <0>;
compatible = "rockchip,dummy-codec";
status = "okay";
};
};
};
fragment@2 {
target = <&i2s3_2ch>;
__overlay__ {
status = "okay";
};
};
};
/dts-v1/;
/plugin/;
/ {
metadata {
title = "TC358743 HDMI RX";
compatible = "radxa,zero3";
description = "Allow use of TC358743 HDMI -> CSI2 input.";
category = "video";
};
fragment@0 {
target-path = "/";
__overlay__ {
clk_cam_27m: external-camera-clock-27m {
status = "okay";
compatible = "fixed-clock";
clock-frequency = <27000000>;
clock-output-names = "clk_cam_27mhz";
#clock-cells = <0>;
};
camera_pwdn_gpio: camera-pwdn-gpio {
status = "okay";
compatible = "regulator-fixed";
regulator-name = "camera_pwdn_gpio";
regulator-always-on;
regulator-boot-on;
enable-active-high;
// gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH> // Commented so no included needed.
gpio = <&gpio3 22 0>;
};
};
};
fragment@1 {
target = <&i2c2>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m1_xfer>;
#address-cells = <1>;
#size-cells = <0>;
camera_tc358743: tc358743@f {
status = "okay";
compatible = "toshiba,tc358743";
reg = <0x0f>;
clocks = <&clk_cam_27m>;
clock-names = "refclk";
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "tc358743";
rockchip,camera-module-lens-name = "default";
port {
hdmi_rx_out: endpoint {
remote-endpoint = <&mipi_in_hdmirx0>;
clock-lanes = <0>;
clock-noncontinuous;
link-frequencies = /bits/ 64 <297000000>;
data-lanes = <1 2 3 4>;
};
};
};
};
};
fragment@2 {
target = <&csi2_dphy_hw>;
__overlay__ {
status = "okay";
};
};
fragment@3 {
target = <&csi2_dphy0>;
__overlay__ {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_hdmirx0: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_rx_out>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_out_dphy0: endpoint@1 {
reg = <1>;
remote-endpoint = <&rkisp_mipi_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
};
fragment@4 {
target = <&rkisp_vir0>;
__overlay__ {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
rkisp_mipi_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_out_dphy0>;
};
};
};
};
fragment@5 {
target = <&rkisp>;
__overlay__ {
status = "okay";
};
};
fragment@6 {
target = <&rkisp_mmu>;
__overlay__ {
status = "okay";
};
};
fragment@7 {
target = <&rkcif_mmu>;
__overlay__ {
status = "okay";
};
};
fragment@8 {
target = <&rkcif>;
__overlay__ {
status = "okay";
};
};
};
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