Skip to content

Instantly share code, notes, and snippets.

View diningyo's full-sized avatar
😆
Learning Chisel!!

diningyo diningyo

😆
Learning Chisel!!
View GitHub Profile
@diningyo
diningyo / Top.dot.svg
Created February 24, 2019 12:37
Sodor 1st stage のトップブロックの構造
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
@diningyo
diningyo / SampleBundleRegInit2.v
Created April 27, 2019 05:12
BundleとRegInitで作る初期化済みレジスタ(コンパニオン・オブジェクト版)から生成したRTL
module SampleBundleRegInit2(
input clock,
input reset,
input io_en,
input [31:0] io_data,
output [3:0] io_out1_a,
output [3:0] io_out1_b,
output [3:0] io_out2_a,
output [3:0] io_out2_b
);
@diningyo
diningyo / iotester_option
Created June 20, 2019 14:48
chisel3.iotesters.Driverの引数
[info] Running chisel3.iotesters.Driver
Usage: chisel-testers [options] [<arg>...]
common options
-tn, --top-name <top-level-circuit-name>
This options defines the top level circuit, defaults to dut when possible
-td, --target-dir <target-directory>
This options defines a work directory for intermediate files, default is .
-ll, --log-level <Error|Warn|Info|Debug|Trace>
This options defines a work directory for intermediate files, default is .
@diningyo
diningyo / Idu.v
Last active November 23, 2020 11:58
Chisel 3.3.2 vs. Chisel 3.4.0 (dirv-idu moudle)
// Chisel 3.4.0 w/ compiler pulg-in version
module Idu(
input io_ifu2idu_valid,
output io_ifu2idu_ready,
input [31:0] io_ifu2idu_inst,
input io_idu2exu_inst_ready,
output io_idu2exu_inst_valid,
output [31:0] io_idu2exu_inst_bits_rawData,
output [6:0] io_idu2exu_inst_bits_funct7,
output [4:0] io_idu2exu_inst_bits_rs2,