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module SampleBundleRegInit2( | |
input clock, | |
input reset, | |
input io_en, | |
input [31:0] io_data, | |
output [3:0] io_out1_a, | |
output [3:0] io_out1_b, | |
output [3:0] io_out2_a, | |
output [3:0] io_out2_b | |
); |
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[info] Running chisel3.iotesters.Driver | |
Usage: chisel-testers [options] [<arg>...] | |
common options | |
-tn, --top-name <top-level-circuit-name> | |
This options defines the top level circuit, defaults to dut when possible | |
-td, --target-dir <target-directory> | |
This options defines a work directory for intermediate files, default is . | |
-ll, --log-level <Error|Warn|Info|Debug|Trace> | |
This options defines a work directory for intermediate files, default is . |
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// Chisel 3.4.0 w/ compiler pulg-in version | |
module Idu( | |
input io_ifu2idu_valid, | |
output io_ifu2idu_ready, | |
input [31:0] io_ifu2idu_inst, | |
input io_idu2exu_inst_ready, | |
output io_idu2exu_inst_valid, | |
output [31:0] io_idu2exu_inst_bits_rawData, | |
output [6:0] io_idu2exu_inst_bits_funct7, | |
output [4:0] io_idu2exu_inst_bits_rs2, |
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