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View fhdl.rs
use proc_macro2::{Span, TokenStream};
use quote::quote;
use syn::{
fold::Fold,
parse::{Parse, ParseStream, Result},
parse_quote,
punctuated::Punctuated,
Expr, ExprLit, FieldValue, Ident, ItemFn, LitStr, Local, Member, Pat, Stmt, Token,
};
@djg
djg / image.rs
Created Dec 16, 2018
WebRender ImageKey and ImageTemplate
View image.rs
#[cfg_attr(feature = "capture", derive(Serialize))]
#[cfg_attr(feature = "replay", derive(Deserialize))]
#[derive(Debug, Clone, Eq, PartialEq, Hash)]
pub struct ImageKey {
pub common: PrimKeyCommonData,
pub key: ApiImageKey,
pub stretch_size: SizeKey,
pub tile_spacing: SizeKey,
pub color: ColorU,
pub sub_rect: Option<DeviceIntRect>,
@djg
djg / gross.rs
Created Sep 14, 2018
SIMD in Rust is kinda gross.
View gross.rs
// Type your code here, or load an example.
#[cfg(target_arch = "x86")]
use std::arch::x86::__m128;
#[cfg(target_arch = "x86_64")]
use std::arch::x86_64::__m128;
#[cfg(all(any(target_arch = "x86", target_arch = "x86_64"), target_feature = "sse2"))]
pub struct Ray {
pub pt: __m128,
pub dir: __m128,
@djg
djg / halpstahp.rs
Created Sep 14, 2018
functional programming cry for help
View halpstahp.rs
pub fn hit_zip(aabb: &Aabb, r: &Ray, t_min: f32, t_max: f32) -> bool {
r.direction
.iter()
.zip(
r.point
.iter()
.zip(aabb.min.iter().zip(aabb.max.iter())),
).all(|(d, (p, (min, max)))| {
let inv_d = 1. / d;
let t0 = (min - p) * inv_d;
@djg
djg / after.cpp
Created Mar 15, 2018
verilated-rs generated binds to verilator simulation class.
View after.cpp
#include <Vtop.h>
extern "C" {
// CONSTRUCTORS
Vtop*
top_new() {
return new Vtop();
}
void
View unpack_sample.rs
// Samples are delta-encoded
pub fn unpack_sample<T: Default + ops::AddAssign + Clone>(input: &[u8])
-> Result<Vec<T>, &'static str> {
if input.len() % mem::size_of::<T>() != 0 {
return Err("packed sample data is not aligned");
}
let packed_sample: &[T] = unsafe {
slice::from_raw_parts(input.as_ptr() as *const T,
input.len() / mem::size_of::<T>())
@djg
djg / sample.rs
Created Jan 19, 2018
Rust future/result and_then style control flow.
View sample.rs
open_server_stream().ok()
.and_then(|stream| UnixStream::from_stream(stream, &handle).ok())
.and_then(|stream| bind_and_send_client(stream, &handle, &tx_rpc))
.ok_or_else(|| io::Error::new(
io::ErrorKind::Other,
"Failed to open stream and create rpc."
))
@djg
djg / two_8.8_one_reg.txt
Created Aug 14, 2017
Adding two numbers in one register
View two_8.8_one_reg.txt
Square by Pulse does this trick of adding two 8.8 fixed numbers in
"one 40-bit register" in the inner loop of it's pin-mapping routine. I
wonder if this is a known bit-twiddling trick documented some where?
(It feels like Lamport's 1976 paper where u is a 23 bit number)
Say we have u and v in 8.8 fixed point format and we want to increment
those by some signed deltas du and dv also in 8.8 fixed point.
I'll only consider a negative du because that seems to be an
interesting case in the code. Eg. let u = v = 64 = 64.00 = 0x4000 and
@djg
djg / reading-list.md
Last active Oct 23, 2019
Fabian's Recommened Reading List
View reading-list.md
@djg
djg / 0001-Fix-compilation-on-osx-with-cmake.patch
Created May 18, 2017
OpenSCAD: Fix compilation on OSX with cmake
View 0001-Fix-compilation-on-osx-with-cmake.patch
From 518dd61cfbdcaa4c8815f15ae484552125134d4b Mon Sep 17 00:00:00 2001
From: Dan Glastonbury <dglastonbury@mozilla.com>
Date: Thu, 18 May 2017 10:14:47 +1000
Subject: [PATCH] Fix compilation on osx with cmake.
---
CMakeLists.txt | 7 ++++++-
cmake/Modules/FindQt5QScintilla.cmake | 2 +-
src/AboutDialog.cc | 9 +++++++++
src/AboutDialog.h | 8 +-------
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