configure_pat.cc

static void mmu_configure_pat(void)
{
    // We are expecting this to be in the AP startup code before it enters
    // the threading system, and the BSP has the cache and MTRRs disabled
    // and is spinning waiting for this CPU to enter the threading system

    assert(!(cpu_eflags_get() & CPU_EFLAGS_IF));
    if (likely(cpuid_has_pat())) {
        // Intel manual vol 3 11.11.8 MTRR Considerations in MP Systems
        // for explanation of why all this
        
        cpu_cache_disable();
        
        // Manual specifically says you can skip flush if self snoop supported
        if (likely(!cpuid_has_self_snoop()))
            cpu_cache_flush();
        
        cpu_tlb_flush();
        
        // Disable the MTRRs
        cpu_msr_change_bits(CPU_MTRR_DEF_TYPE, 
            CPU_MTRR_DEF_TYPE_MTRR_EN | CPU_MTRR_DEF_TYPE_FIXED_EN, 0);
        
        // Now that we have utterly killed it and all memory access is UC,
        // and everything is a cache miss every time...
        
        // Change the PAT config
        cpu_msr_set(CPU_MSR_IA32_PAT, PAT_CFG);
        
        // Enable the MTRRs
        cpu_msr_change_bits(CPU_MTRR_DEF_TYPE, 
            0, CPU_MTRR_DEF_TYPE_MTRR_EN | CPU_MTRR_DEF_TYPE_FIXED_EN);
        
        // Intel manual vaguely implies that future processors might need this
        cpu_cache_flush();
        
        // Required on all out of order processors
        cpu_tlb_flush();
        
        cpu_cache_enable();
    }
}