dvtalk

1. Wait for an objection drop in other uvm component. phase.phase_done.wait_for(UVM_ALL_DROPPED, smthing_manager_component );
2. Check current objector that has not drop objection yet

phase.phase_done.get_objectors(tmp_q);
		$display(" check objection %d", tmp_q.size());
		$display(" check objection %d", tmp_q.size() - phase.get_objection_count(this));
		$display(" check objection %p", tmp_q);

dvtalk

• $display("Object handle var1 %p\n var2 %p", m_obj1, m_obj2);
• Not all simulators EDA support this.

dvtalk

Why using

• Avoid dependent between object.
• Avoid OOP restriction when use factory override.
  • For example: if we assign object directly top_env.module_a_agent.m_obj = m_obj; However, the m_obj only exist in the overriden type of module a agent --> issue.
• In sequence to get data, comp handle.

Why not using

• From uvm cookbook, intensive use of uvm_config_db slows simulation

• Only use with class type, not primitive type variable.

dvtalk

For testbench loop:

• Not found any solution,
• check forever and while(1) in all the code

For the design: using vcs with this

• compile: vcs +vcs+loopreport+20000
• run sim: simv +vcs+loopreport+1000000 (the simuation option will override the compile option)
• later VCS version will support start_time: simv +vcs+loopreport+1000000+start_time=1
• Use start_time to avoid loop at 0 simulation time (could have many loop caused by X value)
• If +start_time is not supported, incrase the number of loop value.

dvtalk

class base_test extend uvm_test;

   base_sequence m_seq;

//..
   set_type_override_by_type(base_sequence::get_type(), aes_sequence::get_type());

//..
   $display($psprintf("Sequence: %s", m_seq.get_type_name()));
// ...

dvtalk

Sure, here is an example of how you can use hdl_path_slice for backdoor register access in UVM RAL:

class ral_control_reg extends uvm_reg;
  rand uvm_reg_field rsvd;
  rand uvm_reg_field parity_en;
  rand uvm_reg_field dbg_en;
  rand uvm_reg_field mod_en;

  `uvm_object_utils(ral_control_reg)

dvtalk

m_var = 10;
#(m_var * 1ns); // delay 10 ns

dvtalk

+uvm_set_severity=uvm_test_top.env0.*,ALL,UVM_ERROR,UVM_WARNING
set_report_severity_id_verbosity_hier() in the test after the build_phase is complete.



// demote uvm error to warning


class uvm_reg_error_demoter extends uvm_report_catcher;
   function new(string name="uvm_reg_error_demoter");

dvtalk

      uvm_object_wrapper obj_wrapper = uvm_factory::get().find_override_by_name(<base class type>::type_id::type_name, "*");

dvtalk

1. A register will have multiple register fields:

   • Step: inside register build() function construct reg field m_reg_field_a --> m_reg_field_a.configure()

2. reg block will contains registers, and address maps block:

   • We can have multiple address map blocks inside a register block.
   • A register can be added to these address map blocks, meaning each register can have multiple address, and each address map has different access requirements