inifite loop debug in design

loop_vcs_cmd.md

For testbench loop:

• Not found any solution,
• check forever and while(1) in all the code

For the design: using vcs with this

• compile: vcs +vcs+loopreport+20000
• run sim: simv +vcs+loopreport+1000000 (the simuation option will override the compile option)
• later VCS version will support start_time: simv +vcs+loopreport+1000000+start_time=1
• Use start_time to avoid loop at 0 simulation time (could have many loop caused by X value)
• If +start_time is not supported, incrase the number of loop value.