UVM RAL and add_hdl_path_slice

sv

Sure, here is an example of how you can use hdl_path_slice for backdoor register access in UVM RAL:

class ral_control_reg extends uvm_reg;
  rand uvm_reg_field rsvd;
  rand uvm_reg_field parity_en;
  rand uvm_reg_field dbg_en;
  rand uvm_reg_field mod_en;

  `uvm_object_utils(ral_control_reg)

  function new(string name = "ral_control_reg");
    super.new(name, 32, build_coverage(UVM_NO_COVERAGE));
  endfunction

  virtual function void build();
    rsvd = uvm_reg_field::type_id::create("rsvd");
    parity_en = uvm_reg_field::type_id::create("parity_en");
    dbg_en = uvm_reg_field::type_id::create("dbg_en");
    mod_en = uvm_reg_field::type_id::create("mod_en");

    rsvd.configure     (this, 29, 3, "RO", 0, 1'b0, 1, 1, 0);
    parity_en.configure(this,  1, 2, "RW", 0, 1'b1, 1, 1, 0);
    dbg_en.configure   (this,  1, 1, "RW", 0, 1'b0, 1, 1, 0);
    mod_en.configure   (this,  1, 0, "RW", 0, 1'b1, 1, 1, 0);

    //To access BACKDOOR
    add_hdl_path_slice( .name("parity_en"), .offset(2), .size(1));
    add_hdl_path_slice( .name("dbg_en"   ), .offset(1), .size(1));
    add_hdl_path_slice( .name("mod_en"   ), .offset(0), .size(1));
  endfunction
endclass

In this example, add_hdl_path_slice is used to specify the backdoor path for each field in the ral_control_reg1. The name argument is the name of the field, offset is the bit position of the field in the register, and size is the width of the field1. Please make sure that the HDL path is correctly defined in your testbench1.

Sure, here is an example of how you can integrate the ral_control_reg class into a larger hierarchy and use add_hdl_path_slice to extend the hierarchy path of the instance:

class ral_block extends uvm_reg_block;
  rand ral_control_reg control_reg;
  rand ral_debug_reg debug_reg;

  `uvm_object_utils(ral_block)

  function new(string name = "ral_block");
    super.new(name, build_coverage(UVM_NO_COVERAGE));
  endfunction

  virtual function void build();
    control_reg = ral_control_reg::type_id::create("control_reg");
    debug_reg = ral_debug_reg::type_id::create("debug_reg");

    control_reg.configure(this, "");
    debug_reg.configure(this, "");

    // Add the registers to the block
    this.add_reg(control_reg, 'h0, "RW");
    this.add_reg(debug_reg, 'h4, "RW");

    // Extend the hierarchy path for the instance
    control_reg.add_hdl_path_slice("top.dut.control_reg", 0, 32);
    debug_reg.add_hdl_path_slice("top.dut.debug_reg", 0, 32);
  endfunction
endclass

In this example, the ral_block class is a register block that contains the control_reg and debug_reg registers1. The add_hdl_path_slice method is used to extend the hierarchy path for each register instance1. The first argument is the HDL path to the register in the DUT, the second argument is the bit offset, and the third argument is the size2. Please make sure that the HDL path is correctly defined in your testbench1
Sure, if you want to integrate the ral_block into a larger hierarchy, you can use add_hdl_path_slice to extend the hierarchy path of the block instance. Here’s an example:

class ral_top extends uvm_reg_block;
  rand ral_block block1;
  rand ral_block block2;

  `uvm_object_utils(ral_top)

  function new(string name = "ral_top");
    super.new(name, build_coverage(UVM_NO_COVERAGE));
  endfunction

  virtual function void build();
    block1 = ral_block::type_id::create("block1");
    block2 = ral_block::type_id::create("block2");

    block1.configure(this, "");
    block2.configure(this, "");

    // Add the blocks to the top block
    this.add_block(block1);
    this.add_block(block2);

    // Extend the hierarchy path for the instances
    block1.add_hdl_path_slice("top.dut.block1", 0, 32);
    block2.add_hdl_path_slice("top.dut.block2", 0, 32);
  endfunction
endclass

In this example, the ral_top class is a top-level block that contains two instances of the ral_block1. The add_hdl_path_slice method is used to extend the hierarchy path for each block instance1. The first argument is the HDL path to the block in the DUT, the second argument is the bit offset, and the third argument is the size2. Please make sure that the HDL path is correctly defined in your testbench1.