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• pack

class data_obj extends uvm_object
   virtual function void do_pack(uvm_packer packer);
      packer.pack_field_int(32'habcd_1234, 32); //DW0
      packer.pack_field_int(32'h0, 32);         //DW1
      packer.pack_field_int(32'h0, 32);         //DW2
      packer.pack_field_int(32'h0, 32);         //DW3
   endfunction: do_pack
   ...

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Sometimes an expression syntax that is easy to read and easy to write is useful, even ifthe syntax is not as expressive as the full power of posix regular expressions. A popularsubstitute for regular expressions is globs. A glob is a simplified regular expression. Itonly has three metacharacters -- *, +, and ?. Character ranges are not allowed anddots are not a metacharacter in globs as they are in regular expressions. The followingtable shows glob metacharacters.

UVM 1.1 Class Reference 142 UVM html 1.2 https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/index.html Check "uvm_resource" page

UVM cookbook 2018 page 30

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• $display("Object handle var1 %p\n var2 %p", m_obj1, m_obj2);
• Not all simulators EDA support this.

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Why using

• Avoid dependent between object.
• Avoid OOP restriction when use factory override.
  • For example: if we assign object directly top_env.module_a_agent.m_obj = m_obj; However, the m_obj only exist in the overriden type of module a agent --> issue.
• In sequence to get data, comp handle.

Why not using

• From uvm cookbook, intensive use of uvm_config_db slows simulation

• Only use with class type, not primitive type variable.

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For testbench loop:

• Not found any solution,
• check forever and while(1) in all the code

For the design: using vcs with this

• compile: vcs +vcs+loopreport+20000
• run sim: simv +vcs+loopreport+1000000 (the simuation option will override the compile option)
• later VCS version will support start_time: simv +vcs+loopreport+1000000+start_time=1
• Use start_time to avoid loop at 0 simulation time (could have many loop caused by X value)
• If +start_time is not supported, incrase the number of loop value.

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class base_test extend uvm_test;

   base_sequence m_seq;

//..
   set_type_override_by_type(base_sequence::get_type(), aes_sequence::get_type());

//..
   $display($psprintf("Sequence: %s", m_seq.get_type_name()));
// ...

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Sure, here is an example of how you can use hdl_path_slice for backdoor register access in UVM RAL:

class ral_control_reg extends uvm_reg;
  rand uvm_reg_field rsvd;
  rand uvm_reg_field parity_en;
  rand uvm_reg_field dbg_en;
  rand uvm_reg_field mod_en;

  `uvm_object_utils(ral_control_reg)

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// https://dvtalk.me/2021/08/29/systemverilog-dpi-example-with-aes-openssl-cmodel/
#ifndef __AES_C__
#define __AES_C__

#include "aes.h"
#include <openssl/conf.h>
#include <openssl/evp.h>
#include <openssl/err.h>
#include <stdio.h>
#include <stdlib.h>

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// https://dvtalk.me
// Example of using UVM do_compare() and do_copy();
// Should chain the function of parent classes
//
//       aes_data  m_obj_1, m_obj_2;
//       m_obj_2 = new();
//       
//   use copy():
//       m_obj_1 = new();        // must contruct m_obj_1, before call copy() function
//       m_obj_1.copy(m_obj_2);  

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// https://dvtalk.me
//

   //performance
   class perf_data;
      crypto_ip_idx_e m_ip_type;
      int             m_loop_idx;
      int             m_obj_id;
      time            m_start_time;
      time            m_end_time;