- DDR3 SDRAM has eight banks, which allows more efficient interleave
Output driver impedance (Ron), ODT and ZQ calibration
- The output driver impedence (Ron) of DQ, DQS, /DQS, and DM is selectable. Ron may fluctuate with PVR. DDR3 uses ZQ calibration.
- ODT (On Die Termination). A termination resistor is provided by the chip to suppress signal refection. ODT resistance Rtt can be adjusted by MR2.
- ZQ calibrate long to be issued during initialization. ZQ calibrate short to issue periodically during operation.
CLK-Dqs timing deskew
- Read levelling: DDR3 SDRAM outputs training pattern. Controller adjusts DQ and DQS captuing timing using MPR.
- Write levelling: DDR3 SDRAM outputs CLK-DQS skey information. Controller adjusts signal timing using the skew information so that the CMD, ADD, and CLK signals arrive at DDR3 at the same time as DQ, DM, and DQS signals.