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RISC-V User-Level ISA


  • ISA separated into small base ISA and support for extensions
  • JAL stores the address of the instruction following the jump (pc+4) into register rd. Calling convention is x1 as return address and x5 as alternate link register. Return address stack can be manipulated by JAL/JALR.
  • Aligned loads and stores are guaranteed to execute atomically, misaligned loads and stores are not
  • Each hart observes its own memory operations as if they are executed in sequential program order. RISC-V observes a relaxed memory model between harts. Explicit FENCE instructions are required to guarantee ordering between memory operations from different harts.
  • FENCE is used to order I/O and memory accesses as viewed by other RISC-V harts, external devices, and co-processors. No other hart or external device can observe any operation in the successor set following a FENCE operation before any operation in the predecessor set before the FENCE.

Atomic "A"

  • LR/SC there to support more efficient support of release consistency. AQ and RL bits specify additional ordering constraints as viewed by other harts. Bits order accesses to one or the address domains (mem or I/O). No memory ordering between domains. Use FENCE to order across domains.
    • When aq is set. Memory operations is treated as acquire, i.e. no following memory operations on this RISC-V can be observed before the acquire is complete
    • When rl, atomic memory is treated as release, i.e., the release memory operation can not be observed to take place before any earlier memory operations on this hart.
    • When aq and rl are set, full sequential consistency is required.
  • AMO (Atomic memory operations) were designed to implement C11 and C++11 memory models efficienly (i.e. to implement a lock)
  • Example instructions are SWAP, ADD, AND, OR, XOR, MAX, MIN, etc.

Floating "P"

  • fcsr defines the rounding mode, round to nearest, round to zero, round down, round up, etc.
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