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RISC-V Debug Spec

Chapter 2

Each hart in the platform is controlled by exactly one DM? But, usually all harts in a single core are controlled by the same DM.

Abstract commands provide access to GPRs. Addt. registers are accessible through abstract commands or by writing to the optional program buffer.

The program buffer allows the debugger to execute arbitrary instructions on a hart. A bus access block allows memory access without using a RISC-V hart to perform the access.

Chapter 3

Debug Modules (DM) are slaves to a bus called Debug Module Interface (DMI). The master bus is the Debug Transport Model (DTM).

See Table 3.7 for debug module debug bus registers. Rest of chapter explains the module usage.

Chapter 4

Debug mode is a special processor mode used only when a hart is halted for external debugging.

Upon entry to debug mode, dpc is updated with the virtual address of the next instruction to be executed.

Chapter 5

Triggers can cause a breakpoint exceptiojn, entry into Debug Mode, or a trace action without having to execute a special instruction.

Chapter 6

Debug Transport Modules provide access to the DM over one or more transports (e.g., JTAG).

JTAG DTM based around a normal JTAG TAP. The JTAG TAP allows access to arbitrary JTAG registers by first selecting the instruction register (IR) register then accessing it through the data register (DR).

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