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@edcote edcote/
Created Apr 9, 2018

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Timing constraints

Synplify users are recommended to use FDC format constraint files. I have found the TCL View and constraint syntax checker in constraint editor GUI to be helpful.

# clocks
create_clock -name {clk_20} [get_ports {clock}] -period 20
# inputs/output delays
set_input_delay  -clock {c:clk_20} -add_delay [expr {20*0.01}] [all_inputs]
set_output_delay -clock {c:clk_20} -add_delay [expr {20*0.01}] [all_outputs]


Make sure to set option auto_constraint_io to false. Options num_critical_paths and num_startend_points must be set to obtain meaningful timing reports.

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