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edcote / boomv2.md
Last active Oct 3, 2018
BOOM v2: An Open-Source OoO RISC-V Core
View boomv2.md

Notes

Link to tech report

Alpha 21264 has 15 FO4 delays. (FO4 delay is the delay of inverter, driven by an inverter 4x smaller than itself, and driving an interter 4x bigger than itself). BOOMv2 is 35 FO4.

BOOMv1 follows the 6-stage pipeline structure of MIPS R10K - fetch, decode/rename, issue/register-read, excute, memory, and writeback.

Frontend fetches instructions for execution in the backend.

@edcote
edcote / jenkins_docker.md
Last active Oct 3, 2018
Jenkins and Docker
View jenkins_docker.md

Goal

  • To deploy riscv-ci on docker, with preserved data.

    mkdir -p docker/riscv-ci cd docker/riscv-ci

Docker and Jenkins setup

  • Create an image on top of the Jenkins image with log, cache directories and java opts
@edcote
edcote / git.md
Last active Sep 19, 2018
GIT Notes
View git.md

GIT

Getting started

  • Clone repository

    • Upload your public key to Bitbucket/GitHub
    • Clone using command: git clone git@bitbucket.org:<username>/<repo>.git
  • Pull from master branch

    • Use command git pull
@edcote
edcote / uvm.md
Last active Sep 14, 2018
UVM Cookbook
View uvm.md

UVM Basics

UVM employs a layered, object-oriented approach to testbench development.

uvm_sequence_item is a uvm_object that contains data fields to implement protocols and communicate with with DUT. uvm_driver is responsible for converted the sequence item(s) into "pin wiggles". The sequence_item(s) are provided by one uvm_sequence objects that define stimulus at the transaction level and execute on the agent's uvm_sequencer component. The sequencer is responsible for executing the sequences, arbitrating between them, and routing sequence items between the driver and the sequence.

UVM agents have a configuration object that allows the test writer to control how the testbench is assembled and executed.

Components

@edcote
edcote / coverage_cookbook.md
Last active Sep 7, 2018
Coverage Cookbook
View coverage_cookbook.md

Theory

What doesn't get measured might not get done.

  • Covergroup should be wrapped in a class:
class my_cg_mon extends uvm_subscriber #(my_txn);

  covergroup my_cg;
View virtualbox.md

Notes

  • Start Ubuntu at command line

Edit /etc/defaults/grub.

#GRUB_CMDLINE_LINUX_DEFAULT="splash quiet"
GRUB_CMDLINE_LINUX="3"

sudo update-grub
@edcote
edcote / rock.md
Created Jul 31, 2018
Sun Rock Processor
View rock.md

I used to work on Rock. Getting around to re-read some papers on it.

SST: A Novel Architecture Implemented in Sun's ROCK Processor

SST hardware dynamically extracts two threads of execution from a single sequential program. SST uses an "efficient" checkpointing mechanism to eliminate the need for renaming logic, reorder buffer, memory disambiguation, issue windows, etc.

SST uses a traditional multithreaded pipeline with an additional mechanism to checkpoint the register file.

SST implements two hardware thread (ahead and behind). Ahead thread speculatively executes under a cache miss and speculatively retires instructions out of order. A behind thread executes instructions dependent on the cache miss.

@edcote
edcote / primer_consistency_coherence.md
Last active Jul 31, 2018
Primer on Memory Consistency and Cache Coherence
View primer_consistency_coherence.md

Chapter 1

Consistency models define correct shared memory behavior in terms of loads and stores without references to caches or coherence.

Chapter 2

  1. Single-Writer, Multiple-Read (Invariant): For any memory location A, at any given time, there exists only a single core that may write to A (and can also read it) ot some number of cores that may only read A.
  2. Data-Value Invariant: The value of the memory location at the start of an epoch is the same as the value of the memory location at the end of its last read-write epoch.

Chapter 3 - Memory Consistency Motivation and Sequential Consistency

@edcote
edcote / shen_lipasti.md
Last active Jul 31, 2018
Modern Processor Design - Shen, Lipasti
View shen_lipasti.md

Chapter 1

  • "Iron law": 1/Perf = time/program = instructions/program (cycle count) * cycles/instruction (CPI) * time/cycle (cycle time)
  • "Amdahl's law" = speedup = 1 / time = 1 / ((1-f)+(f/N))
    • speedup is limited by sequential bottlenec

Chapter 2

  • Three possible data dependences between two instructions, true (RAW), anti (WAR), and output (WAW). Also applies to memory data dependencies (not applicable in simple five stage pipeline).
  • There is also control dependencies.
@edcote
edcote / scala_for_ml.md
Last active Jul 18, 2018
Scala for Machine Learning
View scala_for_ml.md

Notes for 'Scala for Machine Learning, P. Nicolas" url

  • Chapter 1

Critical to understand the different classes of ML algorithms and to select the ones that are relevant to the domain.

ML problems are categorized as classification, prediction, optimization, and regression.

  • Classification is to extract knowledge for historical data. For example, a classifier can be built to identify a disease from a set of symptoms.
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