clock.rs

pub mod clock {
    use super::regs;

    pub fn init_system_clock() {
        regs::SYSCON().pdruncfg
            .set_sysosc_pd(regs::SYSCON_pdruncfg_sysosc_pd::POWERED);
        regs::SYSCON().sysoscctrl.ignoring_state()
            .set_bypass(regs::SYSCON_sysoscctrl_bypass::NOBYPASS)
            .set_freqrange(regs::SYSCON_sysoscctrl_freqrange::LOW);
        regs::SYSCON().syspllclksel.ignoring_state()
            .set_sel(regs::SYSCON_syspllclksel_sel::SYSTEM_OSCILLATOR);

        regs::SYSCON().syspllclkuen.ignoring_state()
            .set_ena(regs::SYSCON_syspllclkuen_ena::UPDATE_CLOCK_SOURCE);
        regs::SYSCON().syspllclkuen.ignoring_state()
            .set_ena(regs::SYSCON_syspllclkuen_ena::NO_CHANGE);
        regs::SYSCON().syspllclkuen.ignoring_state()
            .set_ena(regs::SYSCON_syspllclkuen_ena::UPDATE_CLOCK_SOURCE);

        loop {
            if regs::SYSCON().syspllclkuen.ena() == regs::SYSCON_syspllclkuen_ena::UPDATE_CLOCK_SOURCE {
                break
            }
        }
    }
}

test.rs

describe! clock {
    it "initializes system clock" {
        use ::clock;
        use volatile_cell::{VolatileCellReplayer, set_replayer};

        let mut replayer = VolatileCellReplayer::new();
        set_replayer(&mut replayer);

        replayer.expect_read( 0x4004_8238, 0x0000_EDF0);
        replayer.expect_write(0x4004_8238, 0x0000_EDD0);

        replayer.expect_write(0x4004_8020, 0x0000_0000);

        replayer.expect_write(0x4004_8040, 0x0000_0001);

        replayer.expect_write(0x4004_8044, 0x0000_0001);
        replayer.expect_write(0x4004_8044, 0x0000_0000);
        replayer.expect_write(0x4004_8044, 0x0000_0001);

        replayer.expect_read( 0x4004_8044, 0x0000_0000);
        replayer.expect_read( 0x4004_8044, 0x0000_0000);
        replayer.expect_read( 0x4004_8044, 0x0000_0000);
        replayer.expect_read( 0x4004_8044, 0x0000_0001);

        clock::init_system_clock();

        replayer.verify();
    }
}