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file.ll
; ModuleID = 'chip8_avr.cgu-0.rs'
source_filename = "chip8_avr.cgu-0.rs"
target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-n8"
target triple = "avr-atmel-none"
%str_slice = type { i8*, i16 }
%"libcore_mini::option::Option<chip8_engine::opcodes::Op>" = type { i16, [0 x i16], [3 x i16] }
%"chip8_engine::machine::Machine" = type { i16, [0 x i8], i16, [0 x i8], [16 x i16], [0 x i8], i16, [0 x i8], [16 x i8], [0 x i8] }
@_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE = internal global [84 x [6 x i8]] zeroinitializer, align 1
@_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE = internal unnamed_addr global i8 0, align 1
@str.0 = internal constant [58 x i8] c"/home/cactus/prog/rust/avr/chip8-engine-avr/src/machine.rs"
@panic_bounds_check_loc.1 = internal unnamed_addr constant { %str_slice, i32 } { %str_slice { i8* getelementptr inbounds ([58 x i8], [58 x i8]* @str.0, i32 0, i32 0), i16 58 }, i32 232 }, align 4
@panic_bounds_check_loc.2 = internal unnamed_addr constant { %str_slice, i32 } { %str_slice { i8* getelementptr inbounds ([58 x i8], [58 x i8]* @str.0, i32 0, i32 0), i16 58 }, i32 235 }, align 4
@"_ZN46_$LT$libcore_mini..option..Option$LT$T$GT$$GT$6unwrap14_MSG_FILE_LINE17h851ca770e1e941b6E" = external global { i32, [0 x i8], %str_slice, [0 x i8], %str_slice, [0 x i8] }
@str.3 = internal constant [11 x i8] c"src/main.rs"
@panic_bounds_check_loc.4 = internal unnamed_addr constant { %str_slice, i32 } { %str_slice { i8* getelementptr inbounds ([11 x i8], [11 x i8]* @str.3, i32 0, i32 0), i16 11 }, i32 92 }, align 4
; Function Attrs: norecurse nounwind readnone uwtable
define void @rust_eh_personality({}* nocapture, {}* nocapture) unnamed_addr #0 {
start:
ret void
}
; Function Attrs: noinline nounwind uwtable
define internal fastcc void @_ZN9chip8_avr7pcd85444send17ha4d7d9011426a038E() unnamed_addr #1 {
start:
%0 = load volatile i8, i8* inttoptr (i16 43 to i8*), align 1
%1 = and i8 %0, -16
store volatile i8 %1, i8* inttoptr (i16 43 to i8*), align 1
%2 = load volatile i8, i8* inttoptr (i16 43 to i8*), align 1
%3 = and i8 %2, -64
store volatile i8 %3, i8* inttoptr (i16 43 to i8*), align 1
store volatile i8 34, i8* inttoptr (i16 78 to i8*), align 2
br label %bb2.i
bb2.i: ; preds = %bb2.i, %start
%4 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
%5 = icmp sgt i8 %4, -1
br i1 %5, label %bb2.i, label %_ZN9chip8_avr3spi4sync17ha7796991a5161a60E.exit
_ZN9chip8_avr3spi4sync17ha7796991a5161a60E.exit: ; preds = %bb2.i
%6 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
store volatile i8 -128, i8* inttoptr (i16 78 to i8*), align 2
br label %bb2.i10
bb2.i10: ; preds = %bb2.i10, %_ZN9chip8_avr3spi4sync17ha7796991a5161a60E.exit
%7 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
%8 = icmp sgt i8 %7, -1
br i1 %8, label %bb2.i10, label %_ZN9chip8_avr3spi4sync17ha7796991a5161a60E.exit11
_ZN9chip8_avr3spi4sync17ha7796991a5161a60E.exit11: ; preds = %bb2.i10
%9 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
store volatile i8 64, i8* inttoptr (i16 78 to i8*), align 2
br label %bb2.i8
bb2.i8: ; preds = %bb2.i8, %_ZN9chip8_avr3spi4sync17ha7796991a5161a60E.exit11
%10 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
%11 = icmp sgt i8 %10, -1
br i1 %11, label %bb2.i8, label %_ZN9chip8_avr3spi4sync17ha7796991a5161a60E.exit9
_ZN9chip8_avr3spi4sync17ha7796991a5161a60E.exit9: ; preds = %bb2.i8
%12 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
%13 = load volatile i8, i8* inttoptr (i16 43 to i8*), align 1
%14 = or i8 %13, 32
store volatile i8 %14, i8* inttoptr (i16 43 to i8*), align 1
br label %bb21
bb12.loopexit: ; preds = %bb2.i4.5
%15 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
%16 = icmp eq [6 x i8]* %19, getelementptr inbounds ([84 x [6 x i8]], [84 x [6 x i8]]* @_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE, i16 1, i16 0)
br i1 %16, label %bb14, label %bb21
bb14: ; preds = %bb12.loopexit
%17 = load volatile i8, i8* inttoptr (i16 43 to i8*), align 1
%18 = or i8 %17, 8
store volatile i8 %18, i8* inttoptr (i16 43 to i8*), align 1
ret void
bb21: ; preds = %bb12.loopexit, %_ZN9chip8_avr3spi4sync17ha7796991a5161a60E.exit9
%iter.sroa.0.031 = phi [6 x i8]* [ getelementptr inbounds ([84 x [6 x i8]], [84 x [6 x i8]]* @_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE, i16 0, i16 0), %_ZN9chip8_avr3spi4sync17ha7796991a5161a60E.exit9 ], [ %19, %bb12.loopexit ]
%19 = getelementptr inbounds [6 x i8], [6 x i8]* %iter.sroa.0.031, i16 1
%20 = getelementptr inbounds [6 x i8], [6 x i8]* %iter.sroa.0.031, i16 0, i16 1
%21 = getelementptr inbounds [6 x i8], [6 x i8]* %iter.sroa.0.031, i16 0, i16 0
%22 = load i8, i8* %21, align 1
store volatile i8 %22, i8* inttoptr (i16 78 to i8*), align 2
br label %bb2.i4
bb2.i4: ; preds = %bb2.i4, %bb21
%23 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
%24 = icmp sgt i8 %23, -1
br i1 %24, label %bb2.i4, label %bb21.1
bb21.1: ; preds = %bb2.i4
%25 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
%26 = getelementptr inbounds [6 x i8], [6 x i8]* %iter.sroa.0.031, i16 0, i16 2
%27 = load i8, i8* %20, align 1
store volatile i8 %27, i8* inttoptr (i16 78 to i8*), align 2
br label %bb2.i4.1
bb2.i4.1: ; preds = %bb2.i4.1, %bb21.1
%28 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
%29 = icmp sgt i8 %28, -1
br i1 %29, label %bb2.i4.1, label %bb21.2
bb21.2: ; preds = %bb2.i4.1
%30 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
%31 = getelementptr inbounds [6 x i8], [6 x i8]* %iter.sroa.0.031, i16 0, i16 3
%32 = load i8, i8* %26, align 1
store volatile i8 %32, i8* inttoptr (i16 78 to i8*), align 2
br label %bb2.i4.2
bb2.i4.2: ; preds = %bb2.i4.2, %bb21.2
%33 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
%34 = icmp sgt i8 %33, -1
br i1 %34, label %bb2.i4.2, label %bb21.3
bb21.3: ; preds = %bb2.i4.2
%35 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
%36 = getelementptr inbounds [6 x i8], [6 x i8]* %iter.sroa.0.031, i16 0, i16 4
%37 = load i8, i8* %31, align 1
store volatile i8 %37, i8* inttoptr (i16 78 to i8*), align 2
br label %bb2.i4.3
bb2.i4.3: ; preds = %bb2.i4.3, %bb21.3
%38 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
%39 = icmp sgt i8 %38, -1
br i1 %39, label %bb2.i4.3, label %bb21.4
bb21.4: ; preds = %bb2.i4.3
%40 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
%41 = getelementptr inbounds [6 x i8], [6 x i8]* %iter.sroa.0.031, i16 0, i16 5
%42 = load i8, i8* %36, align 1
store volatile i8 %42, i8* inttoptr (i16 78 to i8*), align 2
br label %bb2.i4.4
bb2.i4.4: ; preds = %bb2.i4.4, %bb21.4
%43 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
%44 = icmp sgt i8 %43, -1
br i1 %44, label %bb2.i4.4, label %bb21.5
bb21.5: ; preds = %bb2.i4.4
%45 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
%46 = load i8, i8* %41, align 1
store volatile i8 %46, i8* inttoptr (i16 78 to i8*), align 2
br label %bb2.i4.5
bb2.i4.5: ; preds = %bb2.i4.5, %bb21.5
%47 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
%48 = icmp sgt i8 %47, -1
br i1 %48, label %bb2.i4.5, label %bb12.loopexit
}
; Function Attrs: nounwind uwtable
define avr_signalcc void @__vector_11() unnamed_addr #2 {
start:
%0 = load i8, i8* @_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE, align 1, !range !1
%1 = icmp eq i8 %0, 0
br i1 %1, label %_ZN9chip8_avr6redraw17ha921a84576a20039E.exit, label %bb1.i
bb1.i: ; preds = %start
tail call fastcc void @_ZN9chip8_avr7pcd85444send17ha4d7d9011426a038E() #5
store i8 0, i8* @_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE, align 1
br label %_ZN9chip8_avr6redraw17ha921a84576a20039E.exit
_ZN9chip8_avr6redraw17ha921a84576a20039E.exit: ; preds = %start, %bb1.i
ret void
}
; Function Attrs: nounwind uwtable
define void @main() unnamed_addr #2 personality void ({}*, {}*)* @rust_eh_personality {
start:
%_12.i = alloca %"libcore_mini::option::Option<chip8_engine::opcodes::Op>", align 8
%machine = alloca %"chip8_engine::machine::Machine", align 8
%0 = bitcast %"chip8_engine::machine::Machine"* %machine to i8*
call void @llvm.lifetime.start(i64 54, i8* nonnull %0)
call void @_ZN12chip8_engine7machine7Machine3new17h5d9b1122ec0b67d7E(%"chip8_engine::machine::Machine"* noalias nocapture nonnull sret dereferenceable(54) %machine) #5
%1 = getelementptr inbounds %"chip8_engine::machine::Machine", %"chip8_engine::machine::Machine"* %machine, i16 0, i32 2
%2 = load i16, i16* %1, align 2
%3 = add i16 %2, 2
store i16 %3, i16* %1, align 2
%4 = bitcast %"libcore_mini::option::Option<chip8_engine::opcodes::Op>"* %_12.i to i8*
call void @llvm.lifetime.start(i64 8, i8* nonnull %4) #5
call void @_ZN12chip8_engine7opcodes6decode17hf4e3bc0cfe15527dE(%"libcore_mini::option::Option<chip8_engine::opcodes::Op>"* noalias nocapture nonnull sret dereferenceable(8) %_12.i, i8 0, i8 0) #5
%self.sroa.0.0..sroa_idx.i.i = getelementptr inbounds %"libcore_mini::option::Option<chip8_engine::opcodes::Op>", %"libcore_mini::option::Option<chip8_engine::opcodes::Op>"* %_12.i, i16 0, i32 0
%self.sroa.0.0.copyload.i.i = load i16, i16* %self.sroa.0.0..sroa_idx.i.i, align 8, !alias.scope !2, !noalias !5
%self.sroa.4.i.sroa.4.0.self.sroa.4.0..sroa_cast3.i.sroa_raw_idx.i = getelementptr inbounds i8, i8* %4, i16 3
%self.sroa.4.i.sroa.4.0.copyload.i = load i8, i8* %self.sroa.4.i.sroa.4.0.self.sroa.4.0..sroa_cast3.i.sroa_raw_idx.i, align 1
%self.sroa.4.i.sroa.5.0.self.sroa.4.0..sroa_cast3.i.sroa_idx.i = getelementptr inbounds %"libcore_mini::option::Option<chip8_engine::opcodes::Op>", %"libcore_mini::option::Option<chip8_engine::opcodes::Op>"* %_12.i, i16 0, i32 2, i16 1
%self.sroa.4.i.sroa.5.0.self.sroa.4.0..sroa_cast3.i.sroa_cast.i = bitcast i16* %self.sroa.4.i.sroa.5.0.self.sroa.4.0..sroa_cast3.i.sroa_idx.i to i8*
%self.sroa.4.i.sroa.5.0.copyload.i = load i8, i8* %self.sroa.4.i.sroa.5.0.self.sroa.4.0..sroa_cast3.i.sroa_cast.i, align 2
%self.sroa.4.i.sroa.6.0.self.sroa.4.0..sroa_cast3.i.sroa_raw_idx.i = getelementptr inbounds i8, i8* %4, i16 5
%self.sroa.4.i.sroa.6.0.copyload.i = load i8, i8* %self.sroa.4.i.sroa.6.0.self.sroa.4.0..sroa_cast3.i.sroa_raw_idx.i, align 1
%cond.i.i = icmp eq i16 %self.sroa.0.0.copyload.i.i, 0
br i1 %cond.i.i, label %bb3.i.i, label %"_ZN46_$LT$libcore_mini..option..Option$LT$T$GT$$GT$6unwrap17h487731fe8c37b530E.exit.i"
bb3.i.i: ; preds = %start
tail call void @_ZN12libcore_mini9panicking5panic17hf8396a035740071dE({ i32, [0 x i8], %str_slice, [0 x i8], %str_slice, [0 x i8] }* noalias nonnull readonly dereferenceable(12) @"_ZN46_$LT$libcore_mini..option..Option$LT$T$GT$$GT$6unwrap14_MSG_FILE_LINE17h851ca770e1e941b6E") #5, !noalias !7
unreachable
"_ZN46_$LT$libcore_mini..option..Option$LT$T$GT$$GT$6unwrap17h487731fe8c37b530E.exit.i": ; preds = %start
%self.sroa.4.i.sroa.0.0.self.sroa.4.0..sroa_cast3.i.sroa_idx.i = getelementptr inbounds %"libcore_mini::option::Option<chip8_engine::opcodes::Op>", %"libcore_mini::option::Option<chip8_engine::opcodes::Op>"* %_12.i, i16 0, i32 2
%self.sroa.4.i.sroa.0.0.self.sroa.4.0..sroa_cast3.i.sroa_cast.i = bitcast [3 x i16]* %self.sroa.4.i.sroa.0.0.self.sroa.4.0..sroa_cast3.i.sroa_idx.i to i8*
%self.sroa.4.i.sroa.0.0.copyload.i = load i8, i8* %self.sroa.4.i.sroa.0.0.self.sroa.4.0..sroa_cast3.i.sroa_cast.i, align 2
call void @llvm.lifetime.end(i64 8, i8* nonnull %4) #5
%cond.i = icmp ne i8 %self.sroa.4.i.sroa.0.0.copyload.i, 13
%5 = icmp eq i8 %self.sroa.4.i.sroa.6.0.copyload.i, 0
%or.cond.i = or i1 %5, %cond.i
br i1 %or.cond.i, label %_ZN12chip8_engine7machine7Machine4step17hbe4bf8bf2822362fE.exit, label %bb12.lr.ph.i
bb12.lr.ph.i: ; preds = %"_ZN46_$LT$libcore_mini..option..Option$LT$T$GT$$GT$6unwrap17h487731fe8c37b530E.exit.i"
%6 = zext i8 %self.sroa.4.i.sroa.5.0.copyload.i to i16
%7 = icmp ult i8 %self.sroa.4.i.sroa.5.0.copyload.i, 16
%8 = zext i8 %self.sroa.4.i.sroa.4.0.copyload.i to i16
%9 = getelementptr inbounds %"chip8_engine::machine::Machine", %"chip8_engine::machine::Machine"* %machine, i16 0, i32 8, i16 %8
br i1 %7, label %bb12.us.i.preheader, label %panic.i, !prof !8
bb12.us.i.preheader: ; preds = %bb12.lr.ph.i
%10 = icmp ult i8 %self.sroa.4.i.sroa.4.0.copyload.i, 16
%11 = getelementptr inbounds %"chip8_engine::machine::Machine", %"chip8_engine::machine::Machine"* %machine, i16 0, i32 8, i16 %6
%12 = load i8, i8* %11, align 1
br i1 %10, label %bb12.us.i.preheader1, label %panic7.i.split, !prof !9
bb12.us.i.preheader1: ; preds = %bb12.us.i.preheader
%.pre = load i8, i8* %9, align 1
%13 = and i8 %.pre, 63
%14 = add nuw nsw i8 %13, 10
%15 = zext i8 %14 to i16
%16 = icmp ult i8 %14, 84
%17 = add i8 %.pre, 1
%18 = and i8 %17, 63
%19 = add nuw nsw i8 %18, 10
%20 = zext i8 %19 to i16
%21 = icmp ult i8 %19, 84
%22 = add i8 %.pre, 2
%23 = and i8 %22, 63
%24 = add nuw nsw i8 %23, 10
%25 = zext i8 %24 to i16
%26 = icmp ult i8 %24, 84
%27 = add i8 %.pre, 3
%28 = and i8 %27, 63
%29 = add nuw nsw i8 %28, 10
%30 = zext i8 %29 to i16
%31 = icmp ult i8 %29, 84
%32 = add i8 %.pre, 4
%33 = and i8 %32, 63
%34 = add nuw nsw i8 %33, 10
%35 = zext i8 %34 to i16
%36 = icmp ult i8 %34, 84
%37 = add i8 %.pre, 5
%38 = and i8 %37, 63
%39 = add nuw nsw i8 %38, 10
%40 = zext i8 %39 to i16
%41 = icmp ult i8 %39, 84
%42 = add i8 %.pre, 6
%43 = and i8 %42, 63
%44 = add nuw nsw i8 %43, 10
%45 = zext i8 %44 to i16
%46 = icmp ult i8 %44, 84
%47 = add i8 %.pre, 7
%48 = and i8 %47, 63
%49 = add nuw nsw i8 %48, 10
%50 = zext i8 %49 to i16
%51 = icmp ult i8 %49, 84
br label %bb12.us.i
bb12.us.i: ; preds = %bb12.us.i.preheader1, %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.7.i"
%iter.sroa.0.0.30.us.i = phi i8 [ %.iter.sroa.0.029.us.i, %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.7.i" ], [ 0, %bb12.us.i.preheader1 ]
%.iter.sroa.0.029.us.i = phi i8 [ %.iter.sroa.0.0.us.i, %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.7.i" ], [ 1, %bb12.us.i.preheader1 ]
%52 = add i8 %12, %iter.sroa.0.0.30.us.i
%53 = and i8 %52, 31
%54 = add nuw nsw i8 %53, 8
%55 = and i8 %52, 7
%56 = shl i8 1, %55
%57 = lshr i8 %54, 3
%58 = zext i8 %57 to i16
%59 = xor i8 %56, -1
br i1 %16, label %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.i", label %panic.i.i, !prof !8
"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.i": ; preds = %bb12.us.i
%60 = getelementptr inbounds [84 x [6 x i8]], [84 x [6 x i8]]* @_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE, i16 0, i16 %15, i16 %58
%61 = load i8, i8* %60, align 1
%62 = and i8 %61, %59
store i8 %62, i8* %60, align 1
store i8 1, i8* @_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE, align 1
br i1 %21, label %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.1.i", label %panic.i.i, !prof !8
panic.i.i: ; preds = %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.6.i", %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.5.i", %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.4.i", %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.3.i", %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.2.i", %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.1.i", %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.i", %bb12.us.i
%.lcssa.i = phi i16 [ %15, %bb12.us.i ], [ %20, %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.i" ], [ %25, %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.1.i" ], [ %30, %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.2.i" ], [ %35, %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.3.i" ], [ %40, %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.4.i" ], [ %45, %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.5.i" ], [ %50, %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.6.i" ]
tail call void @_ZN12libcore_mini9panicking18panic_bounds_check17h201496b58059e323E({ %str_slice, [0 x i8], i32, [0 x i8] }* bitcast ({ %str_slice, i32 }* @panic_bounds_check_loc.4 to { %str_slice, [0 x i8], i32, [0 x i8] }*), i16 %.lcssa.i, i16 84) #5
unreachable
panic.i: ; preds = %bb12.lr.ph.i
tail call void @_ZN12libcore_mini9panicking18panic_bounds_check17h201496b58059e323E({ %str_slice, [0 x i8], i32, [0 x i8] }* bitcast ({ %str_slice, i32 }* @panic_bounds_check_loc.1 to { %str_slice, [0 x i8], i32, [0 x i8] }*), i16 %6, i16 16) #5
unreachable
panic7.i.split: ; preds = %bb12.us.i.preheader
tail call void @_ZN12libcore_mini9panicking18panic_bounds_check17h201496b58059e323E({ %str_slice, [0 x i8], i32, [0 x i8] }* bitcast ({ %str_slice, i32 }* @panic_bounds_check_loc.2 to { %str_slice, [0 x i8], i32, [0 x i8] }*), i16 %8, i16 16) #5
unreachable
"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.1.i": ; preds = %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.i"
%63 = getelementptr inbounds [84 x [6 x i8]], [84 x [6 x i8]]* @_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE, i16 0, i16 %20, i16 %58
%64 = load i8, i8* %63, align 1
%65 = and i8 %64, %59
store i8 %65, i8* %63, align 1
store i8 1, i8* @_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE, align 1
br i1 %26, label %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.2.i", label %panic.i.i, !prof !8
"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.2.i": ; preds = %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.1.i"
%66 = getelementptr inbounds [84 x [6 x i8]], [84 x [6 x i8]]* @_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE, i16 0, i16 %25, i16 %58
%67 = load i8, i8* %66, align 1
%68 = and i8 %67, %59
store i8 %68, i8* %66, align 1
store i8 1, i8* @_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE, align 1
br i1 %31, label %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.3.i", label %panic.i.i, !prof !8
"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.3.i": ; preds = %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.2.i"
%69 = getelementptr inbounds [84 x [6 x i8]], [84 x [6 x i8]]* @_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE, i16 0, i16 %30, i16 %58
%70 = load i8, i8* %69, align 1
%71 = and i8 %70, %59
store i8 %71, i8* %69, align 1
store i8 1, i8* @_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE, align 1
br i1 %36, label %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.4.i", label %panic.i.i, !prof !8
"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.4.i": ; preds = %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.3.i"
%72 = getelementptr inbounds [84 x [6 x i8]], [84 x [6 x i8]]* @_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE, i16 0, i16 %35, i16 %58
%73 = load i8, i8* %72, align 1
%74 = and i8 %73, %59
store i8 %74, i8* %72, align 1
store i8 1, i8* @_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE, align 1
br i1 %41, label %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.5.i", label %panic.i.i, !prof !8
"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.5.i": ; preds = %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.4.i"
%75 = getelementptr inbounds [84 x [6 x i8]], [84 x [6 x i8]]* @_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE, i16 0, i16 %40, i16 %58
%76 = load i8, i8* %75, align 1
%77 = and i8 %76, %59
store i8 %77, i8* %75, align 1
store i8 1, i8* @_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE, align 1
br i1 %46, label %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.6.i", label %panic.i.i, !prof !8
"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.6.i": ; preds = %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.5.i"
%78 = getelementptr inbounds [84 x [6 x i8]], [84 x [6 x i8]]* @_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE, i16 0, i16 %45, i16 %58
%79 = load i8, i8* %78, align 1
%80 = and i8 %79, %59
store i8 %80, i8* %78, align 1
store i8 1, i8* @_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE, align 1
br i1 %51, label %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.7.i", label %panic.i.i, !prof !8
"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.7.i": ; preds = %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.6.i"
%81 = getelementptr inbounds [84 x [6 x i8]], [84 x [6 x i8]]* @_ZN9chip8_avr9FB_PIXELS17h37784e37313c02fcE, i16 0, i16 %50, i16 %58
%82 = load i8, i8* %81, align 1
%83 = and i8 %82, %59
store i8 %83, i8* %81, align 1
store i8 1, i8* @_ZN9chip8_avr8FB_DIRTY17h9ed51fcdff89accbE, align 1
%84 = icmp ult i8 %.iter.sroa.0.029.us.i, %self.sroa.4.i.sroa.6.0.copyload.i
%85 = zext i1 %84 to i8
%.iter.sroa.0.0.us.i = add i8 %85, %.iter.sroa.0.029.us.i
br i1 %84, label %bb12.us.i, label %_ZN12chip8_engine7machine7Machine4step17hbe4bf8bf2822362fE.exit.loopexit
_ZN12chip8_engine7machine7Machine4step17hbe4bf8bf2822362fE.exit.loopexit: ; preds = %"_ZN75_$LT$chip8_avr..Board$u20$as$u20$chip8_engine..peripherals..Peripherals$GT$9set_pixel17hee943df6a3c5cf5fE.exit.us.us.us.7.i"
br label %_ZN12chip8_engine7machine7Machine4step17hbe4bf8bf2822362fE.exit
_ZN12chip8_engine7machine7Machine4step17hbe4bf8bf2822362fE.exit: ; preds = %_ZN12chip8_engine7machine7Machine4step17hbe4bf8bf2822362fE.exit.loopexit, %"_ZN46_$LT$libcore_mini..option..Option$LT$T$GT$$GT$6unwrap17h487731fe8c37b530E.exit.i"
call void @llvm.lifetime.end(i64 54, i8* nonnull %0)
ret void
}
; Function Attrs: argmemonly nounwind
declare void @llvm.lifetime.start(i64, i8* nocapture) #3
; Function Attrs: argmemonly nounwind
declare void @llvm.lifetime.end(i64, i8* nocapture) #3
declare void @_ZN12chip8_engine7opcodes6decode17hf4e3bc0cfe15527dE(%"libcore_mini::option::Option<chip8_engine::opcodes::Op>"* noalias nocapture sret dereferenceable(8), i8, i8) unnamed_addr
; Function Attrs: cold noinline noreturn
declare void @_ZN12libcore_mini9panicking18panic_bounds_check17h201496b58059e323E({ %str_slice, [0 x i8], i32, [0 x i8] }* noalias readonly dereferenceable(8), i16, i16) unnamed_addr #4
; Function Attrs: cold noinline noreturn
declare void @_ZN12libcore_mini9panicking5panic17hf8396a035740071dE({ i32, [0 x i8], %str_slice, [0 x i8], %str_slice, [0 x i8] }* noalias readonly dereferenceable(12)) unnamed_addr #4
declare void @_ZN12chip8_engine7machine7Machine3new17h5d9b1122ec0b67d7E(%"chip8_engine::machine::Machine"* noalias nocapture sret dereferenceable(54)) unnamed_addr
attributes #0 = { norecurse nounwind readnone uwtable }
attributes #1 = { noinline nounwind uwtable }
attributes #2 = { nounwind uwtable }
attributes #3 = { argmemonly nounwind }
attributes #4 = { cold noinline noreturn }
attributes #5 = { nounwind }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"PIE Level", i32 2}
!1 = !{i8 0, i8 2}
!2 = !{!3}
!3 = distinct !{!3, !4, !"_ZN46_$LT$libcore_mini..option..Option$LT$T$GT$$GT$6unwrap17h487731fe8c37b530E: argument 1"}
!4 = distinct !{!4, !"_ZN46_$LT$libcore_mini..option..Option$LT$T$GT$$GT$6unwrap17h487731fe8c37b530E"}
!5 = !{!6}
!6 = distinct !{!6, !4, !"_ZN46_$LT$libcore_mini..option..Option$LT$T$GT$$GT$6unwrap17h487731fe8c37b530E: argument 0"}
!7 = !{!6, !3}
!8 = !{!"branch_weights", i32 2000, i32 1}
!9 = !{!"branch_weights", i32 1, i32 2000}
Raw
gistfile1.txt
LLVM ERROR: Cannot select: t44: i8 = rotl Constant:i8<-2>, t17
t43: i8 = Constant<-2>
t17: i8 = and t11, Constant:i8<7>
t11: i8 = add t8, t10
t8: i8,ch = CopyFromReg t0, Register:i8 %vreg6
t7: i8 = Register %vreg6
t10: i8,ch = CopyFromReg t0, Register:i8 %vreg23
t9: i8 = Register %vreg23
t16: i8 = Constant<7>
In function: main
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