View clk_summary
| clock enable_cnt prepare_cnt rate accuracy phase | |
| ---------------------------------------------------------------------------------------- | |
| spi0.1-tx_lo_dummy 0 0 1200000000 0 0 | |
| spi0.1-rx_lo_dummy 0 0 1200000000 0 0 | |
| spi0.0-tx_lo_dummy 0 0 1200000000 0 0 | |
| spi0.0-rx_lo_dummy 0 0 1200000000 0 0 | |
| clock-generator3 0 0 148499999 0 0 | |
| clock-generator2 0 0 299999997 0 0 | |
| ad9361_ext_refclk 8 8 10000000 0 0 | |
| spi0.1-bb_refclk 1 1 20000000 0 0 |
View system.dts
| /dts-v1/; | |
| / { | |
| compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| model = "ZynqMP ZCU102 Rev1.0"; | |
| cpus { | |
| #address-cells = <0x1>; |