zap adder example code

adder_wb.ino

/*
Wishbone Adder Example - A toy example to show adding two registers with the result read from a third.
based on template created 2014
by Jack Gassett
http://www.gadgetfactory.net
This example code is in the public domain.

Modified by Greg Samsa to create an adder example

*/


//This is what wishbone slot you are using
#define MYBASE IO_SLOT(9)
#define MYREG(x) REGISTER(MYBASE,x) 

void setup() {
  // put your setup code here, to run once:
  Serial.begin(9600);

  //Set our Wishbone registers to a value
  MYREG(0) = 9;
  MYREG(1) = 13;
 // MYREG(2) = 0xEE;       //8-bit register

}

void loop() {
  // put your main code here, to run repeatedly: 
  
  //Read and printout our Wishbone registers
  Serial.print("Register0: ");
  Serial.println(MYREG(0),DEC);
  Serial.print("Register1: ");
  Serial.println(MYREG(1),DEC);
  Serial.print("Register2: ");
  Serial.println(MYREG(2),DEC);

  Serial.println("");  
  delay(3000);
}




//This is what wishbone slot you are using
#define MYBASE IO_SLOT(9)
#define MYREG(x) REGISTER(MYBASE,x) 

void setup() {
  // put your setup code here, to run once:
  Serial.begin(9600);

  //Set our Wishbone registers to a value
  MYREG(0) = 9;
  MYREG(1) = 13;
 // MYREG(2) = 0xEE;       //8-bit register

}

void loop() {
  // put your main code here, to run repeatedly: 
  
  //Read and printout our Wishbone registers
  Serial.print("Register0: ");
  Serial.println(MYREG(0),DEC);
  Serial.print("Register1: ");
  Serial.println(MYREG(1),DEC);
  Serial.print("Register2: ");
  Serial.println(MYREG(2),DEC);

  Serial.println("");  
  delay(3000);
}

adder_wb.vhd

----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
-- Modified by Greg Samsa to create an toy adder
-- 
-- Create Date:    13:56:50 12/10/2013 
-- Design Name: 
-- Module Name: adder_wb 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity adder_wb is
  port (
  	 wishbone_in : in std_logic_vector(61 downto 0);
	 wishbone_out : out std_logic_vector(33 downto 0)
  );
end entity adder_wb;

architecture rtl of adder_wb is

--Define your registers here
  signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits) (input 1)
  signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) (input 2)

--Wishbone signals - Don't touch.
  signal  wb_clk_i:    std_logic;                     -- Wishbone clock
  signal  wb_rst_i:    std_logic;                     -- Wishbone reset (synchronous)
  signal  wb_dat_i:    std_logic_vector(31 downto 0); -- Wishbone data input  (32 bits)
  signal  wb_adr_i:    std_logic_vector(26 downto 2); -- Wishbone address input  (32 bits)
  signal  wb_we_i:     std_logic;                     -- Wishbone write enable signal
  signal  wb_cyc_i:    std_logic;                     -- Wishbone cycle signal
  signal  wb_stb_i:    std_logic;                     -- Wishbone strobe signal  

  signal  wb_dat_o:    std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
  signal  wb_ack_o:    std_logic;                      -- Wishbone acknowledge out signal
  signal  wb_inta_o:   std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
  wb_clk_i <= wishbone_in(61);
  wb_rst_i <= wishbone_in(60);
  wb_dat_i <= wishbone_in(59 downto 28);
  wb_adr_i <= wishbone_in(27 downto 3);
  wb_we_i <= wishbone_in(2);
  wb_cyc_i <= wishbone_in(1);
  wb_stb_i <= wishbone_in(0); 
  
  wishbone_out(33 downto 2) <= wb_dat_o;
  wishbone_out(1) <= wb_ack_o;
  wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals

  -- Asynchronous acknowledge
  wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';

  -- Multiplex the data output (asynchronous)
  process(register0, register1, wb_adr_i)
  begin
    -- Multiplex the read depending on the address. 
    -- Use only the 2 lowest bits of addr
    case wb_adr_i(3 downto 2) is
      when "00" => -- read the input of register 1 back
        wb_dat_o <= register0;
      when "01" => -- read the input of register 2 back
        wb_dat_o <= register1;
      when "10" => -- output to address 3
        wb_dat_o <= register0 + register1;  -- Output the sum of register0 + register1
      when others =>
        wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
    end case;
  end process;

  process(wb_clk_i)
  begin

    if rising_edge(wb_clk_i) then  -- Synchronous to the rising edge of the clock
      if wb_rst_i='1' then
        -- Reset request, put register0 and register1 with zeroes,
        register0 <= (others => '0');
        register1 <= (others => '0');

      else -- Not reset
        -- Check if someone is writing
        if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
          -- Yes, it's a write. See for which register based on address
          case wb_adr_i(3 downto 2) is
            when "00" =>
              register0 <= wb_dat_i;  -- Set register0
            when "01" =>
              register1 <= wb_dat_i;  -- Set register1
            when others =>
              null; -- Nothing to do for other addresses
          end case;
        end if;
      end if;
    end if;
  end process;
end rtl;