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# Generated file, editing void
# This file is part of the cyrite HDL suite
# (c) 202* section5.ch
from cyhdl import *
from cyrite.library.soc import Reg, BF
from cyrite.netpp_soc import mmr
from cyrite.netpp_soc.peripheral_cores import *
st7565_cmds_DATA_WIDTH = 8
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@hackfin
hackfin / conversion_vhdl.ipynb
Created August 22, 2024 10:49
Conversion from VHDL to cyHDL
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@hackfin
hackfin / myhdl_shifting.ipynb
Last active April 25, 2022 16:37
Shit bifting part 1
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