early_mmu.c

#define ARM64_MMU_VALID           (1UL << 0)
#define ARM64_MMU_TABLE           (1UL << 1)
#define ARM64_MMU_BLOCK           (0 << 1)
#define ARM64_MMU_XN              (1UL << 54)
#define ARM64_MMU_PXN             (1UL << 53)
#define ARM64_MMU_CONTIGUOUS      (1UL << 52)
#define ARM64_MMU_DBM             (1UL << 51)
#define ARM64_MMU_nG              (1UL << 11)
#define ARM64_MMU_AF              (1UL << 10)
#define ARM64_MMU_NON_SHAREABLE   (0 << 8)
#define ARM64_MMU_OUTER_SHAREABLE (1 << 9)
#define ARM64_MMU_INNER_SHAREABLE (3 << 8)
#define ARM64_MMU_WRITEABLE       (1 << 7)
#define ARM64_MMU_EL0             (1 << 6)

__attribute__((section(".boot"))) __attribute__((no_sanitize("undefined"))) void arm64_setup_mmu(
    uint64_t *boot_page_tables, uint64_t phys_base)
{
    uint64_t *top_page_table = boot_page_tables;
    uint64_t *second_level[2] = {&boot_page_tables[512], &boot_page_tables[1024]};
    uint64_t *third_level = &boot_page_tables[512UL * 3];

    top_page_table[0] = ((uint64_t) second_level[0] >> 12) << 12 | ARM64_MMU_TABLE;
    top_page_table[511] = ((uint64_t) second_level[1] >> 12) << 12 | ARM64_MMU_TABLE;

    const uint64_t prot = ARM64_MMU_WRITEABLE | ARM64_MMU_INNER_SHAREABLE | ARM64_MMU_BLOCK;
    second_level[0][0] = 0 | prot;
    second_level[0][1] = 0x40000000 | prot;
    second_level[0][2] = 0x80000000 | prot;
    second_level[0][3] = 0xc0000000 | prot;

    second_level[1][510] =
        (uint64_t) third_level | ARM64_MMU_WRITEABLE | ARM64_MMU_INNER_SHAREABLE | ARM64_MMU_TABLE;

    for (unsigned int i = 0; i < 512; i++)
    {
        third_level[i] = phys_base | prot;
        phys_base += 0x200000;
    }
}