An example myhdl sim showing an earlier sim stepping on the toes of a later one.

confused_sim.py

from myhdl import *

PERIOD = 10

A = Signal(intbv(0)[25:])
clock = Signal(bool(0))
reset = ResetSignal(0, async=False, active=1)

def ClockSource(clock):

    @instance
    def clockgen():
        while True:
            yield(delay(PERIOD//2))
            clock.next = not clock

    return clockgen

def Foo(A, clock, reset):

    @always_seq(clock.posedge, reset)
    def bar():
        print A

    return bar

def Source(signal, clock, reset):

    state = [0]

    @always_seq(clock.posedge, reset)
    def source_inst():

        signal.next = state[0]
        state[0] = state[0] + 1


    return source_inst

cycles = 4
instances = [Foo(A, clock, reset), Source(A, clock, reset), ClockSource(clock)]
sim = Simulation(instances)
sim.run(duration=cycles*PERIOD)

clock._clear()
sim.run(duration=cycles*PERIOD)

# the waiters are still on the clock, which results in the previous instances
# still being used. This is because StopSimulation was never called.
print clock._posedgeWaiters

A.val[:] = 0
clock._clear()

clock2 = clock #Signal(bool(0))
cycles = 4
instances2 = [Foo(A, clock2, reset), Source(A, clock2, reset), ClockSource(clock2)]

sim = Simulation(instances2)
sim.run(duration=cycles*PERIOD)