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hinzundcode / clock.js
Created October 3, 2018 18:43
puck js clock
function update() {
var now = new Date();
var minutes = now.getMinutes();
if (minutes < 10)
minutes = "0"+minutes;
var seconds = now.getSeconds();
if (seconds < 10)
seconds = "0"+seconds;
var time = now.getHours()+":"+minutes+":"+seconds;
"use strict";
const { Transform } = require("stream");
function createStreamPair() {
let config = {
objectMode: true,
transform(chunk, encoding, callback) {
this.other.push(chunk);
callback();
<!DOCTYPE html>
<canvas id="canvas" style="width: 200px; height: 200px; border: 1px solid #000;" width=200 height=200></canvas>
<script type="module">
const circle = (mx, my, r) => (x, y) => Math.pow(x - mx, 2) + Math.pow(y - my, 2) < Math.pow(r, 2);
let canvas = document.getElementById("canvas");
let context = canvas.getContext("2d");
let drawables = [
{
@hinzundcode
hinzundcode / main.c
Created July 7, 2019 00:33
nrf52840 scan for ble advertisements, based on the nrf5 sdk ble_central/ble_app_hrs_c example
/**
* Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
#![allow(dead_code)]
#![allow(unused_variables)]
#![allow(unused_assignments)]
#![allow(unused_mut)]
#![allow(unused_imports)]
#![allow(unused_macros)]
#![allow(unreachable_code)]
use futures::lock::Mutex;
use futures::future::select_all;
use std::collections::HashMap;
use futures::Future;
use futures::prelude::*;
use std::pin::Pin;
use futures_timer::Delay;
use std::time::Duration;
use serde::de::DeserializeOwned;
use serde_json::{json, Value};
use serde::{Serialize, Deserialize};
// user_1 is R, G and B (VGA pins 1, 2 and 3)
// user_2 is Ground
// user_3 is HSYNC (VGA pin 13)
// user_4 is VSYNC (VGA pin 15)
// from https://8bitworkshop.com/v3.6.0/?file=hvsync_generator.v&platform=verilog-vga
module hvsync_generator(clk, reset, hsync, vsync, display_on, hpos, vpos);
input clk;
input reset;
@hinzundcode
hinzundcode / README
Last active April 23, 2024 07:59
fomu litex vga
user_1 is R, G and B (VGA pins 1, 2 and 3)
user_2 is Ground
user_3 is HSYNC (VGA pin 13)
user_4 is VSYNC (VGA pin 15)
$ python workshop_vga.py --board pvt && dfu-util -D build/gateware/top.dfu
$ wishbone-tool 0x60003000 150
csr_register,gpu_x0,0x60003000,2,rw
csr_register,gpu_x1,0x60003008,2,rw
@hinzundcode
hinzundcode / psf_font.rs
Created July 22, 2021 15:25
psf font parser in rust
use std::fs;
use std::mem;
// https://www.win.tue.nl/~aeb/linux/kbd/font-formats-1.html
const PSF1_MAGIC: [u8;2] = [0x36, 0x04];
const PSF2_MAGIC: [u8;4] = [0x72, 0xb5, 0x4a, 0x86];
#[derive(Debug)]
enum Error {