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houmei/CT7INS22.PLD

Created October 19, 2020 16:17
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Instruction Decoder & Counter / for Fenestra6502
Raw
CT7INS22.jed

CUPL(WM) 5.0a Serial# 60008009
Device g22v10 Library DLIB-h-40-1
Created Thu Oct 15 00:35:11 2020
Name CT7INS22
Partno Fenestra6502
Revision 01
Date 20/10/14
Designer Katunori Takesita
Company
Assembly
Location
*QP24
*QF5892
*G0
*F0
*L00000 11111111111111111111111111111111
*L00032 11111111111011111111111111111111
*L00064 11111111111111111111111111110111
*L00096 11111111111111111111111111111111
*L00128 11110000000000000000000000000000
*L00416 00000000000000000000000011111111
*L00448 11111111111111111111111111111111
*L00480 11111111111110111011101110111011
*L00512 01111111101111110000000000000000
*L00896 00000000000000000000000000001111
*L00928 11111111111111111111111111111111
*L00960 11111111111111111011101110111011
*L00992 10110111101110111111000000000000
*L01472 00000000000000000000000011111111
*L01504 11111111111111111111111111111111
*L01536 11111111110111111110111111111111
*L01568 11111111111111111111111011111101
*L01600 11111111111111111111111111110000
*L02144 00000000000011111111111111111111
*L02176 11111111111111111111111111111101
*L02208 11111111111011111111111111111111
*L02240 11111111111011101110110111111111
*L02272 11111111111111111111111011011101
*L02304 11011111111111111111111111110000
*L02880 00000000000000000000000011111111
*L02912 11111111111111111111111111111111
*L02944 11111111110111111111111111101111
*L02976 11111111111111111111111011101110
*L03008 11101101111111111111111111111111
*L03040 11101101110111011101111111111111
*L03072 11111111000000000000000000000000
*L03648 00001111111111111111111111111111
*L03680 11111111111111111111110111111111
*L03712 11111111111011111111111111111111
*L03744 11101110111011101110110111111111
*L03776 11111111111111101101110111011101
*L03808 11011111111111111111000000000000
*L04288 00000000000000000000000011111111
*L04320 11111111111111111111111111111111
*L04352 11111111110111111111111111111111
*L04384 11101111111111111111111011101110
*L04416 11101110111011011111111111111111
*L04448 11101101111111111111110111011111
*L04480 11111111111111101101111111111101
*L04512 11111101111111111111111111101101
*L04544 11111101111111111101111111111111
*L04576 11111110110111011111111111111101
*L04608 11111111111100000000000000000000
*L04864 00000000000000000000111111111111
*L04896 11111111111111111111111111111111
*L04928 11111101111111111111111111111111
*L04960 11101111111111111110111011101110
*L04992 11101110111011011111111111111110
*L05024 11011111111111111101110111011111
*L05056 11111111111011011111111111011111
*L05088 11011101111111111111111011011101
*L05120 11111111111111011101111111111111
*L05152 11101101111111011111111111011101
*L05184 11111111000000000000000000000000
*L05344 00000000000000000000000011111111
*L05376 11111111111111111111111111111111
*L05408 11111111110111111111111111111111
*L05440 11111111111011111111111011101110
*L05472 11101110111011101110110111111111
*L05504 11101101111111111111110111011101
*L05536 11011111111111101101111111111101
*L05568 11111101110111011111111111101101
*L05600 11111101111111111101110111011111
*L05632 11111110110111011111111111111101
*L05664 11011101111100000000000000000000
*L05792 00000000000000000101011010101010
*L05824 10100100011001100101011011100110
*L05856 01010111001101110100011100100110
*L05888 0001
*CD64E
*8BC3
Raw
CT7INS22.PLD
Name CT7INS22;
PartNo Fenestra6502;
Revision 01;
Date 20/10/14;
Designer Katunori Takesita;
Company ;
Assembly ;
Location ;
Device G22V10;
/* INPUTS */
Pin 1 = CLK;
Pin 2 = SYNC;
Pin [3..10] = [D0..7];
pin 13 = !RESET;
/* OUTPUTS */
Pin 23 = !SYNCOUT;
Pin 22 = !CTEN;
Pin 21 = DU;
Pin [14..20] = [Q6..0];
[Q6..0].ar = RESET;
[Q6..0].sp = 'b'0;
/** Logic Equations **/
SYNCOUT = SYNC; /* !SYNCOUT -> connect to CLK (external) */
/* JSR $20 00100000 */
/* RTS $60 01100000 */
$DEFINE JSR (!D7 & !D6 & D5 & !D4 & !D3 & !D2 & !D1 & !D0)
$DEFINE RTS (!D7 & D6 & D5 & !D4 & !D3 & !D2 & !D1 & !D0)
CTEN = (JSR # RTS);
DU = !(JSR); /* JSR..INCREMENT RTS..DECREMENT */
/* COUNTER */
APPEND [Q0..6].d = !CTEN & [Q0..6];
APPEND Q0.d = CTEN & !Q0;
APPEND Q1.d = CTEN & !DU & Q0 & !Q1;
APPEND Q1.d = CTEN & DU & !Q0 & !Q1;
APPEND Q2.d = CTEN & !DU & Q1 & Q0 & !Q2;
APPEND Q2.d = CTEN & DU & !Q1 & !Q0 & !Q2;
APPEND Q3.d = CTEN & !DU & Q2 & Q1 & Q0 & !Q3;
APPEND Q3.d = CTEN & DU & !Q2 & !Q1 & !Q0 & !Q3;
$DEFINE C4 (Q3 & Q2 & Q1 & Q0)
APPEND Q4.d = CTEN & !DU & C4 & !Q4;
APPEND Q4.d = CTEN & DU & !C4 & !Q4;
APPEND Q5.d = CTEN & !DU & Q4 & C4 & !Q5;
APPEND Q5.d = CTEN & DU & !Q4 & !C4 & !Q5;
APPEND Q6.d = CTEN & !DU & Q5 & Q4 & C4 & !Q6;
APPEND Q6.d = CTEN & DU & !Q5 & !Q4 & !C4 & !Q6;
/* END */
Raw
CT7INS22.sim
%SIGNAL
PIN 1 = CLK
PIN 22 = !CTEN
PIN 3 = D0
PIN 4 = D1
PIN 5 = D2
PIN 6 = D3
PIN 7 = D4
PIN 8 = D5
PIN 9 = D6
PIN 10 = D7
PIN 21 = DU
PIN 20 = Q0
PIN 19 = Q1
PIN 18 = Q2
PIN 17 = Q3
PIN 16 = Q4
PIN 15 = Q5
PIN 14 = Q6
PIN 13 = !RESET
PIN 2 = SYNC
PIN 23 = !SYNCOUT
%END
%FIELD
%END
%EQUATION
CTEN =>
!D0 & !D1 & !D2 & !D3 & !D4 & D5 & !D7
DU =>
!D0 & !D1 & !D2 & !D3 & !D4 & D5 & !D6 & !D7
Q0.d =>
CTEN & !Q0
# !CTEN & Q0
Q0.ar Q1.ar Q2.ar Q3.ar Q4.ar Q5.ar Q6.ar =>
!RESET
Q0.sp Q1.sp Q2.sp Q3.sp Q4.sp Q5.sp Q6.sp =>
0
Q1.d =>
CTEN & !Q1
# !CTEN & !DU & !Q0 & Q1
# !CTEN & DU & Q0 & Q1
Q1.ar =>
Q1.sp =>
Q2.d =>
CTEN & !Q2
# !CTEN & !DU & !Q0 & !Q1 & Q2
# !CTEN & DU & Q0 & Q1 & Q2
Q2.ar =>
Q2.sp =>
Q3.d =>
CTEN & !Q3
# !CTEN & !DU & !Q0 & !Q1 & !Q2 & Q3
# !CTEN & DU & Q0 & Q1 & Q2 & Q3
Q3.ar =>
Q3.sp =>
Q4.d =>
CTEN & !Q4
# !CTEN & !DU & !Q0 & !Q1 & !Q2 & !Q3 & Q4
# !CTEN & DU & Q3 & Q4
# !CTEN & DU & Q2 & Q4
# !CTEN & DU & Q1 & Q4
# !CTEN & DU & Q0 & Q4
Q4.ar =>
Q4.sp =>
Q5.d =>
CTEN & !Q5
# !CTEN & !DU & !Q0 & !Q1 & !Q2 & !Q3 & !Q4 & Q5
# !CTEN & DU & Q3 & Q4 & Q5
# !CTEN & DU & Q2 & Q4 & Q5
# !CTEN & DU & Q0 & Q4 & Q5
# !CTEN & DU & Q1 & Q4 & Q5
Q5.ar =>
Q5.sp =>
Q6.d =>
CTEN & !Q6
# !CTEN & !DU & !Q0 & !Q1 & !Q2 & !Q3 & !Q4 & !Q5 & Q6
# !CTEN & DU & Q3 & Q4 & Q5 & Q6
# !CTEN & DU & Q2 & Q4 & Q5 & Q6
# !CTEN & DU & Q1 & Q4 & Q5 & Q6
# !CTEN & DU & Q0 & Q4 & Q5 & Q6
Q6.ar =>
Q6.sp =>
SYNCOUT =>
SYNC
CTEN.oe =>
1
DU.oe =>
1
Q0.oe =>
1
Q1.oe =>
1
Q2.oe =>
1
Q3.oe =>
1
Q4.oe =>
1
Q5.oe =>
1
Q6.oe =>
1
SYNCOUT.oe =>
1
%END
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