8bit LFSR with PRESET / GAL22V10 WinCUPL (compile only)

LFSR8.jed


CUPL(WM)        5.0a  Serial# 60008009
Device          g22v10  Library DLIB-h-40-1
Created         Mon Oct 12 04:40:26 2020
Name            LFSR8
Partno          PRACTICE
Revision        01
Date            20/10/11
Designer        Katunori Takesita
Company         
Assembly        
Location        
*QP24 
*QF5892 
*G0 
*F0 
*L00000 11111111111111111111111111111111
*L00032 11111110111111111111111111111111
*L00064 11111111111111111111111011011111
*L00096 11111111111111111111111111110111
*L00128 01111111110111111111111111111111
*L00160 11111111101101111111011111111111
*L00192 11111111111111111111111110110000
*L00416 00000000000000000000000011111111
*L00448 11111111111111111111111111111111
*L00480 11101111110111111111111111111111
*L00512 11111111011101111111111111011111
*L00544 11111111111111111111101101111111
*L00576 11110111111111111111111111111111
*L00608 11111011000000000000000000000000
*L00896 00000000000000000000000000001111
*L00928 11111111111111111111111111111111
*L00960 11111110111111111101111111111111
*L00992 11111111111101110111111111111111
*L01024 11011111111111111111111110110111
*L01056 11111111111101111111111111111111
*L01088 11111111101100000000000000000000
*L01472 00000000000000000000000011111111
*L01504 11111111111111111111111111111111
*L01536 11101111111111111101111111111111
*L01568 11111111011101111110111111111111
*L01600 11011111111111111111101101111101
*L01632 11111111111111101111111111111111
*L01664 10110111111111111111111101111111
*L01696 11111111111111111011000000000000
*L02144 00000000000011111111111111111111
*L02176 11111111111111111111111011111111
*L02208 11111111110111111111111111110111
*L02240 01111110111111111111111111011111
*L02272 11111111101101111101111111111111
*L02304 11111110111111111111101101111111
*L02336 11111111111111110111111111111111
*L02368 11111011000000000000000000000000
*L02880 00000000000000000000000011111111
*L02912 11111111111111111111111111111111
*L02944 11101111111111111111111111011111
*L02976 11111111011101111110111111111111
*L03008 11111111110111111111101101111101
*L03040 11111111111111111111111011111111
*L03072 10110111111111111111111111111111
*L03104 01111111111111111011000000000000
*L03648 00001111111111111111111111111111
*L03680 11111111111111101111111111111111
*L03712 11111111110111111111011101111111
*L03744 11111111111111111111111111011111
*L03776 10110111111111111111111111111111
*L03808 11110111111111111011000000000000
*L04288 00000000000000000000000011111111
*L04320 11111111111111111111111111111111
*L04352 11101111111111111111111111111111
*L04384 11011111011101111101111111111111
*L04416 11111111111111111111101101111111
*L04448 11111111111111111111111111110111
*L04480 11111011000000000000000000000000
*L05792 00000000000000001010101010101010
*L05824 00010101000001010010010000010100
*L05856 00110101010001001001010000110100
*L05888 0101
*CBFFA
*2C04

LFSR8.PLD

Name        LFSR8;
PartNo      PRACTICE;
Revision    01;
Date        20/10/11;
Designer    Katunori Takesita;
Company     ;
Assembly    ;
Location    ;
Device      G22V10;

/* INPUTS */
Pin 1 = CLK;
Pin [2..9] = [S7..0];
Pin 10 = !CTEN;
pin 11 = !PR;
pin 13 = !OE;
pin 14 = !RESET;

/* OUTPUTS */
Pin [16..23] = [Q0..7];

[Q0..7].ar = RESET;
[Q0..7].sp = 'b'0;  /* = [S0..7] & PR;  NG! */
[Q0..7].oe = OE;

/** Logic Equations **/

/* x^8+x^6+x^5+x^4+1 */

/* Q0.d = CTEN & (Q7 $ Q5 $ Q4 $ Q3) # !CTEN & Q0; */

Q0.d = !PR & (CTEN & !Q7 # !CTEN & !Q0) # PR & S0;
Q1.d = !PR & (CTEN & !Q0 # !CTEN & !Q1) # PR & S1;
Q2.d = !PR & (CTEN & (!Q1 $ !Q7) # !CTEN & !Q2) # PR & S2;
Q3.d = !PR & (CTEN & (!Q2 $ !Q7) # !CTEN & !Q3) # PR & S3;
Q4.d = !PR & (CTEN & (!Q3 $ !Q7) # !CTEN & !Q4) # PR & S4;
Q5.d = !PR & (CTEN & !Q4 # !CTEN & !Q5) # PR & S5;
Q6.d = !PR & (CTEN & !Q5 # !CTEN & !Q6) # PR & S6;
Q7.d = !PR & (CTEN & !Q6 # !CTEN & !Q7) # PR & S7;

/* END */

LFSR8.sim

%SIGNAL
PIN   1 =  CLK 
PIN  10 = !CTEN 
PIN  13 = !OE 
PIN  11 = !PR 
PIN  16 =  Q0 
PIN  17 =  Q1 
PIN  18 =  Q2 
PIN  19 =  Q3 
PIN  20 =  Q4 
PIN  21 =  Q5 
PIN  22 =  Q6 
PIN  23 =  Q7 
PIN  14 = !RESET 
PIN   9 =  S0 
PIN   8 =  S1 
PIN   7 =  S2 
PIN   6 =  S3 
PIN   5 =  S4 
PIN   4 =  S5 
PIN   3 =  S6 
PIN   2 =  S7 
%END

%FIELD
%END

%EQUATION
Q0.d  =>
    CTEN & PR & Q0
  # !CTEN & PR & Q7
  # !PR & S0

Q0.ar Q1.ar Q2.ar Q3.ar Q4.ar Q5.ar Q6.ar Q7.ar  =>
    !RESET

Q0.oe  =>
    !OE

Q0.sp Q1.sp Q2.sp Q3.sp Q4.sp Q5.sp Q6.sp Q7.sp  =>
    0 

Q1.d  =>
    CTEN & PR & Q1
  # !CTEN & PR & Q0
  # !PR & S1

Q1.ar  =>
    
Q1.oe  =>
    !OE

Q1.sp  =>
    
Q2.d  =>
    CTEN & PR & Q2
  # !CTEN & PR & Q1 & !Q7
  # !CTEN & PR & !Q1 & Q7
  # !PR & S2

Q2.ar  =>
    
Q2.oe  =>
    !OE

Q2.sp  =>
    
Q3.d  =>
    CTEN & PR & Q3
  # !CTEN & PR & Q2 & !Q7
  # !CTEN & PR & !Q2 & Q7
  # !PR & S3

Q3.ar  =>
    
Q3.oe  =>
    !OE

Q3.sp  =>
    
Q4.d  =>
    CTEN & PR & Q4
  # !CTEN & PR & Q3 & !Q7
  # !CTEN & PR & !Q3 & Q7
  # !PR & S4

Q4.ar  =>
    
Q4.oe  =>
    !OE

Q4.sp  =>
    
Q5.d  =>
    CTEN & PR & Q5
  # !CTEN & PR & Q4
  # !PR & S5

Q5.ar  =>
    
Q5.oe  =>
    !OE

Q5.sp  =>
    
Q6.d  =>
    CTEN & PR & Q6
  # !CTEN & PR & Q5
  # !PR & S6

Q6.ar  =>
    
Q6.oe  =>
    !OE

Q6.sp  =>
    
Q7.d  =>
    CTEN & PR & Q7
  # !CTEN & PR & Q6
  # !PR & S7

Q7.ar  =>
    
Q7.oe  =>
    !OE

Q7.sp  =>
    
RESET.oe  =>
    0 

%END