An LLVM Patch to add custom written MachineFunctionPass that writes MachineInstruction before each Call Instruction

MachineFunctionPass-insert-MachineInstruction.patch

diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index 9a0c2209c88..7dcbdc67f37 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -29,6 +29,7 @@ add_llvm_target(RISCVCodeGen
   RISCVLegalizerInfo.cpp
   RISCVMCInstLower.cpp
   RISCVMergeBaseOffset.cpp
+  RISCVMachineInstrPrinter.cpp
   RISCVRegisterBankInfo.cpp
   RISCVRegisterInfo.cpp
   RISCVSubtarget.cpp
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 9baa2cc2741..f8acbf1177e 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -30,6 +30,7 @@ class MachineInstr;
 class MachineOperand;
 class PassRegistry;
 
+
 void LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                     const AsmPrinter &AP);
 bool LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
@@ -40,6 +41,9 @@ FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM);
 FunctionPass *createRISCVMergeBaseOffsetOptPass();
 void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
 
+FunctionPass *createRISCVMachineInstrPrinterPass();
+void initializeRISCVMachineInstrPrinterPass(PassRegistry &);
+
 FunctionPass *createRISCVExpandPseudoPass();
 void initializeRISCVExpandPseudoPass(PassRegistry &);
 
diff --git a/llvm/lib/Target/RISCV/RISCVMachineInstrPrinter.cpp b/llvm/lib/Target/RISCV/RISCVMachineInstrPrinter.cpp
new file mode 100644
index 00000000000..46109f78499
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVMachineInstrPrinter.cpp
@@ -0,0 +1,121 @@
+// derry
+
+#include "RISCV.h"
+#include "RISCVInstrInfo.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+using namespace llvm;
+
+#define RISCV_MACHINEINSTR_PRINTER_PASS_NAME                                   \
+  "Dummy RISCV machineinstr printer pass"
+
+namespace {
+
+class RISCVMachineInstrPrinter : public MachineFunctionPass {
+public:
+  static char ID;
+
+  RISCVMachineInstrPrinter() : MachineFunctionPass(ID) {
+    initializeRISCVMachineInstrPrinterPass(*PassRegistry::getPassRegistry());
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  StringRef getPassName() const override {
+    return RISCV_MACHINEINSTR_PRINTER_PASS_NAME;
+  }
+};
+
+char RISCVMachineInstrPrinter::ID = 0;
+
+bool RISCVMachineInstrPrinter::runOnMachineFunction(MachineFunction &MF) {
+
+  for (auto &MBB : MF) {
+    /*
+    outs() << "Contents of MachineBasicBlock:\n";
+    outs() << MBB << "\n";
+    const BasicBlock *BB = MBB.getBasicBlock();
+    outs() << "Contents of BasicBlock corresponding to MachineBasicBlock:\n";
+    outs() << BB << "\n";
+    */
+    for (auto &MI : MBB) {
+
+      MachineInstr *currInstrPtr = &MI;
+      // is this a load instruction?
+
+      // if (CallInst *CI = isa<CallInst>(currInstrPtr))
+
+      if (MI.mayStore()) {
+        outs() << "Found Store\n";
+      }
+      if (MI.isCall()) {
+        outs() << "Found Call\n";
+
+        outs() << MI.getOpcode() << "\n";
+
+        //RISCVInstrInfo *XII; // target instruction info
+                             // MachineBasicBlock::iterator I = MI;
+        // MachineBasicBlock *MBB = YourCallInst->getParent(); // basic block
+        // location of your call inst BuildMI(*MBB, MI,
+        // DebugLoc(),TII->get(RISCV:::INSTRUCTION)......);
+        // BuildMI(MBB, MI, MI.getDebugLoc(), XII->get(RISCV::ADDI), RISCV::X31)
+        //    .addReg(RISCV::X31)
+        //    .addImm(-4);
+        // BuildMI(MBB, MI, MI.getDebugLoc(),
+        // XII->get(0)).addImm(MI.getOpcode());
+        
+        //BuildMI(MBB, MI, MI.getDebugLoc(), XII->get(RISCV::SW), RISCV::X1)
+        //    .addReg(RISCV::X31)
+        //    .addImm(0);
+        
+        // llvm::InlineAsm *AsmCode = llvm::InlineAsm::get(Asm, nopInstruction,
+        // "", true, false, llvm::InlineAsm::AD_Intel); module asm "NOP" edited
+        // = instrumentCall(CI); edited = instrumentLoad(LD); Instruction
+        // *newInst = new AllocaInst(Type::Int32Ty);
+
+        //&B->getInstList().insertAfter(I, newInst);
+        // Insert *after* `op`.
+        // IRBuilder<> builder(CI);
+        // builder.SetInsertPoint(&B, ++builder.GetInsertPoint());
+
+        // Insert a call to our function.
+        // Value *args[] = {CI};
+        // builder.CreateCall(logFunc, args);
+
+        
+        /*RISCVInstrInfo *XII; // target instruction info
+        MachineBasicBlock::iterator MI = MachineBasicBlock(CI);
+        MachineBasicBlock *MBB =
+            YourCallInst->getParent(); // basic block location of your call inst
+        BuildMI(*MBB, MI, DebugLoc(), XII->get(RISCV::: INSTRUCTION)......);*/
+        //MachineBasicBlock::iterator MMI = MachineBasicBlock(MI);
+        const TargetInstrInfo *XII = MF.getSubtarget().getInstrInfo(); // target instruction info
+        DebugLoc DL;
+        MachineBasicBlock::iterator MBBI = BuildMI(MBB, MI ,DL, XII->get(RISCV::SW), RISCV::X1)
+            .addReg(RISCV::X31)
+            .addImm(0);
+        return true;
+      }
+    }
+  }
+
+  return false;
+}
+
+} // end of anonymous namespace
+
+INITIALIZE_PASS(RISCVMachineInstrPrinter, "RISCV-machineinstr-printer",
+                RISCV_MACHINEINSTR_PRINTER_PASS_NAME,
+                true, // is CFG only?
+                true  // is analysis?
+)
+
+namespace llvm {
+
+FunctionPass *createRISCVMachineInstrPrinterPass() {
+  return new RISCVMachineInstrPrinter();
+}
+
+} // namespace llvm
\ No newline at end of file
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 75683e2fd8e..9d2ea1b66dd 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -38,6 +38,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   auto PR = PassRegistry::getPassRegistry();
   initializeGlobalISel(*PR);
   initializeRISCVExpandPseudoPass(*PR);
+  initializeRISCVMachineInstrPrinterPass(*PR);
 }
 
 static StringRef computeDataLayout(const Triple &TT) {
@@ -131,7 +132,7 @@ public:
   void addPreSched2() override;
   void addPreRegAlloc() override;
 };
-}
+} // namespace
 
 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new RISCVPassConfig(*this, PM);
@@ -178,6 +179,7 @@ void RISCVPassConfig::addPreEmitPass2() {
   // possibility for other passes to break the requirements for forward
   // progress in the LR/SC block.
   addPass(createRISCVExpandAtomicPseudoPass());
+  addPass(createRISCVMachineInstrPrinterPass());
 }
 
 void RISCVPassConfig::addPreRegAlloc() {