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iviarcio/resnet50-16.lir

Last active July 4, 2021 19:14
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resnet50 low-level intemediate representation compiled with int16 quantization
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resnet50-16.lir
function resnet50
declare {
%gpu_0_pred_b = WeightVar i16[S:0.000001907 O:0][-0.062,0.062]<1000> const // size: 2000 // Users: @in 205
%gpu_0_pred_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<2048 x 1000> const // size: 4096000 // Users: @in 205
%gpu_0_conv1_bias_constfold = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<64> const // size: 128 // Users: @in 3
%gpu_0_res2_0_branch2c_bias_constfold = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<256> const // size: 512 // Users: @in 154
%gpu_0_res3_0_branch2a_bias_constfold = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<128> const // size: 256 // Users: @in 85
%gpu_0_res3_0_branch2c_bias_constfold = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<512> const // size: 1024 // Users: @in 192
%gpu_0_res4_0_branch2c_bias_constfold = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<1024> const // size: 2048 // Users: @in 157
%gpu_0_res5_0_branch2c_bias_constfold = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<2048> const // size: 4096 // Users: @in 195
%gpu_0_res2_0_branch2c_bias_constfold__1 = WeightVar i16[S:0.000488281 O:0][-16.000,16.000]<256> const // size: 512 // Users: @in 17
%gpu_0_conv1_bias_constfold__1 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<64> const // size: 128 // Users: @in 9
%gpu_0_conv1_bias_constfold__2 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<64> const // size: 128 // Users: @in 11
%gpu_0_res2_0_branch2c_bias_constfold__2 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<256> const // size: 512 // Users: @in 14
%gpu_0_conv1_bias_constfold__3 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<64> const // size: 128 // Users: @in 25
%gpu_0_conv1_bias_constfold__4 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<64> const // size: 128 // Users: @in 27
%gpu_0_res2_0_branch2c_bias_constfold__3 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<256> const // size: 512 // Users: @in 30
%gpu_0_conv1_bias_constfold__5 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<64> const // size: 128 // Users: @in 36
%gpu_0_conv1_bias_constfold__6 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<64> const // size: 128 // Users: @in 38
%gpu_0_res2_0_branch2c_bias_constfold__4 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<256> const // size: 512 // Users: @in 41
%gpu_0_res3_0_branch2c_bias_constfold__1 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<512> const // size: 1024 // Users: @in 55
%gpu_0_res3_0_branch2a_bias_constfold__1 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<128> const // size: 256 // Users: @in 47
%gpu_0_res3_0_branch2a_bias_constfold__2 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<128> const // size: 256 // Users: @in 49
%gpu_0_res3_0_branch2c_bias_constfold__2 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<512> const // size: 1024 // Users: @in 52
%gpu_0_res3_0_branch2a_bias_constfold__3 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<128> const // size: 256 // Users: @in 61
%gpu_0_res3_0_branch2a_bias_constfold__4 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<128> const // size: 256 // Users: @in 63
%gpu_0_res3_0_branch2c_bias_constfold__3 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<512> const // size: 1024 // Users: @in 66
%gpu_0_res3_0_branch2a_bias_constfold__5 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<128> const // size: 256 // Users: @in 72
%gpu_0_res3_0_branch2a_bias_constfold__6 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<128> const // size: 256 // Users: @in 74
%gpu_0_res3_0_branch2c_bias_constfold__4 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<512> const // size: 1024 // Users: @in 77
%gpu_0_res3_0_branch2a_bias_constfold__7 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<128> const // size: 256 // Users: @in 83
%gpu_0_res3_0_branch2c_bias_constfold__5 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<512> const // size: 1024 // Users: @in 88
%gpu_0_res4_0_branch2c_bias_constfold__1 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<1024> const // size: 2048 // Users: @in 102
%gpu_0_res2_0_branch2c_bias_constfold__5 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<256> const // size: 512 // Users: @in 94
%gpu_0_res2_0_branch2c_bias_constfold__6 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<256> const // size: 512 // Users: @in 96
%gpu_0_res4_0_branch2c_bias_constfold__2 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<1024> const // size: 2048 // Users: @in 99
%gpu_0_res2_0_branch2c_bias_constfold__7 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<256> const // size: 512 // Users: @in 108
%gpu_0_res2_0_branch2c_bias_constfold__8 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<256> const // size: 512 // Users: @in 110
%gpu_0_res4_0_branch2c_bias_constfold__3 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<1024> const // size: 2048 // Users: @in 113
%gpu_0_res2_0_branch2c_bias_constfold__9 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<256> const // size: 512 // Users: @in 119
%gpu_0_res2_0_branch2c_bias_constfold__10 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<256> const // size: 512 // Users: @in 121
%gpu_0_res4_0_branch2c_bias_constfold__4 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<1024> const // size: 2048 // Users: @in 124
%gpu_0_res2_0_branch2c_bias_constfold__11 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<256> const // size: 512 // Users: @in 130
%gpu_0_res2_0_branch2c_bias_constfold__12 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<256> const // size: 512 // Users: @in 132
%gpu_0_res4_0_branch2c_bias_constfold__5 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<1024> const // size: 2048 // Users: @in 135
%gpu_0_res2_0_branch2c_bias_constfold__13 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<256> const // size: 512 // Users: @in 141
%gpu_0_res2_0_branch2c_bias_constfold__14 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<256> const // size: 512 // Users: @in 143
%gpu_0_res4_0_branch2c_bias_constfold__6 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<1024> const // size: 2048 // Users: @in 146
%gpu_0_res2_0_branch2c_bias_constfold__15 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<256> const // size: 512 // Users: @in 152
%gpu_0_res5_0_branch2c_bias_constfold__1 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<2048> const // size: 4096 // Users: @in 171
%gpu_0_res3_0_branch2c_bias_constfold__6 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<512> const // size: 1024 // Users: @in 163
%gpu_0_res3_0_branch2c_bias_constfold__7 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<512> const // size: 1024 // Users: @in 165
%gpu_0_res5_0_branch2c_bias_constfold__2 = WeightVar i16[S:0.000488281 O:0][-16.000,16.000]<2048> const // size: 4096 // Users: @in 168
%gpu_0_res3_0_branch2c_bias_constfold__8 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<512> const // size: 1024 // Users: @in 179
%gpu_0_res3_0_branch2c_bias_constfold__9 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<512> const // size: 1024 // Users: @in 181
%gpu_0_res5_0_branch2c_bias_constfold__3 = WeightVar i16[S:0.000488281 O:0][-16.000,16.000]<2048> const // size: 4096 // Users: @in 184
%gpu_0_res3_0_branch2c_bias_constfold__10 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<512> const // size: 1024 // Users: @in 190
%gpu_0_res2_0_branch1_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<256 x 64 x 1 x 1> const // size: 32768 // Users: @in 17
%gpu_0_res2_0_branch2a_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<64 x 64 x 1 x 1> const // size: 8192 // Users: @in 9
%gpu_0_res2_0_branch2c_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<256 x 64 x 1 x 1> const // size: 32768 // Users: @in 14
%gpu_0_res2_1_branch2a_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<64 x 256 x 1 x 1> const // size: 32768 // Users: @in 25
%gpu_0_res2_1_branch2c_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<256 x 64 x 1 x 1> const // size: 32768 // Users: @in 30
%gpu_0_res2_2_branch2a_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<64 x 256 x 1 x 1> const // size: 32768 // Users: @in 36
%gpu_0_res2_2_branch2c_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<256 x 64 x 1 x 1> const // size: 32768 // Users: @in 41
%gpu_0_res3_0_branch1_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<512 x 256 x 1 x 1> const // size: 262144 // Users: @in 55
%gpu_0_res3_0_branch2a_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<128 x 256 x 1 x 1> const // size: 65536 // Users: @in 47
%gpu_0_res3_0_branch2c_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<512 x 128 x 1 x 1> const // size: 131072 // Users: @in 52
%gpu_0_res3_1_branch2a_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<128 x 512 x 1 x 1> const // size: 131072 // Users: @in 61
%gpu_0_res3_1_branch2c_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<512 x 128 x 1 x 1> const // size: 131072 // Users: @in 66
%gpu_0_res3_2_branch2a_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<128 x 512 x 1 x 1> const // size: 131072 // Users: @in 72
%gpu_0_res3_2_branch2c_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<512 x 128 x 1 x 1> const // size: 131072 // Users: @in 77
%gpu_0_res3_3_branch2a_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<128 x 512 x 1 x 1> const // size: 131072 // Users: @in 83
%gpu_0_res3_3_branch2c_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<512 x 128 x 1 x 1> const // size: 131072 // Users: @in 88
%gpu_0_res4_0_branch1_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<1024 x 512 x 1 x 1> const // size: 1048576 // Users: @in 102
%gpu_0_res4_0_branch2a_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<256 x 512 x 1 x 1> const // size: 262144 // Users: @in 94
%gpu_0_res4_0_branch2c_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<1024 x 256 x 1 x 1> const // size: 524288 // Users: @in 99
%gpu_0_res4_1_branch2a_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<256 x 1024 x 1 x 1> const // size: 524288 // Users: @in 108
%gpu_0_res4_1_branch2c_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<1024 x 256 x 1 x 1> const // size: 524288 // Users: @in 113
%gpu_0_res4_2_branch2a_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<256 x 1024 x 1 x 1> const // size: 524288 // Users: @in 119
%gpu_0_res4_2_branch2c_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<1024 x 256 x 1 x 1> const // size: 524288 // Users: @in 124
%gpu_0_res4_3_branch2a_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<256 x 1024 x 1 x 1> const // size: 524288 // Users: @in 130
%gpu_0_res4_3_branch2c_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<1024 x 256 x 1 x 1> const // size: 524288 // Users: @in 135
%gpu_0_res4_4_branch2a_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<256 x 1024 x 1 x 1> const // size: 524288 // Users: @in 141
%gpu_0_res4_4_branch2c_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<1024 x 256 x 1 x 1> const // size: 524288 // Users: @in 146
%gpu_0_res4_5_branch2a_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<256 x 1024 x 1 x 1> const // size: 524288 // Users: @in 152
%gpu_0_res4_5_branch2c_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<1024 x 256 x 1 x 1> const // size: 524288 // Users: @in 157
%gpu_0_res5_0_branch1_w__2 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<2048 x 1024 x 1 x 1> const // size: 4194304 // Users: @in 171
%gpu_0_res5_0_branch2a_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<512 x 1024 x 1 x 1> const // size: 1048576 // Users: @in 163
%gpu_0_res5_0_branch2c_w__2 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<2048 x 512 x 1 x 1> const // size: 2097152 // Users: @in 168
%gpu_0_res5_1_branch2a_w__2 = WeightVar i16[S:0.000003815 O:0][-0.125,0.125]<512 x 2048 x 1 x 1> const // size: 2097152 // Users: @in 179
%gpu_0_res5_1_branch2c_w__2 = WeightVar i16[S:0.000122070 O:0][-4.000,4.000]<2048 x 512 x 1 x 1> const // size: 2097152 // Users: @in 184
%gpu_0_res5_2_branch2a_w__2 = WeightVar i16[S:0.000007629 O:0][-0.250,0.250]<512 x 2048 x 1 x 1> const // size: 2097152 // Users: @in 190
%gpu_0_res5_2_branch2c_w__2 = WeightVar i16[S:0.000244141 O:0][-8.000,8.000]<2048 x 512 x 1 x 1> const // size: 2097152 // Users: @in 195
%gpu_0_conv1_w__2 = WeightVar i16[S:0.000061035 O:0][-2.000,2.000]<64 x 3 x 7 x 7> const // size: 18816 // Users: @in 3
%gpu_0_res2_0_branch2b_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<64 x 64 x 3 x 3> const // size: 73728 // Users: @in 11
%gpu_0_res2_1_branch2b_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<64 x 64 x 3 x 3> const // size: 73728 // Users: @in 27
%gpu_0_res2_2_branch2b_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<64 x 64 x 3 x 3> const // size: 73728 // Users: @in 38
%gpu_0_res3_0_branch2b_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<128 x 128 x 3 x 3> const // size: 294912 // Users: @in 49
%gpu_0_res3_1_branch2b_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<128 x 128 x 3 x 3> const // size: 294912 // Users: @in 63
%gpu_0_res3_2_branch2b_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<128 x 128 x 3 x 3> const // size: 294912 // Users: @in 74
%gpu_0_res3_3_branch2b_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<128 x 128 x 3 x 3> const // size: 294912 // Users: @in 85
%gpu_0_res4_0_branch2b_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<256 x 256 x 3 x 3> const // size: 1179648 // Users: @in 96
%gpu_0_res4_1_branch2b_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<256 x 256 x 3 x 3> const // size: 1179648 // Users: @in 110
%gpu_0_res4_2_branch2b_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<256 x 256 x 3 x 3> const // size: 1179648 // Users: @in 121
%gpu_0_res4_3_branch2b_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<256 x 256 x 3 x 3> const // size: 1179648 // Users: @in 132
%gpu_0_res4_4_branch2b_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<256 x 256 x 3 x 3> const // size: 1179648 // Users: @in 143
%gpu_0_res4_5_branch2b_w__2 = WeightVar i16[S:0.000030518 O:0][-1.000,1.000]<256 x 256 x 3 x 3> const // size: 1179648 // Users: @in 154
%gpu_0_res5_0_branch2b_w__2 = WeightVar i16[S:0.000015259 O:0][-0.500,0.500]<512 x 512 x 3 x 3> const // size: 4718592 // Users: @in 165
%gpu_0_res5_1_branch2b_w__2 = WeightVar i16[S:0.000007629 O:0][-0.250,0.250]<512 x 512 x 3 x 3> const // size: 4718592 // Users: @in 181
%gpu_0_res5_2_branch2b_w__2 = WeightVar i16[S:0.000007629 O:0][-0.250,0.250]<512 x 512 x 3 x 3> const // size: 4718592 // Users: @in 192
%gpu_0_data = WeightVar float<1 x 3 x 224 x 224> mutable // size: 602112 // Users: @in 1
%gpu_0_softmax = WeightVar float<1 x 1000> mutable // size: 4000 // Users: @out 210
; size = 51667056 bytes
}
code {
0 %gpu_0_conv1_quantize_res = allocactivation { Ty: i16[S:0.000061035 O:0][-2.000,2.000]<1 x 3 x 224 x 224>} // size: 301056 // Users: @out 4, @in 3, @out 1
1 %gpu_0_conv1_quantize = quantize @out %gpu_0_conv1_quantize_res, @in %gpu_0_data
2 %gpu_0_conv1__10_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 64 x 112 x 112>} // size: 1605632 // Users: @in 6, @out 7, @out 3
3 %gpu_0_conv1__10 = convolution @out %gpu_0_conv1__10_res, @in %gpu_0_conv1_quantize_res, @in %gpu_0_conv1_w__2, @in %gpu_0_conv1_bias_constfold { Kernels: [7, 7], Strides: [2, 2], Pads: [3, 3, 3, 3], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
4 %dealloc_gpu_0_conv1_quantize_res = deallocactivation @out %gpu_0_conv1_quantize_res // size: 301056
5 %gpu_0_pool1__4_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 64 x 56 x 56>} // size: 401408 // Users: @out 6, @out 18, @in 17, @in 9
6 %gpu_0_pool1__1 = maxpool @out %gpu_0_pool1__4_res, @in %gpu_0_conv1__10_res { Kernels: [3, 3], Strides: [2, 2], Pads: [1, 1, 1, 1], Layout: 1}
7 %dealloc_gpu_0_conv1__10_res = deallocactivation @out %gpu_0_conv1__10_res // size: 1605632
8 %gpu_0_res2_0_branch2a__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 64 x 56 x 56>} // size: 401408 // Users: @out 12, @in 11, @out 9
9 %gpu_0_res2_0_branch2a__5 = convolution @out %gpu_0_res2_0_branch2a__5_res, @in %gpu_0_pool1__4_res, @in %gpu_0_res2_0_branch2a_w__2, @in %gpu_0_conv1_bias_constfold__1 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
10 %gpu_0_res2_0_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 64 x 56 x 56>} // size: 401408 // Users: @out 15, @in 14, @out 11
11 %gpu_0_res2_0_branch2b__5 = convolution @out %gpu_0_res2_0_branch2b__5_res, @in %gpu_0_res2_0_branch2a__5_res, @in %gpu_0_res2_0_branch2b_w__2, @in %gpu_0_conv1_bias_constfold__2 { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
12 %dealloc_gpu_0_res2_0_branch2a__5_res = deallocactivation @out %gpu_0_res2_0_branch2a__5_res // size: 401408
13 %gpu_0_res2_0_branch2c__6_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 256 x 56 x 56>} // size: 1605632 // Users: @out 20, @in 19, @out 14
14 %gpu_0_res2_0_branch2c__6 = convolution @out %gpu_0_res2_0_branch2c__6_res, @in %gpu_0_res2_0_branch2b__5_res, @in %gpu_0_res2_0_branch2c_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__2 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
15 %dealloc_gpu_0_res2_0_branch2b__5_res = deallocactivation @out %gpu_0_res2_0_branch2b__5_res // size: 401408
16 %gpu_0_res2_0_branch1__4_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 256 x 56 x 56>} // size: 1605632 // Users: @in 22, @out 19, @out 23, @in 19, @out 17
17 %gpu_0_res2_0_branch1__4 = convolution @out %gpu_0_res2_0_branch1__4_res, @in %gpu_0_pool1__4_res, @in %gpu_0_res2_0_branch1_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__1 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
18 %dealloc_gpu_0_pool1__4_res = deallocactivation @out %gpu_0_pool1__4_res // size: 401408
19 %gpu_0_res2_0_branch2c_bn__6 = elementadd @out %gpu_0_res2_0_branch1__4_res, @in %gpu_0_res2_0_branch2c__6_res, @in %gpu_0_res2_0_branch1__4_res
20 %dealloc_gpu_0_res2_0_branch2c__6_res = deallocactivation @out %gpu_0_res2_0_branch2c__6_res // size: 1605632
21 %gpu_0_res2_0_branch2c_bn__7_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 256 x 56 x 56>} // size: 1605632 // Users: @out 33, @in 32, @in 25, @out 22
22 %gpu_0_res2_0_branch2c_bn__7 = relu @out %gpu_0_res2_0_branch2c_bn__7_res, @in %gpu_0_res2_0_branch1__4_res
23 %dealloc_gpu_0_res2_0_branch1__4_res = deallocactivation @out %gpu_0_res2_0_branch1__4_res // size: 1605632
24 %gpu_0_res2_1_branch2a__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 64 x 56 x 56>} // size: 401408 // Users: @out 28, @in 27, @out 25
25 %gpu_0_res2_1_branch2a__5 = convolution @out %gpu_0_res2_1_branch2a__5_res, @in %gpu_0_res2_0_branch2c_bn__7_res, @in %gpu_0_res2_1_branch2a_w__2, @in %gpu_0_conv1_bias_constfold__3 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
26 %gpu_0_res2_1_branch2b__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 64 x 56 x 56>} // size: 401408 // Users: @out 31, @in 30, @out 27
27 %gpu_0_res2_1_branch2b__5 = convolution @out %gpu_0_res2_1_branch2b__5_res, @in %gpu_0_res2_1_branch2a__5_res, @in %gpu_0_res2_1_branch2b_w__2, @in %gpu_0_conv1_bias_constfold__4 { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
28 %dealloc_gpu_0_res2_1_branch2a__5_res = deallocactivation @out %gpu_0_res2_1_branch2a__5_res // size: 401408
29 %gpu_0_res2_1_branch2c_bn__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 256 x 56 x 56>} // size: 1605632 // Users: @in 32, @out 30, @in 43, @in 36, @out 34, @out 44, @in 34, @out 32
30 %gpu_0_res2_1_branch2c__6 = convolution @out %gpu_0_res2_1_branch2c_bn__6_res, @in %gpu_0_res2_1_branch2b__5_res, @in %gpu_0_res2_1_branch2c_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__3 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
31 %dealloc_gpu_0_res2_1_branch2b__5_res = deallocactivation @out %gpu_0_res2_1_branch2b__5_res // size: 401408
32 %gpu_0_res2_1_branch2c_bn__6 = elementadd @out %gpu_0_res2_1_branch2c_bn__6_res, @in %gpu_0_res2_1_branch2c_bn__6_res, @in %gpu_0_res2_0_branch2c_bn__7_res
33 %dealloc_gpu_0_res2_0_branch2c_bn__7_res = deallocactivation @out %gpu_0_res2_0_branch2c_bn__7_res // size: 1605632
34 %gpu_0_res2_1_branch2c_bn__7 = relu @out %gpu_0_res2_1_branch2c_bn__6_res, @in %gpu_0_res2_1_branch2c_bn__6_res
35 %gpu_0_res2_2_branch2a__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 64 x 56 x 56>} // size: 401408 // Users: @out 39, @in 38, @out 36
36 %gpu_0_res2_2_branch2a__5 = convolution @out %gpu_0_res2_2_branch2a__5_res, @in %gpu_0_res2_1_branch2c_bn__6_res, @in %gpu_0_res2_2_branch2a_w__2, @in %gpu_0_conv1_bias_constfold__5 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
37 %gpu_0_res2_2_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 64 x 56 x 56>} // size: 401408 // Users: @out 42, @in 41, @out 38
38 %gpu_0_res2_2_branch2b__5 = convolution @out %gpu_0_res2_2_branch2b__5_res, @in %gpu_0_res2_2_branch2a__5_res, @in %gpu_0_res2_2_branch2b_w__2, @in %gpu_0_conv1_bias_constfold__6 { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
39 %dealloc_gpu_0_res2_2_branch2a__5_res = deallocactivation @out %gpu_0_res2_2_branch2a__5_res // size: 401408
40 %gpu_0_res2_2_branch2c_bn__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 256 x 56 x 56>} // size: 1605632 // Users: @in 43, @out 41, @in 55, @in 47, @out 45, @out 56, @in 45, @out 43
41 %gpu_0_res2_2_branch2c__6 = convolution @out %gpu_0_res2_2_branch2c_bn__6_res, @in %gpu_0_res2_2_branch2b__5_res, @in %gpu_0_res2_2_branch2c_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__4 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
42 %dealloc_gpu_0_res2_2_branch2b__5_res = deallocactivation @out %gpu_0_res2_2_branch2b__5_res // size: 401408
43 %gpu_0_res2_2_branch2c_bn__6 = elementadd @out %gpu_0_res2_2_branch2c_bn__6_res, @in %gpu_0_res2_2_branch2c_bn__6_res, @in %gpu_0_res2_1_branch2c_bn__6_res
44 %dealloc_gpu_0_res2_1_branch2c_bn__6_res = deallocactivation @out %gpu_0_res2_1_branch2c_bn__6_res // size: 1605632
45 %gpu_0_res2_2_branch2c_bn__7 = relu @out %gpu_0_res2_2_branch2c_bn__6_res, @in %gpu_0_res2_2_branch2c_bn__6_res
46 %gpu_0_res3_0_branch2a__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 128 x 56 x 56>} // size: 802816 // Users: @out 50, @in 49, @out 47
47 %gpu_0_res3_0_branch2a__5 = convolution @out %gpu_0_res3_0_branch2a__5_res, @in %gpu_0_res2_2_branch2c_bn__6_res, @in %gpu_0_res3_0_branch2a_w__2, @in %gpu_0_res3_0_branch2a_bias_constfold__1 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
48 %gpu_0_res3_0_branch2b__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 128 x 28 x 28>} // size: 200704 // Users: @out 53, @in 52, @out 49
49 %gpu_0_res3_0_branch2b__5 = convolution @out %gpu_0_res3_0_branch2b__5_res, @in %gpu_0_res3_0_branch2a__5_res, @in %gpu_0_res3_0_branch2b_w__2, @in %gpu_0_res3_0_branch2a_bias_constfold__2 { Kernels: [3, 3], Strides: [2, 2], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
50 %dealloc_gpu_0_res3_0_branch2a__5_res = deallocactivation @out %gpu_0_res3_0_branch2a__5_res // size: 802816
51 %gpu_0_res3_2_branch2c_bn__6_res = allocactivation { Ty: i16[S:0.000976562 O:0][-32.000,31.999]<1 x 512 x 28 x 28>} // size: 802816 // Users: @in 57, @out 52, @in 59, @out 57, @in 68, @in 61, @out 59, @in 70, @out 68, @in 79, @in 72, @out 70, @in 90, @in 83, @out 81, @out 91, @in 81, @out 79
52 %gpu_0_res3_0_branch2c__6 = convolution @out %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_0_branch2b__5_res, @in %gpu_0_res3_0_branch2c_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold__2 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
53 %dealloc_gpu_0_res3_0_branch2b__5_res = deallocactivation @out %gpu_0_res3_0_branch2b__5_res // size: 200704
54 %gpu_0_res3_0_branch1__4_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 512 x 28 x 28>} // size: 802816 // Users: @out 58, @in 57, @out 55
55 %gpu_0_res3_0_branch1__4 = convolution @out %gpu_0_res3_0_branch1__4_res, @in %gpu_0_res2_2_branch2c_bn__6_res, @in %gpu_0_res3_0_branch1_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold__1 { Kernels: [1, 1], Strides: [2, 2], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
56 %dealloc_gpu_0_res2_2_branch2c_bn__6_res = deallocactivation @out %gpu_0_res2_2_branch2c_bn__6_res // size: 1605632
57 %gpu_0_res3_0_branch2c_bn__6 = elementadd @out %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_0_branch1__4_res
58 %dealloc_gpu_0_res3_0_branch1__4_res = deallocactivation @out %gpu_0_res3_0_branch1__4_res // size: 802816
59 %gpu_0_res3_0_branch2c_bn__7 = relu @out %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_2_branch2c_bn__6_res
60 %gpu_0_res3_1_branch2a__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 128 x 28 x 28>} // size: 200704 // Users: @out 64, @in 63, @out 61
61 %gpu_0_res3_1_branch2a__5 = convolution @out %gpu_0_res3_1_branch2a__5_res, @in %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_1_branch2a_w__2, @in %gpu_0_res3_0_branch2a_bias_constfold__3 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
62 %gpu_0_res3_1_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 128 x 28 x 28>} // size: 200704 // Users: @out 67, @in 66, @out 63
63 %gpu_0_res3_1_branch2b__5 = convolution @out %gpu_0_res3_1_branch2b__5_res, @in %gpu_0_res3_1_branch2a__5_res, @in %gpu_0_res3_1_branch2b_w__2, @in %gpu_0_res3_0_branch2a_bias_constfold__4 { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
64 %dealloc_gpu_0_res3_1_branch2a__5_res = deallocactivation @out %gpu_0_res3_1_branch2a__5_res // size: 200704
65 %gpu_0_res3_1_branch2c__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 512 x 28 x 28>} // size: 802816 // Users: @out 69, @in 68, @out 66
66 %gpu_0_res3_1_branch2c__6 = convolution @out %gpu_0_res3_1_branch2c__6_res, @in %gpu_0_res3_1_branch2b__5_res, @in %gpu_0_res3_1_branch2c_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold__3 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
67 %dealloc_gpu_0_res3_1_branch2b__5_res = deallocactivation @out %gpu_0_res3_1_branch2b__5_res // size: 200704
68 %gpu_0_res3_1_branch2c_bn__6 = elementadd @out %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_1_branch2c__6_res, @in %gpu_0_res3_2_branch2c_bn__6_res
69 %dealloc_gpu_0_res3_1_branch2c__6_res = deallocactivation @out %gpu_0_res3_1_branch2c__6_res // size: 802816
70 %gpu_0_res3_1_branch2c_bn__7 = relu @out %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_2_branch2c_bn__6_res
71 %gpu_0_res3_2_branch2a__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 128 x 28 x 28>} // size: 200704 // Users: @out 75, @in 74, @out 72
72 %gpu_0_res3_2_branch2a__5 = convolution @out %gpu_0_res3_2_branch2a__5_res, @in %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_2_branch2a_w__2, @in %gpu_0_res3_0_branch2a_bias_constfold__5 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
73 %gpu_0_res3_2_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 128 x 28 x 28>} // size: 200704 // Users: @out 78, @in 77, @out 74
74 %gpu_0_res3_2_branch2b__5 = convolution @out %gpu_0_res3_2_branch2b__5_res, @in %gpu_0_res3_2_branch2a__5_res, @in %gpu_0_res3_2_branch2b_w__2, @in %gpu_0_res3_0_branch2a_bias_constfold__6 { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
75 %dealloc_gpu_0_res3_2_branch2a__5_res = deallocactivation @out %gpu_0_res3_2_branch2a__5_res // size: 200704
76 %gpu_0_res3_2_branch2c__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 512 x 28 x 28>} // size: 802816 // Users: @out 80, @in 79, @out 77
77 %gpu_0_res3_2_branch2c__6 = convolution @out %gpu_0_res3_2_branch2c__6_res, @in %gpu_0_res3_2_branch2b__5_res, @in %gpu_0_res3_2_branch2c_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold__4 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
78 %dealloc_gpu_0_res3_2_branch2b__5_res = deallocactivation @out %gpu_0_res3_2_branch2b__5_res // size: 200704
79 %gpu_0_res3_2_branch2c_bn__6 = elementadd @out %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_2_branch2c__6_res, @in %gpu_0_res3_2_branch2c_bn__6_res
80 %dealloc_gpu_0_res3_2_branch2c__6_res = deallocactivation @out %gpu_0_res3_2_branch2c__6_res // size: 802816
81 %gpu_0_res3_2_branch2c_bn__7 = relu @out %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_2_branch2c_bn__6_res
82 %gpu_0_res3_3_branch2a__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 128 x 28 x 28>} // size: 200704 // Users: @out 86, @in 85, @out 83
83 %gpu_0_res3_3_branch2a__5 = convolution @out %gpu_0_res3_3_branch2a__5_res, @in %gpu_0_res3_2_branch2c_bn__6_res, @in %gpu_0_res3_3_branch2a_w__2, @in %gpu_0_res3_0_branch2a_bias_constfold__7 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
84 %gpu_0_res3_3_branch2b__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 128 x 28 x 28>} // size: 200704 // Users: @out 89, @in 88, @out 85
85 %gpu_0_res3_3_branch2b__5 = convolution @out %gpu_0_res3_3_branch2b__5_res, @in %gpu_0_res3_3_branch2a__5_res, @in %gpu_0_res3_3_branch2b_w__2, @in %gpu_0_res3_0_branch2a_bias_constfold { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
86 %dealloc_gpu_0_res3_3_branch2a__5_res = deallocactivation @out %gpu_0_res3_3_branch2a__5_res // size: 200704
87 %gpu_0_res3_3_branch2c_bn__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 512 x 28 x 28>} // size: 802816 // Users: @in 90, @out 88, @in 102, @in 94, @out 92, @out 103, @in 92, @out 90
88 %gpu_0_res3_3_branch2c__6 = convolution @out %gpu_0_res3_3_branch2c_bn__6_res, @in %gpu_0_res3_3_branch2b__5_res, @in %gpu_0_res3_3_branch2c_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold__5 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
89 %dealloc_gpu_0_res3_3_branch2b__5_res = deallocactivation @out %gpu_0_res3_3_branch2b__5_res // size: 200704
90 %gpu_0_res3_3_branch2c_bn__6 = elementadd @out %gpu_0_res3_3_branch2c_bn__6_res, @in %gpu_0_res3_3_branch2c_bn__6_res, @in %gpu_0_res3_2_branch2c_bn__6_res
91 %dealloc_gpu_0_res3_2_branch2c_bn__6_res = deallocactivation @out %gpu_0_res3_2_branch2c_bn__6_res // size: 802816
92 %gpu_0_res3_3_branch2c_bn__7 = relu @out %gpu_0_res3_3_branch2c_bn__6_res, @in %gpu_0_res3_3_branch2c_bn__6_res
93 %gpu_0_res4_0_branch2a__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 256 x 28 x 28>} // size: 401408 // Users: @out 97, @in 96, @out 94
94 %gpu_0_res4_0_branch2a__5 = convolution @out %gpu_0_res4_0_branch2a__5_res, @in %gpu_0_res3_3_branch2c_bn__6_res, @in %gpu_0_res4_0_branch2a_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__5 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
95 %gpu_0_res4_0_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 100, @in 99, @out 96
96 %gpu_0_res4_0_branch2b__5 = convolution @out %gpu_0_res4_0_branch2b__5_res, @in %gpu_0_res4_0_branch2a__5_res, @in %gpu_0_res4_0_branch2b_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__6 { Kernels: [3, 3], Strides: [2, 2], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
97 %dealloc_gpu_0_res4_0_branch2a__5_res = deallocactivation @out %gpu_0_res4_0_branch2a__5_res // size: 401408
98 %gpu_0_res4_0_branch2c_bn__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 1024 x 14 x 14>} // size: 401408 // Users: @in 104, @out 99, @in 115, @in 108, @out 106, @out 116, @in 106, @out 104
99 %gpu_0_res4_0_branch2c__6 = convolution @out %gpu_0_res4_0_branch2c_bn__6_res, @in %gpu_0_res4_0_branch2b__5_res, @in %gpu_0_res4_0_branch2c_w__2, @in %gpu_0_res4_0_branch2c_bias_constfold__2 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
100 %dealloc_gpu_0_res4_0_branch2b__5_res = deallocactivation @out %gpu_0_res4_0_branch2b__5_res // size: 100352
101 %gpu_0_res4_0_branch1__4_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 1024 x 14 x 14>} // size: 401408 // Users: @out 105, @in 104, @out 102
102 %gpu_0_res4_0_branch1__4 = convolution @out %gpu_0_res4_0_branch1__4_res, @in %gpu_0_res3_3_branch2c_bn__6_res, @in %gpu_0_res4_0_branch1_w__2, @in %gpu_0_res4_0_branch2c_bias_constfold__1 { Kernels: [1, 1], Strides: [2, 2], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
103 %dealloc_gpu_0_res3_3_branch2c_bn__6_res = deallocactivation @out %gpu_0_res3_3_branch2c_bn__6_res // size: 802816
104 %gpu_0_res4_0_branch2c_bn__6 = elementadd @out %gpu_0_res4_0_branch2c_bn__6_res, @in %gpu_0_res4_0_branch2c_bn__6_res, @in %gpu_0_res4_0_branch1__4_res
105 %dealloc_gpu_0_res4_0_branch1__4_res = deallocactivation @out %gpu_0_res4_0_branch1__4_res // size: 401408
106 %gpu_0_res4_0_branch2c_bn__7 = relu @out %gpu_0_res4_0_branch2c_bn__6_res, @in %gpu_0_res4_0_branch2c_bn__6_res
107 %gpu_0_res4_1_branch2a__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 111, @in 110, @out 108
108 %gpu_0_res4_1_branch2a__5 = convolution @out %gpu_0_res4_1_branch2a__5_res, @in %gpu_0_res4_0_branch2c_bn__6_res, @in %gpu_0_res4_1_branch2a_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__7 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
109 %gpu_0_res4_1_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 114, @in 113, @out 110
110 %gpu_0_res4_1_branch2b__5 = convolution @out %gpu_0_res4_1_branch2b__5_res, @in %gpu_0_res4_1_branch2a__5_res, @in %gpu_0_res4_1_branch2b_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__8 { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
111 %dealloc_gpu_0_res4_1_branch2a__5_res = deallocactivation @out %gpu_0_res4_1_branch2a__5_res // size: 100352
112 %gpu_0_res4_2_branch2c_bn__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 1024 x 14 x 14>} // size: 401408 // Users: @in 115, @out 113, @in 117, @out 115, @in 126, @in 119, @out 117, @in 137, @in 130, @out 128, @out 138, @in 128, @out 126
113 %gpu_0_res4_1_branch2c__6 = convolution @out %gpu_0_res4_2_branch2c_bn__6_res, @in %gpu_0_res4_1_branch2b__5_res, @in %gpu_0_res4_1_branch2c_w__2, @in %gpu_0_res4_0_branch2c_bias_constfold__3 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
114 %dealloc_gpu_0_res4_1_branch2b__5_res = deallocactivation @out %gpu_0_res4_1_branch2b__5_res // size: 100352
115 %gpu_0_res4_1_branch2c_bn__6 = elementadd @out %gpu_0_res4_2_branch2c_bn__6_res, @in %gpu_0_res4_2_branch2c_bn__6_res, @in %gpu_0_res4_0_branch2c_bn__6_res
116 %dealloc_gpu_0_res4_0_branch2c_bn__6_res = deallocactivation @out %gpu_0_res4_0_branch2c_bn__6_res // size: 401408
117 %gpu_0_res4_1_branch2c_bn__7 = relu @out %gpu_0_res4_2_branch2c_bn__6_res, @in %gpu_0_res4_2_branch2c_bn__6_res
118 %gpu_0_res4_2_branch2a__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 122, @in 121, @out 119
119 %gpu_0_res4_2_branch2a__5 = convolution @out %gpu_0_res4_2_branch2a__5_res, @in %gpu_0_res4_2_branch2c_bn__6_res, @in %gpu_0_res4_2_branch2a_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__9 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
120 %gpu_0_res4_2_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 125, @in 124, @out 121
121 %gpu_0_res4_2_branch2b__5 = convolution @out %gpu_0_res4_2_branch2b__5_res, @in %gpu_0_res4_2_branch2a__5_res, @in %gpu_0_res4_2_branch2b_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__10 { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
122 %dealloc_gpu_0_res4_2_branch2a__5_res = deallocactivation @out %gpu_0_res4_2_branch2a__5_res // size: 100352
123 %gpu_0_res4_2_branch2c__6_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 1024 x 14 x 14>} // size: 401408 // Users: @out 127, @in 126, @out 124
124 %gpu_0_res4_2_branch2c__6 = convolution @out %gpu_0_res4_2_branch2c__6_res, @in %gpu_0_res4_2_branch2b__5_res, @in %gpu_0_res4_2_branch2c_w__2, @in %gpu_0_res4_0_branch2c_bias_constfold__4 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
125 %dealloc_gpu_0_res4_2_branch2b__5_res = deallocactivation @out %gpu_0_res4_2_branch2b__5_res // size: 100352
126 %gpu_0_res4_2_branch2c_bn__6 = elementadd @out %gpu_0_res4_2_branch2c_bn__6_res, @in %gpu_0_res4_2_branch2c__6_res, @in %gpu_0_res4_2_branch2c_bn__6_res
127 %dealloc_gpu_0_res4_2_branch2c__6_res = deallocactivation @out %gpu_0_res4_2_branch2c__6_res // size: 401408
128 %gpu_0_res4_2_branch2c_bn__7 = relu @out %gpu_0_res4_2_branch2c_bn__6_res, @in %gpu_0_res4_2_branch2c_bn__6_res
129 %gpu_0_res4_3_branch2a__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 133, @in 132, @out 130
130 %gpu_0_res4_3_branch2a__5 = convolution @out %gpu_0_res4_3_branch2a__5_res, @in %gpu_0_res4_2_branch2c_bn__6_res, @in %gpu_0_res4_3_branch2a_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__11 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
131 %gpu_0_res4_3_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 136, @in 135, @out 132
132 %gpu_0_res4_3_branch2b__5 = convolution @out %gpu_0_res4_3_branch2b__5_res, @in %gpu_0_res4_3_branch2a__5_res, @in %gpu_0_res4_3_branch2b_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__12 { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
133 %dealloc_gpu_0_res4_3_branch2a__5_res = deallocactivation @out %gpu_0_res4_3_branch2a__5_res // size: 100352
134 %gpu_0_res4_3_branch2c_bn__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 1024 x 14 x 14>} // size: 401408 // Users: @in 137, @out 135, @in 148, @in 141, @out 139, @out 149, @in 139, @out 137
135 %gpu_0_res4_3_branch2c__6 = convolution @out %gpu_0_res4_3_branch2c_bn__6_res, @in %gpu_0_res4_3_branch2b__5_res, @in %gpu_0_res4_3_branch2c_w__2, @in %gpu_0_res4_0_branch2c_bias_constfold__5 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
136 %dealloc_gpu_0_res4_3_branch2b__5_res = deallocactivation @out %gpu_0_res4_3_branch2b__5_res // size: 100352
137 %gpu_0_res4_3_branch2c_bn__6 = elementadd @out %gpu_0_res4_3_branch2c_bn__6_res, @in %gpu_0_res4_3_branch2c_bn__6_res, @in %gpu_0_res4_2_branch2c_bn__6_res
138 %dealloc_gpu_0_res4_2_branch2c_bn__6_res = deallocactivation @out %gpu_0_res4_2_branch2c_bn__6_res // size: 401408
139 %gpu_0_res4_3_branch2c_bn__7 = relu @out %gpu_0_res4_3_branch2c_bn__6_res, @in %gpu_0_res4_3_branch2c_bn__6_res
140 %gpu_0_res4_4_branch2a__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 144, @in 143, @out 141
141 %gpu_0_res4_4_branch2a__5 = convolution @out %gpu_0_res4_4_branch2a__5_res, @in %gpu_0_res4_3_branch2c_bn__6_res, @in %gpu_0_res4_4_branch2a_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__13 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
142 %gpu_0_res4_4_branch2b__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 147, @in 146, @out 143
143 %gpu_0_res4_4_branch2b__5 = convolution @out %gpu_0_res4_4_branch2b__5_res, @in %gpu_0_res4_4_branch2a__5_res, @in %gpu_0_res4_4_branch2b_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__14 { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
144 %dealloc_gpu_0_res4_4_branch2a__5_res = deallocactivation @out %gpu_0_res4_4_branch2a__5_res // size: 100352
145 %gpu_0_res4_4_branch2c_bn__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 1024 x 14 x 14>} // size: 401408 // Users: @in 148, @out 146, @in 159, @in 152, @out 150, @out 160, @in 150, @out 148
146 %gpu_0_res4_4_branch2c__6 = convolution @out %gpu_0_res4_4_branch2c_bn__6_res, @in %gpu_0_res4_4_branch2b__5_res, @in %gpu_0_res4_4_branch2c_w__2, @in %gpu_0_res4_0_branch2c_bias_constfold__6 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
147 %dealloc_gpu_0_res4_4_branch2b__5_res = deallocactivation @out %gpu_0_res4_4_branch2b__5_res // size: 100352
148 %gpu_0_res4_4_branch2c_bn__6 = elementadd @out %gpu_0_res4_4_branch2c_bn__6_res, @in %gpu_0_res4_4_branch2c_bn__6_res, @in %gpu_0_res4_3_branch2c_bn__6_res
149 %dealloc_gpu_0_res4_3_branch2c_bn__6_res = deallocactivation @out %gpu_0_res4_3_branch2c_bn__6_res // size: 401408
150 %gpu_0_res4_4_branch2c_bn__7 = relu @out %gpu_0_res4_4_branch2c_bn__6_res, @in %gpu_0_res4_4_branch2c_bn__6_res
151 %gpu_0_res4_5_branch2a__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 155, @in 154, @out 152
152 %gpu_0_res4_5_branch2a__5 = convolution @out %gpu_0_res4_5_branch2a__5_res, @in %gpu_0_res4_4_branch2c_bn__6_res, @in %gpu_0_res4_5_branch2a_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold__15 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
153 %gpu_0_res4_5_branch2b__5_res = allocactivation { Ty: i16[S:0.000976562 O:0][-32.000,31.999]<1 x 256 x 14 x 14>} // size: 100352 // Users: @out 158, @in 157, @out 154
154 %gpu_0_res4_5_branch2b__5 = convolution @out %gpu_0_res4_5_branch2b__5_res, @in %gpu_0_res4_5_branch2a__5_res, @in %gpu_0_res4_5_branch2b_w__2, @in %gpu_0_res2_0_branch2c_bias_constfold { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
155 %dealloc_gpu_0_res4_5_branch2a__5_res = deallocactivation @out %gpu_0_res4_5_branch2a__5_res // size: 100352
156 %gpu_0_res4_5_branch2c_bn__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 1024 x 14 x 14>} // size: 401408 // Users: @in 159, @out 157, @in 171, @in 163, @out 161, @out 172, @in 161, @out 159
157 %gpu_0_res4_5_branch2c__6 = convolution @out %gpu_0_res4_5_branch2c_bn__6_res, @in %gpu_0_res4_5_branch2b__5_res, @in %gpu_0_res4_5_branch2c_w__2, @in %gpu_0_res4_0_branch2c_bias_constfold { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
158 %dealloc_gpu_0_res4_5_branch2b__5_res = deallocactivation @out %gpu_0_res4_5_branch2b__5_res // size: 100352
159 %gpu_0_res4_5_branch2c_bn__6 = elementadd @out %gpu_0_res4_5_branch2c_bn__6_res, @in %gpu_0_res4_5_branch2c_bn__6_res, @in %gpu_0_res4_4_branch2c_bn__6_res
160 %dealloc_gpu_0_res4_4_branch2c_bn__6_res = deallocactivation @out %gpu_0_res4_4_branch2c_bn__6_res // size: 401408
161 %gpu_0_res4_5_branch2c_bn__7 = relu @out %gpu_0_res4_5_branch2c_bn__6_res, @in %gpu_0_res4_5_branch2c_bn__6_res
162 %gpu_0_res5_0_branch2a__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 512 x 14 x 14>} // size: 200704 // Users: @out 166, @in 165, @out 163
163 %gpu_0_res5_0_branch2a__5 = convolution @out %gpu_0_res5_0_branch2a__5_res, @in %gpu_0_res4_5_branch2c_bn__6_res, @in %gpu_0_res5_0_branch2a_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold__6 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
164 %gpu_0_res5_0_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 512 x 7 x 7>} // size: 50176 // Users: @out 169, @in 168, @out 165
165 %gpu_0_res5_0_branch2b__5 = convolution @out %gpu_0_res5_0_branch2b__5_res, @in %gpu_0_res5_0_branch2a__5_res, @in %gpu_0_res5_0_branch2b_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold__7 { Kernels: [3, 3], Strides: [2, 2], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
166 %dealloc_gpu_0_res5_0_branch2a__5_res = deallocactivation @out %gpu_0_res5_0_branch2a__5_res // size: 200704
167 %gpu_0_res5_0_branch2c__6_res = allocactivation { Ty: i16[S:0.000976562 O:0][-32.000,31.999]<1 x 2048 x 7 x 7>} // size: 200704 // Users: @out 175, @in 174, @out 168
168 %gpu_0_res5_0_branch2c__6 = convolution @out %gpu_0_res5_0_branch2c__6_res, @in %gpu_0_res5_0_branch2b__5_res, @in %gpu_0_res5_0_branch2c_w__2, @in %gpu_0_res5_0_branch2c_bias_constfold__2 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
169 %dealloc_gpu_0_res5_0_branch2b__5_res = deallocactivation @out %gpu_0_res5_0_branch2b__5_res // size: 50176
170 %gpu_0_res5_0_branch1__4_res = allocactivation { Ty: i16[S:0.000976562 O:0][-32.000,31.999]<1 x 2048 x 7 x 7>} // size: 200704 // Users: @out 176, @in 174, @out 171
171 %gpu_0_res5_0_branch1__4 = convolution @out %gpu_0_res5_0_branch1__4_res, @in %gpu_0_res4_5_branch2c_bn__6_res, @in %gpu_0_res5_0_branch1_w__2, @in %gpu_0_res5_0_branch2c_bias_constfold__1 { Kernels: [1, 1], Strides: [2, 2], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
172 %dealloc_gpu_0_res4_5_branch2c_bn__6_res = deallocactivation @out %gpu_0_res4_5_branch2c_bn__6_res // size: 401408
173 %gpu_0_res5_2_branch2c_bn__6_res = allocactivation { Ty: i16[S:0.001953125 O:0][-64.000,63.998]<1 x 2048 x 7 x 7>} // size: 200704 // Users: @in 177, @out 174, @in 186, @in 179, @out 177, @in 188, @out 186, @in 197, @in 190, @out 188, @in 201, @out 199, @out 202, @in 199, @out 197
174 %gpu_0_res5_0_branch2c_bn__6 = elementadd @out %gpu_0_res5_2_branch2c_bn__6_res, @in %gpu_0_res5_0_branch2c__6_res, @in %gpu_0_res5_0_branch1__4_res
175 %dealloc_gpu_0_res5_0_branch2c__6_res = deallocactivation @out %gpu_0_res5_0_branch2c__6_res // size: 200704
176 %dealloc_gpu_0_res5_0_branch1__4_res = deallocactivation @out %gpu_0_res5_0_branch1__4_res // size: 200704
177 %gpu_0_res5_0_branch2c_bn__7 = relu @out %gpu_0_res5_2_branch2c_bn__6_res, @in %gpu_0_res5_2_branch2c_bn__6_res
178 %gpu_0_res5_1_branch2a__5_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 512 x 7 x 7>} // size: 50176 // Users: @out 182, @in 181, @out 179
179 %gpu_0_res5_1_branch2a__5 = convolution @out %gpu_0_res5_1_branch2a__5_res, @in %gpu_0_res5_2_branch2c_bn__6_res, @in %gpu_0_res5_1_branch2a_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold__8 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
180 %gpu_0_res5_1_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 512 x 7 x 7>} // size: 50176 // Users: @out 185, @in 184, @out 181
181 %gpu_0_res5_1_branch2b__5 = convolution @out %gpu_0_res5_1_branch2b__5_res, @in %gpu_0_res5_1_branch2a__5_res, @in %gpu_0_res5_1_branch2b_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold__9 { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
182 %dealloc_gpu_0_res5_1_branch2a__5_res = deallocactivation @out %gpu_0_res5_1_branch2a__5_res // size: 50176
183 %gpu_0_res5_1_branch2c__6_res = allocactivation { Ty: i16[S:0.000976562 O:0][-32.000,31.999]<1 x 2048 x 7 x 7>} // size: 200704 // Users: @out 187, @in 186, @out 184
184 %gpu_0_res5_1_branch2c__6 = convolution @out %gpu_0_res5_1_branch2c__6_res, @in %gpu_0_res5_1_branch2b__5_res, @in %gpu_0_res5_1_branch2c_w__2, @in %gpu_0_res5_0_branch2c_bias_constfold__3 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
185 %dealloc_gpu_0_res5_1_branch2b__5_res = deallocactivation @out %gpu_0_res5_1_branch2b__5_res // size: 50176
186 %gpu_0_res5_1_branch2c_bn__6 = elementadd @out %gpu_0_res5_2_branch2c_bn__6_res, @in %gpu_0_res5_1_branch2c__6_res, @in %gpu_0_res5_2_branch2c_bn__6_res
187 %dealloc_gpu_0_res5_1_branch2c__6_res = deallocactivation @out %gpu_0_res5_1_branch2c__6_res // size: 200704
188 %gpu_0_res5_1_branch2c_bn__7 = relu @out %gpu_0_res5_2_branch2c_bn__6_res, @in %gpu_0_res5_2_branch2c_bn__6_res
189 %gpu_0_res5_2_branch2a__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 512 x 7 x 7>} // size: 50176 // Users: @out 193, @in 192, @out 190
190 %gpu_0_res5_2_branch2a__5 = convolution @out %gpu_0_res5_2_branch2a__5_res, @in %gpu_0_res5_2_branch2c_bn__6_res, @in %gpu_0_res5_2_branch2a_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold__10 { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
191 %gpu_0_res5_2_branch2b__5_res = allocactivation { Ty: i16[S:0.000244141 O:0][-8.000,8.000]<1 x 512 x 7 x 7>} // size: 50176 // Users: @out 196, @in 195, @out 192
192 %gpu_0_res5_2_branch2b__5 = convolution @out %gpu_0_res5_2_branch2b__5_res, @in %gpu_0_res5_2_branch2a__5_res, @in %gpu_0_res5_2_branch2b_w__2, @in %gpu_0_res3_0_branch2c_bias_constfold { Kernels: [3, 3], Strides: [1, 1], Pads: [1, 1, 1, 1], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: RELU, FusedActivationArgs: []}
193 %dealloc_gpu_0_res5_2_branch2a__5_res = deallocactivation @out %gpu_0_res5_2_branch2a__5_res // size: 50176
194 %gpu_0_res5_2_branch2c__6_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 2048 x 7 x 7>} // size: 200704 // Users: @out 198, @in 197, @out 195
195 %gpu_0_res5_2_branch2c__6 = convolution @out %gpu_0_res5_2_branch2c__6_res, @in %gpu_0_res5_2_branch2b__5_res, @in %gpu_0_res5_2_branch2c_w__2, @in %gpu_0_res5_0_branch2c_bias_constfold { Kernels: [1, 1], Strides: [1, 1], Pads: [0, 0, 0, 0], Group: 1, Dilation: [1, 1], Layout: NCHW, FusedActivation: NONE, FusedActivationArgs: []}
196 %dealloc_gpu_0_res5_2_branch2b__5_res = deallocactivation @out %gpu_0_res5_2_branch2b__5_res // size: 50176
197 %gpu_0_res5_2_branch2c_bn__6 = elementadd @out %gpu_0_res5_2_branch2c_bn__6_res, @in %gpu_0_res5_2_branch2c__6_res, @in %gpu_0_res5_2_branch2c_bn__6_res
198 %dealloc_gpu_0_res5_2_branch2c__6_res = deallocactivation @out %gpu_0_res5_2_branch2c__6_res // size: 200704
199 %gpu_0_res5_2_branch2c_bn__7 = relu @out %gpu_0_res5_2_branch2c_bn__6_res, @in %gpu_0_res5_2_branch2c_bn__6_res
200 %gpu_0_pool5__4_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 2048 x 1 x 1>} // size: 4096 // Users: @in 203, @out 206, @out 201
201 %gpu_0_pool5__4 = avgpool @out %gpu_0_pool5__4_res, @in %gpu_0_res5_2_branch2c_bn__6_res { Kernels: [7, 7], Strides: [1, 1], Pads: [0, 0, 0, 0], Layout: 1, CountIncludePads: 1}
202 %dealloc_gpu_0_res5_2_branch2c_bn__6_res = deallocactivation @out %gpu_0_res5_2_branch2c_bn__6_res // size: 200704
203 %gpu_0_pool5__4_res__2 = tensorview @in %gpu_0_pool5__4_res { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 2048>, Offsets: [0, 0, 0, 0]} // Users: @in 205
204 %gpu_0_pred_res = allocactivation { Ty: i16[S:0.000488281 O:0][-16.000,16.000]<1 x 1000>} // size: 2000 // Users: @out 209, @in 208, @out 205
205 %gpu_0_pred = fullyconnected @out %gpu_0_pred_res, @in %gpu_0_pool5__4_res__2, @in %gpu_0_pred_w__2, @in %gpu_0_pred_b
206 %dealloc_gpu_0_pool5__4_res = deallocactivation @out %gpu_0_pool5__4_res // size: 4096
207 %gpu_0_softmax__1_res = allocactivation { Ty: i16[S:0.000030518 O:0][-1.000,1.000]<1 x 1000>} // size: 2000 // Users: @out 211, @in 210, @out 208
208 %gpu_0_softmax__1 = softmax @out %gpu_0_softmax__1_res, @in %gpu_0_pred_res
209 %dealloc_gpu_0_pred_res = deallocactivation @out %gpu_0_pred_res // size: 2000
210 %gpu_0_softmax__1_dequantize = dequantize @out %gpu_0_softmax, @in %gpu_0_softmax__1_res
211 %dealloc_gpu_0_softmax__1_res = deallocactivation @out %gpu_0_softmax__1_res // size: 2000
}
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