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dump.txt
****** START compiling Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort (MethodHash=c9f11a7d)
Generating code for Windows arm
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 0e 04 ldarg.s 0x4
IL_0002 2c 28 brfalse.s 40 (IL_002c)
IL_0004 7e 03 00 00 04 ldsfld 0x4000003
IL_0009 6a conv.i8
IL_000a 0a stloc.0
IL_000b 7e 04 00 00 04 ldsfld 0x4000004
IL_0010 16 ldc.i4.0
IL_0011 93 ldelem.u2
IL_0012 10 02 starg.s 0x2
IL_0014 04 ldarg.2
IL_0015 0b stloc.1
IL_0016 7e 01 00 00 04 ldsfld 0x4000001
IL_001b 06 ldloc.0
IL_001c 6f 01 00 00 2b callvirt 0x2B000001
IL_0021 7e 01 00 00 04 ldsfld 0x4000001
IL_0026 07 ldloc.1
IL_0027 6f 02 00 00 2b callvirt 0x2B000002
IL_002c 0e 04 ldarg.s 0x4
IL_002e 2d 04 brtrue.s 4 (IL_0034)
IL_0030 02 ldarg.0
IL_0031 16 ldc.i4.0
IL_0032 93 ldelem.u2
IL_0033 26 pop
IL_0034 0e 05 ldarg.s 0x5
IL_0036 16 ldc.i4.0
IL_0037 05 ldarg.3
IL_0038 9c stelem.i1
IL_0039 03 ldarg.1
IL_003a 2a ret
lvaSetClass: setting class for V00 to (30911096) System.UInt16[]
Set preferred register for V00 to [r0]
Arg #0 passed in register(s) r0
Set preferred register for V01 to [r1]
Arg #1 passed in register(s) r1
Set preferred register for V02 to [r2]
Arg #2 passed in register(s) r2
Set preferred register for V03 to [r3]
Arg #3 passed in register(s) r3
lvaSetClass: setting class for V05 to (3090EC4E) System.Byte[]
lvaGrabTemp returning 8 (V08 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 arg0 ref class-hnd
; V01 arg1 ushort
; V02 arg2 ushort
; V03 arg3 ubyte
; V04 arg4 bool
; V05 arg5 ref class-hnd
; V06 loc0 long
; V07 loc1 ushort
; V08 OutArgs lclBlk (na)
*************** In compInitDebuggingInfo() for Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 8
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 03Bh
1: 01h 01h V01 arg1 000h 03Bh
2: 02h 02h V02 arg2 000h 03Bh
3: 03h 03h V03 arg3 000h 03Bh
4: 04h 04h V04 arg4 000h 03Bh
5: 05h 05h V05 arg5 000h 03Bh
6: 06h 06h V06 loc0 000h 03Bh
7: 07h 07h V07 loc1 000h 03Bh
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort
Jump targets:
IL_002c
IL_0034
New Basic Block BB01 [0000] created.
BB01 [000..004)
New Basic Block BB02 [0001] created.
BB02 [004..02C)
New Basic Block BB03 [0002] created.
BB03 [02C..030)
New Basic Block BB04 [0003] created.
BB04 [030..034)
New Basic Block BB05 [0004] created.
BB05 [034..03B)
IL Code Size,Instr 59, 29, Basic Block count 5, Local Variable Num,Ref count 9, 12 for method Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond )
BB02 [0001] 1 1 [004..02C)
BB03 [0002] 2 1 [02C..030)-> BB05 ( cond )
BB04 [0003] 1 1 [030..034)
BB05 [0004] 2 1 [034..03B) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
[ 0] 0 (0x000) ldarg.s 4
[ 1] 2 (0x002) brfalse.s
[000005] ------------- * STMT void (IL 0x000... ???)
[000004] ------------- \--* JTRUE void
[000002] ------------- | /--* CNS_INT int 0
[000003] ------------- \--* EQ int
[000001] ------------- \--* LCL_VAR bool V04 arg4
impImportBlockPending for BB02
impImportBlockPending for BB03
Importing BB03 (PC=044) of 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
[ 0] 44 (0x02c) ldarg.s 4
[ 1] 46 (0x02e) brtrue.s
[000011] ------------- * STMT void (IL 0x02C... ???)
[000010] ------------- \--* JTRUE void
[000008] ------------- | /--* CNS_INT int 0
[000009] ------------- \--* NE int
[000007] ------------- \--* LCL_VAR bool V04 arg4
impImportBlockPending for BB04
impImportBlockPending for BB05
Importing BB05 (PC=052) of 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
[ 0] 52 (0x034) ldarg.s 5
[ 1] 54 (0x036) ldc.i4.0 0
[ 2] 55 (0x037) ldarg.3
[ 3] 56 (0x038) stelem.i1
[000018] ------------- * STMT void (IL 0x034... ???)
[000015] ------------- | /--* LCL_VAR ubyte V03 arg3
[000017] -A-XG-------- \--* ASG byte
[000014] ------------- | /--* CNS_INT int 0
[000016] ---XG--N----- \--* INDEX byte
[000013] ------------- \--* LCL_VAR ref V05 arg5
[ 0] 57 (0x039) ldarg.1
[ 1] 58 (0x03a) ret
[000021] ------------- * STMT void (IL 0x039... ???)
[000020] ------------- \--* RETURN int
[000019] ------------- \--* LCL_VAR ushort V01 arg1
Importing BB04 (PC=048) of 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
[ 0] 48 (0x030) ldarg.0
[ 1] 49 (0x031) ldc.i4.0 0
[ 2] 50 (0x032) ldelem.u2
[ 1] 51 (0x033) pop
[000028] ------------- * STMT void (IL 0x030... ???)
[000026] ------------- | /--* NOP void
[000027] ---XG-------- \--* COMMA void
[000024] ------------- | /--* CNS_INT int 0
[000025] ---XG-------- \--* INDEX ushort
[000023] ------------- \--* LCL_VAR ref V00 arg0
impImportBlockPending for BB05
Importing BB02 (PC=004) of 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
[ 0] 4 (0x004) ldsfld 04000003
[ 1] 9 (0x009) conv.i8
[ 1] 10 (0x00a) stloc.0
[000034] ------------- * STMT void (IL 0x004... ???)
[000031] ----G-------- | /--* CAST long <- int
[000030] ----G-------- | | \--* FIELD int s_3
[000033] -A--G-------- \--* ASG long
[000032] D------N----- \--* LCL_VAR long V06 loc0
[ 0] 11 (0x00b) ldsfld 04000004
[ 1] 16 (0x010) ldc.i4.0 0
[ 2] 17 (0x011) ldelem.u2
[ 1] 18 (0x012) starg.s 2
[000040] ------------- * STMT void (IL 0x00B... ???)
[000036] ------------- | /--* CNS_INT int 0
[000037] ---XG-------- | /--* INDEX ushort
[000035] ----G-------- | | \--* FIELD ref s_8
[000039] -A-XG-------- \--* ASG ushort
[000038] D------N----- \--* LCL_VAR ushort V02 arg2
[ 0] 20 (0x014) ldarg.2
[ 1] 21 (0x015) stloc.1
[000044] ------------- * STMT void (IL 0x014... ???)
[000041] ------------- | /--* LCL_VAR ushort V02 arg2
[000043] -A----------- \--* ASG int
[000042] D------N----- \--* LCL_VAR int V07 loc1
[ 0] 22 (0x016) ldsfld 04000001
[ 1] 27 (0x01b) ldloc.0
[ 2] 28 (0x01c) callvirt 2B000001
In Compiler::impImportCall: opcode is callvirt, kind=3, callRetType is void, structSize is 0
lvaGrabTemp returning 9 (V09 tmp1) called for LDVIRTFTN this pointer.
[000050] ------------- * STMT void (IL 0x016... ???)
[000045] ----G-------- | /--* FIELD ref s_rt
[000049] -A--G-------- \--* ASG ref
[000048] D------N----- \--* LCL_VAR ref V09 tmp1
lvaGrabTemp returning 10 (V10 tmp2) called for VirtualCall through function pointer.
[000061] ------------- * STMT void (IL ???... ???)
[000058] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000052] ------------- arg0 | | +--* LCL_VAR ref V09 tmp1
[000053] ------------- arg1 | | +--* CNS_INT(h) int 0x924994 token
[000054] ------------- arg2 | | \--* CNS_INT(h) int 0x924B10 token
[000060] -ACXG-------- \--* ASG int
[000059] D------N----- \--* LCL_VAR int V10 tmp2
INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct managed' for 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort' calling 'n/a'
INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct managed'
[000064] ------------- * STMT void (IL ???... ???)
[000063] --CXG-------- \--* CALL ind void
[000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1
[000046] ------------- arg1 +--* LCL_VAR long V06 loc0
[000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2
[ 0] 33 (0x021) ldsfld 04000001
[ 1] 38 (0x026) ldloc.1
[ 2] 39 (0x027) callvirt 2B000002
In Compiler::impImportCall: opcode is callvirt, kind=3, callRetType is void, structSize is 0
lvaGrabTemp returning 11 (V11 tmp3) called for LDVIRTFTN this pointer.
[000070] ------------- * STMT void (IL 0x021... ???)
[000065] ----G-------- | /--* FIELD ref s_rt
[000069] -A--G-------- \--* ASG ref
[000068] D------N----- \--* LCL_VAR ref V11 tmp3
lvaGrabTemp returning 12 (V12 tmp4) called for VirtualCall through function pointer.
[000081] ------------- * STMT void (IL ???... ???)
[000078] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000072] ------------- arg0 | | +--* LCL_VAR ref V11 tmp3
[000073] ------------- arg1 | | +--* CNS_INT(h) int 0x924994 token
[000074] ------------- arg2 | | \--* CNS_INT(h) int 0x924B74 token
[000080] -ACXG-------- \--* ASG int
[000079] D------N----- \--* LCL_VAR int V12 tmp4
INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct managed' for 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort' calling 'n/a'
INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct managed'
[000084] ------------- * STMT void (IL ???... ???)
[000083] --CXG-------- \--* CALL ind void
[000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3
[000066] ------------- arg1 +--* LCL_VAR int V07 loc1
[000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4
impImportBlockPending for BB03
New BlockSet epoch 1, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** In fgInline()
*************** After fgInline()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i
BB02 [0001] 1 1 [004..02C) i
BB03 [0002] 2 1 [02C..030)-> BB05 ( cond ) i
BB04 [0003] 1 1 [030..034) i idxlen
BB05 [0004] 2 1 [034..03B) (return) i idxlen
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000005] ------------- * STMT void (IL 0x000...0x002)
[000004] ------------- \--* JTRUE void
[000002] ------------- | /--* CNS_INT int 0
[000003] ------------- \--* EQ int
[000001] ------------- \--* LCL_VAR bool V04 arg4
------------ BB02 [004..02C), preds={} succs={BB03}
***** BB02, stmt 2
[000034] ------------- * STMT void (IL 0x004...0x00A)
[000031] ----G-------- | /--* CAST long <- int
[000030] ----G-------- | | \--* FIELD int s_3
[000033] -A--G-------- \--* ASG long
[000032] D------N----- \--* LCL_VAR long V06 loc0
***** BB02, stmt 3
[000040] ------------- * STMT void (IL 0x00B...0x012)
[000036] ------------- | /--* CNS_INT int 0
[000037] ---XG-------- | /--* INDEX ushort
[000035] ----G-------- | | \--* FIELD ref s_8
[000039] -A-XG-------- \--* ASG ushort
[000038] D------N----- \--* LCL_VAR ushort V02 arg2
***** BB02, stmt 4
[000044] ------------- * STMT void (IL 0x014...0x015)
[000041] ------------- | /--* LCL_VAR ushort V02 arg2
[000043] -A----------- \--* ASG int
[000042] D------N----- \--* LCL_VAR int V07 loc1
***** BB02, stmt 5
[000050] ------------- * STMT void (IL 0x016...0x027)
[000045] ----G-------- | /--* FIELD ref s_rt
[000049] -A--G-------- \--* ASG ref
[000048] D------N----- \--* LCL_VAR ref V09 tmp1
***** BB02, stmt 6
[000061] ------------- * STMT void (IL ???... ???)
[000058] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000052] ------------- arg0 | | +--* LCL_VAR ref V09 tmp1
[000053] ------------- arg1 | | +--* CNS_INT(h) int 0x924994 token
[000054] ------------- arg2 | | \--* CNS_INT(h) int 0x924B10 token
[000060] -ACXG-------- \--* ASG int
[000059] D------N----- \--* LCL_VAR int V10 tmp2
***** BB02, stmt 7
[000064] ------------- * STMT void (IL ???... ???)
[000063] --CXG-------- \--* CALL ind void
[000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1
[000046] ------------- arg1 +--* LCL_VAR long V06 loc0
[000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2
***** BB02, stmt 8
[000070] ------------- * STMT void (IL 0x021... ???)
[000065] ----G-------- | /--* FIELD ref s_rt
[000069] -A--G-------- \--* ASG ref
[000068] D------N----- \--* LCL_VAR ref V11 tmp3
***** BB02, stmt 9
[000081] ------------- * STMT void (IL ???... ???)
[000078] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000072] ------------- arg0 | | +--* LCL_VAR ref V11 tmp3
[000073] ------------- arg1 | | +--* CNS_INT(h) int 0x924994 token
[000074] ------------- arg2 | | \--* CNS_INT(h) int 0x924B74 token
[000080] -ACXG-------- \--* ASG int
[000079] D------N----- \--* LCL_VAR int V12 tmp4
***** BB02, stmt 10
[000084] ------------- * STMT void (IL ???... ???)
[000083] --CXG-------- \--* CALL ind void
[000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3
[000066] ------------- arg1 +--* LCL_VAR int V07 loc1
[000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4
------------ BB03 [02C..030) -> BB05 (cond), preds={} succs={BB04,BB05}
***** BB03, stmt 11
[000011] ------------- * STMT void (IL 0x02C...0x02E)
[000010] ------------- \--* JTRUE void
[000008] ------------- | /--* CNS_INT int 0
[000009] ------------- \--* NE int
[000007] ------------- \--* LCL_VAR bool V04 arg4
------------ BB04 [030..034), preds={} succs={BB05}
***** BB04, stmt 12
[000028] ------------- * STMT void (IL 0x030...0x033)
[000026] ------------- | /--* NOP void
[000027] ---XG-------- \--* COMMA void
[000024] ------------- | /--* CNS_INT int 0
[000025] ---XG-------- \--* INDEX ushort
[000023] ------------- \--* LCL_VAR ref V00 arg0
------------ BB05 [034..03B) (return), preds={} succs={}
***** BB05, stmt 13
[000018] ------------- * STMT void (IL 0x034...0x038)
[000015] ------------- | /--* LCL_VAR ubyte V03 arg3
[000017] -A-XG-------- \--* ASG byte
[000014] ------------- | /--* CNS_INT int 0
[000016] ---XG--N----- \--* INDEX byte
[000013] ------------- \--* LCL_VAR ref V05 arg5
***** BB05, stmt 14
[000021] ------------- * STMT void (IL 0x039...0x03A)
[000020] ------------- \--* RETURN int
[000019] ------------- \--* LCL_VAR ushort V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 06000005 Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort
Budget: initialTime=237, finalTime=237, initialBudget=2370, currentBudget=2370
Budget: initialSize=1476, finalSize=1476
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i
BB02 [0001] 1 1 [004..02C) i
BB03 [0002] 2 1 [02C..030)-> BB05 ( cond ) i
BB04 [0003] 1 1 [030..034) i idxlen
BB05 [0004] 2 1 [034..03B) (return) i idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
In fgUpdateFinallyTargetFlags, updating finally target flag bits
*************** In fgClearAllFinallyTargetBits()
*************** In fgAddFinallyTargetFlags()
No EH in this method, no flags to set.
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 ref class-hnd
; V01 arg1 ushort
; V02 arg2 ushort
; V03 arg3 ubyte
; V04 arg4 bool
; V05 arg5 ref class-hnd
; V06 loc0 long
; V07 loc1 ushort
; V08 OutArgs lclBlk (na)
; V09 tmp1 ref
; V10 tmp2 int
; V11 tmp3 ref
; V12 tmp4 int
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 ref class-hnd
; V01 arg1 ushort
; V02 arg2 ushort
; V03 arg3 ubyte
; V04 arg4 bool
; V05 arg5 ref class-hnd
; V06 loc0 long
; V07 loc1 ushort
; V08 OutArgs lclBlk (na)
; V09 tmp1 ref
; V10 tmp2 int
; V11 tmp3 ref
; V12 tmp4 int
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
fgMorphTree BB01, stmt 1 (before)
[000004] ------------- * JTRUE void
[000002] ------------- | /--* CNS_INT int 0
[000003] ------------- \--* EQ int
[000001] ------------- \--* LCL_VAR bool V04 arg4
fgMorphTree BB01, stmt 1 (after)
[000004] -----+------- * JTRUE void
[000002] -----+------- | /--* CNS_INT int 0
[000003] J----+-N--S-- \--* EQ int
[000085] -----+----S-- \--* CAST int <- bool <- int
[000001] -----+------- \--* LCL_VAR int V04 arg4
Morphing BB02 of 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
fgMorphTree BB02, stmt 2 (before)
[000031] ----G-------- /--* CAST long <- int
[000030] ----G-------- | \--* FIELD int s_3
[000033] -A--G-------- * ASG long
[000032] D------N----- \--* LCL_VAR long V06 loc0
fgMorphTree BB02, stmt 2 (after)
[000031] ----G+------- /--* CAST long <- int
[000030] ----G+------- | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3]
[000033] -A--G+------- * ASG long
[000032] D----+-N----- \--* LCL_VAR long V06 loc0
fgMorphTree BB02, stmt 3 (before)
[000036] ------------- /--* CNS_INT int 0
[000037] ---XG-------- /--* INDEX ushort
[000035] ----G-------- | \--* FIELD ref s_8
[000039] -A-XG-------- * ASG ushort
[000038] D------N----- \--* LCL_VAR ushort V02 arg2
lvaGrabTemp returning 13 (V13 tmp5) called for arr expr.
GenTreeNode creates assertion:
[000091] ---X--------- * ARR_LENGTH int
In BB02 New Local Constant Assertion: V13 != null index=#01, mask=0000000000000001
Folding operator with constant nodes into a constant:
[000093] -----+-N----- /--* CNS_INT int 2
[000094] ------------- * MUL int
[000090] -----+------- \--* CNS_INT int 0
Bashed to int constant:
[000094] ------------- * CNS_INT int 0
Folding operator with constant nodes into a constant:
[000095] -----+------- /--* CNS_INT int 8
[000096] ------------- * ADD int
[000094] -----+------- \--* CNS_INT int 0
Bashed to int constant:
[000096] ------------- * CNS_INT int 8
GenTreeNode creates assertion:
[000039] -A-XG-------- * ASG ushort
In BB02 New Local Subrange Assertion: V02 in [0..65535] index=#02, mask=0000000000000002
fgMorphTree BB02, stmt 3 (after)
[000037] a--XG+------- /--* IND ushort
[000096] -----+------- | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000097] -----+------- | \--* ADD byref
[000089] -----+------- | \--* LCL_VAR ref V13 tmp5
[000098] ---XG+------- /--* COMMA ushort
[000092] ---X-+------- | \--* ARR_BOUNDS_CHECK_Rng void
[000036] -----+------- | +--* CNS_INT int 0
[000091] ---X-+------- | \--* ARR_LENGTH int
[000088] -----+------- | \--* LCL_VAR ref V13 tmp5
[000099] -A-XG+------- /--* COMMA ushort
[000035] ----G+------- | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8]
[000087] -A--G+------- | \--* ASG ref
[000086] D----+-N----- | \--* LCL_VAR ref V13 tmp5
[000039] -A-XG+------- * ASG ushort
[000038] D----+-N----- \--* LCL_VAR ushort V02 arg2
fgMorphTree BB02, stmt 4 (before)
[000041] ------------- /--* LCL_VAR ushort V02 arg2
[000043] -A----------- * ASG int
[000042] D------N----- \--* LCL_VAR int V07 loc1
GenTreeNode creates assertion:
[000043] -A----------- * ASG int
In BB02 New Local Copy Assertion: V07 == V02 index=#03, mask=0000000000000004
fgMorphTree BB02, stmt 5 (before)
[000045] ----G-------- /--* FIELD ref s_rt
[000049] -A--G-------- * ASG ref
[000048] D------N----- \--* LCL_VAR ref V09 tmp1
fgMorphTree BB02, stmt 5 (after)
[000045] ----G+------- /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
[000049] -A--G+------- * ASG ref
[000048] D----+-N----- \--* LCL_VAR ref V09 tmp1
fgMorphTree BB02, stmt 6 (before)
[000058] --CXG-------- /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000052] ------------- arg0 | +--* LCL_VAR ref V09 tmp1
[000053] ------------- arg1 | +--* CNS_INT(h) int 0x924994 token
[000054] ------------- arg2 | \--* CNS_INT(h) int 0x924B10 token
[000060] -ACXG-------- * ASG int
[000059] D------N----- \--* LCL_VAR int V10 tmp2
argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0
Sorting the arguments:
Deferred argument ('r0'):
[000052] -----+------- * LCL_VAR ref V09 tmp1
Replaced with placeholder node:
[000100] -----------L- * ARGPLACE ref
Deferred argument ('r1'):
[000053] -----+------- * CNS_INT(h) int 0x924994 token
Replaced with placeholder node:
[000102] -----------L- * ARGPLACE int
Deferred argument ('r2'):
[000054] -----+------- * CNS_INT(h) int 0x924B10 token
Replaced with placeholder node:
[000104] -----------L- * ARGPLACE int
Shuffled argument table: r0 r1 r2
fgArgTabEntry[arg 0 52.LCL_VAR, 1 reg: r0, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 53.CNS_INT, 1 reg: r1, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 2 54.CNS_INT, 1 reg: r2, align=1, lateArgInx=2, processed]
fgMorphTree BB02, stmt 6 (after)
[000058] --CXG+------- /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000052] -----+------- arg0 in r0 | +--* LCL_VAR ref V09 tmp1
[000053] -----+------- arg1 in r1 | +--* CNS_INT(h) int 0x924994 token
[000054] -----+------- arg2 in r2 | \--* CNS_INT(h) int 0x924B10 token
[000060] -ACXG+------- * ASG int
[000059] D----+-N----- \--* LCL_VAR int V10 tmp2
fgMorphTree BB02, stmt 7 (before)
[000063] --CXG-------- * CALL ind void
[000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1
[000046] ------------- arg1 +--* LCL_VAR long V06 loc0
[000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2
argSlots=4, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0
Sorting the arguments:
Deferred argument ('r0'):
[000051] -----+------- * LCL_VAR ref V09 tmp1
Replaced with placeholder node:
[000106] -----------L- * ARGPLACE ref
Deferred argument ('r2'):
[000046] -----+------- * LCL_VAR long V06 loc0
Replaced with placeholder node:
[000108] -----------L- * ARGPLACE long
Shuffled argument table: r0 r2
fgArgTabEntry[arg 0 51.LCL_VAR, 1 reg: r0, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 46.LCL_VAR, 2 regs: r2 r3, align=2, lateArgInx=1, processed]
fgMorphTree BB02, stmt 7 (after)
[000063] --CXG+------- * CALL ind void
[000062] -----+------- calli tgt \--* LCL_VAR int V10 tmp2
[000051] -----+------- this in r0 +--* LCL_VAR ref V09 tmp1
[000046] -----+------- arg1 r2,r3 \--* LCL_VAR long V06 loc0
fgMorphTree BB02, stmt 8 (before)
[000065] ----G-------- /--* FIELD ref s_rt
[000069] -A--G-------- * ASG ref
[000068] D------N----- \--* LCL_VAR ref V11 tmp3
fgMorphTree BB02, stmt 8 (after)
[000065] ----G+------- /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
[000069] -A--G+------- * ASG ref
[000068] D----+-N----- \--* LCL_VAR ref V11 tmp3
fgMorphTree BB02, stmt 9 (before)
[000078] --CXG-------- /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000072] ------------- arg0 | +--* LCL_VAR ref V11 tmp3
[000073] ------------- arg1 | +--* CNS_INT(h) int 0x924994 token
[000074] ------------- arg2 | \--* CNS_INT(h) int 0x924B74 token
[000080] -ACXG-------- * ASG int
[000079] D------N----- \--* LCL_VAR int V12 tmp4
argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0
Sorting the arguments:
Deferred argument ('r0'):
[000072] -----+------- * LCL_VAR ref V11 tmp3
Replaced with placeholder node:
[000110] -----------L- * ARGPLACE ref
Deferred argument ('r1'):
[000073] -----+------- * CNS_INT(h) int 0x924994 token
Replaced with placeholder node:
[000112] -----------L- * ARGPLACE int
Deferred argument ('r2'):
[000074] -----+------- * CNS_INT(h) int 0x924B74 token
Replaced with placeholder node:
[000114] -----------L- * ARGPLACE int
Shuffled argument table: r0 r1 r2
fgArgTabEntry[arg 0 72.LCL_VAR, 1 reg: r0, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 73.CNS_INT, 1 reg: r1, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 2 74.CNS_INT, 1 reg: r2, align=1, lateArgInx=2, processed]
fgMorphTree BB02, stmt 9 (after)
[000078] --CXG+------- /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000072] -----+------- arg0 in r0 | +--* LCL_VAR ref V11 tmp3
[000073] -----+------- arg1 in r1 | +--* CNS_INT(h) int 0x924994 token
[000074] -----+------- arg2 in r2 | \--* CNS_INT(h) int 0x924B74 token
[000080] -ACXG+------- * ASG int
[000079] D----+-N----- \--* LCL_VAR int V12 tmp4
fgMorphTree BB02, stmt 10 (before)
[000083] --CXG-------- * CALL ind void
[000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3
[000066] ------------- arg1 +--* LCL_VAR int V07 loc1
[000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4
Assertion prop in BB02:
Copy Assertion: V07 == V02 index=#03, mask=0000000000000004
[000066] ------------- * LCL_VAR int V02 arg2
argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0
Sorting the arguments:
Deferred argument ('r0'):
[000071] -----+------- * LCL_VAR ref V11 tmp3
Replaced with placeholder node:
[000116] -----------L- * ARGPLACE ref
Deferred argument ('r1'):
[000066] -----+------- * LCL_VAR int V02 arg2
Replaced with placeholder node:
[000118] -----------L- * ARGPLACE int
Shuffled argument table: r0 r1
fgArgTabEntry[arg 0 71.LCL_VAR, 1 reg: r0, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 66.LCL_VAR, 1 reg: r1, align=1, lateArgInx=1, processed]
fgMorphTree BB02, stmt 10 (after)
[000083] --CXG+------- * CALL ind void
[000082] -----+------- calli tgt \--* LCL_VAR int V12 tmp4
[000071] -----+------- this in r0 +--* LCL_VAR ref V11 tmp3
[000066] -----+------- arg1 in r1 \--* LCL_VAR int V02 arg2
Morphing BB03 of 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
fgMorphTree BB03, stmt 11 (before)
[000010] ------------- * JTRUE void
[000008] ------------- | /--* CNS_INT int 0
[000009] ------------- \--* NE int
[000007] ------------- \--* LCL_VAR bool V04 arg4
fgMorphTree BB03, stmt 11 (after)
[000010] -----+------- * JTRUE void
[000008] -----+------- | /--* CNS_INT int 0
[000009] J----+-N--S-- \--* NE int
[000120] -----+----S-- \--* CAST int <- bool <- int
[000007] -----+------- \--* LCL_VAR int V04 arg4
Morphing BB04 of 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
fgMorphTree BB04, stmt 12 (before)
[000026] ------------- /--* NOP void
[000027] ---XG-------- * COMMA void
[000024] ------------- | /--* CNS_INT int 0
[000025] ---XG-------- \--* INDEX ushort
[000023] ------------- \--* LCL_VAR ref V00 arg0
GenTreeNode creates assertion:
[000123] ---X--------- * ARR_LENGTH int
In BB04 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001
Folding operator with constant nodes into a constant:
[000125] -----+-N----- /--* CNS_INT int 2
[000126] ------------- * MUL int
[000122] -----+------- \--* CNS_INT int 0
Bashed to int constant:
[000126] ------------- * CNS_INT int 0
Folding operator with constant nodes into a constant:
[000127] -----+------- /--* CNS_INT int 8
[000128] ------------- * ADD int
[000126] -----+------- \--* CNS_INT int 0
Bashed to int constant:
[000128] ------------- * CNS_INT int 8
fgMorphTree BB04, stmt 12 (after)
[000026] -----+------- /--* NOP void
[000027] ---XG+------- * COMMA void
[000025] a--XG+------- | /--* IND ushort
[000128] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000129] -----+------- | | \--* ADD byref
[000121] -----+------- | | \--* LCL_VAR ref V00 arg0
[000131] ---XG-------- \--* COMMA void
[000124] ---X-+------- \--* ARR_BOUNDS_CHECK_Rng void
[000024] -----+------- +--* CNS_INT int 0
[000123] ---X-+------- \--* ARR_LENGTH int
[000023] -----+------- \--* LCL_VAR ref V00 arg0
Morphing BB05 of 'Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort'
fgMorphTree BB05, stmt 13 (before)
[000015] ------------- /--* LCL_VAR ubyte V03 arg3
[000017] -A-XG-------- * ASG byte
[000014] ------------- | /--* CNS_INT int 0
[000016] ---XG--N----- \--* INDEX byte
[000013] ------------- \--* LCL_VAR ref V05 arg5
GenTreeNode creates assertion:
[000134] ---X--------- * ARR_LENGTH int
In BB05 New Local Constant Assertion: V05 != null index=#01, mask=0000000000000001
Folding operator with constant nodes into a constant:
[000136] -----+------- /--* CNS_INT int 8
[000137] ------------- * ADD int
[000133] -----+------- \--* CNS_INT int 0
Bashed to int constant:
[000137] ------------- * CNS_INT int 8
fgMorphTree BB05, stmt 13 (after)
[000015] -----+------- /--* LCL_VAR int V03 arg3
[000017] -A-XG+------- * ASG byte
[000016] a--XG+-N----- | /--* IND byte
[000137] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000138] -----+------- | | \--* ADD byref
[000132] -----+------- | | \--* LCL_VAR ref V05 arg5
[000139] ---XG+-N----- \--* COMMA byte
[000135] ---X-+------- \--* ARR_BOUNDS_CHECK_Rng void
[000014] -----+------- +--* CNS_INT int 0
[000134] ---X-+------- \--* ARR_LENGTH int
[000013] -----+------- \--* LCL_VAR ref V05 arg5
fgMorphTree BB05, stmt 14 (before)
[000020] ------------- * RETURN int
[000019] ------------- \--* LCL_VAR ushort V01 arg1
fgMorphTree BB05, stmt 14 (after)
[000020] -----+------- * RETURN int
[000141] -----+------- \--* CAST int <- ushort <- int
[000019] -----+------- \--* LCL_VAR int V01 arg1
*************** In fgAddFinallyTargetFlags()
No EH in this method, no flags to set.
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i
BB02 [0001] 1 1 [004..02C) i gcsafe
BB03 [0002] 2 1 [02C..030)-> BB05 ( cond ) i
BB04 [0003] 1 1 [030..034) i idxlen
BB05 [0004] 2 1 [034..03B) (return) i idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i
BB02 [0001] 1 1 [004..02C) i gcsafe
BB03 [0002] 2 1 [02C..030)-> BB05 ( cond ) i
BB04 [0003] 1 1 [030..034) i idxlen
BB05 [0004] 2 1 [034..03B) (return) i idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 1 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeEdgeWeights()
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 1 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
fgComputeEdgeWeights() was able to compute exact edge weights for all of the 6 edges, using 1 passes.
Edge weights into BB02 :BB01 (100)
Edge weights into BB03 :BB01 (0), BB02 (100)
Edge weights into BB04 :BB03 (100)
Edge weights into BB05 :BB03 (0), BB04 (100)
*************** In fgCreateFunclets()
After fgCreateFunclets()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 1 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 1 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()
Initial BasicBlocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 1 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 1 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 1 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB01 BB02
BB03 : BB01 BB02 BB03
BB04 : BB01 BB02 BB03 BB04
BB05 : BB01 BB02 BB03 BB04 BB05
After computing reachability:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 1 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
BB02: BB02 BB01
BB03: BB03 BB01
BB04: BB04 BB03 BB01
BB05: BB05 BB03 BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB03 BB02
BB03 : BB05 BB04
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 1 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000005] ------------- * STMT void (IL 0x000...0x002)
[000004] -----+------- \--* JTRUE void
[000002] -----+------- | /--* CNS_INT int 0
[000003] J----+-N--S-- \--* EQ int
[000085] -----+----S-- \--* CAST int <- bool <- int
[000001] -----+------- \--* LCL_VAR int V04 arg4
------------ BB02 [004..02C), preds={BB01} succs={BB03}
***** BB02, stmt 2
[000034] ------------- * STMT void (IL 0x004...0x00A)
[000031] ----G+------- | /--* CAST long <- int
[000030] ----G+------- | | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3]
[000033] -A--G+------- \--* ASG long
[000032] D----+-N----- \--* LCL_VAR long V06 loc0
***** BB02, stmt 3
[000040] ------------- * STMT void (IL 0x00B...0x012)
[000037] a--XG+------- | /--* IND ushort
[000096] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000097] -----+------- | | \--* ADD byref
[000089] -----+------- | | \--* LCL_VAR ref V13 tmp5
[000098] ---XG+------- | /--* COMMA ushort
[000092] ---X-+------- | | \--* ARR_BOUNDS_CHECK_Rng void
[000036] -----+------- | | +--* CNS_INT int 0
[000091] ---X-+------- | | \--* ARR_LENGTH int
[000088] -----+------- | | \--* LCL_VAR ref V13 tmp5
[000099] -A-XG+------- | /--* COMMA ushort
[000035] ----G+------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8]
[000087] -A--G+------- | | \--* ASG ref
[000086] D----+-N----- | | \--* LCL_VAR ref V13 tmp5
[000039] -A-XG+------- \--* ASG ushort
[000038] D----+-N----- \--* LCL_VAR ushort V02 arg2
***** BB02, stmt 4
[000044] ------------- * STMT void (IL 0x014...0x015)
[000041] -----+------- | /--* LCL_VAR ushort V02 arg2
[000043] -A---+------- \--* ASG int
[000042] D----+-N----- \--* LCL_VAR int V07 loc1
***** BB02, stmt 5
[000050] ------------- * STMT void (IL 0x016...0x027)
[000045] ----G+------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
[000049] -A--G+------- \--* ASG ref
[000048] D----+-N----- \--* LCL_VAR ref V09 tmp1
***** BB02, stmt 6
[000061] ------------- * STMT void (IL ???... ???)
[000058] --CXG+------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000052] -----+------- arg0 in r0 | | +--* LCL_VAR ref V09 tmp1
[000053] -----+------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token
[000054] -----+------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B10 token
[000060] -ACXG+------- \--* ASG int
[000059] D----+-N----- \--* LCL_VAR int V10 tmp2
***** BB02, stmt 7
[000064] ------------- * STMT void (IL ???... ???)
[000063] --CXG+------- \--* CALL ind void
[000062] -----+------- calli tgt \--* LCL_VAR int V10 tmp2
[000051] -----+------- this in r0 +--* LCL_VAR ref V09 tmp1
[000046] -----+------- arg1 r2,r3 \--* LCL_VAR long V06 loc0
***** BB02, stmt 8
[000070] ------------- * STMT void (IL 0x021... ???)
[000065] ----G+------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
[000069] -A--G+------- \--* ASG ref
[000068] D----+-N----- \--* LCL_VAR ref V11 tmp3
***** BB02, stmt 9
[000081] ------------- * STMT void (IL ???... ???)
[000078] --CXG+------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000072] -----+------- arg0 in r0 | | +--* LCL_VAR ref V11 tmp3
[000073] -----+------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token
[000074] -----+------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B74 token
[000080] -ACXG+------- \--* ASG int
[000079] D----+-N----- \--* LCL_VAR int V12 tmp4
***** BB02, stmt 10
[000084] ------------- * STMT void (IL ???... ???)
[000083] --CXG+------- \--* CALL ind void
[000082] -----+------- calli tgt \--* LCL_VAR int V12 tmp4
[000071] -----+------- this in r0 +--* LCL_VAR ref V11 tmp3
[000066] -----+------- arg1 in r1 \--* LCL_VAR int V02 arg2
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 11
[000011] ------------- * STMT void (IL 0x02C...0x02E)
[000010] -----+------- \--* JTRUE void
[000008] -----+------- | /--* CNS_INT int 0
[000009] J----+-N--S-- \--* NE int
[000120] -----+----S-- \--* CAST int <- bool <- int
[000007] -----+------- \--* LCL_VAR int V04 arg4
------------ BB04 [030..034), preds={BB03} succs={BB05}
***** BB04, stmt 12
[000028] ------------- * STMT void (IL 0x030...0x033)
[000026] -----+------- | /--* NOP void
[000027] ---XG+------- \--* COMMA void
[000025] a--XG+------- | /--* IND ushort
[000128] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000129] -----+------- | | \--* ADD byref
[000121] -----+------- | | \--* LCL_VAR ref V00 arg0
[000131] ---XG-------- \--* COMMA void
[000124] ---X-+------- \--* ARR_BOUNDS_CHECK_Rng void
[000024] -----+------- +--* CNS_INT int 0
[000123] ---X-+------- \--* ARR_LENGTH int
[000023] -----+------- \--* LCL_VAR ref V00 arg0
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 13
[000018] ------------- * STMT void (IL 0x034...0x038)
[000015] -----+------- | /--* LCL_VAR int V03 arg3
[000017] -A-XG+------- \--* ASG byte
[000016] a--XG+-N----- | /--* IND byte
[000137] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000138] -----+------- | | \--* ADD byref
[000132] -----+------- | | \--* LCL_VAR ref V05 arg5
[000139] ---XG+-N----- \--* COMMA byte
[000135] ---X-+------- \--* ARR_BOUNDS_CHECK_Rng void
[000014] -----+------- +--* CNS_INT int 0
[000134] ---X-+------- \--* ARR_LENGTH int
[000013] -----+------- \--* LCL_VAR ref V05 arg5
***** BB05, stmt 14
[000021] ------------- * STMT void (IL 0x039...0x03A)
[000020] -----+------- \--* RETURN int
[000141] -----+------- \--* CAST int <- ushort <- int
[000019] -----+------- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 1 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000005] ------------- * STMT void (IL 0x000...0x002)
[000004] -----+------- \--* JTRUE void
[000002] -----+------- | /--* CNS_INT int 0
[000003] J----+-N--S-- \--* EQ int
[000085] -----+----S-- \--* CAST int <- bool <- int
[000001] -----+------- \--* LCL_VAR int V04 arg4
------------ BB02 [004..02C), preds={BB01} succs={BB03}
***** BB02, stmt 2
[000034] ------------- * STMT void (IL 0x004...0x00A)
[000031] ----G+------- | /--* CAST long <- int
[000030] ----G+------- | | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3]
[000033] -A--G+------- \--* ASG long
[000032] D----+-N----- \--* LCL_VAR long V06 loc0
***** BB02, stmt 3
[000040] ------------- * STMT void (IL 0x00B...0x012)
[000037] a--XG+------- | /--* IND ushort
[000096] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000097] -----+------- | | \--* ADD byref
[000089] -----+------- | | \--* LCL_VAR ref V13 tmp5
[000098] ---XG+------- | /--* COMMA ushort
[000092] ---X-+------- | | \--* ARR_BOUNDS_CHECK_Rng void
[000036] -----+------- | | +--* CNS_INT int 0
[000091] ---X-+------- | | \--* ARR_LENGTH int
[000088] -----+------- | | \--* LCL_VAR ref V13 tmp5
[000099] -A-XG+------- | /--* COMMA ushort
[000035] ----G+------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8]
[000087] -A--G+------- | | \--* ASG ref
[000086] D----+-N----- | | \--* LCL_VAR ref V13 tmp5
[000039] -A-XG+------- \--* ASG ushort
[000038] D----+-N----- \--* LCL_VAR ushort V02 arg2
***** BB02, stmt 4
[000044] ------------- * STMT void (IL 0x014...0x015)
[000041] -----+------- | /--* LCL_VAR ushort V02 arg2
[000043] -A---+------- \--* ASG int
[000042] D----+-N----- \--* LCL_VAR int V07 loc1
***** BB02, stmt 5
[000050] ------------- * STMT void (IL 0x016...0x027)
[000045] ----G+------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
[000049] -A--G+------- \--* ASG ref
[000048] D----+-N----- \--* LCL_VAR ref V09 tmp1
***** BB02, stmt 6
[000061] ------------- * STMT void (IL ???... ???)
[000058] --CXG+------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000052] -----+------- arg0 in r0 | | +--* LCL_VAR ref V09 tmp1
[000053] -----+------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token
[000054] -----+------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B10 token
[000060] -ACXG+------- \--* ASG int
[000059] D----+-N----- \--* LCL_VAR int V10 tmp2
***** BB02, stmt 7
[000064] ------------- * STMT void (IL ???... ???)
[000063] --CXG+------- \--* CALL ind void
[000062] -----+------- calli tgt \--* LCL_VAR int V10 tmp2
[000051] -----+------- this in r0 +--* LCL_VAR ref V09 tmp1
[000046] -----+------- arg1 r2,r3 \--* LCL_VAR long V06 loc0
***** BB02, stmt 8
[000070] ------------- * STMT void (IL 0x021... ???)
[000065] ----G+------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
[000069] -A--G+------- \--* ASG ref
[000068] D----+-N----- \--* LCL_VAR ref V11 tmp3
***** BB02, stmt 9
[000081] ------------- * STMT void (IL ???... ???)
[000078] --CXG+------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000072] -----+------- arg0 in r0 | | +--* LCL_VAR ref V11 tmp3
[000073] -----+------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token
[000074] -----+------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B74 token
[000080] -ACXG+------- \--* ASG int
[000079] D----+-N----- \--* LCL_VAR int V12 tmp4
***** BB02, stmt 10
[000084] ------------- * STMT void (IL ???... ???)
[000083] --CXG+------- \--* CALL ind void
[000082] -----+------- calli tgt \--* LCL_VAR int V12 tmp4
[000071] -----+------- this in r0 +--* LCL_VAR ref V11 tmp3
[000066] -----+------- arg1 in r1 \--* LCL_VAR int V02 arg2
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 11
[000011] ------------- * STMT void (IL 0x02C...0x02E)
[000010] -----+------- \--* JTRUE void
[000008] -----+------- | /--* CNS_INT int 0
[000009] J----+-N--S-- \--* NE int
[000120] -----+----S-- \--* CAST int <- bool <- int
[000007] -----+------- \--* LCL_VAR int V04 arg4
------------ BB04 [030..034), preds={BB03} succs={BB05}
***** BB04, stmt 12
[000028] ------------- * STMT void (IL 0x030...0x033)
[000026] -----+------- | /--* NOP void
[000027] ---XG+------- \--* COMMA void
[000025] a--XG+------- | /--* IND ushort
[000128] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000129] -----+------- | | \--* ADD byref
[000121] -----+------- | | \--* LCL_VAR ref V00 arg0
[000131] ---XG-------- \--* COMMA void
[000124] ---X-+------- \--* ARR_BOUNDS_CHECK_Rng void
[000024] -----+------- +--* CNS_INT int 0
[000123] ---X-+------- \--* ARR_LENGTH int
[000023] -----+------- \--* LCL_VAR ref V00 arg0
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 13
[000018] ------------- * STMT void (IL 0x034...0x038)
[000015] -----+------- | /--* LCL_VAR int V03 arg3
[000017] -A-XG+------- \--* ASG byte
[000016] a--XG+-N----- | /--* IND byte
[000137] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000138] -----+------- | | \--* ADD byref
[000132] -----+------- | | \--* LCL_VAR ref V05 arg5
[000139] ---XG+-N----- \--* COMMA byte
[000135] ---X-+------- \--* ARR_BOUNDS_CHECK_Rng void
[000014] -----+------- +--* CNS_INT int 0
[000134] ---X-+------- \--* ARR_LENGTH int
[000013] -----+------- \--* LCL_VAR ref V05 arg5
***** BB05, stmt 14
[000021] ------------- * STMT void (IL 0x039...0x03A)
[000020] -----+------- \--* RETURN int
[000141] -----+------- \--* CAST int <- ushort <- int
[000019] -----+------- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optOptimizeLoops()
After optSetBlockWeights:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optCloneLoops()
*************** In lvaMarkLocalVars()
*** marking local variables in block BB01 (weight=1 )
[000005] ------------- * STMT void (IL 0x000...0x002)
[000004] -----+------- \--* JTRUE void
[000002] -----+------- | /--* CNS_INT int 0
[000003] J----+-N--S-- \--* EQ int
[000085] -----+----S-- \--* CAST int <- bool <- int
[000001] -----+------- \--* LCL_VAR int V04 arg4
New refCnts for V04: refCnt = 1, refCntWtd = 1
*** marking local variables in block BB02 (weight=0.50)
[000034] ------------- * STMT void (IL 0x004...0x00A)
[000031] ----G+------- | /--* CAST long <- int
[000030] ----G+------- | | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3]
[000033] -A--G+------- \--* ASG long
[000032] D----+-N----- \--* LCL_VAR long V06 loc0
New refCnts for V06: refCnt = 1, refCntWtd = 0.50
[000040] ------------- * STMT void (IL 0x00B...0x012)
[000037] a--XG+------- | /--* IND ushort
[000096] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000097] -----+------- | | \--* ADD byref
[000089] -----+------- | | \--* LCL_VAR ref V13 tmp5
[000098] ---XG+------- | /--* COMMA ushort
[000092] ---X-+------- | | \--* ARR_BOUNDS_CHECK_Rng void
[000036] -----+------- | | +--* CNS_INT int 0
[000091] ---X-+------- | | \--* ARR_LENGTH int
[000088] -----+------- | | \--* LCL_VAR ref V13 tmp5
[000099] -A-XG+------- | /--* COMMA ushort
[000035] ----G+------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8]
[000087] -A--G+------- | | \--* ASG ref
[000086] D----+-N----- | | \--* LCL_VAR ref V13 tmp5
[000039] -A-XG+------- \--* ASG ushort
[000038] D----+-N----- \--* LCL_VAR ushort V02 arg2
New refCnts for V02: refCnt = 1, refCntWtd = 0.50
New refCnts for V13: refCnt = 1, refCntWtd = 1
New refCnts for V13: refCnt = 2, refCntWtd = 2
New refCnts for V13: refCnt = 3, refCntWtd = 3
[000044] ------------- * STMT void (IL 0x014...0x015)
[000041] -----+------- | /--* LCL_VAR ushort V02 arg2
[000043] -A---+------- \--* ASG int
[000042] D----+-N----- \--* LCL_VAR int V07 loc1
New refCnts for V07: refCnt = 1, refCntWtd = 0.50
New refCnts for V02: refCnt = 2, refCntWtd = 1
[000050] ------------- * STMT void (IL 0x016...0x027)
[000045] ----G+------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
[000049] -A--G+------- \--* ASG ref
[000048] D----+-N----- \--* LCL_VAR ref V09 tmp1
New refCnts for V09: refCnt = 1, refCntWtd = 1
[000061] ------------- * STMT void (IL ???... ???)
[000058] --CXG+------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000052] -----+------- arg0 in r0 | | +--* LCL_VAR ref V09 tmp1
[000053] -----+------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token
[000054] -----+------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B10 token
[000060] -ACXG+------- \--* ASG int
[000059] D----+-N----- \--* LCL_VAR int V10 tmp2
New refCnts for V10: refCnt = 1, refCntWtd = 1
New refCnts for V09: refCnt = 2, refCntWtd = 2
[000064] ------------- * STMT void (IL ???... ???)
[000063] --CXG+------- \--* CALL ind void
[000062] -----+------- calli tgt \--* LCL_VAR int V10 tmp2
[000051] -----+------- this in r0 +--* LCL_VAR ref V09 tmp1
[000046] -----+------- arg1 r2,r3 \--* LCL_VAR long V06 loc0
New refCnts for V09: refCnt = 3, refCntWtd = 3
New refCnts for V06: refCnt = 2, refCntWtd = 1
New refCnts for V10: refCnt = 2, refCntWtd = 2
[000070] ------------- * STMT void (IL 0x021... ???)
[000065] ----G+------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
[000069] -A--G+------- \--* ASG ref
[000068] D----+-N----- \--* LCL_VAR ref V11 tmp3
New refCnts for V11: refCnt = 1, refCntWtd = 1
[000081] ------------- * STMT void (IL ???... ???)
[000078] --CXG+------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
[000072] -----+------- arg0 in r0 | | +--* LCL_VAR ref V11 tmp3
[000073] -----+------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token
[000074] -----+------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B74 token
[000080] -ACXG+------- \--* ASG int
[000079] D----+-N----- \--* LCL_VAR int V12 tmp4
New refCnts for V12: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 2, refCntWtd = 2
[000084] ------------- * STMT void (IL ???... ???)
[000083] --CXG+------- \--* CALL ind void
[000082] -----+------- calli tgt \--* LCL_VAR int V12 tmp4
[000071] -----+------- this in r0 +--* LCL_VAR ref V11 tmp3
[000066] -----+------- arg1 in r1 \--* LCL_VAR int V02 arg2
New refCnts for V11: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 3, refCntWtd = 1.50
New refCnts for V12: refCnt = 2, refCntWtd = 2
*** marking local variables in block BB03 (weight=1 )
[000011] ------------- * STMT void (IL 0x02C...0x02E)
[000010] -----+------- \--* JTRUE void
[000008] -----+------- | /--* CNS_INT int 0
[000009] J----+-N--S-- \--* NE int
[000120] -----+----S-- \--* CAST int <- bool <- int
[000007] -----+------- \--* LCL_VAR int V04 arg4
New refCnts for V04: refCnt = 2, refCntWtd = 2
*** marking local variables in block BB04 (weight=0.50)
[000028] ------------- * STMT void (IL 0x030...0x033)
[000026] -----+------- | /--* NOP void
[000027] ---XG+------- \--* COMMA void
[000025] a--XG+------- | /--* IND ushort
[000128] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000129] -----+------- | | \--* ADD byref
[000121] -----+------- | | \--* LCL_VAR ref V00 arg0
[000131] ---XG-------- \--* COMMA void
[000124] ---X-+------- \--* ARR_BOUNDS_CHECK_Rng void
[000024] -----+------- +--* CNS_INT int 0
[000123] ---X-+------- \--* ARR_LENGTH int
[000023] -----+------- \--* LCL_VAR ref V00 arg0
New refCnts for V00: refCnt = 1, refCntWtd = 0.50
New refCnts for V00: refCnt = 2, refCntWtd = 1
*** marking local variables in block BB05 (weight=1 )
[000018] ------------- * STMT void (IL 0x034...0x038)
[000015] -----+------- | /--* LCL_VAR int V03 arg3
[000017] -A-XG+------- \--* ASG byte
[000016] a--XG+-N----- | /--* IND byte
[000137] -----+------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
[000138] -----+------- | | \--* ADD byref
[000132] -----+------- | | \--* LCL_VAR ref V05 arg5
[000139] ---XG+-N----- \--* COMMA byte
[000135] ---X-+------- \--* ARR_BOUNDS_CHECK_Rng void
[000014] -----+------- +--* CNS_INT int 0
[000134] ---X-+------- \--* ARR_LENGTH int
[000013] -----+------- \--* LCL_VAR ref V05 arg5
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V03: refCnt = 1, refCntWtd = 1
[000021] ------------- * STMT void (IL 0x039...0x03A)
[000020] -----+------- \--* RETURN int
[000141] -----+------- \--* CAST int <- ushort <- int
[000019] -----+------- \--* LCL_VAR int V01 arg1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 3, refCntWtd = 2
New refCnts for V00: refCnt = 4, refCntWtd = 3
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 4, refCntWtd = 2.50
New refCnts for V02: refCnt = 5, refCntWtd = 3.50
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V03: refCnt = 3, refCntWtd = 3
*************** In optAddCopies()
refCnt table for 'M11':
V02 arg2 [ushort]: refCnt = 5, refCntWtd = 3.50 pref [r2]
V00 arg0 [ ref]: refCnt = 4, refCntWtd = 3 pref [r0]
V01 arg1 [ushort]: refCnt = 3, refCntWtd = 3 pref [r1]
V03 arg3 [ ubyte]: refCnt = 3, refCntWtd = 3 pref [r3]
V09 tmp1 [ ref]: refCnt = 3, refCntWtd = 3
V11 tmp3 [ ref]: refCnt = 3, refCntWtd = 3
V13 tmp5 [ ref]: refCnt = 3, refCntWtd = 3
V05 arg5 [ ref]: refCnt = 2, refCntWtd = 2
V04 arg4 [ bool]: refCnt = 2, refCntWtd = 2
V10 tmp2 [ int]: refCnt = 2, refCntWtd = 2
V12 tmp4 [ int]: refCnt = 2, refCntWtd = 2
V06 loc0 [ long]: refCnt = 2, refCntWtd = 1
V07 loc1 [ushort]: refCnt = 1, refCntWtd = 0.50
V08 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 15 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 8, 7) [000005] ------------- * STMT void (IL 0x000...0x002)
N005 ( 8, 7) [000004] ------------- \--* JTRUE void
N003 ( 1, 1) [000002] ------------- | /--* CNS_INT int 0
N004 ( 6, 5) [000003] J------N--S-- \--* EQ int
N002 ( 4, 3) [000085] ----------S-- \--* CAST int <- bool <- int
N001 ( 3, 2) [000001] ------------- \--* LCL_VAR int V04 arg4
------------ BB02 [004..02C), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 14, 17) [000034] ------------- * STMT void (IL 0x004...0x00A)
N002 ( 7, 11) [000031] ----G-------- | /--* CAST long <- int
N001 ( 6, 10) [000030] ----G-------- | | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3]
N004 ( 14, 17) [000033] -A--G---R---- \--* ASG long
N003 ( 3, 2) [000032] D------N----- \--* LCL_VAR long V06 loc0
***** BB02, stmt 3
( 19, 24) [000040] ------------- * STMT void (IL 0x00B...0x012)
N011 ( 5, 3) [000037] a--XG-------- | /--* IND ushort
N009 ( 1, 1) [000096] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
N010 ( 3, 3) [000097] -------N----- | | \--* ADD byref
N008 ( 1, 1) [000089] ------------- | | \--* LCL_VAR ref V13 tmp5
N012 ( 13, 14) [000098] ---XG-------- | /--* COMMA ushort
N007 ( 8, 11) [000092] ---X--------- | | \--* ARR_BOUNDS_CHECK_Rng void
N004 ( 1, 1) [000036] ------------- | | +--* CNS_INT int 0
N006 ( 3, 3) [000091] ---X--------- | | \--* ARR_LENGTH int
N005 ( 1, 1) [000088] ------------- | | \--* LCL_VAR ref V13 tmp5
N013 ( 19, 24) [000099] -A-XG-------- | /--* COMMA ushort
N001 ( 6, 10) [000035] ----G-------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8]
N003 ( 6, 10) [000087] -A--G---R---- | | \--* ASG ref
N002 ( 1, 1) [000086] D------N----- | | \--* LCL_VAR ref V13 tmp5
N015 ( 19, 24) [000039] -A-XG---R---- \--* ASG ushort
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2
***** BB02, stmt 4
( 6, 5) [000044] ------------- * STMT void (IL 0x014...0x015)
N001 ( 2, 2) [000041] ------------- | /--* LCL_VAR ushort V02 arg2
N003 ( 6, 5) [000043] -A------R---- \--* ASG int
N002 ( 3, 2) [000042] D------N----- \--* LCL_VAR int V07 loc1
***** BB02, stmt 5
( 6, 10) [000050] ------------- * STMT void (IL 0x016...0x027)
N001 ( 6, 10) [000045] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
N003 ( 6, 10) [000049] -A--G---R---- \--* ASG ref
N002 ( 1, 1) [000048] D------N----- \--* LCL_VAR ref V09 tmp1
***** BB02, stmt 6
( 27, 31) [000061] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000058] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
N007 ( 1, 1) [000052] ------------- arg0 in r0 | | +--* LCL_VAR ref V09 tmp1
N008 ( 3, 7) [000053] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token
N009 ( 3, 7) [000054] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B10 token
N015 ( 27, 31) [000060] -ACXG---R---- \--* ASG int
N014 ( 3, 2) [000059] D------N----- \--* LCL_VAR int V10 tmp2
***** BB02, stmt 7
( 24, 10) [000064] ------------- * STMT void (IL ???... ???)
N009 ( 24, 10) [000063] --CXG-------- \--* CALL ind void
N008 ( 3, 2) [000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2
N004 ( 1, 1) [000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1
N005 ( 3, 2) [000046] ------------- arg1 r2,r3 \--* LCL_VAR long V06 loc0
***** BB02, stmt 8
( 6, 10) [000070] ------------- * STMT void (IL 0x021... ???)
N001 ( 6, 10) [000065] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
N003 ( 6, 10) [000069] -A--G---R---- \--* ASG ref
N002 ( 1, 1) [000068] D------N----- \--* LCL_VAR ref V11 tmp3
***** BB02, stmt 9
( 27, 31) [000081] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000078] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
N007 ( 1, 1) [000072] ------------- arg0 in r0 | | +--* LCL_VAR ref V11 tmp3
N008 ( 3, 7) [000073] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token
N009 ( 3, 7) [000074] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B74 token
N015 ( 27, 31) [000080] -ACXG---R---- \--* ASG int
N014 ( 3, 2) [000079] D------N----- \--* LCL_VAR int V12 tmp4
***** BB02, stmt 10
( 23, 10) [000084] ------------- * STMT void (IL ???... ???)
N009 ( 23, 10) [000083] --CXG-------- \--* CALL ind void
N008 ( 3, 2) [000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4
N004 ( 1, 1) [000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3
N005 ( 2, 2) [000066] ------------- arg1 in r1 \--* LCL_VAR int V02 arg2
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 11
( 8, 7) [000011] ------------- * STMT void (IL 0x02C...0x02E)
N005 ( 8, 7) [000010] ------------- \--* JTRUE void
N003 ( 1, 1) [000008] ------------- | /--* CNS_INT int 0
N004 ( 6, 5) [000009] J------N--S-- \--* NE int
N002 ( 4, 3) [000120] ----------S-- \--* CAST int <- bool <- int
N001 ( 3, 2) [000007] ------------- \--* LCL_VAR int V04 arg4
------------ BB04 [030..034), preds={BB03} succs={BB05}
***** BB04, stmt 12
( 13, 14) [000028] ------------- * STMT void (IL 0x030...0x033)
N010 ( 0, 0) [000026] ------------- | /--* NOP void
N011 ( 13, 14) [000027] ---XG-------- \--* COMMA void
N008 ( 5, 3) [000025] a--XG-------- | /--* IND ushort
N006 ( 1, 1) [000128] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
N007 ( 3, 3) [000129] -------N----- | | \--* ADD byref
N005 ( 1, 1) [000121] ------------- | | \--* LCL_VAR ref V00 arg0
N009 ( 13, 14) [000131] ---XG-------- \--* COMMA void
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 13
( 20, 19) [000018] ------------- * STMT void (IL 0x034...0x038)
N010 ( 2, 2) [000015] ------------- | /--* LCL_VAR int V03 arg3
N011 ( 20, 19) [000017] -A-XG-------- \--* ASG byte
N008 ( 7, 4) [000016] a--XG--N----- | /--* IND byte
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
N007 ( 5, 4) [000138] -------N----- | | \--* ADD byref
N005 ( 3, 2) [000132] ------------- | | \--* LCL_VAR ref V05 arg5
N009 ( 17, 16) [000139] ---XG--N----- \--* COMMA byte
N004 ( 10, 12) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0
N003 ( 5, 4) [000134] ---X--------- \--* ARR_LENGTH int
N002 ( 3, 2) [000013] ------------- \--* LCL_VAR ref V05 arg5
***** BB05, stmt 14
( 4, 4) [000021] ------------- * STMT void (IL 0x039...0x03A)
N003 ( 4, 4) [000020] ------------- \--* RETURN int
N002 ( 3, 3) [000141] ------------- \--* CAST int <- ushort <- int
N001 ( 2, 2) [000019] ------------- \--* LCL_VAR int V01 arg1
-------------------------------------------------------------------------------------------------------------------
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 6.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
*************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...)
*************** In SsaBuilder::InsertPhiFunctions()
*************** In fgLocalVarLiveness()
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V04}
DEF(0)={ }
BB02 USE(0)={ } + ByrefExposed + GcHeap
DEF(8)={V02 V09 V11 V13 V10 V12 V06 V07} + ByrefExposed* + GcHeap*
BB03 USE(1)={V04}
DEF(0)={ }
BB04 USE(1)={V00} + ByrefExposed + GcHeap
DEF(0)={ }
BB05 USE(3)={V01 V03 V05} + ByrefExposed + GcHeap
DEF(0)={ } + ByrefExposed + GcHeap
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (5)={V00 V01 V03 V05 V04} + ByrefExposed + GcHeap
OUT(5)={V00 V01 V03 V05 V04} + ByrefExposed + GcHeap
BB02 IN (5)={V00 V01 V03 V05 V04} + ByrefExposed + GcHeap
OUT(5)={V00 V01 V03 V05 V04} + ByrefExposed + GcHeap
BB03 IN (5)={V00 V01 V03 V05 V04} + ByrefExposed + GcHeap
OUT(4)={V00 V01 V03 V05 } + ByrefExposed + GcHeap
BB04 IN (4)={V00 V01 V03 V05} + ByrefExposed + GcHeap
OUT(3)={ V01 V03 V05} + ByrefExposed + GcHeap
BB05 IN (3)={V01 V03 V05} + ByrefExposed + GcHeap
OUT(0)={ }
top level assign
removing stmt with no side effects
Removing statement [000044] in BB02 as useless:
( 6, 5) [000044] ------------- * STMT void (IL 0x014...0x015)
N001 ( 2, 2) [000041] ------------- | /--* LCL_VAR ushort V02 arg2
N003 ( 6, 5) [000043] -A------R---- \--* ASG int
N002 ( 3, 2) [000042] D------N----- \--* LCL_VAR int V07 loc1
New refCnts for V07: refCnt = 0, refCntWtd = 0
New refCnts for V02: refCnt = 4, refCntWtd = 3
In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal)
Inserting phi functions:
Inserting phi definition for ByrefExposed at start of BB03.
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 8, 7) [000005] ------------- * STMT void (IL 0x000...0x002)
N005 ( 8, 7) [000004] ------------- \--* JTRUE void
N003 ( 1, 1) [000002] ------------- | /--* CNS_INT int 0
N004 ( 6, 5) [000003] J------N--S-- \--* EQ int
N002 ( 4, 3) [000085] ----------S-- \--* CAST int <- bool <- int
N001 ( 3, 2) [000001] ------------- \--* LCL_VAR int V04 arg4 u:2
------------ BB02 [004..02C), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 14, 17) [000034] ------------- * STMT void (IL 0x004...0x00A)
N002 ( 7, 11) [000031] ----G-------- | /--* CAST long <- int
N001 ( 6, 10) [000030] ----G-------- | | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3]
N004 ( 14, 17) [000033] -A--G---R---- \--* ASG long
N003 ( 3, 2) [000032] D------N----- \--* LCL_VAR long V06 loc0 d:3
***** BB02, stmt 3
( 19, 24) [000040] ------------- * STMT void (IL 0x00B...0x012)
N011 ( 5, 3) [000037] a--XG-------- | /--* IND ushort
N009 ( 1, 1) [000096] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
N010 ( 3, 3) [000097] -------N----- | | \--* ADD byref
N008 ( 1, 1) [000089] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 (last use)
N012 ( 13, 14) [000098] ---XG-------- | /--* COMMA ushort
N007 ( 8, 11) [000092] ---X--------- | | \--* ARR_BOUNDS_CHECK_Rng void
N004 ( 1, 1) [000036] ------------- | | +--* CNS_INT int 0
N006 ( 3, 3) [000091] ---X--------- | | \--* ARR_LENGTH int
N005 ( 1, 1) [000088] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3
N013 ( 19, 24) [000099] -A-XG-------- | /--* COMMA ushort
N001 ( 6, 10) [000035] ----G-------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8]
N003 ( 6, 10) [000087] -A--G---R---- | | \--* ASG ref
N002 ( 1, 1) [000086] D------N----- | | \--* LCL_VAR ref V13 tmp5 d:3
N015 ( 19, 24) [000039] -A-XG---R---- \--* ASG ushort
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2 d:3
***** BB02, stmt 4
( 6, 10) [000050] ------------- * STMT void (IL 0x016...0x027)
N001 ( 6, 10) [000045] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
N003 ( 6, 10) [000049] -A--G---R---- \--* ASG ref
N002 ( 1, 1) [000048] D------N----- \--* LCL_VAR ref V09 tmp1 d:3
***** BB02, stmt 5
( 27, 31) [000061] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000058] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
N007 ( 1, 1) [000052] ------------- arg0 in r0 | | +--* LCL_VAR ref V09 tmp1 u:3
N008 ( 3, 7) [000053] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token
N009 ( 3, 7) [000054] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B10 token
N015 ( 27, 31) [000060] -ACXG---R---- \--* ASG int
N014 ( 3, 2) [000059] D------N----- \--* LCL_VAR int V10 tmp2 d:3
***** BB02, stmt 6
( 24, 10) [000064] ------------- * STMT void (IL ???... ???)
N009 ( 24, 10) [000063] --CXG-------- \--* CALL ind void
N008 ( 3, 2) [000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2 u:3 (last use)
N004 ( 1, 1) [000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1 u:3 (last use)
N005 ( 3, 2) [000046] ------------- arg1 r2,r3 \--* LCL_VAR long V06 loc0 u:3 (last use)
***** BB02, stmt 7
( 6, 10) [000070] ------------- * STMT void (IL 0x021... ???)
N001 ( 6, 10) [000065] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
N003 ( 6, 10) [000069] -A--G---R---- \--* ASG ref
N002 ( 1, 1) [000068] D------N----- \--* LCL_VAR ref V11 tmp3 d:3
***** BB02, stmt 8
( 27, 31) [000081] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000078] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
N007 ( 1, 1) [000072] ------------- arg0 in r0 | | +--* LCL_VAR ref V11 tmp3 u:3
N008 ( 3, 7) [000073] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token
N009 ( 3, 7) [000074] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B74 token
N015 ( 27, 31) [000080] -ACXG---R---- \--* ASG int
N014 ( 3, 2) [000079] D------N----- \--* LCL_VAR int V12 tmp4 d:3
***** BB02, stmt 9
( 23, 10) [000084] ------------- * STMT void (IL ???... ???)
N009 ( 23, 10) [000083] --CXG-------- \--* CALL ind void
N008 ( 3, 2) [000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4 u:3 (last use)
N004 ( 1, 1) [000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3 u:3 (last use)
N005 ( 2, 2) [000066] ------------- arg1 in r1 \--* LCL_VAR int V02 arg2 u:3 (last use)
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 8, 7) [000011] ------------- * STMT void (IL 0x02C...0x02E)
N005 ( 8, 7) [000010] ------------- \--* JTRUE void
N003 ( 1, 1) [000008] ------------- | /--* CNS_INT int 0
N004 ( 6, 5) [000009] J------N--S-- \--* NE int
N002 ( 4, 3) [000120] ----------S-- \--* CAST int <- bool <- int
N001 ( 3, 2) [000007] ------------- \--* LCL_VAR int V04 arg4 u:2 (last use)
------------ BB04 [030..034), preds={BB03} succs={BB05}
***** BB04, stmt 11
( 13, 14) [000028] ------------- * STMT void (IL 0x030...0x033)
N010 ( 0, 0) [000026] ------------- | /--* NOP void
N011 ( 13, 14) [000027] ---XG-------- \--* COMMA void
N008 ( 5, 3) [000025] a--XG-------- | /--* IND ushort
N006 ( 1, 1) [000128] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
N007 ( 3, 3) [000129] -------N----- | | \--* ADD byref
N005 ( 1, 1) [000121] ------------- | | \--* LCL_VAR ref V00 arg0 u:2 (last use)
N009 ( 13, 14) [000131] ---XG-------- \--* COMMA void
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0 u:2
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 12
( 20, 19) [000018] ------------- * STMT void (IL 0x034...0x038)
N010 ( 2, 2) [000015] ------------- | /--* LCL_VAR int V03 arg3 u:2 (last use)
N011 ( 20, 19) [000017] -A-XG-------- \--* ASG byte
N008 ( 7, 4) [000016] a--XG--N----- | /--* IND byte
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
N007 ( 5, 4) [000138] -------N----- | | \--* ADD byref
N005 ( 3, 2) [000132] ------------- | | \--* LCL_VAR ref V05 arg5 u:2 (last use)
N009 ( 17, 16) [000139] ---XG--N----- \--* COMMA byte
N004 ( 10, 12) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0
N003 ( 5, 4) [000134] ---X--------- \--* ARR_LENGTH int
N002 ( 3, 2) [000013] ------------- \--* LCL_VAR ref V05 arg5 u:2
***** BB05, stmt 13
( 4, 4) [000021] ------------- * STMT void (IL 0x039...0x03A)
N003 ( 4, 4) [000020] ------------- \--* RETURN int
N002 ( 3, 3) [000141] ------------- \--* CAST int <- ushort <- int
N001 ( 2, 2) [000019] ------------- \--* LCL_VAR int V01 arg1 u:2 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In optEarlyProp()
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $82
The SSA definition for ByrefExposed (#2) at start of BB01 is $82 {InitVal($46)}
The SSA definition for GcHeap (#2) at start of BB01 is $82 {InitVal($46)}
***** BB01, stmt 1 (before)
N005 ( 8, 7) [000004] ------------- * JTRUE void
N003 ( 1, 1) [000002] ------------- | /--* CNS_INT int 0
N004 ( 6, 5) [000003] J------N--S-- \--* EQ int
N002 ( 4, 3) [000085] ----------S-- \--* CAST int <- bool <- int
N001 ( 3, 2) [000001] ------------- \--* LCL_VAR int V04 arg4 u:2
N001 [000001] LCL_VAR V04 arg4 u:2 => $140 {InitVal($44)}
VNForCastOper(bool) is $44
N002 [000085] CAST => $200 {Cast($140, $44)}
N003 [000002] CNS_INT 0 => $40 {IntCns 0}
N004 [000003] EQ => $201 {EQ($200, $40)}
***** BB01, stmt 1 (after)
N005 ( 8, 7) [000004] ------------- * JTRUE void
N003 ( 1, 1) [000002] ------------- | /--* CNS_INT int 0 $40
N004 ( 6, 5) [000003] J------N--S-- \--* EQ int $201
N002 ( 4, 3) [000085] ----------S-- \--* CAST int <- bool <- int $200
N001 ( 3, 2) [000001] ------------- \--* LCL_VAR int V04 arg4 u:2 $140
finish(BB01).
Succ(BB02).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB03).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
The SSA definition for ByrefExposed (#2) at start of BB02 is $82 {InitVal($46)}
The SSA definition for GcHeap (#2) at start of BB02 is $82 {InitVal($46)}
***** BB02, stmt 2 (before)
N002 ( 7, 11) [000031] ----G-------- /--* CAST long <- int
N001 ( 6, 10) [000030] ----G-------- | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3]
N004 ( 14, 17) [000033] -A--G---R---- * ASG long
N003 ( 3, 2) [000032] D------N----- \--* LCL_VAR long V06 loc0 d:3
VNApplySelectors:
VNForHandle(Fseq[s_3]) is $240, fieldType is int
VNForMapSelect($82, $240):int returns $202 {$82[$240]}
N001 [000030] CLS_VAR Hnd=0x9247f8 Fseq[s_3] => <l:$202 {$82[$240]}, c:$280 {280}>
VNForCastOper(long) is $47
N002 [000031] CAST => <l:$2c1 {Cast($202, $47)}, c:$2c0 {Cast($280, $47)}>
N003 [000032] LCL_VAR V06 loc0 d:3 => <l:$2c1 {Cast($202, $47)}, c:$2c0 {Cast($280, $47)}>
N004 [000033] ASG => <l:$2c1 {Cast($202, $47)}, c:$2c0 {Cast($280, $47)}>
***** BB02, stmt 2 (after)
N002 ( 7, 11) [000031] ----G-------- /--* CAST long <- int <l:$2c1, c:$2c0>
N001 ( 6, 10) [000030] ----G-------- | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3] <l:$202, c:$280>
N004 ( 14, 17) [000033] -A--G---R---- * ASG long <l:$2c1, c:$2c0>
N003 ( 3, 2) [000032] D------N----- \--* LCL_VAR long V06 loc0 d:3 <l:$2c1, c:$2c0>
---------
***** BB02, stmt 3 (before)
N011 ( 5, 3) [000037] a--XG-------- /--* IND ushort
N009 ( 1, 1) [000096] ------------- | | /--* CNS_INT int 8 Fseq[#FirstElem]
N010 ( 3, 3) [000097] -------N----- | \--* ADD byref
N008 ( 1, 1) [000089] ------------- | \--* LCL_VAR ref V13 tmp5 u:3 (last use)
N012 ( 13, 14) [000098] ---XG-------- /--* COMMA ushort
N007 ( 8, 11) [000092] ---X--------- | \--* ARR_BOUNDS_CHECK_Rng void
N004 ( 1, 1) [000036] ------------- | +--* CNS_INT int 0
N006 ( 3, 3) [000091] ---X--------- | \--* ARR_LENGTH int
N005 ( 1, 1) [000088] ------------- | \--* LCL_VAR ref V13 tmp5 u:3
N013 ( 19, 24) [000099] -A-XG-------- /--* COMMA ushort
N001 ( 6, 10) [000035] ----G-------- | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8]
N003 ( 6, 10) [000087] -A--G---R---- | \--* ASG ref
N002 ( 1, 1) [000086] D------N----- | \--* LCL_VAR ref V13 tmp5 d:3
N015 ( 19, 24) [000039] -A-XG---R---- * ASG ushort
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2 d:3
VNApplySelectors:
VNForHandle(Fseq[s_8]) is $241, fieldType is ref
VNForMapSelect($82, $241):ref returns $340 {$82[$241]}
N001 [000035] CLS_VAR Hnd=0x924808 Fseq[s_8] => <l:$340 {$82[$241]}, c:$380 {380}>
N002 [000086] LCL_VAR V13 tmp5 d:3 => <l:$340 {$82[$241]}, c:$380 {380}>
N003 [000087] ASG => <l:$340 {$82[$241]}, c:$380 {380}>
N004 [000036] CNS_INT 0 => $40 {IntCns 0}
N005 [000088] LCL_VAR V13 tmp5 u:3 => <l:$340 {$82[$241]}, c:$380 {380}>
N006 [000091] ARR_LENGTH => <l:$3c1 {ARR_LENGTH($340)}, c:$3c0 {ARR_LENGTH($380)}>
$343 = singleton exc set {IndexOutOfRangeExc($40, $3c0)}
$344 = singleton exc set {IndexOutOfRangeExc($40, $3c1)}
N007 [000092] ARR_BOUNDS_CHECK_Rng => <l:$346 {ValWithExc($3, $344)}, c:$345 {ValWithExc($3, $343)}>
N008 [000089] LCL_VAR V13 tmp5 u:3 (last use) => <l:$340 {$82[$241]}, c:$380 {380}>
N009 [000096] CNS_INT 8 Fseq[#FirstElem] => $48 {IntCns 8}
N010 [000097] ADD => <l:$401 {ADD($48, $340)}, c:$400 {ADD($48, $380)}>
Relabeled IND_ARR_INDEX address node [000097] with l:$440: {PtrToArrElem($242, $340, $40, $0)}
VNForMapSelect($82, $242):ref returns $347 {$82[$242]}
VNForMapSelect($347, $340):ref returns $348 {$347[$340]}
VNForMapSelect($348, $40):short returns $480 {$348[$40]}
hAtArrType $347 is MapSelect(curGcHeap($82), short[]).
hAtArrTypeAtArr $348 is MapSelect(hAtArrType($347), arr=$340).
wholeElem $480 is MapSelect(hAtArrTypeAtArr($348), ind=$40).
VNForCastOper(ushort) is $49
VNForCast($480, $49) returns $203 {Cast($480, $49)}
selectedElem is $203 after applying selectors.
N011 [000037] IND => <l:$203 {Cast($480, $49)}, c:$4c0 {4c0}>
N012 [000098] COMMA => <l:$204 {ValWithExc($203, $344)}, c:$500 {ValWithExc($4c0, $343)}>
N013 [000099] COMMA => <l:$204 {ValWithExc($203, $344)}, c:$500 {ValWithExc($4c0, $343)}>
N014 [000038] LCL_VAR V02 arg2 d:3 => <l:$203 {Cast($480, $49)}, c:$4c0 {4c0}>
N015 [000039] ASG => <l:$204 {ValWithExc($203, $344)}, c:$500 {ValWithExc($4c0, $343)}>
***** BB02, stmt 3 (after)
N011 ( 5, 3) [000037] a--XG-------- /--* IND ushort <l:$203, c:$4c0>
N009 ( 1, 1) [000096] ------------- | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N010 ( 3, 3) [000097] -------N----- | \--* ADD byref $440
N008 ( 1, 1) [000089] ------------- | \--* LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
N012 ( 13, 14) [000098] ---XG-------- /--* COMMA ushort <l:$204, c:$500>
N007 ( 8, 11) [000092] ---X--------- | \--* ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N004 ( 1, 1) [000036] ------------- | +--* CNS_INT int 0 $40
N006 ( 3, 3) [000091] ---X--------- | \--* ARR_LENGTH int <l:$3c1, c:$3c0>
N005 ( 1, 1) [000088] ------------- | \--* LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
N013 ( 19, 24) [000099] -A-XG-------- /--* COMMA ushort <l:$204, c:$500>
N001 ( 6, 10) [000035] ----G-------- | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8] <l:$340, c:$380>
N003 ( 6, 10) [000087] -A--G---R---- | \--* ASG ref <l:$340, c:$380>
N002 ( 1, 1) [000086] D------N----- | \--* LCL_VAR ref V13 tmp5 d:3 <l:$340, c:$380>
N015 ( 19, 24) [000039] -A-XG---R---- * ASG ushort <l:$204, c:$500>
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2 d:3 <l:$203, c:$4c0>
---------
***** BB02, stmt 4 (before)
N001 ( 6, 10) [000045] ----G-------- /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
N003 ( 6, 10) [000049] -A--G---R---- * ASG ref
N002 ( 1, 1) [000048] D------N----- \--* LCL_VAR ref V09 tmp1 d:3
VNApplySelectors:
VNForHandle(Fseq[s_rt]) is $243, fieldType is ref
VNForMapSelect($82, $243):ref returns $349 {$82[$243]}
N001 [000045] CLS_VAR Hnd=0x9247d8 Fseq[s_rt] => <l:$349 {$82[$243]}, c:$382 {382}>
N002 [000048] LCL_VAR V09 tmp1 d:3 => <l:$349 {$82[$243]}, c:$382 {382}>
N003 [000049] ASG => <l:$349 {$82[$243]}, c:$382 {382}>
***** BB02, stmt 4 (after)
N001 ( 6, 10) [000045] ----G-------- /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$349, c:$382>
N003 ( 6, 10) [000049] -A--G---R---- * ASG ref <l:$349, c:$382>
N002 ( 1, 1) [000048] D------N----- \--* LCL_VAR ref V09 tmp1 d:3 <l:$349, c:$382>
---------
***** BB02, stmt 5 (before)
N013 ( 23, 28) [000058] --CXG-------- /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
N007 ( 1, 1) [000052] ------------- arg0 in r0 | +--* LCL_VAR ref V09 tmp1 u:3
N008 ( 3, 7) [000053] ------------- arg1 in r1 | +--* CNS_INT(h) int 0x924994 token
N009 ( 3, 7) [000054] ------------- arg2 in r2 | \--* CNS_INT(h) int 0x924B10 token
N015 ( 27, 31) [000060] -ACXG---R---- * ASG int
N014 ( 3, 2) [000059] D------N----- \--* LCL_VAR int V10 tmp2 d:3
N001 [000100] ARGPLACE => $384 {384}
N002 [000102] ARGPLACE => $281 {281}
N003 [000104] ARGPLACE => $282 {282}
N004 [000055] LIST => $540 {LIST($282, $0)}
N005 [000056] LIST => $541 {LIST($281, $540)}
N006 [000057] LIST => $542 {LIST($384, $541)}
N007 [000052] LCL_VAR V09 tmp1 u:3 => <l:$349 {$82[$243]}, c:$382 {382}>
N008 [000053] CNS_INT(h) 0x924994 token => $244 {Hnd const: 0x00924994}
N009 [000054] CNS_INT(h) 0x924B10 token => $245 {Hnd const: 0x00924B10}
N010 [000105] LIST => $543 {LIST($245, $0)}
N011 [000103] LIST => $544 {LIST($244, $543)}
N012 [000101] LIST => <l:$546 {LIST($349, $544)}, c:$545 {LIST($382, $544)}>
VN of ARGPLACE tree [000100] updated to <l:$349 {$82[$243]}, c:$382 {382}>
VN of ARGPLACE tree [000102] updated to $244 {Hnd const: 0x00924994}
VN of ARGPLACE tree [000104] updated to $245 {Hnd const: 0x00924B10}
N004 [000055] LIST => $543 {LIST($245, $0)}
N005 [000056] LIST => $544 {LIST($244, $543)}
N006 [000057] LIST => <l:$546 {LIST($349, $544)}, c:$545 {LIST($382, $544)}>
$34a = singleton exc set {HelperMultipleExc()}
$34a = singleton exc set {HelperMultipleExc()}
fgCurMemoryVN[GcHeap] assigned by HELPER - modifies heap at [000058] to VN: $385.
N013 [000058] CALL help => $205 {ValWithExc($283, $34a)}
N014 [000059] LCL_VAR V10 tmp2 d:3 => $283 {283}
N015 [000060] ASG => $205 {ValWithExc($283, $34a)}
***** BB02, stmt 5 (after)
N013 ( 23, 28) [000058] --CXG-------- /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
N007 ( 1, 1) [000052] ------------- arg0 in r0 | +--* LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
N008 ( 3, 7) [000053] ------------- arg1 in r1 | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000054] ------------- arg2 in r2 | \--* CNS_INT(h) int 0x924B10 token $245
N015 ( 27, 31) [000060] -ACXG---R---- * ASG int $205
N014 ( 3, 2) [000059] D------N----- \--* LCL_VAR int V10 tmp2 d:3 $283
---------
***** BB02, stmt 6 (before)
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void
N008 ( 3, 2) [000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2 u:3 (last use)
N004 ( 1, 1) [000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1 u:3 (last use)
N005 ( 3, 2) [000046] ------------- arg1 r2,r3 \--* LCL_VAR long V06 loc0 u:3 (last use)
N001 [000106] ARGPLACE => $386 {386}
N002 [000108] ARGPLACE => $301 {301}
N003 [000047] LIST => $547 {LIST($301, $0)}
N004 [000051] LCL_VAR V09 tmp1 u:3 (last use) => <l:$349 {$82[$243]}, c:$382 {382}>
N005 [000046] LCL_VAR V06 loc0 u:3 (last use) => <l:$2c1 {Cast($202, $47)}, c:$2c0 {Cast($280, $47)}>
N006 [000109] LIST => <l:$549 {LIST($2c1, $0)}, c:$548 {LIST($2c0, $0)}>
N007 [000107] LIST => <l:$54b {LIST($349, $549)}, c:$54a {LIST($382, $548)}>
N008 [000062] LCL_VAR V10 tmp2 u:3 (last use) => $283 {283}
VN of ARGPLACE tree [000108] updated to <l:$349 {$82[$243]}, c:$382 {382}>
N003 [000047] LIST => <l:$54d {LIST($349, $0)}, c:$54c {LIST($382, $0)}>
fgCurMemoryVN[GcHeap] assigned by CALL at [000063] to VN: $387.
N009 [000063] CALL ind => $VN.Void
***** BB02, stmt 6 (after)
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
N008 ( 3, 2) [000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2 u:3 (last use) $283
N004 ( 1, 1) [000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
N005 ( 3, 2) [000046] ------------- arg1 r2,r3 \--* LCL_VAR long V06 loc0 u:3 (last use) <l:$2c1, c:$2c0>
---------
***** BB02, stmt 7 (before)
N001 ( 6, 10) [000065] ----G-------- /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt]
N003 ( 6, 10) [000069] -A--G---R---- * ASG ref
N002 ( 1, 1) [000068] D------N----- \--* LCL_VAR ref V11 tmp3 d:3
VNApplySelectors:
VNForHandle(Fseq[s_rt]) is $243, fieldType is ref
VNForMapSelect($387, $243):ref returns $34b {$387[$243]}
N001 [000065] CLS_VAR Hnd=0x9247d8 Fseq[s_rt] => <l:$34b {$387[$243]}, c:$388 {388}>
N002 [000068] LCL_VAR V11 tmp3 d:3 => <l:$34b {$387[$243]}, c:$388 {388}>
N003 [000069] ASG => <l:$34b {$387[$243]}, c:$388 {388}>
***** BB02, stmt 7 (after)
N001 ( 6, 10) [000065] ----G-------- /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$34b, c:$388>
N003 ( 6, 10) [000069] -A--G---R---- * ASG ref <l:$34b, c:$388>
N002 ( 1, 1) [000068] D------N----- \--* LCL_VAR ref V11 tmp3 d:3 <l:$34b, c:$388>
---------
***** BB02, stmt 8 (before)
N013 ( 23, 28) [000078] --CXG-------- /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR
N007 ( 1, 1) [000072] ------------- arg0 in r0 | +--* LCL_VAR ref V11 tmp3 u:3
N008 ( 3, 7) [000073] ------------- arg1 in r1 | +--* CNS_INT(h) int 0x924994 token
N009 ( 3, 7) [000074] ------------- arg2 in r2 | \--* CNS_INT(h) int 0x924B74 token
N015 ( 27, 31) [000080] -ACXG---R---- * ASG int
N014 ( 3, 2) [000079] D------N----- \--* LCL_VAR int V12 tmp4 d:3
N001 [000110] ARGPLACE => $38a {38a}
N002 [000112] ARGPLACE => $285 {285}
N003 [000114] ARGPLACE => $286 {286}
N004 [000075] LIST => $54e {LIST($286, $0)}
N005 [000076] LIST => $54f {LIST($285, $54e)}
N006 [000077] LIST => $550 {LIST($38a, $54f)}
N007 [000072] LCL_VAR V11 tmp3 u:3 => <l:$34b {$387[$243]}, c:$388 {388}>
N008 [000073] CNS_INT(h) 0x924994 token => $244 {Hnd const: 0x00924994}
N009 [000074] CNS_INT(h) 0x924B74 token => $246 {Hnd const: 0x00924B74}
N010 [000115] LIST => $551 {LIST($246, $0)}
N011 [000113] LIST => $552 {LIST($244, $551)}
N012 [000111] LIST => <l:$554 {LIST($34b, $552)}, c:$553 {LIST($388, $552)}>
VN of ARGPLACE tree [000110] updated to <l:$34b {$387[$243]}, c:$388 {388}>
VN of ARGPLACE tree [000112] updated to $244 {Hnd const: 0x00924994}
VN of ARGPLACE tree [000114] updated to $246 {Hnd const: 0x00924B74}
N004 [000075] LIST => $551 {LIST($246, $0)}
N005 [000076] LIST => $552 {LIST($244, $551)}
N006 [000077] LIST => <l:$554 {LIST($34b, $552)}, c:$553 {LIST($388, $552)}>
$34a = singleton exc set {HelperMultipleExc()}
$34a = singleton exc set {HelperMultipleExc()}
fgCurMemoryVN[GcHeap] assigned by HELPER - modifies heap at [000078] to VN: $38b.
N013 [000078] CALL help => $206 {ValWithExc($287, $34a)}
N014 [000079] LCL_VAR V12 tmp4 d:3 => $287 {287}
N015 [000080] ASG => $206 {ValWithExc($287, $34a)}
***** BB02, stmt 8 (after)
N013 ( 23, 28) [000078] --CXG-------- /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
N007 ( 1, 1) [000072] ------------- arg0 in r0 | +--* LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
N008 ( 3, 7) [000073] ------------- arg1 in r1 | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000074] ------------- arg2 in r2 | \--* CNS_INT(h) int 0x924B74 token $246
N015 ( 27, 31) [000080] -ACXG---R---- * ASG int $206
N014 ( 3, 2) [000079] D------N----- \--* LCL_VAR int V12 tmp4 d:3 $287
---------
***** BB02, stmt 9 (before)
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void
N008 ( 3, 2) [000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4 u:3 (last use)
N004 ( 1, 1) [000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3 u:3 (last use)
N005 ( 2, 2) [000066] ------------- arg1 in r1 \--* LCL_VAR int V02 arg2 u:3 (last use)
N001 [000116] ARGPLACE => $38c {38c}
N002 [000118] ARGPLACE => $289 {289}
N003 [000067] LIST => $555 {LIST($289, $0)}
N004 [000071] LCL_VAR V11 tmp3 u:3 (last use) => <l:$34b {$387[$243]}, c:$388 {388}>
N005 [000066] LCL_VAR V02 arg2 u:3 (last use) => <l:$203 {Cast($480, $49)}, c:$4c0 {4c0}>
N006 [000119] LIST => <l:$557 {LIST($203, $0)}, c:$556 {LIST($4c0, $0)}>
N007 [000117] LIST => <l:$559 {LIST($34b, $557)}, c:$558 {LIST($388, $556)}>
N008 [000082] LCL_VAR V12 tmp4 u:3 (last use) => $287 {287}
VN of ARGPLACE tree [000118] updated to <l:$34b {$387[$243]}, c:$388 {388}>
N003 [000067] LIST => <l:$55b {LIST($34b, $0)}, c:$55a {LIST($388, $0)}>
fgCurMemoryVN[GcHeap] assigned by CALL at [000083] to VN: $38d.
N009 [000083] CALL ind => $VN.Void
***** BB02, stmt 9 (after)
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
N008 ( 3, 2) [000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4 u:3 (last use) $287
N004 ( 1, 1) [000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
N005 ( 2, 2) [000066] ------------- arg1 in r1 \--* LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
finish(BB02).
Succ(BB03).
Not yet completed.
All preds complete, adding to allDone.
Building phi application: $43 = SSA# 3.
Building phi application: $42 = SSA# 2.
Building phi application: $34c = phi($42, $43).
The SSA definition for GcHeap (#4) at start of BB03 is $34d {PhiMemoryDef($247, $34c)}
***** BB03, stmt 10 (before)
N005 ( 8, 7) [000010] ------------- * JTRUE void
N003 ( 1, 1) [000008] ------------- | /--* CNS_INT int 0
N004 ( 6, 5) [000009] J------N--S-- \--* NE int
N002 ( 4, 3) [000120] ----------S-- \--* CAST int <- bool <- int
N001 ( 3, 2) [000007] ------------- \--* LCL_VAR int V04 arg4 u:2 (last use)
N001 [000007] LCL_VAR V04 arg4 u:2 (last use) => $140 {InitVal($44)}
VNForCastOper(bool) is $44
N002 [000120] CAST => $200 {Cast($140, $44)}
N003 [000008] CNS_INT 0 => $40 {IntCns 0}
N004 [000009] NE => $207 {NE($200, $40)}
***** BB03, stmt 10 (after)
N005 ( 8, 7) [000010] ------------- * JTRUE void
N003 ( 1, 1) [000008] ------------- | /--* CNS_INT int 0 $40
N004 ( 6, 5) [000009] J------N--S-- \--* NE int $207
N002 ( 4, 3) [000120] ----------S-- \--* CAST int <- bool <- int $200
N001 ( 3, 2) [000007] ------------- \--* LCL_VAR int V04 arg4 u:2 (last use) $140
finish(BB03).
Succ(BB04).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB05).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
The SSA definition for ByrefExposed (#4) at start of BB04 is $34d {PhiMemoryDef($247, $34c)}
The SSA definition for GcHeap (#4) at start of BB04 is $34d {PhiMemoryDef($247, $34c)}
***** BB04, stmt 11 (before)
N010 ( 0, 0) [000026] ------------- /--* NOP void
N011 ( 13, 14) [000027] ---XG-------- * COMMA void
N008 ( 5, 3) [000025] a--XG-------- | /--* IND ushort
N006 ( 1, 1) [000128] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
N007 ( 3, 3) [000129] -------N----- | | \--* ADD byref
N005 ( 1, 1) [000121] ------------- | | \--* LCL_VAR ref V00 arg0 u:2 (last use)
N009 ( 13, 14) [000131] ---XG-------- \--* COMMA void
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0 u:2
N001 [000024] CNS_INT 0 => $40 {IntCns 0}
N002 [000023] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)}
N003 [000123] ARR_LENGTH => $3c2 {ARR_LENGTH($80)}
$34f = singleton exc set {IndexOutOfRangeExc($40, $3c2)}
$34f = singleton exc set {IndexOutOfRangeExc($40, $3c2)}
N004 [000124] ARR_BOUNDS_CHECK_Rng => $350 {ValWithExc($3, $34f)}
N005 [000121] LCL_VAR V00 arg0 u:2 (last use) => $80 {InitVal($40)}
N006 [000128] CNS_INT 8 Fseq[#FirstElem] => $48 {IntCns 8}
N007 [000129] ADD => $402 {ADD($48, $80)}
Relabeled IND_ARR_INDEX address node [000129] with l:$441: {PtrToArrElem($242, $80, $40, $0)}
VNForMapSelect($34d, $242):ref returns $352 {$34d[$242]}
VNForMapSelect($352, $80):ref returns $353 {$352[$80]}
VNForMapSelect($353, $40):short returns $481 {$353[$40]}
hAtArrType $352 is MapSelect(curGcHeap($34d), short[]).
hAtArrTypeAtArr $353 is MapSelect(hAtArrType($352), arr=$80).
wholeElem $481 is MapSelect(hAtArrTypeAtArr($353), ind=$40).
VNForCastOper(ushort) is $49
VNForCast($481, $49) returns $208 {Cast($481, $49)}
selectedElem is $208 after applying selectors.
N008 [000025] IND => <l:$208 {Cast($481, $49)}, c:$4c2 {4c2}>
N009 [000131] COMMA => <l:$209 {ValWithExc($208, $34f)}, c:$501 {ValWithExc($4c2, $34f)}>
N010 [000026] NOP => $5c0 {5c0}
N011 [000027] COMMA => $55c {ValWithExc($5c0, $34f)}
***** BB04, stmt 11 (after)
N010 ( 0, 0) [000026] ------------- /--* NOP void $5c0
N011 ( 13, 14) [000027] ---XG-------- * COMMA void $55c
N008 ( 5, 3) [000025] a--XG-------- | /--* IND ushort <l:$208, c:$4c2>
N006 ( 1, 1) [000128] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000129] -------N----- | | \--* ADD byref $441
N005 ( 1, 1) [000121] ------------- | | \--* LCL_VAR ref V00 arg0 u:2 (last use) $80
N009 ( 13, 14) [000131] ---XG-------- \--* COMMA void <l:$209, c:$501>
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $350
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int $3c2
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0 u:2 $80
finish(BB04).
Succ(BB05).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#4) at start of BB05 is $34d {PhiMemoryDef($247, $34c)}
The SSA definition for GcHeap (#4) at start of BB05 is $34d {PhiMemoryDef($247, $34c)}
***** BB05, stmt 12 (before)
N010 ( 2, 2) [000015] ------------- /--* LCL_VAR int V03 arg3 u:2 (last use)
N011 ( 20, 19) [000017] -A-XG-------- * ASG byte
N008 ( 7, 4) [000016] a--XG--N----- | /--* IND byte
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem]
N007 ( 5, 4) [000138] -------N----- | | \--* ADD byref
N005 ( 3, 2) [000132] ------------- | | \--* LCL_VAR ref V05 arg5 u:2 (last use)
N009 ( 17, 16) [000139] ---XG--N----- \--* COMMA byte
N004 ( 10, 12) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0
N003 ( 5, 4) [000134] ---X--------- \--* ARR_LENGTH int
N002 ( 3, 2) [000013] ------------- \--* LCL_VAR ref V05 arg5 u:2
N001 [000014] CNS_INT 0 => $40 {IntCns 0}
N002 [000013] LCL_VAR V05 arg5 u:2 => $81 {InitVal($45)}
N003 [000134] ARR_LENGTH => $3c3 {ARR_LENGTH($81)}
$355 = singleton exc set {IndexOutOfRangeExc($40, $3c3)}
$355 = singleton exc set {IndexOutOfRangeExc($40, $3c3)}
N004 [000135] ARR_BOUNDS_CHECK_Rng => $356 {ValWithExc($3, $355)}
N005 [000132] LCL_VAR V05 arg5 u:2 (last use) => $81 {InitVal($45)}
N006 [000137] CNS_INT 8 Fseq[#FirstElem] => $48 {IntCns 8}
N007 [000138] ADD => $403 {ADD($48, $81)}
Relabeled IND_ARR_INDEX address node [000138] with l:$442: {PtrToArrElem($248, $81, $40, $0)}
N009 [000139] COMMA => $356 {ValWithExc($3, $355)}
N010 [000015] LCL_VAR V03 arg3 u:2 (last use) => $100 {InitVal($43)}
VNForCastOper(byte) is $4a
Tree [000017] assigns to an array element:
VNForMapSelect($34d, $248):ref returns $359 {$34d[$248]}
VNForMapSelect($359, $81):ref returns $35a {$359[$81]}
VNForMapSelect($35a, $40):byte returns $600 {$35a[$40]}
VNForCastOper(byte) is $4a
VNForCast($20a, $4a) returns $20b {Cast($20a, $4a)}
VNForMapStore($35a, $40, $20b):byte returns $640 {$35a[$40 := $20b]}
VNForMapStore($359, $81, $640):ref returns $680 {$359[$81 := $640]}
hAtArrType $359 is MapSelect(curGcHeap($34d), byte[]).
hAtArrTypeAtArr $35a is MapSelect(hAtArrType($359), arr=$81)
hAtArrTypeAtArrAtInx $600 is MapSelect(hAtArrTypeAtArr($35a), inx=$40):byte
newValAtInd $20b is {Cast($20a, $4a)}
newValAtArr $640 is {$35a[$40 := $20b]}
newValAtArrType $680 is {$359[$81 := $640]}
fgCurMemoryVN assigned:
VNForMapStore($34d, $248, $680):ref returns $681 {$34d[$248 := $680]}
fgCurMemoryVN[GcHeap] assigned by Array element assignment at [000017] to VN: $681.
N011 [000017] ASG => $VN.Void
***** BB05, stmt 12 (after)
N010 ( 2, 2) [000015] ------------- /--* LCL_VAR int V03 arg3 u:2 (last use) $100
N011 ( 20, 19) [000017] -A-XG-------- * ASG byte $VN.Void
N008 ( 7, 4) [000016] a--XG--N----- | /--* IND byte $20a
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 5, 4) [000138] -------N----- | | \--* ADD byref $442
N005 ( 3, 2) [000132] ------------- | | \--* LCL_VAR ref V05 arg5 u:2 (last use) $81
N009 ( 17, 16) [000139] ---XG--N----- \--* COMMA byte $VN.Void
N004 ( 10, 12) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $356
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0 $40
N003 ( 5, 4) [000134] ---X--------- \--* ARR_LENGTH int $3c3
N002 ( 3, 2) [000013] ------------- \--* LCL_VAR ref V05 arg5 u:2 $81
---------
***** BB05, stmt 13 (before)
N003 ( 4, 4) [000020] ------------- * RETURN int
N002 ( 3, 3) [000141] ------------- \--* CAST int <- ushort <- int
N001 ( 2, 2) [000019] ------------- \--* LCL_VAR int V01 arg1 u:2 (last use)
N001 [000019] LCL_VAR V01 arg1 u:2 (last use) => $c0 {InitVal($41)}
VNForCastOper(ushort) is $49
N002 [000141] CAST => $20c {Cast($c0, $49)}
N003 [000020] RETURN => $28a {28a}
***** BB05, stmt 13 (after)
N003 ( 4, 4) [000020] ------------- * RETURN int $28a
N002 ( 3, 3) [000141] ------------- \--* CAST int <- ushort <- int $20c
N001 ( 2, 2) [000019] ------------- \--* LCL_VAR int V01 arg1 u:2 (last use) $c0
finish(BB05).
*************** In optVnCopyProp()
*************** In SsaBuilder::ComputeDominators(Compiler*, ...)
Copy Assertion for BB01
curSsaName stack: { }
Copy Assertion for BB03
curSsaName stack: { 4-[000001]:V04 }
Live vars: {V00 V01 V03 V04 V05} => {V00 V01 V03 V05}
Copy Assertion for BB05
curSsaName stack: { 4-[000001]:V04 }
Live vars: {V01 V03 V05} => {V01 V03}
Live vars: {V01 V03} => {V01}
Live vars: {V01} => {}
Copy Assertion for BB04
curSsaName stack: { 1-[000019]:V01 3-[000015]:V03 4-[000001]:V04 5-[000013]:V05 }
Live vars: {V00 V01 V03 V05} => {V01 V03 V05}
Copy Assertion for BB02
curSsaName stack: { 0-[000023]:V00 1-[000019]:V01 3-[000015]:V03 4-[000001]:V04 5-[000013]:V05 }
Live vars: {V00 V01 V03 V04 V05} => {V00 V01 V03 V04 V05 V06}
Live vars: {V00 V01 V03 V04 V05 V06} => {V00 V01 V03 V04 V05 V06 V13}
Live vars: {V00 V01 V03 V04 V05 V06 V13} => {V00 V01 V03 V04 V05 V06}
Live vars: {V00 V01 V03 V04 V05 V06} => {V00 V01 V02 V03 V04 V05 V06}
Live vars: {V00 V01 V02 V03 V04 V05 V06} => {V00 V01 V02 V03 V04 V05 V06 V09}
Live vars: {V00 V01 V02 V03 V04 V05 V06 V09} => {V00 V01 V02 V03 V04 V05 V06 V09 V10}
Live vars: {V00 V01 V02 V03 V04 V05 V06 V09 V10} => {V00 V01 V02 V03 V04 V05 V06 V10}
Live vars: {V00 V01 V02 V03 V04 V05 V06 V10} => {V00 V01 V02 V03 V04 V05 V10}
Live vars: {V00 V01 V02 V03 V04 V05 V10} => {V00 V01 V02 V03 V04 V05}
Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V11}
Live vars: {V00 V01 V02 V03 V04 V05 V11} => {V00 V01 V02 V03 V04 V05 V11 V12}
Live vars: {V00 V01 V02 V03 V04 V05 V11 V12} => {V00 V01 V02 V03 V04 V05 V12}
Live vars: {V00 V01 V02 V03 V04 V05 V12} => {V00 V01 V03 V04 V05 V12}
Live vars: {V00 V01 V03 V04 V05 V12} => {V00 V01 V03 V04 V05}
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 8, 7) [000005] ------------- * STMT void (IL 0x000...0x002)
N005 ( 8, 7) [000004] ------------- \--* JTRUE void
N003 ( 1, 1) [000002] ------------- | /--* CNS_INT int 0 $40
N004 ( 6, 5) [000003] J------N--S-- \--* EQ int $201
N002 ( 4, 3) [000085] ----------S-- \--* CAST int <- bool <- int $200
N001 ( 3, 2) [000001] ------------- \--* LCL_VAR int V04 arg4 u:2 $140
------------ BB02 [004..02C), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 14, 17) [000034] ------------- * STMT void (IL 0x004...0x00A)
N002 ( 7, 11) [000031] ----G-------- | /--* CAST long <- int <l:$2c1, c:$2c0>
N001 ( 6, 10) [000030] ----G-------- | | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3] <l:$202, c:$280>
N004 ( 14, 17) [000033] -A--G---R---- \--* ASG long <l:$2c1, c:$2c0>
N003 ( 3, 2) [000032] D------N----- \--* LCL_VAR long V06 loc0 d:3 <l:$2c1, c:$2c0>
***** BB02, stmt 3
( 19, 24) [000040] ------------- * STMT void (IL 0x00B...0x012)
N011 ( 5, 3) [000037] a--XG-------- | /--* IND ushort <l:$203, c:$4c0>
N009 ( 1, 1) [000096] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N010 ( 3, 3) [000097] -------N----- | | \--* ADD byref $440
N008 ( 1, 1) [000089] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
N012 ( 13, 14) [000098] ---XG-------- | /--* COMMA ushort <l:$204, c:$500>
N007 ( 8, 11) [000092] ---X--------- | | \--* ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N004 ( 1, 1) [000036] ------------- | | +--* CNS_INT int 0 $40
N006 ( 3, 3) [000091] ---X--------- | | \--* ARR_LENGTH int <l:$3c1, c:$3c0>
N005 ( 1, 1) [000088] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
N013 ( 19, 24) [000099] -A-XG-------- | /--* COMMA ushort <l:$204, c:$500>
N001 ( 6, 10) [000035] ----G-------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8] <l:$340, c:$380>
N003 ( 6, 10) [000087] -A--G---R---- | | \--* ASG ref <l:$340, c:$380>
N002 ( 1, 1) [000086] D------N----- | | \--* LCL_VAR ref V13 tmp5 d:3 <l:$340, c:$380>
N015 ( 19, 24) [000039] -A-XG---R---- \--* ASG ushort <l:$204, c:$500>
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2 d:3 <l:$203, c:$4c0>
***** BB02, stmt 4
( 6, 10) [000050] ------------- * STMT void (IL 0x016...0x027)
N001 ( 6, 10) [000045] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$349, c:$382>
N003 ( 6, 10) [000049] -A--G---R---- \--* ASG ref <l:$349, c:$382>
N002 ( 1, 1) [000048] D------N----- \--* LCL_VAR ref V09 tmp1 d:3 <l:$349, c:$382>
***** BB02, stmt 5
( 27, 31) [000061] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000058] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
N007 ( 1, 1) [000052] ------------- arg0 in r0 | | +--* LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
N008 ( 3, 7) [000053] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000054] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B10 token $245
N015 ( 27, 31) [000060] -ACXG---R---- \--* ASG int $205
N014 ( 3, 2) [000059] D------N----- \--* LCL_VAR int V10 tmp2 d:3 $283
***** BB02, stmt 6
( 24, 10) [000064] ------------- * STMT void (IL ???... ???)
N009 ( 24, 10) [000063] --CXG-------- \--* CALL ind void $VN.Void
N008 ( 3, 2) [000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2 u:3 (last use) $283
N004 ( 1, 1) [000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
N005 ( 3, 2) [000046] ------------- arg1 r2,r3 \--* LCL_VAR long V06 loc0 u:3 (last use) <l:$2c1, c:$2c0>
***** BB02, stmt 7
( 6, 10) [000070] ------------- * STMT void (IL 0x021... ???)
N001 ( 6, 10) [000065] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$34b, c:$388>
N003 ( 6, 10) [000069] -A--G---R---- \--* ASG ref <l:$34b, c:$388>
N002 ( 1, 1) [000068] D------N----- \--* LCL_VAR ref V11 tmp3 d:3 <l:$34b, c:$388>
***** BB02, stmt 8
( 27, 31) [000081] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000078] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
N007 ( 1, 1) [000072] ------------- arg0 in r0 | | +--* LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
N008 ( 3, 7) [000073] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000074] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B74 token $246
N015 ( 27, 31) [000080] -ACXG---R---- \--* ASG int $206
N014 ( 3, 2) [000079] D------N----- \--* LCL_VAR int V12 tmp4 d:3 $287
***** BB02, stmt 9
( 23, 10) [000084] ------------- * STMT void (IL ???... ???)
N009 ( 23, 10) [000083] --CXG-------- \--* CALL ind void $VN.Void
N008 ( 3, 2) [000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4 u:3 (last use) $287
N004 ( 1, 1) [000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
N005 ( 2, 2) [000066] ------------- arg1 in r1 \--* LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 8, 7) [000011] ------------- * STMT void (IL 0x02C...0x02E)
N005 ( 8, 7) [000010] ------------- \--* JTRUE void
N003 ( 1, 1) [000008] ------------- | /--* CNS_INT int 0 $40
N004 ( 6, 5) [000009] J------N--S-- \--* NE int $207
N002 ( 4, 3) [000120] ----------S-- \--* CAST int <- bool <- int $200
N001 ( 3, 2) [000007] ------------- \--* LCL_VAR int V04 arg4 u:2 (last use) $140
------------ BB04 [030..034), preds={BB03} succs={BB05}
***** BB04, stmt 11
( 13, 14) [000028] ------------- * STMT void (IL 0x030...0x033)
N010 ( 0, 0) [000026] ------------- | /--* NOP void $5c0
N011 ( 13, 14) [000027] ---XG-------- \--* COMMA void $55c
N008 ( 5, 3) [000025] a--XG-------- | /--* IND ushort <l:$208, c:$4c2>
N006 ( 1, 1) [000128] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000129] -------N----- | | \--* ADD byref $441
N005 ( 1, 1) [000121] ------------- | | \--* LCL_VAR ref V00 arg0 u:2 (last use) $80
N009 ( 13, 14) [000131] ---XG-------- \--* COMMA void <l:$209, c:$501>
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $350
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int $3c2
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0 u:2 $80
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 12
( 20, 19) [000018] ------------- * STMT void (IL 0x034...0x038)
N010 ( 2, 2) [000015] ------------- | /--* LCL_VAR int V03 arg3 u:2 (last use) $100
N011 ( 20, 19) [000017] -A-XG-------- \--* ASG byte $VN.Void
N008 ( 7, 4) [000016] a--XG--N----- | /--* IND byte $20a
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 5, 4) [000138] -------N----- | | \--* ADD byref $442
N005 ( 3, 2) [000132] ------------- | | \--* LCL_VAR ref V05 arg5 u:2 (last use) $81
N009 ( 17, 16) [000139] ---XG--N----- \--* COMMA byte $VN.Void
N004 ( 10, 12) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $356
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0 $40
N003 ( 5, 4) [000134] ---X--------- \--* ARR_LENGTH int $3c3
N002 ( 3, 2) [000013] ------------- \--* LCL_VAR ref V05 arg5 u:2 $81
***** BB05, stmt 13
( 4, 4) [000021] ------------- * STMT void (IL 0x039...0x03A)
N003 ( 4, 4) [000020] ------------- \--* RETURN int $28a
N002 ( 3, 3) [000141] ------------- \--* CAST int <- ushort <- int $20c
N001 ( 2, 2) [000019] ------------- \--* LCL_VAR int V01 arg1 u:2 (last use) $c0
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
CSE candidate #01, vn=$200 cseMask=0000000000000001 in BB03, [cost= 4, size= 3]:
N002 ( 4, 3) CSE #01 (use)[000120] ----------S-- * CAST int <- bool <- int $200
N001 ( 3, 2) [000007] ------------- \--* LCL_VAR int V04 arg4 u:2 (last use) $140
Blocks that generate CSE def/uses
BB01 cseGen = 0000000000000001
BB02 cseGen = 0000000000000000
BB03 cseGen = 0000000000000001
BB04 cseGen = 0000000000000000
BB05 cseGen = 0000000000000000
After performing DataFlow for ValnumCSE's
BB01 cseIn = 0000000000000000 cseOut = 0000000000000001
BB02 cseIn = 0000000000000001 cseOut = 0000000000000001
BB03 cseIn = 0000000000000001 cseOut = 0000000000000001
BB04 cseIn = 0000000000000001 cseOut = 0000000000000001
BB05 cseIn = 0000000000000001 cseOut = 0000000000000001
Labeling the CSEs with Use/Def information
BB01 [000085] Def of CSE #01 [weight=1 ]
BB03 [000120] Use of CSE #01 [weight=1 ]
************ Trees at start of optValnumCSE_Heuristic()
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 8, 7) [000005] ------------- * STMT void (IL 0x000...0x002)
N005 ( 8, 7) [000004] ------------- \--* JTRUE void
N003 ( 1, 1) [000002] ------------- | /--* CNS_INT int 0 $40
N004 ( 6, 5) [000003] J------N--S-- \--* EQ int $201
N002 ( 4, 3) CSE #01 (def)[000085] ----------S-- \--* CAST int <- bool <- int $200
N001 ( 3, 2) [000001] ------------- \--* LCL_VAR int V04 arg4 u:2 $140
------------ BB02 [004..02C), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 14, 17) [000034] ------------- * STMT void (IL 0x004...0x00A)
N002 ( 7, 11) [000031] ----G-------- | /--* CAST long <- int <l:$2c1, c:$2c0>
N001 ( 6, 10) [000030] ----G-------- | | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3] <l:$202, c:$280>
N004 ( 14, 17) [000033] -A--G---R---- \--* ASG long <l:$2c1, c:$2c0>
N003 ( 3, 2) [000032] D------N----- \--* LCL_VAR long V06 loc0 d:3 <l:$2c1, c:$2c0>
***** BB02, stmt 3
( 19, 24) [000040] ------------- * STMT void (IL 0x00B...0x012)
N011 ( 5, 3) [000037] a--XG-------- | /--* IND ushort <l:$203, c:$4c0>
N009 ( 1, 1) [000096] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N010 ( 3, 3) [000097] -------N----- | | \--* ADD byref $440
N008 ( 1, 1) [000089] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
N012 ( 13, 14) [000098] ---XG-------- | /--* COMMA ushort <l:$204, c:$500>
N007 ( 8, 11) [000092] ---X--------- | | \--* ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N004 ( 1, 1) [000036] ------------- | | +--* CNS_INT int 0 $40
N006 ( 3, 3) [000091] ---X--------- | | \--* ARR_LENGTH int <l:$3c1, c:$3c0>
N005 ( 1, 1) [000088] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
N013 ( 19, 24) [000099] -A-XG-------- | /--* COMMA ushort <l:$204, c:$500>
N001 ( 6, 10) [000035] ----G-------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8] <l:$340, c:$380>
N003 ( 6, 10) [000087] -A--G---R---- | | \--* ASG ref <l:$340, c:$380>
N002 ( 1, 1) [000086] D------N----- | | \--* LCL_VAR ref V13 tmp5 d:3 <l:$340, c:$380>
N015 ( 19, 24) [000039] -A-XG---R---- \--* ASG ushort <l:$204, c:$500>
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2 d:3 <l:$203, c:$4c0>
***** BB02, stmt 4
( 6, 10) [000050] ------------- * STMT void (IL 0x016...0x027)
N001 ( 6, 10) [000045] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$349, c:$382>
N003 ( 6, 10) [000049] -A--G---R---- \--* ASG ref <l:$349, c:$382>
N002 ( 1, 1) [000048] D------N----- \--* LCL_VAR ref V09 tmp1 d:3 <l:$349, c:$382>
***** BB02, stmt 5
( 27, 31) [000061] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000058] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
N007 ( 1, 1) [000052] ------------- arg0 in r0 | | +--* LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
N008 ( 3, 7) [000053] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000054] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B10 token $245
N015 ( 27, 31) [000060] -ACXG---R---- \--* ASG int $205
N014 ( 3, 2) [000059] D------N----- \--* LCL_VAR int V10 tmp2 d:3 $283
***** BB02, stmt 6
( 24, 10) [000064] ------------- * STMT void (IL ???... ???)
N009 ( 24, 10) [000063] --CXG-------- \--* CALL ind void $VN.Void
N008 ( 3, 2) [000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2 u:3 (last use) $283
N004 ( 1, 1) [000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
N005 ( 3, 2) [000046] ------------- arg1 r2,r3 \--* LCL_VAR long V06 loc0 u:3 (last use) <l:$2c1, c:$2c0>
***** BB02, stmt 7
( 6, 10) [000070] ------------- * STMT void (IL 0x021... ???)
N001 ( 6, 10) [000065] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$34b, c:$388>
N003 ( 6, 10) [000069] -A--G---R---- \--* ASG ref <l:$34b, c:$388>
N002 ( 1, 1) [000068] D------N----- \--* LCL_VAR ref V11 tmp3 d:3 <l:$34b, c:$388>
***** BB02, stmt 8
( 27, 31) [000081] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000078] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
N007 ( 1, 1) [000072] ------------- arg0 in r0 | | +--* LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
N008 ( 3, 7) [000073] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000074] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B74 token $246
N015 ( 27, 31) [000080] -ACXG---R---- \--* ASG int $206
N014 ( 3, 2) [000079] D------N----- \--* LCL_VAR int V12 tmp4 d:3 $287
***** BB02, stmt 9
( 23, 10) [000084] ------------- * STMT void (IL ???... ???)
N009 ( 23, 10) [000083] --CXG-------- \--* CALL ind void $VN.Void
N008 ( 3, 2) [000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4 u:3 (last use) $287
N004 ( 1, 1) [000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
N005 ( 2, 2) [000066] ------------- arg1 in r1 \--* LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 8, 7) [000011] ------------- * STMT void (IL 0x02C...0x02E)
N005 ( 8, 7) [000010] ------------- \--* JTRUE void
N003 ( 1, 1) [000008] ------------- | /--* CNS_INT int 0 $40
N004 ( 6, 5) [000009] J------N--S-- \--* NE int $207
N002 ( 4, 3) CSE #01 (use)[000120] ----------S-- \--* CAST int <- bool <- int $200
N001 ( 3, 2) [000007] ------------- \--* LCL_VAR int V04 arg4 u:2 (last use) $140
------------ BB04 [030..034), preds={BB03} succs={BB05}
***** BB04, stmt 11
( 13, 14) [000028] ------------- * STMT void (IL 0x030...0x033)
N010 ( 0, 0) [000026] ------------- | /--* NOP void $5c0
N011 ( 13, 14) [000027] ---XG-------- \--* COMMA void $55c
N008 ( 5, 3) [000025] a--XG-------- | /--* IND ushort <l:$208, c:$4c2>
N006 ( 1, 1) [000128] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000129] -------N----- | | \--* ADD byref $441
N005 ( 1, 1) [000121] ------------- | | \--* LCL_VAR ref V00 arg0 u:2 (last use) $80
N009 ( 13, 14) [000131] ---XG-------- \--* COMMA void <l:$209, c:$501>
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $350
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int $3c2
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0 u:2 $80
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 12
( 20, 19) [000018] ------------- * STMT void (IL 0x034...0x038)
N010 ( 2, 2) [000015] ------------- | /--* LCL_VAR int V03 arg3 u:2 (last use) $100
N011 ( 20, 19) [000017] -A-XG-------- \--* ASG byte $VN.Void
N008 ( 7, 4) [000016] a--XG--N----- | /--* IND byte $20a
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 5, 4) [000138] -------N----- | | \--* ADD byref $442
N005 ( 3, 2) [000132] ------------- | | \--* LCL_VAR ref V05 arg5 u:2 (last use) $81
N009 ( 17, 16) [000139] ---XG--N----- \--* COMMA byte $VN.Void
N004 ( 10, 12) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $356
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0 $40
N003 ( 5, 4) [000134] ---X--------- \--* ARR_LENGTH int $3c3
N002 ( 3, 2) [000013] ------------- \--* LCL_VAR ref V05 arg5 u:2 $81
***** BB05, stmt 13
( 4, 4) [000021] ------------- * STMT void (IL 0x039...0x03A)
N003 ( 4, 4) [000020] ------------- \--* RETURN int $28a
N002 ( 3, 3) [000141] ------------- \--* CAST int <- ushort <- int $20c
N001 ( 2, 2) [000019] ------------- \--* LCL_VAR int V01 arg1 u:2 (last use) $c0
-------------------------------------------------------------------------------------------------------------------
Aggressive CSE Promotion cutoff is 300
Moderate CSE Promotion cutoff is 150
Framesize estimate is 0x0000
We have a small frame
Sorted CSE candidates:
CSE #01,cseMask=0000000000000001,useCnt=1: [def=100, use=100] :: N002 ( 4, 3) CSE #01 (def)[000085] ----------S-- * CAST int <- bool <- int $200
Considering CSE #01 [def=100, use=100, cost= 4] CSE Expression:
N002 ( 4, 3) CSE #01 (def)[000085] ----------S-- * CAST int <- bool <- int $200
N001 ( 3, 2) [000001] ------------- \--* LCL_VAR int V04 arg4 u:2 $140
Aggressive CSE Promotion (300 >= 300)
cseRefCnt=300, aggressiveRefCnt=300, moderateRefCnt=150
defCnt=100, useCnt=100, cost=4, size=3
def_cost=1, use_cost=1, extra_no_cost=4, extra_yes_cost=0
CSE cost savings check (404 >= 200) passes
Promoting CSE:
lvaGrabTemp returning 14 (V14 rat0) (a long lifetime temp) called for ValNumCSE.
CSE #01 def at [000085] replaced in BB01 with def of V14
New refCnts for V14: refCnt = 1, refCntWtd = 1
New refCnts for V14: refCnt = 2, refCntWtd = 2
New refCnts for V14: refCnt = 3, refCntWtd = 3
New refCnts for V04: refCnt = 3, refCntWtd = 3
New refCnts for V14: refCnt = 4, refCntWtd = 4
optValnumCSE morphed tree:
N009 ( 8, 8) [000004] -A----------- * JTRUE void
N007 ( 1, 1) [000002] ------------- | /--* CNS_INT int 0 $40
N008 ( 6, 6) [000003] JA-----N--S-- \--* EQ int $201
N005 ( 1, 1) [000144] ------------- | /--* LCL_VAR int V14 cse0 $200
N006 ( 4, 4) [000145] -A--------S-- \--* COMMA int $200
N002 ( 3, 3) [000085] ----------S-- | /--* CAST int <- bool <- int $200
N001 ( 2, 2) [000001] ------------- | | \--* LCL_VAR int V04 arg4 u:2 $140
N004 ( 3, 3) [000143] -A------R---- \--* ASG int $VN.Void
N003 ( 1, 1) [000142] D------N----- \--* LCL_VAR int V14 cse0 $200
Working on the replacement of the CSE #01 use at [000120] in BB03
New refCnts for V04: refCnt = 2, refCntWtd = 2
CSE #00 use at [000120] replaced in BB03 with temp use.
New refCnts for V14: refCnt = 5, refCntWtd = 5
New refCnts for V14: refCnt = 6, refCntWtd = 6
optValnumCSE morphed tree:
N004 ( 5, 5) [000010] ------------- * JTRUE void
N002 ( 1, 1) [000008] ------------- | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000009] J------N--S-- \--* NE int $207
N001 ( 1, 1) [000146] ------------- \--* LCL_VAR int V14 cse0 $200
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 8, 8) [000005] ------------- * STMT void (IL 0x000...0x002)
N009 ( 8, 8) [000004] -A----------- \--* JTRUE void
N007 ( 1, 1) [000002] ------------- | /--* CNS_INT int 0 $40
N008 ( 6, 6) [000003] JA-----N--S-- \--* EQ int $201
N005 ( 1, 1) [000144] ------------- | /--* LCL_VAR int V14 cse0 $200
N006 ( 4, 4) [000145] -A--------S-- \--* COMMA int $200
N002 ( 3, 3) [000085] ----------S-- | /--* CAST int <- bool <- int $200
N001 ( 2, 2) [000001] ------------- | | \--* LCL_VAR int V04 arg4 u:2 $140
N004 ( 3, 3) [000143] -A------R---- \--* ASG int $VN.Void
N003 ( 1, 1) [000142] D------N----- \--* LCL_VAR int V14 cse0 $200
------------ BB02 [004..02C), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 14, 17) [000034] ------------- * STMT void (IL 0x004...0x00A)
N002 ( 7, 11) [000031] ----G-------- | /--* CAST long <- int <l:$2c1, c:$2c0>
N001 ( 6, 10) [000030] ----G-------- | | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3] <l:$202, c:$280>
N004 ( 14, 17) [000033] -A--G---R---- \--* ASG long <l:$2c1, c:$2c0>
N003 ( 3, 2) [000032] D------N----- \--* LCL_VAR long V06 loc0 d:3 <l:$2c1, c:$2c0>
***** BB02, stmt 3
( 19, 24) [000040] ------------- * STMT void (IL 0x00B...0x012)
N011 ( 5, 3) [000037] a--XG-------- | /--* IND ushort <l:$203, c:$4c0>
N009 ( 1, 1) [000096] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N010 ( 3, 3) [000097] -------N----- | | \--* ADD byref $440
N008 ( 1, 1) [000089] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
N012 ( 13, 14) [000098] ---XG-------- | /--* COMMA ushort <l:$204, c:$500>
N007 ( 8, 11) [000092] ---X--------- | | \--* ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N004 ( 1, 1) [000036] ------------- | | +--* CNS_INT int 0 $40
N006 ( 3, 3) [000091] ---X--------- | | \--* ARR_LENGTH int <l:$3c1, c:$3c0>
N005 ( 1, 1) [000088] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
N013 ( 19, 24) [000099] -A-XG-------- | /--* COMMA ushort <l:$204, c:$500>
N001 ( 6, 10) [000035] ----G-------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8] <l:$340, c:$380>
N003 ( 6, 10) [000087] -A--G---R---- | | \--* ASG ref <l:$340, c:$380>
N002 ( 1, 1) [000086] D------N----- | | \--* LCL_VAR ref V13 tmp5 d:3 <l:$340, c:$380>
N015 ( 19, 24) [000039] -A-XG---R---- \--* ASG ushort <l:$204, c:$500>
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2 d:3 <l:$203, c:$4c0>
***** BB02, stmt 4
( 6, 10) [000050] ------------- * STMT void (IL 0x016...0x027)
N001 ( 6, 10) [000045] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$349, c:$382>
N003 ( 6, 10) [000049] -A--G---R---- \--* ASG ref <l:$349, c:$382>
N002 ( 1, 1) [000048] D------N----- \--* LCL_VAR ref V09 tmp1 d:3 <l:$349, c:$382>
***** BB02, stmt 5
( 27, 31) [000061] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000058] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
N007 ( 1, 1) [000052] ------------- arg0 in r0 | | +--* LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
N008 ( 3, 7) [000053] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000054] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B10 token $245
N015 ( 27, 31) [000060] -ACXG---R---- \--* ASG int $205
N014 ( 3, 2) [000059] D------N----- \--* LCL_VAR int V10 tmp2 d:3 $283
***** BB02, stmt 6
( 24, 10) [000064] ------------- * STMT void (IL ???... ???)
N009 ( 24, 10) [000063] --CXG-------- \--* CALL ind void $VN.Void
N008 ( 3, 2) [000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2 u:3 (last use) $283
N004 ( 1, 1) [000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
N005 ( 3, 2) [000046] ------------- arg1 r2,r3 \--* LCL_VAR long V06 loc0 u:3 (last use) <l:$2c1, c:$2c0>
***** BB02, stmt 7
( 6, 10) [000070] ------------- * STMT void (IL 0x021... ???)
N001 ( 6, 10) [000065] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$34b, c:$388>
N003 ( 6, 10) [000069] -A--G---R---- \--* ASG ref <l:$34b, c:$388>
N002 ( 1, 1) [000068] D------N----- \--* LCL_VAR ref V11 tmp3 d:3 <l:$34b, c:$388>
***** BB02, stmt 8
( 27, 31) [000081] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000078] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
N007 ( 1, 1) [000072] ------------- arg0 in r0 | | +--* LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
N008 ( 3, 7) [000073] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000074] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B74 token $246
N015 ( 27, 31) [000080] -ACXG---R---- \--* ASG int $206
N014 ( 3, 2) [000079] D------N----- \--* LCL_VAR int V12 tmp4 d:3 $287
***** BB02, stmt 9
( 23, 10) [000084] ------------- * STMT void (IL ???... ???)
N009 ( 23, 10) [000083] --CXG-------- \--* CALL ind void $VN.Void
N008 ( 3, 2) [000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4 u:3 (last use) $287
N004 ( 1, 1) [000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
N005 ( 2, 2) [000066] ------------- arg1 in r1 \--* LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 5, 5) [000011] ------------- * STMT void (IL 0x02C...0x02E)
N004 ( 5, 5) [000010] ------------- \--* JTRUE void
N002 ( 1, 1) [000008] ------------- | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000009] J------N--S-- \--* NE int $207
N001 ( 1, 1) [000146] ------------- \--* LCL_VAR int V14 cse0 $200
------------ BB04 [030..034), preds={BB03} succs={BB05}
***** BB04, stmt 11
( 13, 14) [000028] ------------- * STMT void (IL 0x030...0x033)
N010 ( 0, 0) [000026] ------------- | /--* NOP void $5c0
N011 ( 13, 14) [000027] ---XG-------- \--* COMMA void $55c
N008 ( 5, 3) [000025] a--XG-------- | /--* IND ushort <l:$208, c:$4c2>
N006 ( 1, 1) [000128] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000129] -------N----- | | \--* ADD byref $441
N005 ( 1, 1) [000121] ------------- | | \--* LCL_VAR ref V00 arg0 u:2 (last use) $80
N009 ( 13, 14) [000131] ---XG-------- \--* COMMA void <l:$209, c:$501>
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $350
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int $3c2
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0 u:2 $80
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 12
( 20, 19) [000018] ------------- * STMT void (IL 0x034...0x038)
N010 ( 2, 2) [000015] ------------- | /--* LCL_VAR int V03 arg3 u:2 (last use) $100
N011 ( 20, 19) [000017] -A-XG-------- \--* ASG byte $VN.Void
N008 ( 7, 4) [000016] a--XG--N----- | /--* IND byte $20a
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 5, 4) [000138] -------N----- | | \--* ADD byref $442
N005 ( 3, 2) [000132] ------------- | | \--* LCL_VAR ref V05 arg5 u:2 (last use) $81
N009 ( 17, 16) [000139] ---XG--N----- \--* COMMA byte $VN.Void
N004 ( 10, 12) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $356
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0 $40
N003 ( 5, 4) [000134] ---X--------- \--* ARR_LENGTH int $3c3
N002 ( 3, 2) [000013] ------------- \--* LCL_VAR ref V05 arg5 u:2 $81
***** BB05, stmt 13
( 4, 4) [000021] ------------- * STMT void (IL 0x039...0x03A)
N003 ( 4, 4) [000020] ------------- \--* RETURN int $28a
N002 ( 3, 3) [000141] ------------- \--* CAST int <- ushort <- int $20c
N001 ( 2, 2) [000019] ------------- \--* LCL_VAR int V01 arg1 u:2 (last use) $c0
-------------------------------------------------------------------------------------------------------------------
GenTreeNode creates assertion:
N002 ( 3, 3) [000085] ----------S-- * CAST int <- bool <- int $200
In BB01 New Global Subrange Assertion: (320, 0) ($140,$0) V04.02 in [0..1] index=#01, mask=0000000000000001
GenTreeNode creates assertion:
N006 ( 3, 3) [000091] ---X--------- * ARR_LENGTH int <l:$3c1, c:$3c0>
In BB02 New Global Constant Assertion: (896, 0) ($380,$0) V13.03 != null index=#02, mask=0000000000000002
GenTreeNode creates assertion:
N007 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
In BB02 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {IntCns 0};len: {ARR_LENGTH($380)}] in range index=#03, mask=0000000000000004
GenTreeNode creates assertion:
N003 ( 3, 3) [000123] ---X--------- * ARR_LENGTH int $3c2
In BB04 New Global Constant Assertion: (128, 0) ($80,$0) V00.02 != null index=#04, mask=0000000000000008
GenTreeNode creates assertion:
N004 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
In BB04 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {IntCns 0};len: {ARR_LENGTH($80)}] in range index=#05, mask=0000000000000010
GenTreeNode creates assertion:
N003 ( 5, 4) [000134] ---X--------- * ARR_LENGTH int $3c3
In BB05 New Global Constant Assertion: (129, 0) ($81,$0) V05.02 != null index=#06, mask=0000000000000020
GenTreeNode creates assertion:
N004 ( 10, 12) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
In BB05 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {IntCns 0};len: {ARR_LENGTH($81)}] in range index=#07, mask=0000000000000040
GenTreeNode creates assertion:
N002 ( 3, 3) [000141] ------------- * CAST int <- ushort <- int $20c
In BB05 New Global Subrange Assertion: (192, 0) ($c0,$0) V01.02 in [0..65535] index=#08, mask=0000000000000080
BB01 valueGen = 0000000000000000 => BB03 valueGen = 0000000000000000,
BB02 valueGen = 0000000000000006
BB03 valueGen = 0000000000000000 => BB05 valueGen = 0000000000000000,
BB04 valueGen = 0000000000000018
BB05 valueGen = 0000000000000060AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000
AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000
AssertionPropCallback::Changed : BB01 before out -> 00000000000000FF; after out -> 0000000000000000;
jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000000;
AssertionPropCallback::StartMerge: BB02 in -> 00000000000000FF
AssertionPropCallback::Merge : BB02 in -> 00000000000000FF, predBlock BB01 out -> 0000000000000000
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000000
AssertionPropCallback::Changed : BB02 before out -> 00000000000000FF; after out -> 0000000000000006;
jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000000;
AssertionPropCallback::StartMerge: BB03 in -> 00000000000000FF
AssertionPropCallback::Merge : BB03 in -> 00000000000000FF, predBlock BB01 out -> 0000000000000000
AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB02 out -> 0000000000000006
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000
AssertionPropCallback::Changed : BB03 before out -> 00000000000000FF; after out -> 0000000000000000;
jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000000;
AssertionPropCallback::StartMerge: BB03 in -> 0000000000000000
AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB01 out -> 0000000000000000
AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB02 out -> 0000000000000006
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000
AssertionPropCallback::Unchanged : BB03 out -> 0000000000000000; jumpDest out -> 0000000000000000
AssertionPropCallback::StartMerge: BB04 in -> 00000000000000FF
AssertionPropCallback::Merge : BB04 in -> 00000000000000FF, predBlock BB03 out -> 0000000000000000
AssertionPropCallback::EndMerge : BB04 in -> 0000000000000000
AssertionPropCallback::Changed : BB04 before out -> 00000000000000FF; after out -> 0000000000000018;
jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000000;
AssertionPropCallback::StartMerge: BB05 in -> 00000000000000FF
AssertionPropCallback::Merge : BB05 in -> 00000000000000FF, predBlock BB03 out -> 0000000000000000
AssertionPropCallback::Merge : BB05 in -> 0000000000000000, predBlock BB04 out -> 0000000000000018
AssertionPropCallback::EndMerge : BB05 in -> 0000000000000000
AssertionPropCallback::Changed : BB05 before out -> 00000000000000FF; after out -> 0000000000000060;
jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000000;
AssertionPropCallback::StartMerge: BB05 in -> 0000000000000000
AssertionPropCallback::Merge : BB05 in -> 0000000000000000, predBlock BB03 out -> 0000000000000000
AssertionPropCallback::Merge : BB05 in -> 0000000000000000, predBlock BB04 out -> 0000000000000018
AssertionPropCallback::EndMerge : BB05 in -> 0000000000000000
AssertionPropCallback::Unchanged : BB05 out -> 0000000000000060; jumpDest out -> 0000000000000000
BB01 valueIn = 0000000000000000 valueOut = 0000000000000000 => BB03 valueOut= 0000000000000000
BB02 valueIn = 0000000000000000 valueOut = 0000000000000006
BB03 valueIn = 0000000000000000 valueOut = 0000000000000000 => BB05 valueOut= 0000000000000000
BB04 valueIn = 0000000000000000 valueOut = 0000000000000018
BB05 valueIn = 0000000000000000 valueOut = 0000000000000060
Propagating 0000000000000000 assertions for BB01, stmt [000005], tree [000001], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000005], tree [000085], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000005], tree [000142], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000005], tree [000143], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000005], tree [000144], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000005], tree [000145], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000005], tree [000002], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000005], tree [000003], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000034], tree [000030], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000034], tree [000031], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000034], tree [000032], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000034], tree [000033], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000040], tree [000035], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000040], tree [000086], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000040], tree [000087], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000040], tree [000036], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000040], tree [000088], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt [000040], tree [000091], tree -> 2
Propagating 0000000000000002 assertions for BB02, stmt [000040], tree [000092], tree -> 3
Propagating 0000000000000006 assertions for BB02, stmt [000040], tree [000089], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000040], tree [000096], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000040], tree [000097], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000040], tree [000037], tree -> 2
Non-null prop for index #02 in BB02:
N011 ( 5, 3) [000037] a--XG-------- * IND ushort <l:$203, c:$4c0>
Propagating 0000000000000006 assertions for BB02, stmt [000040], tree [000098], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000040], tree [000099], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000040], tree [000038], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000040], tree [000039], tree -> 0
Re-morphing this stmt:
( 19, 24) [000040] ------------- * STMT void (IL 0x00B...0x012)
N011 ( 5, 3) [000037] a---GO------- | /--* IND ushort <l:$203, c:$4c0>
N009 ( 1, 1) [000096] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N010 ( 3, 3) [000097] -------N----- | | \--* ADD byref $440
N008 ( 1, 1) [000089] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
N012 ( 13, 14) [000098] ---XG-------- | /--* COMMA ushort <l:$204, c:$500>
N007 ( 8, 11) [000092] ---X--------- | | \--* ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N004 ( 1, 1) [000036] ------------- | | +--* CNS_INT int 0 $40
N006 ( 3, 3) [000091] ---X--------- | | \--* ARR_LENGTH int <l:$3c1, c:$3c0>
N005 ( 1, 1) [000088] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
N013 ( 19, 24) [000099] -A-XG-------- | /--* COMMA ushort <l:$204, c:$500>
N001 ( 6, 10) [000035] ----G-------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8] <l:$340, c:$380>
N003 ( 6, 10) [000087] -A--G---R---- | | \--* ASG ref <l:$340, c:$380>
N002 ( 1, 1) [000086] D------N----- | | \--* LCL_VAR ref V13 tmp5 d:3 <l:$340, c:$380>
N015 ( 19, 24) [000039] -A-XG---R---- \--* ASG ushort <l:$204, c:$500>
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2 d:3 <l:$203, c:$4c0>
New refCnts for V02: refCnt = 5, refCntWtd = 3.50
New refCnts for V13: refCnt = 4, refCntWtd = 4
New refCnts for V13: refCnt = 5, refCntWtd = 5
New refCnts for V13: refCnt = 6, refCntWtd = 6
optAssertionPropMain morphed tree:
N011 ( 5, 3) [000037] a---GO------- /--* IND ushort <l:$203, c:$4c0>
N009 ( 1, 1) [000096] ------------- | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N010 ( 3, 3) [000097] -------N----- | \--* ADD byref $440
N008 ( 1, 1) [000089] ------------- | \--* LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
N012 ( 13, 14) [000098] ---XGO------- /--* COMMA ushort <l:$204, c:$500>
N007 ( 8, 11) [000092] ---X--------- | \--* ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N004 ( 1, 1) [000036] ------------- | +--* CNS_INT int 0 $40
N006 ( 3, 3) [000091] ---X--------- | \--* ARR_LENGTH int <l:$3c1, c:$3c0>
N005 ( 1, 1) [000088] ------------- | \--* LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
N013 ( 19, 24) [000099] -A-XGO------- /--* COMMA ushort <l:$204, c:$500>
N001 ( 6, 10) [000035] ----G-------- | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8] <l:$340, c:$380>
N003 ( 6, 10) [000087] -A--G---R---- | \--* ASG ref <l:$340, c:$380>
N002 ( 1, 1) [000086] D------N----- | \--* LCL_VAR ref V13 tmp5 d:3 <l:$340, c:$380>
N015 ( 19, 24) [000039] -A-XGO--R---- * ASG ushort <l:$204, c:$500>
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2 d:3 <l:$203, c:$4c0>
Propagating 0000000000000006 assertions for BB02, stmt [000050], tree [000045], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000050], tree [000048], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000050], tree [000049], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000100], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000102], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000104], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000055], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000056], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000057], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000052], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000053], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000054], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000105], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000103], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000101], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000058], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000059], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000061], tree [000060], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000064], tree [000106], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000064], tree [000108], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000064], tree [000047], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000064], tree [000051], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000064], tree [000046], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000064], tree [000109], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000064], tree [000107], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000064], tree [000062], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000064], tree [000063], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000070], tree [000065], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000070], tree [000068], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000070], tree [000069], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000110], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000112], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000114], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000075], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000076], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000077], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000072], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000073], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000074], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000115], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000113], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000111], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000078], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000079], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000081], tree [000080], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000084], tree [000116], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000084], tree [000118], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000084], tree [000067], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000084], tree [000071], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000084], tree [000066], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000084], tree [000119], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000084], tree [000117], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000084], tree [000082], tree -> 0
Propagating 0000000000000006 assertions for BB02, stmt [000084], tree [000083], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000011], tree [000146], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000011], tree [000008], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000011], tree [000009], tree -> 0
Propagating 0000000000000000 assertions for BB04, stmt [000028], tree [000024], tree -> 0
Propagating 0000000000000000 assertions for BB04, stmt [000028], tree [000023], tree -> 0
Propagating 0000000000000000 assertions for BB04, stmt [000028], tree [000123], tree -> 4
Propagating 0000000000000008 assertions for BB04, stmt [000028], tree [000124], tree -> 5
Propagating 0000000000000018 assertions for BB04, stmt [000028], tree [000121], tree -> 0
Propagating 0000000000000018 assertions for BB04, stmt [000028], tree [000128], tree -> 0
Propagating 0000000000000018 assertions for BB04, stmt [000028], tree [000129], tree -> 0
Propagating 0000000000000018 assertions for BB04, stmt [000028], tree [000025], tree -> 4
Non-null prop for index #04 in BB04:
N008 ( 5, 3) [000025] a--XG-------- * IND ushort <l:$208, c:$4c2>
Propagating 0000000000000018 assertions for BB04, stmt [000028], tree [000131], tree -> 0
Propagating 0000000000000018 assertions for BB04, stmt [000028], tree [000026], tree -> 0
Propagating 0000000000000018 assertions for BB04, stmt [000028], tree [000027], tree -> 0
Re-morphing this stmt:
( 13, 14) [000028] ------------- * STMT void (IL 0x030...0x033)
N010 ( 0, 0) [000026] ------------- | /--* NOP void $5c0
N011 ( 13, 14) [000027] ---XG-------- \--* COMMA void $55c
N008 ( 5, 3) [000025] a---GO------- | /--* IND ushort <l:$208, c:$4c2>
N006 ( 1, 1) [000128] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000129] -------N----- | | \--* ADD byref $441
N005 ( 1, 1) [000121] ------------- | | \--* LCL_VAR ref V00 arg0 u:2 (last use) $80
N009 ( 13, 14) [000131] ---XG-------- \--* COMMA void <l:$209, c:$501>
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $350
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int $3c2
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0 u:2 $80
New refCnts for V00: refCnt = 5, refCntWtd = 3.50
New refCnts for V00: refCnt = 6, refCntWtd = 4
optAssertionPropMain morphed tree:
N008 ( 5, 3) [000025] a---GO------- /--* IND ushort <l:$208, c:$4c2>
N006 ( 1, 1) [000128] ------------- | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000129] -------N----- | \--* ADD byref $441
N005 ( 1, 1) [000121] ------------- | \--* LCL_VAR ref V00 arg0 u:2 (last use) $80
N009 ( 13, 14) [000131] ---XGO------- * COMMA void <l:$209, c:$501>
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $350
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int $3c2
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0 u:2 $80
Propagating 0000000000000000 assertions for BB05, stmt [000018], tree [000014], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000018], tree [000013], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000018], tree [000134], tree -> 6
Propagating 0000000000000020 assertions for BB05, stmt [000018], tree [000135], tree -> 7
Propagating 0000000000000060 assertions for BB05, stmt [000018], tree [000132], tree -> 0
Propagating 0000000000000060 assertions for BB05, stmt [000018], tree [000137], tree -> 0
Propagating 0000000000000060 assertions for BB05, stmt [000018], tree [000138], tree -> 0
Propagating 0000000000000060 assertions for BB05, stmt [000018], tree [000016], tree -> 6
Non-null prop for index #06 in BB05:
N008 ( 7, 4) [000016] a--XG--N----- * IND byte $20a
Propagating 0000000000000060 assertions for BB05, stmt [000018], tree [000139], tree -> 0
Propagating 0000000000000060 assertions for BB05, stmt [000018], tree [000015], tree -> 0
Propagating 0000000000000060 assertions for BB05, stmt [000018], tree [000017], tree -> 0
Re-morphing this stmt:
( 20, 19) [000018] ------------- * STMT void (IL 0x034...0x038)
N010 ( 2, 2) [000015] ------------- | /--* LCL_VAR int V03 arg3 u:2 (last use) $100
N011 ( 20, 19) [000017] -A-XG-------- \--* ASG byte $VN.Void
N008 ( 7, 4) [000016] a---GO-N----- | /--* IND byte $20a
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 5, 4) [000138] -------N----- | | \--* ADD byref $442
N005 ( 3, 2) [000132] ------------- | | \--* LCL_VAR ref V05 arg5 u:2 (last use) $81
N009 ( 17, 16) [000139] ---XG--N----- \--* COMMA byte $VN.Void
N004 ( 10, 12) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $356
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0 $40
N003 ( 5, 4) [000134] ---X--------- \--* ARR_LENGTH int $3c3
N002 ( 3, 2) [000013] ------------- \--* LCL_VAR ref V05 arg5 u:2 $81
New refCnts for V05: refCnt = 3, refCntWtd = 3
New refCnts for V05: refCnt = 4, refCntWtd = 4
New refCnts for V03: refCnt = 4, refCntWtd = 4
optAssertionPropMain morphed tree:
N010 ( 2, 2) [000015] ------------- /--* LCL_VAR int V03 arg3 u:2 (last use) $100
N011 ( 16, 17) [000017] -A-XGO------- * ASG byte $VN.Void
N008 ( 5, 3) [000016] a---GO-N----- | /--* IND byte $20a
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000138] -------N----- | | \--* ADD byref $442
N005 ( 1, 1) [000132] ------------- | | \--* LCL_VAR ref V05 arg5 u:2 (last use) $81
N009 ( 13, 14) [000139] ---XGO-N----- \--* COMMA byte $VN.Void
N004 ( 8, 11) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $356
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000134] ---X--------- \--* ARR_LENGTH int $3c3
N002 ( 1, 1) [000013] ------------- \--* LCL_VAR ref V05 arg5 u:2 $81
Propagating 0000000000000060 assertions for BB05, stmt [000021], tree [000019], tree -> 0
Propagating 0000000000000060 assertions for BB05, stmt [000021], tree [000141], tree -> 0
Propagating 0000000000000060 assertions for BB05, stmt [000021], tree [000020], tree -> 0
*************** In fgDebugCheckBBlist
*************** In OptimizeRangeChecks()
Blocks/trees before phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 8, 8) [000005] ------------- * STMT void (IL 0x000...0x002)
N009 ( 8, 8) [000004] -A----------- \--* JTRUE void
N007 ( 1, 1) [000002] ------------- | /--* CNS_INT int 0 $40
N008 ( 6, 6) [000003] JA-----N--S-- \--* EQ int $201
N005 ( 1, 1) [000144] ------------- | /--* LCL_VAR int V14 cse0 $200
N006 ( 4, 4) [000145] -A--------S-- \--* COMMA int $200
N002 ( 3, 3) [000085] ----------S-- | /--* CAST int <- bool <- int $200
N001 ( 2, 2) [000001] ------------- | | \--* LCL_VAR int V04 arg4 u:2 $140
N004 ( 3, 3) [000143] -A------R---- \--* ASG int $VN.Void
N003 ( 1, 1) [000142] D------N----- \--* LCL_VAR int V14 cse0 $200
------------ BB02 [004..02C), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 14, 17) [000034] ------------- * STMT void (IL 0x004...0x00A)
N002 ( 7, 11) [000031] ----G-------- | /--* CAST long <- int <l:$2c1, c:$2c0>
N001 ( 6, 10) [000030] ----G-------- | | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3] <l:$202, c:$280>
N004 ( 14, 17) [000033] -A--G---R---- \--* ASG long <l:$2c1, c:$2c0>
N003 ( 3, 2) [000032] D------N----- \--* LCL_VAR long V06 loc0 d:3 <l:$2c1, c:$2c0>
***** BB02, stmt 3
( 19, 24) [000040] ------------- * STMT void (IL 0x00B...0x012)
N011 ( 5, 3) [000037] a---GO------- | /--* IND ushort <l:$203, c:$4c0>
N009 ( 1, 1) [000096] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N010 ( 3, 3) [000097] -------N----- | | \--* ADD byref $440
N008 ( 1, 1) [000089] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
N012 ( 13, 14) [000098] ---XGO------- | /--* COMMA ushort <l:$204, c:$500>
N007 ( 8, 11) [000092] ---X--------- | | \--* ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N004 ( 1, 1) [000036] ------------- | | +--* CNS_INT int 0 $40
N006 ( 3, 3) [000091] ---X--------- | | \--* ARR_LENGTH int <l:$3c1, c:$3c0>
N005 ( 1, 1) [000088] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
N013 ( 19, 24) [000099] -A-XGO------- | /--* COMMA ushort <l:$204, c:$500>
N001 ( 6, 10) [000035] ----G-------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8] <l:$340, c:$380>
N003 ( 6, 10) [000087] -A--G---R---- | | \--* ASG ref <l:$340, c:$380>
N002 ( 1, 1) [000086] D------N----- | | \--* LCL_VAR ref V13 tmp5 d:3 <l:$340, c:$380>
N015 ( 19, 24) [000039] -A-XGO--R---- \--* ASG ushort <l:$204, c:$500>
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2 d:3 <l:$203, c:$4c0>
***** BB02, stmt 4
( 6, 10) [000050] ------------- * STMT void (IL 0x016...0x027)
N001 ( 6, 10) [000045] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$349, c:$382>
N003 ( 6, 10) [000049] -A--G---R---- \--* ASG ref <l:$349, c:$382>
N002 ( 1, 1) [000048] D------N----- \--* LCL_VAR ref V09 tmp1 d:3 <l:$349, c:$382>
***** BB02, stmt 5
( 27, 31) [000061] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000058] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
N007 ( 1, 1) [000052] ------------- arg0 in r0 | | +--* LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
N008 ( 3, 7) [000053] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000054] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B10 token $245
N015 ( 27, 31) [000060] -ACXG---R---- \--* ASG int $205
N014 ( 3, 2) [000059] D------N----- \--* LCL_VAR int V10 tmp2 d:3 $283
***** BB02, stmt 6
( 24, 10) [000064] ------------- * STMT void (IL ???... ???)
N009 ( 24, 10) [000063] --CXG-------- \--* CALL ind void $VN.Void
N008 ( 3, 2) [000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2 u:3 (last use) $283
N004 ( 1, 1) [000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
N005 ( 3, 2) [000046] ------------- arg1 r2,r3 \--* LCL_VAR long V06 loc0 u:3 (last use) <l:$2c1, c:$2c0>
***** BB02, stmt 7
( 6, 10) [000070] ------------- * STMT void (IL 0x021... ???)
N001 ( 6, 10) [000065] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$34b, c:$388>
N003 ( 6, 10) [000069] -A--G---R---- \--* ASG ref <l:$34b, c:$388>
N002 ( 1, 1) [000068] D------N----- \--* LCL_VAR ref V11 tmp3 d:3 <l:$34b, c:$388>
***** BB02, stmt 8
( 27, 31) [000081] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000078] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
N007 ( 1, 1) [000072] ------------- arg0 in r0 | | +--* LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
N008 ( 3, 7) [000073] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000074] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B74 token $246
N015 ( 27, 31) [000080] -ACXG---R---- \--* ASG int $206
N014 ( 3, 2) [000079] D------N----- \--* LCL_VAR int V12 tmp4 d:3 $287
***** BB02, stmt 9
( 23, 10) [000084] ------------- * STMT void (IL ???... ???)
N009 ( 23, 10) [000083] --CXG-------- \--* CALL ind void $VN.Void
N008 ( 3, 2) [000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4 u:3 (last use) $287
N004 ( 1, 1) [000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
N005 ( 2, 2) [000066] ------------- arg1 in r1 \--* LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 5, 5) [000011] ------------- * STMT void (IL 0x02C...0x02E)
N004 ( 5, 5) [000010] ------------- \--* JTRUE void
N002 ( 1, 1) [000008] ------------- | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000009] J------N--S-- \--* NE int $207
N001 ( 1, 1) [000146] ------------- \--* LCL_VAR int V14 cse0 $200
------------ BB04 [030..034), preds={BB03} succs={BB05}
***** BB04, stmt 11
( 13, 14) [000028] ------------- * STMT void (IL 0x030...0x033)
N008 ( 5, 3) [000025] a---GO------- | /--* IND ushort <l:$208, c:$4c2>
N006 ( 1, 1) [000128] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000129] -------N----- | | \--* ADD byref $441
N005 ( 1, 1) [000121] ------------- | | \--* LCL_VAR ref V00 arg0 u:2 (last use) $80
N009 ( 13, 14) [000131] ---XGO------- \--* COMMA void <l:$209, c:$501>
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $350
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int $3c2
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0 u:2 $80
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 12
( 16, 17) [000018] ------------- * STMT void (IL 0x034...0x038)
N010 ( 2, 2) [000015] ------------- | /--* LCL_VAR int V03 arg3 u:2 (last use) $100
N011 ( 16, 17) [000017] -A-XGO------- \--* ASG byte $VN.Void
N008 ( 5, 3) [000016] a---GO-N----- | /--* IND byte $20a
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000138] -------N----- | | \--* ADD byref $442
N005 ( 1, 1) [000132] ------------- | | \--* LCL_VAR ref V05 arg5 u:2 (last use) $81
N009 ( 13, 14) [000139] ---XGO-N----- \--* COMMA byte $VN.Void
N004 ( 8, 11) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $356
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000134] ---X--------- \--* ARR_LENGTH int $3c3
N002 ( 1, 1) [000013] ------------- \--* LCL_VAR ref V05 arg5 u:2 $81
***** BB05, stmt 13
( 4, 4) [000021] ------------- * STMT void (IL 0x039...0x03A)
N003 ( 4, 4) [000020] ------------- \--* RETURN int $28a
N002 ( 3, 3) [000141] ------------- \--* CAST int <- ushort <- int $20c
N001 ( 2, 2) [000019] ------------- \--* LCL_VAR int V01 arg1 u:2 (last use) $c0
-------------------------------------------------------------------------------------------------------------------
ArrSize for lengthVN:3C0 = 0
[RangeCheck::GetRange] BB02N004 ( 1, 1) [000036] ------------- * CNS_INT int 0 $40
{
Computed Range [000036] => <0, 0>
}
Does overflow [000036]?
Range value <0, 0>
[RangeCheck::Widen] BB02,
[000036]
<0, 0> BetweenBounds <0, [000091]>
VN03C0 upper bound is: {ARR_LENGTH($380)}
Array size is: 0
ArrSize for lengthVN:3C2 = 0
[RangeCheck::GetRange] BB04N001 ( 1, 1) [000024] ------------- * CNS_INT int 0 $40
{
Computed Range [000024] => <0, 0>
}
Does overflow [000024]?
Range value <0, 0>
[RangeCheck::Widen] BB04,
[000024]
<0, 0> BetweenBounds <0, [000123]>
VN03C2 upper bound is: {ARR_LENGTH($80)}
Array size is: 0
ArrSize for lengthVN:3C3 = 0
[RangeCheck::GetRange] BB05N001 ( 1, 1) [000014] ------------- * CNS_INT int 0 $40
{
Computed Range [000014] => <0, 0>
}
Does overflow [000014]?
Range value <0, 0>
[RangeCheck::Widen] BB05,
[000014]
<0, 0> BetweenBounds <0, [000134]>
VN03C3 upper bound is: {ARR_LENGTH($81)}
Array size is: 0
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 8, 8) [000005] ------------- * STMT void (IL 0x000...0x002)
N009 ( 8, 8) [000004] -A----------- \--* JTRUE void
N007 ( 1, 1) [000002] ------------- | /--* CNS_INT int 0 $40
N008 ( 6, 6) [000003] JA-----N--S-- \--* EQ int $201
N005 ( 1, 1) [000144] ------------- | /--* LCL_VAR int V14 cse0 $200
N006 ( 4, 4) [000145] -A--------S-- \--* COMMA int $200
N002 ( 3, 3) [000085] ----------S-- | /--* CAST int <- bool <- int $200
N001 ( 2, 2) [000001] ------------- | | \--* LCL_VAR int V04 arg4 u:2 $140
N004 ( 3, 3) [000143] -A------R---- \--* ASG int $VN.Void
N003 ( 1, 1) [000142] D------N----- \--* LCL_VAR int V14 cse0 $200
------------ BB02 [004..02C), preds={BB01} succs={BB03}
***** BB02, stmt 2
( 14, 17) [000034] ------------- * STMT void (IL 0x004...0x00A)
N002 ( 7, 11) [000031] ----G-------- | /--* CAST long <- int <l:$2c1, c:$2c0>
N001 ( 6, 10) [000030] ----G-------- | | \--* CLS_VAR int Hnd=0x9247f8 Fseq[s_3] <l:$202, c:$280>
N004 ( 14, 17) [000033] -A--G---R---- \--* ASG long <l:$2c1, c:$2c0>
N003 ( 3, 2) [000032] D------N----- \--* LCL_VAR long V06 loc0 d:3 <l:$2c1, c:$2c0>
***** BB02, stmt 3
( 19, 24) [000040] ------------- * STMT void (IL 0x00B...0x012)
N011 ( 5, 3) [000037] a---GO------- | /--* IND ushort <l:$203, c:$4c0>
N009 ( 1, 1) [000096] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N010 ( 3, 3) [000097] -------N----- | | \--* ADD byref $440
N008 ( 1, 1) [000089] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
N012 ( 13, 14) [000098] ---XGO------- | /--* COMMA ushort <l:$204, c:$500>
N007 ( 8, 11) [000092] ---X--------- | | \--* ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N004 ( 1, 1) [000036] ------------- | | +--* CNS_INT int 0 $40
N006 ( 3, 3) [000091] ---X--------- | | \--* ARR_LENGTH int <l:$3c1, c:$3c0>
N005 ( 1, 1) [000088] ------------- | | \--* LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
N013 ( 19, 24) [000099] -A-XGO------- | /--* COMMA ushort <l:$204, c:$500>
N001 ( 6, 10) [000035] ----G-------- | | | /--* CLS_VAR ref Hnd=0x924808 Fseq[s_8] <l:$340, c:$380>
N003 ( 6, 10) [000087] -A--G---R---- | | \--* ASG ref <l:$340, c:$380>
N002 ( 1, 1) [000086] D------N----- | | \--* LCL_VAR ref V13 tmp5 d:3 <l:$340, c:$380>
N015 ( 19, 24) [000039] -A-XGO--R---- \--* ASG ushort <l:$204, c:$500>
N014 ( 2, 2) [000038] D------N----- \--* LCL_VAR ushort V02 arg2 d:3 <l:$203, c:$4c0>
***** BB02, stmt 4
( 6, 10) [000050] ------------- * STMT void (IL 0x016...0x027)
N001 ( 6, 10) [000045] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$349, c:$382>
N003 ( 6, 10) [000049] -A--G---R---- \--* ASG ref <l:$349, c:$382>
N002 ( 1, 1) [000048] D------N----- \--* LCL_VAR ref V09 tmp1 d:3 <l:$349, c:$382>
***** BB02, stmt 5
( 27, 31) [000061] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000058] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
N007 ( 1, 1) [000052] ------------- arg0 in r0 | | +--* LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
N008 ( 3, 7) [000053] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000054] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B10 token $245
N015 ( 27, 31) [000060] -ACXG---R---- \--* ASG int $205
N014 ( 3, 2) [000059] D------N----- \--* LCL_VAR int V10 tmp2 d:3 $283
***** BB02, stmt 6
( 24, 10) [000064] ------------- * STMT void (IL ???... ???)
N009 ( 24, 10) [000063] --CXG-------- \--* CALL ind void $VN.Void
N008 ( 3, 2) [000062] ------------- calli tgt \--* LCL_VAR int V10 tmp2 u:3 (last use) $283
N004 ( 1, 1) [000051] ------------- this in r0 +--* LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
N005 ( 3, 2) [000046] ------------- arg1 r2,r3 \--* LCL_VAR long V06 loc0 u:3 (last use) <l:$2c1, c:$2c0>
***** BB02, stmt 7
( 6, 10) [000070] ------------- * STMT void (IL 0x021... ???)
N001 ( 6, 10) [000065] ----G-------- | /--* CLS_VAR ref Hnd=0x9247d8 Fseq[s_rt] <l:$34b, c:$388>
N003 ( 6, 10) [000069] -A--G---R---- \--* ASG ref <l:$34b, c:$388>
N002 ( 1, 1) [000068] D------N----- \--* LCL_VAR ref V11 tmp3 d:3 <l:$34b, c:$388>
***** BB02, stmt 8
( 27, 31) [000081] ------------- * STMT void (IL ???... ???)
N013 ( 23, 28) [000078] --CXG-------- | /--* CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
N007 ( 1, 1) [000072] ------------- arg0 in r0 | | +--* LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
N008 ( 3, 7) [000073] ------------- arg1 in r1 | | +--* CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000074] ------------- arg2 in r2 | | \--* CNS_INT(h) int 0x924B74 token $246
N015 ( 27, 31) [000080] -ACXG---R---- \--* ASG int $206
N014 ( 3, 2) [000079] D------N----- \--* LCL_VAR int V12 tmp4 d:3 $287
***** BB02, stmt 9
( 23, 10) [000084] ------------- * STMT void (IL ???... ???)
N009 ( 23, 10) [000083] --CXG-------- \--* CALL ind void $VN.Void
N008 ( 3, 2) [000082] ------------- calli tgt \--* LCL_VAR int V12 tmp4 u:3 (last use) $287
N004 ( 1, 1) [000071] ------------- this in r0 +--* LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
N005 ( 2, 2) [000066] ------------- arg1 in r1 \--* LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 10
( 5, 5) [000011] ------------- * STMT void (IL 0x02C...0x02E)
N004 ( 5, 5) [000010] ------------- \--* JTRUE void
N002 ( 1, 1) [000008] ------------- | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000009] J------N--S-- \--* NE int $207
N001 ( 1, 1) [000146] ------------- \--* LCL_VAR int V14 cse0 $200
------------ BB04 [030..034), preds={BB03} succs={BB05}
***** BB04, stmt 11
( 13, 14) [000028] ------------- * STMT void (IL 0x030...0x033)
N008 ( 5, 3) [000025] a---GO------- | /--* IND ushort <l:$208, c:$4c2>
N006 ( 1, 1) [000128] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000129] -------N----- | | \--* ADD byref $441
N005 ( 1, 1) [000121] ------------- | | \--* LCL_VAR ref V00 arg0 u:2 (last use) $80
N009 ( 13, 14) [000131] ---XGO------- \--* COMMA void <l:$209, c:$501>
N004 ( 8, 11) [000124] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $350
N001 ( 1, 1) [000024] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000123] ---X--------- \--* ARR_LENGTH int $3c2
N002 ( 1, 1) [000023] ------------- \--* LCL_VAR ref V00 arg0 u:2 $80
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
***** BB05, stmt 12
( 16, 17) [000018] ------------- * STMT void (IL 0x034...0x038)
N010 ( 2, 2) [000015] ------------- | /--* LCL_VAR int V03 arg3 u:2 (last use) $100
N011 ( 16, 17) [000017] -A-XGO------- \--* ASG byte $VN.Void
N008 ( 5, 3) [000016] a---GO-N----- | /--* IND byte $20a
N006 ( 1, 1) [000137] ------------- | | | /--* CNS_INT int 8 Fseq[#FirstElem] $48
N007 ( 3, 3) [000138] -------N----- | | \--* ADD byref $442
N005 ( 1, 1) [000132] ------------- | | \--* LCL_VAR ref V05 arg5 u:2 (last use) $81
N009 ( 13, 14) [000139] ---XGO-N----- \--* COMMA byte $VN.Void
N004 ( 8, 11) [000135] ---X--------- \--* ARR_BOUNDS_CHECK_Rng void $356
N001 ( 1, 1) [000014] ------------- +--* CNS_INT int 0 $40
N003 ( 3, 3) [000134] ---X--------- \--* ARR_LENGTH int $3c3
N002 ( 1, 1) [000013] ------------- \--* LCL_VAR ref V05 arg5 u:2 $81
***** BB05, stmt 13
( 4, 4) [000021] ------------- * STMT void (IL 0x039...0x03A)
N003 ( 4, 4) [000020] ------------- \--* RETURN int $28a
N002 ( 3, 3) [000141] ------------- \--* CAST int <- ushort <- int $20c
N001 ( 2, 2) [000019] ------------- \--* LCL_VAR int V01 arg1 u:2 (last use) $c0
-------------------------------------------------------------------------------------------------------------------
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR long V06 loc0 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N015 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N015 ( 27, 31) [000060] DACXG-------- * STORE_LCL_VAR int V10 tmp2 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N015 ( 27, 31) [000080] DACXG-------- * STORE_LCL_VAR int V12 tmp4 d:3
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
( 8, 8) [000005] ------------- IL_OFFSET void IL offset: 0x0
N001 ( 2, 2) [000001] ------------- t1 = LCL_VAR int V04 arg4 u:2 $140
/--* t1 int
N002 ( 3, 3) [000085] ----------S-- t85 = * CAST int <- bool <- int $200
/--* t85 int
N004 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0
N005 ( 1, 1) [000144] ------------- t144 = LCL_VAR int V14 cse0 $200
N007 ( 1, 1) [000002] ------------- t2 = CNS_INT int 0 $40
/--* t144 int
+--* t2 int
N008 ( 6, 6) [000003] J------N--S-- t3 = * EQ int $201
/--* t3 int
N009 ( 8, 8) [000004] ------------- * JTRUE void
------------ BB02 [004..02C), preds={BB01} succs={BB03}
( 14, 17) [000034] ------------- IL_OFFSET void IL offset: 0x4
N001 ( 6, 10) [000030] ----G-------- t30 = CLS_VAR_ADDR byref Hnd=0x9247f8
/--* t30 byref
[000148] ----G-------- t148 = * IND int
/--* t148 int
N002 ( 7, 11) [000031] ----G-------- t31 = * CAST long <- int <l:$2c1, c:$2c0>
/--* t31 long
N004 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR long V06 loc0 d:3
( 19, 24) [000040] ------------- IL_OFFSET void IL offset: 0xb
N001 ( 6, 10) [000035] ----G-------- t35 = CLS_VAR_ADDR byref Hnd=0x924808
/--* t35 byref
[000149] ----G-------- t149 = * IND ref
/--* t149 ref
N003 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3
N004 ( 1, 1) [000036] ------------- t36 = CNS_INT int 0 $40
N005 ( 1, 1) [000088] ------------- t88 = LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
/--* t88 ref
N006 ( 3, 3) [000091] ---X--------- t91 = * ARR_LENGTH int <l:$3c1, c:$3c0>
/--* t36 int
+--* t91 int
N007 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N008 ( 1, 1) [000089] ------------- t89 = LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
N009 ( 1, 1) [000096] ------------- t96 = CNS_INT int 8 Fseq[#FirstElem] $48
/--* t89 ref
+--* t96 int
N010 ( 3, 3) [000097] -------N----- t97 = * ADD byref $440
/--* t97 byref
N011 ( 5, 3) [000037] a---GO------- t37 = * IND ushort <l:$203, c:$4c0>
/--* t37 ushort
N015 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3
( 6, 10) [000050] ------------- IL_OFFSET void IL offset: 0x16
N001 ( 6, 10) [000045] ----G-------- t45 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t45 byref
[000150] ----G-------- t150 = * IND ref
/--* t150 ref
N003 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3
N007 ( 1, 1) [000052] ------------- t52 = LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
N008 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token $245
/--* t52 ref arg0 in r0
+--* t53 int arg1 in r1
+--* t54 int arg2 in r2
N013 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
/--* t58 int
N015 ( 27, 31) [000060] DA-XG-------- * STORE_LCL_VAR int V10 tmp2 d:3
N004 ( 1, 1) [000051] ------------- t51 = LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR long V06 loc0 u:3 (last use) <l:$2c1, c:$2c0>
N008 ( 3, 2) [000062] ------------- t62 = LCL_VAR int V10 tmp2 u:3 (last use) $283
/--* t51 ref this in r0
+--* t46 long arg1 r2,r3
+--* t62 int calli tgt
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
( 6, 10) [000070] ------------- IL_OFFSET void IL offset: 0x21
N001 ( 6, 10) [000065] ----G-------- t65 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t65 byref
[000151] ----G-------- t151 = * IND ref
/--* t151 ref
N003 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3
N007 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
N008 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token $246
/--* t72 ref arg0 in r0
+--* t73 int arg1 in r1
+--* t74 int arg2 in r2
N013 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
/--* t78 int
N015 ( 27, 31) [000080] DA-XG-------- * STORE_LCL_VAR int V12 tmp4 d:3
N004 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
N005 ( 2, 2) [000066] ------------- t66 = LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
N008 ( 3, 2) [000082] ------------- t82 = LCL_VAR int V12 tmp4 u:3 (last use) $287
/--* t71 ref this in r0
+--* t66 int arg1 in r1
+--* t82 int calli tgt
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
( 5, 5) [000011] ------------- IL_OFFSET void IL offset: 0x2c
N001 ( 1, 1) [000146] ------------- t146 = LCL_VAR int V14 cse0 $200
N002 ( 1, 1) [000008] ------------- t8 = CNS_INT int 0 $40
/--* t146 int
+--* t8 int
N003 ( 3, 3) [000009] J------N--S-- t9 = * NE int $207
/--* t9 int
N004 ( 5, 5) [000010] ------------- * JTRUE void
------------ BB04 [030..034), preds={BB03} succs={BB05}
( 13, 14) [000028] ------------- IL_OFFSET void IL offset: 0x30
N001 ( 1, 1) [000024] ------------- t24 = CNS_INT int 0 $40
N002 ( 1, 1) [000023] ------------- t23 = LCL_VAR ref V00 arg0 u:2 $80
/--* t23 ref
N003 ( 3, 3) [000123] ---X--------- t123 = * ARR_LENGTH int $3c2
/--* t24 int
+--* t123 int
N004 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
N005 ( 1, 1) [000121] ------------- t121 = LCL_VAR ref V00 arg0 u:2 (last use) $80
N006 ( 1, 1) [000128] ------------- t128 = CNS_INT int 8 Fseq[#FirstElem] $48
/--* t121 ref
+--* t128 int
N007 ( 3, 3) [000129] -------N----- t129 = * ADD byref $441
/--* t129 byref
N008 ( 5, 3) [000025] a---GO------- t25 = * IND ushort <l:$208, c:$4c2>
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
( 16, 17) [000018] ------------- IL_OFFSET void IL offset: 0x34
N001 ( 1, 1) [000014] ------------- t14 = CNS_INT int 0 $40
N002 ( 1, 1) [000013] ------------- t13 = LCL_VAR ref V05 arg5 u:2 $81
/--* t13 ref
N003 ( 3, 3) [000134] ---X--------- t134 = * ARR_LENGTH int $3c3
/--* t14 int
+--* t134 int
N004 ( 8, 11) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
N005 ( 1, 1) [000132] ------------- t132 = LCL_VAR ref V05 arg5 u:2 (last use) $81
N006 ( 1, 1) [000137] ------------- t137 = CNS_INT int 8 Fseq[#FirstElem] $48
/--* t132 ref
+--* t137 int
N007 ( 3, 3) [000138] -------N----- t138 = * ADD byref $442
N010 ( 2, 2) [000015] ------------- t15 = LCL_VAR int V03 arg3 u:2 (last use) $100
/--* t138 byref
+--* t15 int
[000152] -A-XGO------- * STOREIND byte
( 4, 4) [000021] ------------- IL_OFFSET void IL offset: 0x39
N001 ( 2, 2) [000019] ------------- t19 = LCL_VAR int V01 arg1 u:2 (last use) $c0
/--* t19 int
N002 ( 3, 3) [000141] ------------- t141 = * CAST int <- ushort <- int $20c
/--* t141 int
N003 ( 4, 4) [000020] ------------- * RETURN int $28a
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*** Computing fgRngChkTarget for block BB02 to stkDepth 0
fgNewBBinRegion(jumpKind=3, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=true, insertAtEnd=true): inserting after BB05
New Basic Block BB06 [0005] created.
fgAddCodeRef - Add BB in non-EH region for RNGCHK_FAIL, new block BB06 [0005], stkDepth is 0
argSlots=0, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0
outgoingArgSpaceSize 0 sufficient for call [000058], which needs 0
outgoingArgSpaceSize 0 sufficient for call [000063], which needs 0
outgoingArgSpaceSize 0 sufficient for call [000078], which needs 0
outgoingArgSpaceSize 0 sufficient for call [000083], which needs 0
*** Computing fgRngChkTarget for block BB04 to stkDepth 0
*** Computing fgRngChkTarget for block BB05 to stkDepth 0
outgoingArgSpaceSize 0 sufficient for call [000155], which needs 0
After fgSimpleLowering() added some RngChk throw blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
BB06 [0005] 0 0 [???..???) (throw ) keep i internal rare label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
BB06 [0005] 0 0 [???..???) (throw ) keep i internal rare label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
( 8, 8) [000005] ------------- IL_OFFSET void IL offset: 0x0
N001 ( 2, 2) [000001] ------------- t1 = LCL_VAR int V04 arg4 u:2 $140
/--* t1 int
N002 ( 3, 3) [000085] ----------S-- t85 = * CAST int <- bool <- int $200
/--* t85 int
N004 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0
N005 ( 1, 1) [000144] ------------- t144 = LCL_VAR int V14 cse0 $200
N007 ( 1, 1) [000002] ------------- t2 = CNS_INT int 0 $40
/--* t144 int
+--* t2 int
N008 ( 6, 6) [000003] J------N--S-- t3 = * EQ int $201
/--* t3 int
N009 ( 8, 8) [000004] ------------- * JTRUE void
------------ BB02 [004..02C), preds={BB01} succs={BB03}
( 14, 17) [000034] ------------- IL_OFFSET void IL offset: 0x4
N001 ( 6, 10) [000030] ----G-------- t30 = CLS_VAR_ADDR byref Hnd=0x9247f8
/--* t30 byref
[000148] ----G-------- t148 = * IND int
/--* t148 int
N002 ( 7, 11) [000031] ----G-------- t31 = * CAST long <- int <l:$2c1, c:$2c0>
/--* t31 long
N004 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR long V06 loc0 d:3
( 19, 24) [000040] ------------- IL_OFFSET void IL offset: 0xb
N001 ( 6, 10) [000035] ----G-------- t35 = CLS_VAR_ADDR byref Hnd=0x924808
/--* t35 byref
[000149] ----G-------- t149 = * IND ref
/--* t149 ref
N003 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3
N004 ( 1, 1) [000036] ------------- t36 = CNS_INT int 0 $40
N005 ( 1, 1) [000088] ------------- t88 = LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
[000153] ------------- t153 = CNS_INT int 4
/--* t88 ref
+--* t153 int
[000154] ------------- t154 = * ADD ref
/--* t154 ref
N006 ( 3, 3) [000091] ---X--------- t91 = * IND int <l:$3c1, c:$3c0>
/--* t36 int
+--* t91 int
N007 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N008 ( 1, 1) [000089] ------------- t89 = LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
N009 ( 1, 1) [000096] ------------- t96 = CNS_INT int 8 Fseq[#FirstElem] $48
/--* t89 ref
+--* t96 int
N010 ( 3, 3) [000097] -------N----- t97 = * ADD byref $440
/--* t97 byref
N011 ( 5, 3) [000037] a---GO------- t37 = * IND ushort <l:$203, c:$4c0>
/--* t37 ushort
N015 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3
( 6, 10) [000050] ------------- IL_OFFSET void IL offset: 0x16
N001 ( 6, 10) [000045] ----G-------- t45 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t45 byref
[000150] ----G-------- t150 = * IND ref
/--* t150 ref
N003 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3
N007 ( 1, 1) [000052] ------------- t52 = LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
N008 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token $245
/--* t52 ref arg0 in r0
+--* t53 int arg1 in r1
+--* t54 int arg2 in r2
N013 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
/--* t58 int
N015 ( 27, 31) [000060] DA-XG-------- * STORE_LCL_VAR int V10 tmp2 d:3
N004 ( 1, 1) [000051] ------------- t51 = LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR long V06 loc0 u:3 (last use) <l:$2c1, c:$2c0>
N008 ( 3, 2) [000062] ------------- t62 = LCL_VAR int V10 tmp2 u:3 (last use) $283
/--* t51 ref this in r0
+--* t46 long arg1 r2,r3
+--* t62 int calli tgt
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
( 6, 10) [000070] ------------- IL_OFFSET void IL offset: 0x21
N001 ( 6, 10) [000065] ----G-------- t65 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t65 byref
[000151] ----G-------- t151 = * IND ref
/--* t151 ref
N003 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3
N007 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
N008 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token $246
/--* t72 ref arg0 in r0
+--* t73 int arg1 in r1
+--* t74 int arg2 in r2
N013 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
/--* t78 int
N015 ( 27, 31) [000080] DA-XG-------- * STORE_LCL_VAR int V12 tmp4 d:3
N004 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
N005 ( 2, 2) [000066] ------------- t66 = LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
N008 ( 3, 2) [000082] ------------- t82 = LCL_VAR int V12 tmp4 u:3 (last use) $287
/--* t71 ref this in r0
+--* t66 int arg1 in r1
+--* t82 int calli tgt
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
( 5, 5) [000011] ------------- IL_OFFSET void IL offset: 0x2c
N001 ( 1, 1) [000146] ------------- t146 = LCL_VAR int V14 cse0 $200
N002 ( 1, 1) [000008] ------------- t8 = CNS_INT int 0 $40
/--* t146 int
+--* t8 int
N003 ( 3, 3) [000009] J------N--S-- t9 = * NE int $207
/--* t9 int
N004 ( 5, 5) [000010] ------------- * JTRUE void
------------ BB04 [030..034), preds={BB03} succs={BB05}
( 13, 14) [000028] ------------- IL_OFFSET void IL offset: 0x30
N001 ( 1, 1) [000024] ------------- t24 = CNS_INT int 0 $40
N002 ( 1, 1) [000023] ------------- t23 = LCL_VAR ref V00 arg0 u:2 $80
[000157] ------------- t157 = CNS_INT int 4
/--* t23 ref
+--* t157 int
[000158] ------------- t158 = * ADD ref
/--* t158 ref
N003 ( 3, 3) [000123] ---X--------- t123 = * IND int $3c2
/--* t24 int
+--* t123 int
N004 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
N005 ( 1, 1) [000121] ------------- t121 = LCL_VAR ref V00 arg0 u:2 (last use) $80
N006 ( 1, 1) [000128] ------------- t128 = CNS_INT int 8 Fseq[#FirstElem] $48
/--* t121 ref
+--* t128 int
N007 ( 3, 3) [000129] -------N----- t129 = * ADD byref $441
/--* t129 byref
N008 ( 5, 3) [000025] a---GO------- t25 = * IND ushort <l:$208, c:$4c2>
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
( 16, 17) [000018] ------------- IL_OFFSET void IL offset: 0x34
N001 ( 1, 1) [000014] ------------- t14 = CNS_INT int 0 $40
N002 ( 1, 1) [000013] ------------- t13 = LCL_VAR ref V05 arg5 u:2 $81
[000160] ------------- t160 = CNS_INT int 4
/--* t13 ref
+--* t160 int
[000161] ------------- t161 = * ADD ref
/--* t161 ref
N003 ( 3, 3) [000134] ---X--------- t134 = * IND int $3c3
/--* t14 int
+--* t134 int
N004 ( 8, 11) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
N005 ( 1, 1) [000132] ------------- t132 = LCL_VAR ref V05 arg5 u:2 (last use) $81
N006 ( 1, 1) [000137] ------------- t137 = CNS_INT int 8 Fseq[#FirstElem] $48
/--* t132 ref
+--* t137 int
N007 ( 3, 3) [000138] -------N----- t138 = * ADD byref $442
N010 ( 2, 2) [000015] ------------- t15 = LCL_VAR int V03 arg3 u:2 (last use) $100
/--* t138 byref
+--* t15 int
[000152] -A-XGO------- * STOREIND byte
( 4, 4) [000021] ------------- IL_OFFSET void IL offset: 0x39
N001 ( 2, 2) [000019] ------------- t19 = LCL_VAR int V01 arg1 u:2 (last use) $c0
/--* t19 int
N002 ( 3, 3) [000141] ------------- t141 = * CAST int <- ushort <- int $20c
/--* t141 int
N003 ( 4, 4) [000020] ------------- * RETURN int $28a
------------ BB06 [???..???) (throw), preds={} succs={}
N001 ( 16, 10) [000155] --CXG-------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
Promoting long local V06:
lvaGrabTemp returning 15 (V15 rat0) (a long lifetime temp) called for field V06.lo (fldOffset=0x0).
lvaGrabTemp returning 16 (V16 rat1) (a long lifetime temp) called for field V06.hi (fldOffset=0x4).
lvaTable after lvaPromoteLongVars
; Initial local variable assignments
;
; V00 arg0 ref class-hnd
; V01 arg1 ushort
; V02 arg2 ushort
; V03 arg3 ubyte
; V04 arg4 bool
; V05 arg5 ref class-hnd
; V06 loc0 long
; V07 loc1 ushort
; V08 OutArgs lclBlk ( 0)
; V09 tmp1 ref
; V10 tmp2 int
; V11 tmp3 ref
; V12 tmp4 int
; V13 tmp5 ref
; V14 cse0 int
; V15 rat0 int V06.lo(offs=0x00)
; V16 rat1 int V06.hi(offs=0x04)
LowerCast for: N002 ( 3, 3) [000085] ----------S-- * CAST int <- bool <- int $200
Decomposing TYP_LONG tree. BEFORE:
N001 ( 6, 10) [000030] ----G-------- t30 = CLS_VAR_ADDR byref Hnd=0x9247f8
/--* t30 byref
[000148] ----G-------- t148 = * IND int
/--* t148 int
N002 ( 7, 11) [000031] ----G-------- t31 = * CAST long <- int <l:$2c1, c:$2c0>
lvaGrabTemp returning 17 (V17 rat2) called for ReplaceWithLclVar is creating a new local variable.
New refCnts for V17: refCnt = 1, refCntWtd = 1
New refCnts for V17: refCnt = 2, refCntWtd = 2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
[000164] DA--G-------- * STORE_LCL_VAR int V17 rat2
ReplaceWithLclVar created store :
[000164] DA--G-------- * STORE_LCL_VAR int V17 rat2
New refCnts for V17: refCnt = 3, refCntWtd = 3
Decomposing TYP_LONG tree. AFTER:
[000165] ------------- t165 = LCL_VAR int V17 rat2
[000166] ------------- t166 = LCL_VAR int V17 rat2
[000167] ------------- t167 = CNS_INT int 31
/--* t166 int
+--* t167 int
[000168] ------------- t168 = * RSH int
/--* t165 int
+--* t168 int
[000169] ------------- t169 = * LONG long
Decomposing TYP_LONG tree. BEFORE:
[000165] ------------- t165 = LCL_VAR int V17 rat2
[000166] ------------- t166 = LCL_VAR int V17 rat2
[000167] ------------- t167 = CNS_INT int 31
/--* t166 int
+--* t167 int
[000168] ------------- t168 = * RSH int
/--* t165 int
+--* t168 int
[000169] ------------- t169 = * LONG long
/--* t169 long
N004 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR long (P) V06 loc0 d:3
* int V06.hi (offs=0x00) -> V15 rat0
* int V06.hi (offs=0x04) -> V16 rat1
New refCnts for V06: refCnt = 1, refCntWtd = 0.50
New refCnts for V15: refCnt = 1, refCntWtd = 0.50
New refCnts for V16: refCnt = 1, refCntWtd = 0.50
Decomposing TYP_LONG tree. AFTER:
[000165] ------------- t165 = LCL_VAR int V17 rat2
[000166] ------------- t166 = LCL_VAR int V17 rat2
[000167] ------------- t167 = CNS_INT int 31
/--* t166 int
+--* t167 int
[000168] ------------- t168 = * RSH int
/--* t165 int
N004 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR int V15 rat0
Decomposing TYP_LONG tree. BEFORE:
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR long (P) V06 loc0 u:3
* int V06.hi (offs=0x00) -> V15 rat0
* int V06.hi (offs=0x04) -> V16 rat1 <l:$2c1, c:$2c0>
New refCnts for V06: refCnt = 0, refCntWtd = 0
New refCnts for V15: refCnt = 2, refCntWtd = 1
New refCnts for V16: refCnt = 2, refCntWtd = 1
Decomposing TYP_LONG tree. AFTER:
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR int V15 rat0 <l:$2c1, c:$2c0>
[000171] ------------- t171 = LCL_VAR int V16 rat1
/--* t46 int
+--* t171 int
[000172] ------------- t172 = * LONG long
No addressing mode:
N001 ( 6, 10) [000030] ----G-------- * CLS_VAR_ADDR byref Hnd=0x9247f8
No addressing mode:
N001 ( 6, 10) [000035] ----G-------- * CLS_VAR_ADDR byref Hnd=0x924808
Addressing mode:
Base
N005 ( 1, 1) [000088] ------------- * LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
+ 4
New addressing mode node:
[000173] ------------- * LEA(b+4) byref
Addressing mode:
Base
N008 ( 1, 1) [000089] ------------- * LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
+ 8
New addressing mode node:
[000174] ------------- * LEA(b+8) byref
No addressing mode:
N001 ( 6, 10) [000045] ----G-------- * CLS_VAR_ADDR byref Hnd=0x9247d8
lowering call (before):
N007 ( 1, 1) [000052] ------------- t52 = LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
N008 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token $245
/--* t52 ref arg0 in r0
+--* t53 int arg1 in r1
+--* t54 int arg2 in r2
N013 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000100] -----------L- * ARGPLACE ref <l:$349, c:$382>
lowering arg : N002 ( 0, 0) [000102] -----------L- * ARGPLACE int $244
lowering arg : N003 ( 0, 0) [000104] -----------L- * ARGPLACE int $245
late:
======
lowering arg : N007 ( 1, 1) [000052] ------------- * LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
new node is : [000175] ------------- * PUTARG_REG ref REG r0
lowering arg : N008 ( 3, 7) [000053] ------------- * CNS_INT(h) int 0x924994 token $244
new node is : [000176] ------------- * PUTARG_REG int REG r1
lowering arg : N009 ( 3, 7) [000054] ------------- * CNS_INT(h) int 0x924B10 token $245
new node is : [000177] ------------- * PUTARG_REG int REG r2
results of lowering call:
N001 ( 3, 7) [000178] ------------- t178 = CNS_INT(h) int 0xFDA55A0 ftn
lowering call (after):
N007 ( 1, 1) [000052] ------------- t52 = LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
/--* t52 ref
[000175] ------------- t175 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token $244
/--* t53 int
[000176] ------------- t176 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token $245
/--* t54 int
[000177] ------------- t177 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000178] ------------- t178 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t175 ref arg0 in r0
+--* t176 int arg1 in r1
+--* t177 int arg2 in r2
+--* t178 int control expr
N013 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
lowering call (before):
N004 ( 1, 1) [000051] ------------- t51 = LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR int V15 rat0 <l:$2c1, c:$2c0>
[000171] ------------- t171 = LCL_VAR int V16 rat1
/--* t46 int
+--* t171 int
[000172] ------------- t172 = * LONG long
N008 ( 3, 2) [000062] ------------- t62 = LCL_VAR int V10 tmp2 u:3 (last use) $283
/--* t51 ref this in r0
+--* t172 long arg1 r2,r3
+--* t62 int calli tgt
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
objp:
======
lowering arg : N001 ( 0, 0) [000106] -----------L- * ARGPLACE ref $386
args:
======
lowering arg : N002 ( 0, 0) [000108] -----------L- * ARGPLACE long <l:$349, c:$382>
late:
======
lowering arg : N004 ( 1, 1) [000051] ------------- * LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
new node is : [000179] ------------- * PUTARG_REG ref REG r0
lowering arg : [000172] ------------- * LONG long
lowering call (after):
N004 ( 1, 1) [000051] ------------- t51 = LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
/--* t51 ref
[000179] ------------- t179 = * PUTARG_REG ref REG r0
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR int V15 rat0 <l:$2c1, c:$2c0>
/--* t46 int
[000182] ------------- t182 = * PUTARG_REG int REG r2
[000171] ------------- t171 = LCL_VAR int V16 rat1
/--* t171 int
[000183] ------------- t183 = * PUTARG_REG int REG r3
/--* t182 int
+--* t183 int
[000180] Hc----------- t180 = * FIELD_LIST int int at offset 0 REG NA
N008 ( 3, 2) [000062] ------------- t62 = LCL_VAR int V10 tmp2 u:3 (last use) $283
/--* t179 ref this in r0
+--* t180 int arg1 r2,r3
+--* t62 int calli tgt
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
No addressing mode:
N001 ( 6, 10) [000065] ----G-------- * CLS_VAR_ADDR byref Hnd=0x9247d8
lowering call (before):
N007 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
N008 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token $244
N009 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token $246
/--* t72 ref arg0 in r0
+--* t73 int arg1 in r1
+--* t74 int arg2 in r2
N013 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000110] -----------L- * ARGPLACE ref <l:$34b, c:$388>
lowering arg : N002 ( 0, 0) [000112] -----------L- * ARGPLACE int $244
lowering arg : N003 ( 0, 0) [000114] -----------L- * ARGPLACE int $246
late:
======
lowering arg : N007 ( 1, 1) [000072] ------------- * LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
new node is : [000184] ------------- * PUTARG_REG ref REG r0
lowering arg : N008 ( 3, 7) [000073] ------------- * CNS_INT(h) int 0x924994 token $244
new node is : [000185] ------------- * PUTARG_REG int REG r1
lowering arg : N009 ( 3, 7) [000074] ------------- * CNS_INT(h) int 0x924B74 token $246
new node is : [000186] ------------- * PUTARG_REG int REG r2
results of lowering call:
N001 ( 3, 7) [000187] ------------- t187 = CNS_INT(h) int 0xFDA55A0 ftn
lowering call (after):
N007 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
/--* t72 ref
[000184] ------------- t184 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token $244
/--* t73 int
[000185] ------------- t185 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token $246
/--* t74 int
[000186] ------------- t186 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000187] ------------- t187 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t184 ref arg0 in r0
+--* t185 int arg1 in r1
+--* t186 int arg2 in r2
+--* t187 int control expr
N013 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
lowering call (before):
N004 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
N005 ( 2, 2) [000066] ------------- t66 = LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
N008 ( 3, 2) [000082] ------------- t82 = LCL_VAR int V12 tmp4 u:3 (last use) $287
/--* t71 ref this in r0
+--* t66 int arg1 in r1
+--* t82 int calli tgt
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
objp:
======
lowering arg : N001 ( 0, 0) [000116] -----------L- * ARGPLACE ref $38c
args:
======
lowering arg : N002 ( 0, 0) [000118] -----------L- * ARGPLACE int <l:$34b, c:$388>
late:
======
lowering arg : N004 ( 1, 1) [000071] ------------- * LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
new node is : [000188] ------------- * PUTARG_REG ref REG r0
lowering arg : N005 ( 2, 2) [000066] ------------- * LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
new node is : [000189] ------------- * PUTARG_REG int REG r1
lowering call (after):
N004 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
/--* t71 ref
[000188] ------------- t188 = * PUTARG_REG ref REG r0
N005 ( 2, 2) [000066] ------------- t66 = LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
/--* t66 int
[000189] ------------- t189 = * PUTARG_REG int REG r1
N008 ( 3, 2) [000082] ------------- t82 = LCL_VAR int V12 tmp4 u:3 (last use) $287
/--* t188 ref this in r0
+--* t189 int arg1 in r1
+--* t82 int calli tgt
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
Addressing mode:
Base
N002 ( 1, 1) [000023] ------------- * LCL_VAR ref V00 arg0 u:2 $80
+ 4
New addressing mode node:
[000190] ------------- * LEA(b+4) byref
Addressing mode:
Base
N005 ( 1, 1) [000121] ------------- * LCL_VAR ref V00 arg0 u:2 (last use) $80
+ 8
New addressing mode node:
[000191] ------------- * LEA(b+8) byref
Addressing mode:
Base
N002 ( 1, 1) [000013] ------------- * LCL_VAR ref V05 arg5 u:2 $81
+ 4
New addressing mode node:
[000192] ------------- * LEA(b+4) byref
Addressing mode:
Base
N005 ( 1, 1) [000132] ------------- * LCL_VAR ref V05 arg5 u:2 (last use) $81
+ 8
New addressing mode node:
[000193] ------------- * LEA(b+8) byref
LowerCast for: N002 ( 3, 3) [000141] ------------- * CAST int <- ushort <- int $20c
lowering GT_RETURN
N003 ( 4, 4) [000020] ------------- * RETURN int $28a
============lowering call (before):
N001 ( 16, 10) [000155] --CXG-------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
objp:
======
args:
======
late:
======
results of lowering call:
N001 ( 3, 7) [000194] ------------- t194 = CNS_INT(h) int 0xFDA7BB0 ftn
lowering call (after):
N001 ( 3, 7) [000194] ------------- t194 = CNS_INT(h) int 0xFDA7BB0 ftn
/--* t194 int control expr
N001 ( 16, 10) [000155] --CXG-------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
Lower has completed modifying nodes.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
BB06 [0005] 0 0 [???..???) (throw ) keep i internal rare label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
( 8, 8) [000005] ------------- IL_OFFSET void IL offset: 0x0
N001 ( 2, 2) [000001] ------------- t1 = LCL_VAR int V04 arg4 u:2 $140
/--* t1 int
N002 ( 3, 3) [000085] ----------S-- t85 = * CAST int <- bool <- int $200
/--* t85 int
N004 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0
N005 ( 1, 1) [000144] ------------- t144 = LCL_VAR int V14 cse0 $200
N007 ( 1, 1) [000002] -c----------- t2 = CNS_INT int 0 $40
/--* t144 int
+--* t2 int
N008 ( 6, 6) [000003] J------N--S-- * EQ void $201
N009 ( 8, 8) [000004] ------------- * JTRUE void
------------ BB02 [004..02C), preds={BB01} succs={BB03}
( 14, 17) [000034] ------------- IL_OFFSET void IL offset: 0x4
N001 ( 6, 10) [000030] ----G-------- t30 = CLS_VAR_ADDR byref Hnd=0x9247f8
/--* t30 byref
[000148] ----G-------- t148 = * IND int
/--* t148 int
[000164] DA--G-------- * STORE_LCL_VAR int V17 rat2
[000165] ------------- t165 = LCL_VAR int V17 rat2
[000166] ------------- t166 = LCL_VAR int V17 rat2
[000167] -c----------- t167 = CNS_INT int 31
/--* t166 int
+--* t167 int
[000168] ------------- t168 = * RSH int
/--* t165 int
N004 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR int V15 rat0
/--* t168 int
[000170] D------------ * STORE_LCL_VAR int V16 rat1
( 19, 24) [000040] ------------- IL_OFFSET void IL offset: 0xb
N001 ( 6, 10) [000035] ----G-------- t35 = CLS_VAR_ADDR byref Hnd=0x924808
/--* t35 byref
[000149] ----G-------- t149 = * IND ref
/--* t149 ref
N003 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3
N004 ( 1, 1) [000036] ------------- t36 = CNS_INT int 0 $40
N005 ( 1, 1) [000088] ------------- t88 = LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
/--* t88 ref
[000173] -c----------- t173 = * LEA(b+4) byref
/--* t173 byref
N006 ( 3, 3) [000091] ---X--------- t91 = * IND int <l:$3c1, c:$3c0>
/--* t36 int
+--* t91 int
N007 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N008 ( 1, 1) [000089] ------------- t89 = LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
/--* t89 ref
[000174] -c----------- t174 = * LEA(b+8) byref
/--* t174 byref
N011 ( 5, 3) [000037] a---GO------- t37 = * IND ushort <l:$203, c:$4c0>
/--* t37 ushort
N015 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3
( 6, 10) [000050] ------------- IL_OFFSET void IL offset: 0x16
N001 ( 6, 10) [000045] ----G-------- t45 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t45 byref
[000150] ----G-------- t150 = * IND ref
/--* t150 ref
N003 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3
N007 ( 1, 1) [000052] ------------- t52 = LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
/--* t52 ref
[000175] ------------- t175 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token $244
/--* t53 int
[000176] ------------- t176 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token $245
/--* t54 int
[000177] ------------- t177 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000178] ------------- t178 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t175 ref arg0 in r0
+--* t176 int arg1 in r1
+--* t177 int arg2 in r2
+--* t178 int control expr
N013 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
/--* t58 int
N015 ( 27, 31) [000060] DA-XG-------- * STORE_LCL_VAR int V10 tmp2 d:3
N004 ( 1, 1) [000051] ------------- t51 = LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
/--* t51 ref
[000179] ------------- t179 = * PUTARG_REG ref REG r0
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR int V15 rat0 <l:$2c1, c:$2c0>
/--* t46 int
[000182] ------------- t182 = * PUTARG_REG int REG r2
[000171] ------------- t171 = LCL_VAR int V16 rat1
/--* t171 int
[000183] ------------- t183 = * PUTARG_REG int REG r3
/--* t182 int
+--* t183 int
[000180] Hc----------- t180 = * FIELD_LIST int int at offset 0 REG NA
N008 ( 3, 2) [000062] ------------- t62 = LCL_VAR int V10 tmp2 u:3 (last use) $283
/--* t179 ref this in r0
+--* t180 int arg1 r2,r3
+--* t62 int calli tgt
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
( 6, 10) [000070] ------------- IL_OFFSET void IL offset: 0x21
N001 ( 6, 10) [000065] ----G-------- t65 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t65 byref
[000151] ----G-------- t151 = * IND ref
/--* t151 ref
N003 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3
N007 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
/--* t72 ref
[000184] ------------- t184 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token $244
/--* t73 int
[000185] ------------- t185 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token $246
/--* t74 int
[000186] ------------- t186 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000187] ------------- t187 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t184 ref arg0 in r0
+--* t185 int arg1 in r1
+--* t186 int arg2 in r2
+--* t187 int control expr
N013 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
/--* t78 int
N015 ( 27, 31) [000080] DA-XG-------- * STORE_LCL_VAR int V12 tmp4 d:3
N004 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
/--* t71 ref
[000188] ------------- t188 = * PUTARG_REG ref REG r0
N005 ( 2, 2) [000066] ------------- t66 = LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
/--* t66 int
[000189] ------------- t189 = * PUTARG_REG int REG r1
N008 ( 3, 2) [000082] ------------- t82 = LCL_VAR int V12 tmp4 u:3 (last use) $287
/--* t188 ref this in r0
+--* t189 int arg1 in r1
+--* t82 int calli tgt
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
( 5, 5) [000011] ------------- IL_OFFSET void IL offset: 0x2c
N001 ( 1, 1) [000146] ------------- t146 = LCL_VAR int V14 cse0 $200
N002 ( 1, 1) [000008] -c----------- t8 = CNS_INT int 0 $40
/--* t146 int
+--* t8 int
N003 ( 3, 3) [000009] J------N--S-- * NE void $207
N004 ( 5, 5) [000010] ------------- * JTRUE void
------------ BB04 [030..034), preds={BB03} succs={BB05}
( 13, 14) [000028] ------------- IL_OFFSET void IL offset: 0x30
N001 ( 1, 1) [000024] ------------- t24 = CNS_INT int 0 $40
N002 ( 1, 1) [000023] ------------- t23 = LCL_VAR ref V00 arg0 u:2 $80
/--* t23 ref
[000190] -c----------- t190 = * LEA(b+4) byref
/--* t190 byref
N003 ( 3, 3) [000123] ---X--------- t123 = * IND int $3c2
/--* t24 int
+--* t123 int
N004 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
N005 ( 1, 1) [000121] ------------- t121 = LCL_VAR ref V00 arg0 u:2 (last use) $80
/--* t121 ref
[000191] -c----------- t191 = * LEA(b+8) byref
/--* t191 byref
N008 ( 5, 3) [000025] a---GO------- t25 = * IND ushort <l:$208, c:$4c2>
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
( 16, 17) [000018] ------------- IL_OFFSET void IL offset: 0x34
N001 ( 1, 1) [000014] ------------- t14 = CNS_INT int 0 $40
N002 ( 1, 1) [000013] ------------- t13 = LCL_VAR ref V05 arg5 u:2 $81
/--* t13 ref
[000192] -c----------- t192 = * LEA(b+4) byref
/--* t192 byref
N003 ( 3, 3) [000134] ---X--------- t134 = * IND int $3c3
/--* t14 int
+--* t134 int
N004 ( 8, 11) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
N005 ( 1, 1) [000132] ------------- t132 = LCL_VAR ref V05 arg5 u:2 (last use) $81
/--* t132 ref
[000193] -c----------- t193 = * LEA(b+8) byref
N010 ( 2, 2) [000015] ------------- t15 = LCL_VAR int V03 arg3 u:2 (last use) $100
/--* t193 byref
+--* t15 int
[000152] -A-XGO------- * STOREIND byte
( 4, 4) [000021] ------------- IL_OFFSET void IL offset: 0x39
N001 ( 2, 2) [000019] ------------- t19 = LCL_VAR int V01 arg1 u:2 (last use) $c0
/--* t19 int
N002 ( 3, 3) [000141] ------------- t141 = * CAST int <- ushort <- int $20c
/--* t141 int
N003 ( 4, 4) [000020] ------------- * RETURN int $28a
------------ BB06 [???..???) (throw), preds={} succs={}
N001 ( 3, 7) [000194] ------------- t194 = CNS_INT(h) int 0xFDA7BB0 ftn
/--* t194 int control expr
N001 ( 16, 10) [000155] --CXG-------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 ref class-hnd
; V01 arg1 ushort
; V02 arg2 ushort
; V03 arg3 ubyte
; V04 arg4 bool
; V05 arg5 ref class-hnd
; V06 loc0 long
; V07 loc1 ushort
; V08 OutArgs lclBlk ( 0)
; V09 tmp1 ref
; V10 tmp2 int
; V11 tmp3 ref
; V12 tmp4 int
; V13 tmp5 ref
; V14 cse0 int
; V15 rat0 int V06.lo(offs=0x00)
; V16 rat1 int V06.hi(offs=0x04)
; V17 rat2 int
In fgLocalVarLivenessInit, sorting locals
refCnt table for 'M11':
V00 arg0 [ ref]: refCnt = 6, refCntWtd = 4 pref [r0]
V13 tmp5 [ ref]: refCnt = 6, refCntWtd = 6
V14 cse0 [ int]: refCnt = 6, refCntWtd = 6
V03 arg3 [ ubyte]: refCnt = 4, refCntWtd = 4 pref [r3]
V02 arg2 [ushort]: refCnt = 5, refCntWtd = 3.50 pref [r2]
V01 arg1 [ushort]: refCnt = 3, refCntWtd = 3 pref [r1]
V05 arg5 [ ref]: refCnt = 4, refCntWtd = 4
V09 tmp1 [ ref]: refCnt = 3, refCntWtd = 3
V11 tmp3 [ ref]: refCnt = 3, refCntWtd = 3
V17 rat2 [ int]: refCnt = 3, refCntWtd = 3
V04 arg4 [ bool]: refCnt = 2, refCntWtd = 2
V10 tmp2 [ int]: refCnt = 2, refCntWtd = 2
V12 tmp4 [ int]: refCnt = 2, refCntWtd = 2
V15 rat0 [ int]: refCnt = 2, refCntWtd = 1
V16 rat1 [ int]: refCnt = 2, refCntWtd = 1
V08 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={ V04}
DEF(1)={V14 }
BB02 USE(0)={ } + ByrefExposed + GcHeap
DEF(9)={V13 V02 V09 V11 V17 V10 V12 V15 V16} + ByrefExposed* + GcHeap*
BB03 USE(1)={V14}
DEF(0)={ }
BB04 USE(1)={V00} + ByrefExposed + GcHeap
DEF(0)={ }
BB05 USE(3)={V03 V01 V05} + ByrefExposed + GcHeap
DEF(0)={ }
BB06 USE(0)={}
DEF(0)={}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (5)={V00 V03 V01 V05 V04} + ByrefExposed + GcHeap
OUT(5)={V00 V14 V03 V01 V05 } + ByrefExposed + GcHeap
BB02 IN (5)={V00 V14 V03 V01 V05} + ByrefExposed + GcHeap
OUT(5)={V00 V14 V03 V01 V05} + ByrefExposed + GcHeap
BB03 IN (5)={V00 V14 V03 V01 V05} + ByrefExposed + GcHeap
OUT(4)={V00 V03 V01 V05} + ByrefExposed + GcHeap
BB04 IN (4)={V00 V03 V01 V05} + ByrefExposed + GcHeap
OUT(3)={ V03 V01 V05} + ByrefExposed + GcHeap
BB05 IN (3)={V03 V01 V05} + ByrefExposed + GcHeap
OUT(0)={ }
BB06 IN (0)={}
OUT(0)={}
Removing dead node:
N008 ( 5, 3) [000025] a---GO------- * IND ushort <l:$208, c:$4c2>
Removing dead node:
[000191] ------------- * LEA(b+8) byref
Removing dead LclVar use:
N005 ( 1, 1) [000121] ------------- * LCL_VAR ref V00 arg0 u:2 (last use) $80
New refCnts for V00: refCnt = 5, refCntWtd = 3.50
In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal)
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
BB06 [0005] 0 0 [???..???) (throw ) keep i internal rare label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Liveness pass finished after lowering, IR:
lvasortagain = 0
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
BB06 [0005] 0 0 [???..???) (throw ) keep i internal rare label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
( 8, 8) [000005] ------------- IL_OFFSET void IL offset: 0x0
N001 ( 2, 2) [000001] ------------- t1 = LCL_VAR int V04 arg4 u:2 (last use) $140
/--* t1 int
N002 ( 3, 3) [000085] ----------S-- t85 = * CAST int <- bool <- int $200
/--* t85 int
N004 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0
N005 ( 1, 1) [000144] ------------- t144 = LCL_VAR int V14 cse0 $200
N007 ( 1, 1) [000002] -c----------- t2 = CNS_INT int 0 $40
/--* t144 int
+--* t2 int
N008 ( 6, 6) [000003] J------N--S-- * EQ void $201
N009 ( 8, 8) [000004] ------------- * JTRUE void
------------ BB02 [004..02C), preds={BB01} succs={BB03}
( 14, 17) [000034] ------------- IL_OFFSET void IL offset: 0x4
N001 ( 6, 10) [000030] ----G-------- t30 = CLS_VAR_ADDR byref Hnd=0x9247f8
/--* t30 byref
[000148] ----G-------- t148 = * IND int
/--* t148 int
[000164] DA--G-------- * STORE_LCL_VAR int V17 rat2
[000165] ------------- t165 = LCL_VAR int V17 rat2
[000166] ------------- t166 = LCL_VAR int V17 rat2 (last use)
[000167] -c----------- t167 = CNS_INT int 31
/--* t166 int
+--* t167 int
[000168] ------------- t168 = * RSH int
/--* t165 int
N004 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR int V15 rat0
/--* t168 int
[000170] D------------ * STORE_LCL_VAR int V16 rat1
( 19, 24) [000040] ------------- IL_OFFSET void IL offset: 0xb
N001 ( 6, 10) [000035] ----G-------- t35 = CLS_VAR_ADDR byref Hnd=0x924808
/--* t35 byref
[000149] ----G-------- t149 = * IND ref
/--* t149 ref
N003 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3
N004 ( 1, 1) [000036] ------------- t36 = CNS_INT int 0 $40
N005 ( 1, 1) [000088] ------------- t88 = LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
/--* t88 ref
[000173] -c----------- t173 = * LEA(b+4) byref
/--* t173 byref
N006 ( 3, 3) [000091] ---X--------- t91 = * IND int <l:$3c1, c:$3c0>
/--* t36 int
+--* t91 int
N007 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N008 ( 1, 1) [000089] ------------- t89 = LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
/--* t89 ref
[000174] -c----------- t174 = * LEA(b+8) byref
/--* t174 byref
N011 ( 5, 3) [000037] a---GO------- t37 = * IND ushort <l:$203, c:$4c0>
/--* t37 ushort
N015 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3
( 6, 10) [000050] ------------- IL_OFFSET void IL offset: 0x16
N001 ( 6, 10) [000045] ----G-------- t45 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t45 byref
[000150] ----G-------- t150 = * IND ref
/--* t150 ref
N003 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3
N007 ( 1, 1) [000052] ------------- t52 = LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
/--* t52 ref
[000175] ------------- t175 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token $244
/--* t53 int
[000176] ------------- t176 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token $245
/--* t54 int
[000177] ------------- t177 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000178] ------------- t178 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t175 ref arg0 in r0
+--* t176 int arg1 in r1
+--* t177 int arg2 in r2
+--* t178 int control expr
N013 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
/--* t58 int
N015 ( 27, 31) [000060] DA-XG-------- * STORE_LCL_VAR int V10 tmp2 d:3
N004 ( 1, 1) [000051] ------------- t51 = LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
/--* t51 ref
[000179] ------------- t179 = * PUTARG_REG ref REG r0
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR int V15 rat0 (last use) <l:$2c1, c:$2c0>
/--* t46 int
[000182] ------------- t182 = * PUTARG_REG int REG r2
[000171] ------------- t171 = LCL_VAR int V16 rat1 (last use)
/--* t171 int
[000183] ------------- t183 = * PUTARG_REG int REG r3
/--* t182 int
+--* t183 int
[000180] Hc----------- t180 = * FIELD_LIST int int at offset 0 REG NA
N008 ( 3, 2) [000062] ------------- t62 = LCL_VAR int V10 tmp2 u:3 (last use) $283
/--* t179 ref this in r0
+--* t180 int arg1 r2,r3
+--* t62 int calli tgt
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
( 6, 10) [000070] ------------- IL_OFFSET void IL offset: 0x21
N001 ( 6, 10) [000065] ----G-------- t65 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t65 byref
[000151] ----G-------- t151 = * IND ref
/--* t151 ref
N003 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3
N007 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
/--* t72 ref
[000184] ------------- t184 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token $244
/--* t73 int
[000185] ------------- t185 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token $246
/--* t74 int
[000186] ------------- t186 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000187] ------------- t187 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t184 ref arg0 in r0
+--* t185 int arg1 in r1
+--* t186 int arg2 in r2
+--* t187 int control expr
N013 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
/--* t78 int
N015 ( 27, 31) [000080] DA-XG-------- * STORE_LCL_VAR int V12 tmp4 d:3
N004 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
/--* t71 ref
[000188] ------------- t188 = * PUTARG_REG ref REG r0
N005 ( 2, 2) [000066] ------------- t66 = LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
/--* t66 int
[000189] ------------- t189 = * PUTARG_REG int REG r1
N008 ( 3, 2) [000082] ------------- t82 = LCL_VAR int V12 tmp4 u:3 (last use) $287
/--* t188 ref this in r0
+--* t189 int arg1 in r1
+--* t82 int calli tgt
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
( 5, 5) [000011] ------------- IL_OFFSET void IL offset: 0x2c
N001 ( 1, 1) [000146] ------------- t146 = LCL_VAR int V14 cse0 (last use) $200
N002 ( 1, 1) [000008] -c----------- t8 = CNS_INT int 0 $40
/--* t146 int
+--* t8 int
N003 ( 3, 3) [000009] J------N--S-- * NE void $207
N004 ( 5, 5) [000010] ------------- * JTRUE void
------------ BB04 [030..034), preds={BB03} succs={BB05}
( 13, 14) [000028] ------------- IL_OFFSET void IL offset: 0x30
N001 ( 1, 1) [000024] ------------- t24 = CNS_INT int 0 $40
N002 ( 1, 1) [000023] ------------- t23 = LCL_VAR ref V00 arg0 u:2 (last use) $80
/--* t23 ref
[000190] -c----------- t190 = * LEA(b+4) byref
/--* t190 byref
N003 ( 3, 3) [000123] ---X--------- t123 = * IND int $3c2
/--* t24 int
+--* t123 int
N004 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
( 16, 17) [000018] ------------- IL_OFFSET void IL offset: 0x34
N001 ( 1, 1) [000014] ------------- t14 = CNS_INT int 0 $40
N002 ( 1, 1) [000013] ------------- t13 = LCL_VAR ref V05 arg5 u:2 $81
/--* t13 ref
[000192] -c----------- t192 = * LEA(b+4) byref
/--* t192 byref
N003 ( 3, 3) [000134] ---X--------- t134 = * IND int $3c3
/--* t14 int
+--* t134 int
N004 ( 8, 11) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
N005 ( 1, 1) [000132] ------------- t132 = LCL_VAR ref V05 arg5 u:2 (last use) $81
/--* t132 ref
[000193] -c----------- t193 = * LEA(b+8) byref
N010 ( 2, 2) [000015] ------------- t15 = LCL_VAR int V03 arg3 u:2 (last use) $100
/--* t193 byref
+--* t15 int
[000152] -A-XGO------- * STOREIND byte
( 4, 4) [000021] ------------- IL_OFFSET void IL offset: 0x39
N001 ( 2, 2) [000019] ------------- t19 = LCL_VAR int V01 arg1 u:2 (last use) $c0
/--* t19 int
N002 ( 3, 3) [000141] ------------- t141 = * CAST int <- ushort <- int $20c
/--* t141 int
N003 ( 4, 4) [000020] ------------- * RETURN int $28a
------------ BB06 [???..???) (throw), preds={} succs={}
N001 ( 3, 7) [000194] ------------- t194 = CNS_INT(h) int 0xFDA7BB0 ftn
/--* t194 int control expr
N001 ( 16, 10) [000155] --CXG-------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
BB06 [0005] 0 0 [???..???) (throw ) keep i internal rare label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
( 8, 8) [000005] ------------- IL_OFFSET void IL offset: 0x0
N001 ( 2, 2) [000001] ------------- t1 = LCL_VAR int V04 arg4 u:2 (last use) $140
/--* t1 int
N002 ( 3, 3) [000085] ----------S-- t85 = * CAST int <- bool <- int $200
/--* t85 int
N004 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0
N005 ( 1, 1) [000144] ------------- t144 = LCL_VAR int V14 cse0 $200
N007 ( 1, 1) [000002] -c----------- t2 = CNS_INT int 0 $40
/--* t144 int
+--* t2 int
N008 ( 6, 6) [000003] J------N--S-- * EQ void $201
N009 ( 8, 8) [000004] ------------- * JTRUE void
------------ BB02 [004..02C), preds={BB01} succs={BB03}
( 14, 17) [000034] ------------- IL_OFFSET void IL offset: 0x4
N001 ( 6, 10) [000030] ----G-------- t30 = CLS_VAR_ADDR byref Hnd=0x9247f8
/--* t30 byref
[000148] ----G-------- t148 = * IND int
/--* t148 int
[000164] DA--G-------- * STORE_LCL_VAR int V17 rat2
[000165] ------------- t165 = LCL_VAR int V17 rat2
[000166] ------------- t166 = LCL_VAR int V17 rat2 (last use)
[000167] -c----------- t167 = CNS_INT int 31
/--* t166 int
+--* t167 int
[000168] ------------- t168 = * RSH int
/--* t165 int
N004 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR int V15 rat0
/--* t168 int
[000170] D------------ * STORE_LCL_VAR int V16 rat1
( 19, 24) [000040] ------------- IL_OFFSET void IL offset: 0xb
N001 ( 6, 10) [000035] ----G-------- t35 = CLS_VAR_ADDR byref Hnd=0x924808
/--* t35 byref
[000149] ----G-------- t149 = * IND ref
/--* t149 ref
N003 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3
N004 ( 1, 1) [000036] ------------- t36 = CNS_INT int 0 $40
N005 ( 1, 1) [000088] ------------- t88 = LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
/--* t88 ref
[000173] -c----------- t173 = * LEA(b+4) byref
/--* t173 byref
N006 ( 3, 3) [000091] ---X--------- t91 = * IND int <l:$3c1, c:$3c0>
/--* t36 int
+--* t91 int
N007 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N008 ( 1, 1) [000089] ------------- t89 = LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
/--* t89 ref
[000174] -c----------- t174 = * LEA(b+8) byref
/--* t174 byref
N011 ( 5, 3) [000037] a---GO------- t37 = * IND ushort <l:$203, c:$4c0>
/--* t37 ushort
N015 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3
( 6, 10) [000050] ------------- IL_OFFSET void IL offset: 0x16
N001 ( 6, 10) [000045] ----G-------- t45 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t45 byref
[000150] ----G-------- t150 = * IND ref
/--* t150 ref
N003 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3
N007 ( 1, 1) [000052] ------------- t52 = LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
/--* t52 ref
[000175] ------------- t175 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token $244
/--* t53 int
[000176] ------------- t176 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token $245
/--* t54 int
[000177] ------------- t177 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000178] ------------- t178 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t175 ref arg0 in r0
+--* t176 int arg1 in r1
+--* t177 int arg2 in r2
+--* t178 int control expr
N013 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
/--* t58 int
N015 ( 27, 31) [000060] DA-XG-------- * STORE_LCL_VAR int V10 tmp2 d:3
N004 ( 1, 1) [000051] ------------- t51 = LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
/--* t51 ref
[000179] ------------- t179 = * PUTARG_REG ref REG r0
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR int V15 rat0 (last use) <l:$2c1, c:$2c0>
/--* t46 int
[000182] ------------- t182 = * PUTARG_REG int REG r2
[000171] ------------- t171 = LCL_VAR int V16 rat1 (last use)
/--* t171 int
[000183] ------------- t183 = * PUTARG_REG int REG r3
/--* t182 int
+--* t183 int
[000180] Hc----------- t180 = * FIELD_LIST int int at offset 0 REG NA
N008 ( 3, 2) [000062] ------------- t62 = LCL_VAR int V10 tmp2 u:3 (last use) $283
/--* t179 ref this in r0
+--* t180 int arg1 r2,r3
+--* t62 int calli tgt
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
( 6, 10) [000070] ------------- IL_OFFSET void IL offset: 0x21
N001 ( 6, 10) [000065] ----G-------- t65 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t65 byref
[000151] ----G-------- t151 = * IND ref
/--* t151 ref
N003 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3
N007 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
/--* t72 ref
[000184] ------------- t184 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token $244
/--* t73 int
[000185] ------------- t185 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token $246
/--* t74 int
[000186] ------------- t186 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000187] ------------- t187 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t184 ref arg0 in r0
+--* t185 int arg1 in r1
+--* t186 int arg2 in r2
+--* t187 int control expr
N013 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
/--* t78 int
N015 ( 27, 31) [000080] DA-XG-------- * STORE_LCL_VAR int V12 tmp4 d:3
N004 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
/--* t71 ref
[000188] ------------- t188 = * PUTARG_REG ref REG r0
N005 ( 2, 2) [000066] ------------- t66 = LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
/--* t66 int
[000189] ------------- t189 = * PUTARG_REG int REG r1
N008 ( 3, 2) [000082] ------------- t82 = LCL_VAR int V12 tmp4 u:3 (last use) $287
/--* t188 ref this in r0
+--* t189 int arg1 in r1
+--* t82 int calli tgt
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
( 5, 5) [000011] ------------- IL_OFFSET void IL offset: 0x2c
N001 ( 1, 1) [000146] ------------- t146 = LCL_VAR int V14 cse0 (last use) $200
N002 ( 1, 1) [000008] -c----------- t8 = CNS_INT int 0 $40
/--* t146 int
+--* t8 int
N003 ( 3, 3) [000009] J------N--S-- * NE void $207
N004 ( 5, 5) [000010] ------------- * JTRUE void
------------ BB04 [030..034), preds={BB03} succs={BB05}
( 13, 14) [000028] ------------- IL_OFFSET void IL offset: 0x30
N001 ( 1, 1) [000024] ------------- t24 = CNS_INT int 0 $40
N002 ( 1, 1) [000023] ------------- t23 = LCL_VAR ref V00 arg0 u:2 (last use) $80
/--* t23 ref
[000190] -c----------- t190 = * LEA(b+4) byref
/--* t190 byref
N003 ( 3, 3) [000123] ---X--------- t123 = * IND int $3c2
/--* t24 int
+--* t123 int
N004 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
( 16, 17) [000018] ------------- IL_OFFSET void IL offset: 0x34
N001 ( 1, 1) [000014] ------------- t14 = CNS_INT int 0 $40
N002 ( 1, 1) [000013] ------------- t13 = LCL_VAR ref V05 arg5 u:2 $81
/--* t13 ref
[000192] -c----------- t192 = * LEA(b+4) byref
/--* t192 byref
N003 ( 3, 3) [000134] ---X--------- t134 = * IND int $3c3
/--* t14 int
+--* t134 int
N004 ( 8, 11) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
N005 ( 1, 1) [000132] ------------- t132 = LCL_VAR ref V05 arg5 u:2 (last use) $81
/--* t132 ref
[000193] -c----------- t193 = * LEA(b+8) byref
N010 ( 2, 2) [000015] ------------- t15 = LCL_VAR int V03 arg3 u:2 (last use) $100
/--* t193 byref
+--* t15 int
[000152] -A-XGO------- * STOREIND byte
( 4, 4) [000021] ------------- IL_OFFSET void IL offset: 0x39
N001 ( 2, 2) [000019] ------------- t19 = LCL_VAR int V01 arg1 u:2 (last use) $c0
/--* t19 int
N002 ( 3, 3) [000141] ------------- t141 = * CAST int <- ushort <- int $20c
/--* t141 int
N003 ( 4, 4) [000020] ------------- * RETURN int $28a
------------ BB06 [???..???) (throw), preds={} succs={}
N001 ( 3, 7) [000194] ------------- t194 = CNS_INT(h) int 0xFDA7BB0 ftn
/--* t194 int control expr
N001 ( 16, 10) [000155] --CXG-------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
BB06 [0005] 0 0 [???..???) (throw ) keep i internal rare label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
( 8, 8) [000005] ------------- IL_OFFSET void IL offset: 0x0
N001 ( 2, 2) [000001] ------------- t1 = LCL_VAR int V04 arg4 u:2 (last use) $140
/--* t1 int
N002 ( 3, 3) [000085] ----------S-- t85 = * CAST int <- bool <- int $200
/--* t85 int
N004 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0
N005 ( 1, 1) [000144] ------------- t144 = LCL_VAR int V14 cse0 $200
N007 ( 1, 1) [000002] -c----------- t2 = CNS_INT int 0 $40
/--* t144 int
+--* t2 int
N008 ( 6, 6) [000003] J------N--S-- * EQ void $201
N009 ( 8, 8) [000004] ------------- * JTRUE void
------------ BB02 [004..02C), preds={BB01} succs={BB03}
( 14, 17) [000034] ------------- IL_OFFSET void IL offset: 0x4
N001 ( 6, 10) [000030] ----G-------- t30 = CLS_VAR_ADDR byref Hnd=0x9247f8
/--* t30 byref
[000148] ----G-------- t148 = * IND int
/--* t148 int
[000164] DA--G-------- * STORE_LCL_VAR int V17 rat2
[000165] ------------- t165 = LCL_VAR int V17 rat2
[000166] ------------- t166 = LCL_VAR int V17 rat2 (last use)
[000167] -c----------- t167 = CNS_INT int 31
/--* t166 int
+--* t167 int
[000168] ------------- t168 = * RSH int
/--* t165 int
N004 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR int V15 rat0
/--* t168 int
[000170] D------------ * STORE_LCL_VAR int V16 rat1
( 19, 24) [000040] ------------- IL_OFFSET void IL offset: 0xb
N001 ( 6, 10) [000035] ----G-------- t35 = CLS_VAR_ADDR byref Hnd=0x924808
/--* t35 byref
[000149] ----G-------- t149 = * IND ref
/--* t149 ref
N003 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3
N004 ( 1, 1) [000036] ------------- t36 = CNS_INT int 0 $40
N005 ( 1, 1) [000088] ------------- t88 = LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
/--* t88 ref
[000173] -c----------- t173 = * LEA(b+4) byref
/--* t173 byref
N006 ( 3, 3) [000091] ---X--------- t91 = * IND int <l:$3c1, c:$3c0>
/--* t36 int
+--* t91 int
N007 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N008 ( 1, 1) [000089] ------------- t89 = LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
/--* t89 ref
[000174] -c----------- t174 = * LEA(b+8) byref
/--* t174 byref
N011 ( 5, 3) [000037] a---GO------- t37 = * IND ushort <l:$203, c:$4c0>
/--* t37 ushort
N015 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3
( 6, 10) [000050] ------------- IL_OFFSET void IL offset: 0x16
N001 ( 6, 10) [000045] ----G-------- t45 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t45 byref
[000150] ----G-------- t150 = * IND ref
/--* t150 ref
N003 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3
N007 ( 1, 1) [000052] ------------- t52 = LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
/--* t52 ref
[000175] ------------- t175 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token $244
/--* t53 int
[000176] ------------- t176 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token $245
/--* t54 int
[000177] ------------- t177 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000178] ------------- t178 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t175 ref arg0 in r0
+--* t176 int arg1 in r1
+--* t177 int arg2 in r2
+--* t178 int control expr
N013 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
/--* t58 int
N015 ( 27, 31) [000060] DA-XG-------- * STORE_LCL_VAR int V10 tmp2 d:3
N004 ( 1, 1) [000051] ------------- t51 = LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
/--* t51 ref
[000179] ------------- t179 = * PUTARG_REG ref REG r0
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR int V15 rat0 (last use) <l:$2c1, c:$2c0>
/--* t46 int
[000182] ------------- t182 = * PUTARG_REG int REG r2
[000171] ------------- t171 = LCL_VAR int V16 rat1 (last use)
/--* t171 int
[000183] ------------- t183 = * PUTARG_REG int REG r3
/--* t182 int
+--* t183 int
[000180] Hc----------- t180 = * FIELD_LIST int int at offset 0 REG NA
N008 ( 3, 2) [000062] ------------- t62 = LCL_VAR int V10 tmp2 u:3 (last use) $283
/--* t179 ref this in r0
+--* t180 int arg1 r2,r3
+--* t62 int calli tgt
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
( 6, 10) [000070] ------------- IL_OFFSET void IL offset: 0x21
N001 ( 6, 10) [000065] ----G-------- t65 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t65 byref
[000151] ----G-------- t151 = * IND ref
/--* t151 ref
N003 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3
N007 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
/--* t72 ref
[000184] ------------- t184 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token $244
/--* t73 int
[000185] ------------- t185 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token $246
/--* t74 int
[000186] ------------- t186 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000187] ------------- t187 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t184 ref arg0 in r0
+--* t185 int arg1 in r1
+--* t186 int arg2 in r2
+--* t187 int control expr
N013 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
/--* t78 int
N015 ( 27, 31) [000080] DA-XG-------- * STORE_LCL_VAR int V12 tmp4 d:3
N004 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
/--* t71 ref
[000188] ------------- t188 = * PUTARG_REG ref REG r0
N005 ( 2, 2) [000066] ------------- t66 = LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
/--* t66 int
[000189] ------------- t189 = * PUTARG_REG int REG r1
N008 ( 3, 2) [000082] ------------- t82 = LCL_VAR int V12 tmp4 u:3 (last use) $287
/--* t188 ref this in r0
+--* t189 int arg1 in r1
+--* t82 int calli tgt
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
( 5, 5) [000011] ------------- IL_OFFSET void IL offset: 0x2c
N001 ( 1, 1) [000146] ------------- t146 = LCL_VAR int V14 cse0 (last use) $200
N002 ( 1, 1) [000008] -c----------- t8 = CNS_INT int 0 $40
/--* t146 int
+--* t8 int
N003 ( 3, 3) [000009] J------N--S-- * NE void $207
N004 ( 5, 5) [000010] ------------- * JTRUE void
------------ BB04 [030..034), preds={BB03} succs={BB05}
( 13, 14) [000028] ------------- IL_OFFSET void IL offset: 0x30
N001 ( 1, 1) [000024] ------------- t24 = CNS_INT int 0 $40
N002 ( 1, 1) [000023] ------------- t23 = LCL_VAR ref V00 arg0 u:2 (last use) $80
/--* t23 ref
[000190] -c----------- t190 = * LEA(b+4) byref
/--* t190 byref
N003 ( 3, 3) [000123] ---X--------- t123 = * IND int $3c2
/--* t24 int
+--* t123 int
N004 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
( 16, 17) [000018] ------------- IL_OFFSET void IL offset: 0x34
N001 ( 1, 1) [000014] ------------- t14 = CNS_INT int 0 $40
N002 ( 1, 1) [000013] ------------- t13 = LCL_VAR ref V05 arg5 u:2 $81
/--* t13 ref
[000192] -c----------- t192 = * LEA(b+4) byref
/--* t192 byref
N003 ( 3, 3) [000134] ---X--------- t134 = * IND int $3c3
/--* t14 int
+--* t134 int
N004 ( 8, 11) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
N005 ( 1, 1) [000132] ------------- t132 = LCL_VAR ref V05 arg5 u:2 (last use) $81
/--* t132 ref
[000193] -c----------- t193 = * LEA(b+8) byref
N010 ( 2, 2) [000015] ------------- t15 = LCL_VAR int V03 arg3 u:2 (last use) $100
/--* t193 byref
+--* t15 int
[000152] -A-XGO------- * STOREIND byte
( 4, 4) [000021] ------------- IL_OFFSET void IL offset: 0x39
N001 ( 2, 2) [000019] ------------- t19 = LCL_VAR int V01 arg1 u:2 (last use) $c0
/--* t19 int
N002 ( 3, 3) [000141] ------------- t141 = * CAST int <- ushort <- int $20c
/--* t141 int
N003 ( 4, 4) [000020] ------------- * RETURN int $28a
------------ BB06 [???..???) (throw), preds={} succs={}
N001 ( 3, 7) [000194] ------------- t194 = CNS_INT(h) int 0xFDA7BB0 ftn
/--* t194 int control expr
N001 ( 16, 10) [000155] --CXG-------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
BB06 [0005] 0 0 [???..???) (throw ) keep i internal rare label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
( 8, 8) [000005] ------------- IL_OFFSET void IL offset: 0x0
N001 ( 2, 2) [000001] ------------- t1 = LCL_VAR int V04 arg4 u:2 (last use) $140
/--* t1 int
N002 ( 3, 3) [000085] ----------S-- t85 = * CAST int <- bool <- int $200
/--* t85 int
N004 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0
N005 ( 1, 1) [000144] ------------- t144 = LCL_VAR int V14 cse0 $200
N007 ( 1, 1) [000002] -c----------- t2 = CNS_INT int 0 $40
/--* t144 int
+--* t2 int
N008 ( 6, 6) [000003] J------N--S-- * EQ void $201
N009 ( 8, 8) [000004] ------------- * JTRUE void
------------ BB02 [004..02C), preds={BB01} succs={BB03}
( 14, 17) [000034] ------------- IL_OFFSET void IL offset: 0x4
N001 ( 6, 10) [000030] ----G-------- t30 = CLS_VAR_ADDR byref Hnd=0x9247f8
/--* t30 byref
[000148] ----G-------- t148 = * IND int
/--* t148 int
[000164] DA--G-------- * STORE_LCL_VAR int V17 rat2
[000165] ------------- t165 = LCL_VAR int V17 rat2
[000166] ------------- t166 = LCL_VAR int V17 rat2 (last use)
[000167] -c----------- t167 = CNS_INT int 31
/--* t166 int
+--* t167 int
[000168] ------------- t168 = * RSH int
/--* t165 int
N004 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR int V15 rat0
/--* t168 int
[000170] D------------ * STORE_LCL_VAR int V16 rat1
( 19, 24) [000040] ------------- IL_OFFSET void IL offset: 0xb
N001 ( 6, 10) [000035] ----G-------- t35 = CLS_VAR_ADDR byref Hnd=0x924808
/--* t35 byref
[000149] ----G-------- t149 = * IND ref
/--* t149 ref
N003 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3
N004 ( 1, 1) [000036] ------------- t36 = CNS_INT int 0 $40
N005 ( 1, 1) [000088] ------------- t88 = LCL_VAR ref V13 tmp5 u:3 <l:$340, c:$380>
/--* t88 ref
[000173] -c----------- t173 = * LEA(b+4) byref
/--* t173 byref
N006 ( 3, 3) [000091] ---X--------- t91 = * IND int <l:$3c1, c:$3c0>
/--* t36 int
+--* t91 int
N007 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N008 ( 1, 1) [000089] ------------- t89 = LCL_VAR ref V13 tmp5 u:3 (last use) <l:$340, c:$380>
/--* t89 ref
[000174] -c----------- t174 = * LEA(b+8) byref
/--* t174 byref
N011 ( 5, 3) [000037] a---GO------- t37 = * IND ushort <l:$203, c:$4c0>
/--* t37 ushort
N015 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3
( 6, 10) [000050] ------------- IL_OFFSET void IL offset: 0x16
N001 ( 6, 10) [000045] ----G-------- t45 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t45 byref
[000150] ----G-------- t150 = * IND ref
/--* t150 ref
N003 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3
N007 ( 1, 1) [000052] ------------- t52 = LCL_VAR ref V09 tmp1 u:3 <l:$349, c:$382>
/--* t52 ref
[000175] ------------- t175 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token $244
/--* t53 int
[000176] ------------- t176 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token $245
/--* t54 int
[000177] ------------- t177 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000178] ------------- t178 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t175 ref arg0 in r0
+--* t176 int arg1 in r1
+--* t177 int arg2 in r2
+--* t178 int control expr
N013 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
/--* t58 int
N015 ( 27, 31) [000060] DA-XG-------- * STORE_LCL_VAR int V10 tmp2 d:3
N004 ( 1, 1) [000051] ------------- t51 = LCL_VAR ref V09 tmp1 u:3 (last use) <l:$349, c:$382>
/--* t51 ref
[000179] ------------- t179 = * PUTARG_REG ref REG r0
N005 ( 3, 2) [000046] ------------- t46 = LCL_VAR int V15 rat0 (last use) <l:$2c1, c:$2c0>
/--* t46 int
[000182] ------------- t182 = * PUTARG_REG int REG r2
[000171] ------------- t171 = LCL_VAR int V16 rat1 (last use)
/--* t171 int
[000183] ------------- t183 = * PUTARG_REG int REG r3
/--* t182 int
+--* t183 int
[000180] Hc----------- t180 = * FIELD_LIST int int at offset 0 REG NA
N008 ( 3, 2) [000062] ------------- t62 = LCL_VAR int V10 tmp2 u:3 (last use) $283
/--* t179 ref this in r0
+--* t180 int arg1 r2,r3
+--* t62 int calli tgt
N009 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
( 6, 10) [000070] ------------- IL_OFFSET void IL offset: 0x21
N001 ( 6, 10) [000065] ----G-------- t65 = CLS_VAR_ADDR byref Hnd=0x9247d8
/--* t65 byref
[000151] ----G-------- t151 = * IND ref
/--* t151 ref
N003 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3
N007 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 <l:$34b, c:$388>
/--* t72 ref
[000184] ------------- t184 = * PUTARG_REG ref REG r0
N008 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token $244
/--* t73 int
[000185] ------------- t185 = * PUTARG_REG int REG r1
N009 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token $246
/--* t74 int
[000186] ------------- t186 = * PUTARG_REG int REG r2
N001 ( 3, 7) [000187] ------------- t187 = CNS_INT(h) int 0xFDA55A0 ftn
/--* t184 ref arg0 in r0
+--* t185 int arg1 in r1
+--* t186 int arg2 in r2
+--* t187 int control expr
N013 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
/--* t78 int
N015 ( 27, 31) [000080] DA-XG-------- * STORE_LCL_VAR int V12 tmp4 d:3
N004 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 (last use) <l:$34b, c:$388>
/--* t71 ref
[000188] ------------- t188 = * PUTARG_REG ref REG r0
N005 ( 2, 2) [000066] ------------- t66 = LCL_VAR int V02 arg2 u:3 (last use) <l:$203, c:$4c0>
/--* t66 int
[000189] ------------- t189 = * PUTARG_REG int REG r1
N008 ( 3, 2) [000082] ------------- t82 = LCL_VAR int V12 tmp4 u:3 (last use) $287
/--* t188 ref this in r0
+--* t189 int arg1 in r1
+--* t82 int calli tgt
N009 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
( 5, 5) [000011] ------------- IL_OFFSET void IL offset: 0x2c
N001 ( 1, 1) [000146] ------------- t146 = LCL_VAR int V14 cse0 (last use) $200
N002 ( 1, 1) [000008] -c----------- t8 = CNS_INT int 0 $40
/--* t146 int
+--* t8 int
N003 ( 3, 3) [000009] J------N--S-- * NE void $207
N004 ( 5, 5) [000010] ------------- * JTRUE void
------------ BB04 [030..034), preds={BB03} succs={BB05}
( 13, 14) [000028] ------------- IL_OFFSET void IL offset: 0x30
N001 ( 1, 1) [000024] ------------- t24 = CNS_INT int 0 $40
N002 ( 1, 1) [000023] ------------- t23 = LCL_VAR ref V00 arg0 u:2 (last use) $80
/--* t23 ref
[000190] -c----------- t190 = * LEA(b+4) byref
/--* t190 byref
N003 ( 3, 3) [000123] ---X--------- t123 = * IND int $3c2
/--* t24 int
+--* t123 int
N004 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
( 16, 17) [000018] ------------- IL_OFFSET void IL offset: 0x34
N001 ( 1, 1) [000014] ------------- t14 = CNS_INT int 0 $40
N002 ( 1, 1) [000013] ------------- t13 = LCL_VAR ref V05 arg5 u:2 $81
/--* t13 ref
[000192] -c----------- t192 = * LEA(b+4) byref
/--* t192 byref
N003 ( 3, 3) [000134] ---X--------- t134 = * IND int $3c3
/--* t14 int
+--* t134 int
N004 ( 8, 11) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
N005 ( 1, 1) [000132] ------------- t132 = LCL_VAR ref V05 arg5 u:2 (last use) $81
/--* t132 ref
[000193] -c----------- t193 = * LEA(b+8) byref
N010 ( 2, 2) [000015] ------------- t15 = LCL_VAR int V03 arg3 u:2 (last use) $100
/--* t193 byref
+--* t15 int
[000152] -A-XGO------- * STOREIND byte
( 4, 4) [000021] ------------- IL_OFFSET void IL offset: 0x39
N001 ( 2, 2) [000019] ------------- t19 = LCL_VAR int V01 arg1 u:2 (last use) $c0
/--* t19 int
N002 ( 3, 3) [000141] ------------- t141 = * CAST int <- ushort <- int $20c
/--* t141 int
N003 ( 4, 4) [000020] ------------- * RETURN int $28a
------------ BB06 [???..???) (throw), preds={} succs={}
N001 ( 3, 7) [000194] ------------- t194 = CNS_INT(h) int 0xFDA7BB0 ftn
/--* t194 int control expr
N001 ( 16, 10) [000155] --CXG-------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{V04}
{V14}
{V00 V01 V03 V04 V05}
{V00 V01 V03 V05 V14}
BB02 use def in out
{}
{V02 V09 V10 V11 V12 V13 V15 V16 V17}
{V00 V01 V03 V05 V14}
{V00 V01 V03 V05 V14}
BB03 use def in out
{V14}
{}
{V00 V01 V03 V05 V14}
{V00 V01 V03 V05}
BB04 use def in out
{V00}
{}
{V00 V01 V03 V05}
{V01 V03 V05}
BB05 use def in out
{V01 V03 V05}
{}
{V01 V03 V05}
{}
BB06 use def in out
{}
{}
{}
{}
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
Interval 7: RefPositions {} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {} physReg:NA Preferences=[allInt]
Interval 9: RefPositions {} physReg:NA Preferences=[allInt]
Interval 10: RefPositions {} physReg:NA Preferences=[allInt]
Interval 11: RefPositions {} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {} physReg:NA Preferences=[allInt]
Interval 13: RefPositions {} physReg:NA Preferences=[allInt]
Interval 14: RefPositions {} physReg:NA Preferences=[allInt]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
lvaTable after IdentifyCandidates
; Pre-RegAlloc local variable assignments
;
; V00 arg0 [V00,T00] ( 5, 3.50) ref -> class-hnd
; V01 arg1 [V01,T05] ( 3, 3 ) ushort ->
; V02 arg2 [V02,T04] ( 5, 3.50) ushort ->
; V03 arg3 [V03,T03] ( 4, 4 ) ubyte ->
; V04 arg4 [V04,T10] ( 2, 2 ) bool ->
; V05 arg5 [V05,T06] ( 4, 4 ) ref -> class-hnd
;* V06 loc0 [V06 ] ( 0, 0 ) long -> zero-ref
;* V07 loc1 [V07 ] ( 0, 0 ) ushort -> zero-ref
;# V08 OutArgs [V08 ] ( 1, 1 ) lclBlk ( 0)
; V09 tmp1 [V09,T07] ( 3, 3 ) ref ->
; V10 tmp2 [V10,T11] ( 2, 2 ) int ->
; V11 tmp3 [V11,T08] ( 3, 3 ) ref ->
; V12 tmp4 [V12,T12] ( 2, 2 ) int ->
; V13 tmp5 [V13,T01] ( 6, 6 ) ref ->
; V14 cse0 [V14,T02] ( 6, 6 ) int ->
; V15 rat0 [V15,T13] ( 2, 1 ) int -> V06.lo(offs=0x00)
; V16 rat1 [V16,T14] ( 2, 1 ) int -> V06.hi(offs=0x04)
; V17 rat2 [V17,T09] ( 3, 3 ) int ->
; Decided to create an EBP based frame for ETW stackwalking (BasicBlock Count)
*************** In lvaAssignFrameOffsets(REGALLOC_FRAME_LAYOUT)
Assign V01 arg1, size=4, stkOffs=-0x30
Assign V02 arg2, size=4, stkOffs=-0x34
Assign V03 arg3, size=4, stkOffs=-0x38
Assign V06 loc0, size=8, stkOffs=-0x44
Assign V07 loc1, size=4, stkOffs=-0x48
Assign V10 tmp2, size=4, stkOffs=-0x4c
Assign V12 tmp4, size=4, stkOffs=-0x50
Assign V14 cse0, size=4, stkOffs=-0x54
Assign V15 rat0, size=4, stkOffs=-0x58
Assign V16 rat1, size=4, stkOffs=-0x5c
Assign V17 rat2, size=4, stkOffs=-0x60
Assign V00 arg0, size=4, stkOffs=-0x64
Assign V09 tmp1, size=4, stkOffs=-0x68
Assign V11 tmp3, size=4, stkOffs=-0x6c
Assign V13 tmp5, size=4, stkOffs=-0x70
compRsvdRegCheck
frame size = 120
compArgSize = 24
maxR11PositiveEncodingOffset = 4095
maxR11NegativeEncodingOffset = 255
maxR11PositiveOffset = 31
maxR11NegativeOffset = 112
maxSPPositiveEncodingOffset = 4095
maxSPLocalsCombinedOffset = 111
Returning false
TUPLE STYLE DUMP BEFORE LSRA
New BlockSet epoch 2, # of blocks (including unused BB00): 7, bitset array size: 1 (short)
LSRA Block Sequence: BB01( 1 ) BB02( 0.50) BB03( 1 ) BB04( 0.50) BB05( 1 ) BB06( 0 )
BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V04(t1*)
N002. t85 = CAST ; t1*
N004. V14(t143); t85
N005. V14(t144)
N007. CNS_INT 0
N008. EQ ; t144
N009. JTRUE
BB02 [004..02C), preds={BB01} succs={BB03}
=====
N000. IL_OFFSET IL offset: 0x4
N001. t30 = CLS_VAR_ADDR Hnd=0x9247f8
N000. t148 = IND ; t30
N000. V17(t164); t148
N000. V17(t165)
N000. V17(t166*)
N000. CNS_INT 31
N000. t168 = RSH ; t166*
N004. V15(t33); t165
N000. V16(t170); t168
N000. IL_OFFSET IL offset: 0xb
N001. t35 = CLS_VAR_ADDR Hnd=0x924808
N000. t149 = IND ; t35
N003. V13(t87); t149
N004. t36 = CNS_INT 0
N005. V13(t88)
N000. t173 = LEA(b+4) ; t88
N006. t91 = IND ; t173
N007. ARR_BOUNDS_CHECK_Rng; t36,t91
N008. V13(t89*)
N000. t174 = LEA(b+8) ; t89*
N011. t37 = IND ; t174
N015. V02(t39); t37
N000. IL_OFFSET IL offset: 0x16
N001. t45 = CLS_VAR_ADDR Hnd=0x9247d8
N000. t150 = IND ; t45
N003. V09(t49); t150
N007. V09(t52)
N000. t175 = PUTARG_REG; t52
N008. t53 = CNS_INT(h) 0x924994 token
N000. t176 = PUTARG_REG; t53
N009. t54 = CNS_INT(h) 0x924B10 token
N000. t177 = PUTARG_REG; t54
N001. t178 = CNS_INT(h) 0xFDA55A0 ftn
N013. t58 = CALL help; t175,t176,t177,t178
N015. V10(t60); t58
N004. V09(t51*)
N000. t179 = PUTARG_REG; t51*
N005. V15(t46*)
N000. t182 = PUTARG_REG; t46*
N000. V16(t171*)
N000. t183 = PUTARG_REG; t171*
N000. t180 = FIELD_LIST; t182,t183
N008. V10(t62*)
N009. CALL ind ; t179,t180,t180,t62*
N000. IL_OFFSET IL offset: 0x21
N001. t65 = CLS_VAR_ADDR Hnd=0x9247d8
N000. t151 = IND ; t65
N003. V11(t69); t151
N007. V11(t72)
N000. t184 = PUTARG_REG; t72
N008. t73 = CNS_INT(h) 0x924994 token
N000. t185 = PUTARG_REG; t73
N009. t74 = CNS_INT(h) 0x924B74 token
N000. t186 = PUTARG_REG; t74
N001. t187 = CNS_INT(h) 0xFDA55A0 ftn
N013. t78 = CALL help; t184,t185,t186,t187
N015. V12(t80); t78
N004. V11(t71*)
N000. t188 = PUTARG_REG; t71*
N005. V02(t66*)
N000. t189 = PUTARG_REG; t66*
N008. V12(t82*)
N009. CALL ind ; t188,t189,t82*
BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
=====
N000. IL_OFFSET IL offset: 0x2c
N001. V14(t146*)
N002. CNS_INT 0
N003. NE ; t146*
N004. JTRUE
BB04 [030..034), preds={BB03} succs={BB05}
=====
N000. IL_OFFSET IL offset: 0x30
N001. t24 = CNS_INT 0
N002. V00(t23*)
N000. t190 = LEA(b+4) ; t23*
N003. t123 = IND ; t190
N004. ARR_BOUNDS_CHECK_Rng; t24,t123
BB05 [034..03B) (return), preds={BB03,BB04} succs={}
=====
N000. IL_OFFSET IL offset: 0x34
N001. t14 = CNS_INT 0
N002. V05(t13)
N000. t192 = LEA(b+4) ; t13
N003. t134 = IND ; t192
N004. ARR_BOUNDS_CHECK_Rng; t14,t134
N005. V05(t132*)
N000. t193 = LEA(b+8) ; t132*
N010. V03(t15*)
N000. STOREIND ; t193,t15*
N000. IL_OFFSET IL offset: 0x39
N001. V01(t19*)
N002. t141 = CAST ; t19*
N003. RETURN ; t141
BB06 [???..???) (throw), preds={} succs={}
=====
N001. t194 = CNS_INT(h) 0xFDA7BB0 ftn
N001. CALL help; t194
buildIntervals second part ========
Int arg V00 in reg r0
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[r0] minReg=1 fixed>
Int arg V03 in reg r3
<RefPosition #1 @0 RefTypeParamDef <Ivl:3 V03> BB00 regmask=[r3] minReg=1 fixed>
Int arg V02 in reg r2
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r2] minReg=1 fixed>
Int arg V01 in reg r1
<RefPosition #3 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[r1] minReg=1 fixed>
<RefPosition #4 @0 RefTypeParamDef <Ivl:5 V05> BB00 regmask=[allInt] minReg=1>
<RefPosition #5 @0 RefTypeParamDef <Ivl:4 V04> BB00 regmask=[allInt] minReg=1>
NEW BLOCK BB01
<RefPosition #6 @1 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N003 ( 8, 8) [000005] ------------- * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N005 ( 2, 2) [000001] ------------- * LCL_VAR int V04 arg4 u:2 NA (last use) REG NA $140
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N007 ( 3, 3) [000085] ----------S-- * CAST int <- bool <- int REG NA $200
<RefPosition #7 @7 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 15: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #8 @8 RefTypeDef <Ivl:15> CAST BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N007.t85. CAST }
N009 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0 NA REG NA
<RefPosition #9 @9 RefTypeUse <Ivl:15> BB01 regmask=[allInt] minReg=1 last>
Assigning related <L11> to <I15>
<RefPosition #10 @10 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N011 ( 1, 1) [000144] ------------- * LCL_VAR int V14 cse0 NA REG NA $200
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N013 ( 1, 1) [000002] -c----------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N015 ( 6, 6) [000003] J------N--S-- * EQ void REG NA $201
<RefPosition #11 @15 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N017 ( 8, 8) [000004] ------------- * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 1, liveout={V00 V01 V03 V05 V14}
==============================
use: {V04}
def: {V14}
NEW BLOCK BB02
Setting BB02 as the predecessor for determining incoming variable registers of BB01
<RefPosition #12 @19 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N021 ( 14, 17) [000034] ------------- * IL_OFFSET void IL offset: 0x4 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N023 ( 6, 10) [000030] ----G-------- * CLS_VAR_ADDR byref Hnd=0x9247f8 REG NA
Interval 16: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #13 @24 RefTypeDef <Ivl:16> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N023.t30. CLS_VAR_ADDR }
N025 (???,???) [000148] ----G-------- * IND int REG NA
<RefPosition #14 @25 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last>
Interval 17: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #15 @26 RefTypeDef <Ivl:17> IND BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N025.t148. IND }
N027 (???,???) [000164] DA--G-------- * STORE_LCL_VAR int V17 rat2 NA REG NA
<RefPosition #16 @27 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L14> to <I17>
<RefPosition #17 @28 RefTypeDef <Ivl:14 V17> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N029 (???,???) [000165] ------------- * LCL_VAR int V17 rat2 NA REG NA
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N031 (???,???) [000166] ------------- * LCL_VAR int V17 rat2 NA (last use) REG NA
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N033 (???,???) [000167] -c----------- * CNS_INT int 31 REG NA
Contained
DefList: { }
N035 (???,???) [000168] ------------- * RSH int REG NA
<RefPosition #18 @35 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 18: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #19 @36 RefTypeDef <Ivl:18> RSH BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N035.t168. RSH }
N037 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR int V15 rat0 NA REG NA
<RefPosition #20 @37 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @38 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { N035.t168. RSH }
N039 (???,???) [000170] D------------ * STORE_LCL_VAR int V16 rat1 NA REG NA
<RefPosition #22 @39 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L13> to <I18>
<RefPosition #23 @40 RefTypeDef <Ivl:13 V16> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N041 ( 19, 24) [000040] ------------- * IL_OFFSET void IL offset: 0xb REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N043 ( 6, 10) [000035] ----G-------- * CLS_VAR_ADDR byref Hnd=0x924808 REG NA
Interval 19: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #24 @44 RefTypeDef <Ivl:19> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N043.t35. CLS_VAR_ADDR }
N045 (???,???) [000149] ----G-------- * IND ref REG NA
<RefPosition #25 @45 RefTypeUse <Ivl:19> BB02 regmask=[allInt] minReg=1 last>
Interval 20: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #26 @46 RefTypeDef <Ivl:20> IND BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N045.t149. IND }
N047 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3 NA REG NA
<RefPosition #27 @47 RefTypeUse <Ivl:20> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L10> to <I20>
<RefPosition #28 @48 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N049 ( 1, 1) [000036] ------------- * CNS_INT int 0 REG NA $40
Interval 21: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #29 @50 RefTypeDef <Ivl:21> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N049.t36. CNS_INT }
N051 ( 1, 1) [000088] ------------- * LCL_VAR ref V13 tmp5 u:3 NA REG NA <l:$340, c:$380>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N049.t36. CNS_INT }
N053 (???,???) [000173] -c----------- * LEA(b+4) byref REG NA
Contained
DefList: { N049.t36. CNS_INT }
N055 ( 3, 3) [000091] ---X--------- * IND int REG NA <l:$3c1, c:$3c0>
<RefPosition #30 @55 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 22: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #31 @56 RefTypeDef <Ivl:22> IND BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N049.t36. CNS_INT; N055.t91. IND }
N057 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
<RefPosition #32 @57 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #33 @57 RefTypeUse <Ivl:22> BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=0
DefList: { }
N059 ( 1, 1) [000089] ------------- * LCL_VAR ref V13 tmp5 u:3 NA (last use) REG NA <l:$340, c:$380>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N061 (???,???) [000174] -c----------- * LEA(b+8) byref REG NA
Contained
DefList: { }
N063 ( 5, 3) [000037] a---GO------- * IND ushort REG NA <l:$203, c:$4c0>
<RefPosition #34 @63 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 23: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #35 @64 RefTypeDef <Ivl:23> IND BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N063.t37. IND }
N065 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3 NA REG NA
<RefPosition #36 @65 RefTypeUse <Ivl:23> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L2> to <I23>
<RefPosition #37 @66 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N067 ( 6, 10) [000050] ------------- * IL_OFFSET void IL offset: 0x16 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N069 ( 6, 10) [000045] ----G-------- * CLS_VAR_ADDR byref Hnd=0x9247d8 REG NA
Interval 24: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #38 @70 RefTypeDef <Ivl:24> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N069.t45. CLS_VAR_ADDR }
N071 (???,???) [000150] ----G-------- * IND ref REG NA
<RefPosition #39 @71 RefTypeUse <Ivl:24> BB02 regmask=[allInt] minReg=1 last>
Interval 25: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #40 @72 RefTypeDef <Ivl:25> IND BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N071.t150. IND }
N073 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3 NA REG NA
<RefPosition #41 @73 RefTypeUse <Ivl:25> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L6> to <I25>
<RefPosition #42 @74 RefTypeDef <Ivl:6 V09> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N075 ( 1, 1) [000052] ------------- * LCL_VAR ref V09 tmp1 u:3 NA REG NA <l:$349, c:$382>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N077 (???,???) [000175] ------------- * PUTARG_REG ref REG r0
<RefPosition #43 @77 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #44 @77 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 26: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #45 @78 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #46 @78 RefTypeDef <Ivl:26> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
Assigning related <L6> to <I26>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N077.t175. PUTARG_REG }
N079 ( 3, 7) [000053] ------------- * CNS_INT(h) int 0x924994 token REG NA $244
Interval 27: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #47 @80 RefTypeDef <Ivl:27> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N077.t175. PUTARG_REG; N079.t53. CNS_INT }
N081 (???,???) [000176] ------------- * PUTARG_REG int REG r1
<RefPosition #48 @81 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #49 @81 RefTypeUse <Ivl:27> BB02 regmask=[r1] minReg=1 last fixed>
Interval 28: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #50 @82 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #51 @82 RefTypeDef <Ivl:28> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N077.t175. PUTARG_REG; N081.t176. PUTARG_REG }
N083 ( 3, 7) [000054] ------------- * CNS_INT(h) int 0x924B10 token REG NA $245
Interval 29: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #52 @84 RefTypeDef <Ivl:29> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N077.t175. PUTARG_REG; N081.t176. PUTARG_REG; N083.t54. CNS_INT }
N085 (???,???) [000177] ------------- * PUTARG_REG int REG r2
<RefPosition #53 @85 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #54 @85 RefTypeUse <Ivl:29> BB02 regmask=[r2] minReg=1 last fixed>
Interval 30: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #55 @86 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #56 @86 RefTypeDef <Ivl:30> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N077.t175. PUTARG_REG; N081.t176. PUTARG_REG; N085.t177. PUTARG_REG }
N087 ( 3, 7) [000178] ------------- * CNS_INT(h) int 0xFDA55A0 ftn REG NA
Interval 31: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #57 @88 RefTypeDef <Ivl:31> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N077.t175. PUTARG_REG; N081.t176. PUTARG_REG; N085.t177. PUTARG_REG; N087.t178. CNS_INT }
N089 ( 23, 28) [000058] --CXG-------- * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
<RefPosition #58 @89 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #59 @89 RefTypeUse <Ivl:26> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #60 @89 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #61 @89 RefTypeUse <Ivl:28> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #62 @89 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #63 @89 RefTypeUse <Ivl:30> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #64 @89 RefTypeUse <Ivl:31> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #65 @90 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #66 @90 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #67 @90 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #68 @90 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #69 @90 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1>
<RefPosition #70 @90 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1>
<RefPosition #71 @90 RefTypeKill <Reg:f0 > BB02 regmask=[f0] minReg=1>
<RefPosition #72 @90 RefTypeKill <Reg:f1 > BB02 regmask=[f1] minReg=1>
<RefPosition #73 @90 RefTypeKill <Reg:f2 > BB02 regmask=[f2] minReg=1>
<RefPosition #74 @90 RefTypeKill <Reg:f3 > BB02 regmask=[f3] minReg=1>
<RefPosition #75 @90 RefTypeKill <Reg:f4 > BB02 regmask=[f4] minReg=1>
<RefPosition #76 @90 RefTypeKill <Reg:f5 > BB02 regmask=[f5] minReg=1>
<RefPosition #77 @90 RefTypeKill <Reg:f6 > BB02 regmask=[f6] minReg=1>
<RefPosition #78 @90 RefTypeKill <Reg:f7 > BB02 regmask=[f7] minReg=1>
<RefPosition #79 @90 RefTypeKill <Reg:f8 > BB02 regmask=[f8] minReg=1>
<RefPosition #80 @90 RefTypeKill <Reg:f9 > BB02 regmask=[f9] minReg=1>
<RefPosition #81 @90 RefTypeKill <Reg:f10> BB02 regmask=[f10] minReg=1>
<RefPosition #82 @90 RefTypeKill <Reg:f11> BB02 regmask=[f11] minReg=1>
<RefPosition #83 @90 RefTypeKill <Reg:f12> BB02 regmask=[f12] minReg=1>
<RefPosition #84 @90 RefTypeKill <Reg:f13> BB02 regmask=[f13] minReg=1>
<RefPosition #85 @90 RefTypeKill <Reg:f14> BB02 regmask=[f14] minReg=1>
<RefPosition #86 @90 RefTypeKill <Reg:f15> BB02 regmask=[f15] minReg=1>
Interval 32: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #87 @90 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #88 @90 RefTypeDef <Ivl:32> CALL BB02 regmask=[r0] minReg=1 fixed>
+<TreeNodeInfo 1=4 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 4 produce=1
DefList: { N089.t58. CALL }
N091 ( 27, 31) [000060] DA-XG-------- * STORE_LCL_VAR int V10 tmp2 d:3 NA REG NA
<RefPosition #89 @91 RefTypeUse <Ivl:32> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L7> to <I32>
<RefPosition #90 @92 RefTypeDef <Ivl:7 V10> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N093 ( 1, 1) [000051] ------------- * LCL_VAR ref V09 tmp1 u:3 NA (last use) REG NA <l:$349, c:$382>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N095 (???,???) [000179] ------------- * PUTARG_REG ref REG r0
<RefPosition #91 @95 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #92 @95 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
Interval 33: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #93 @96 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #94 @96 RefTypeDef <Ivl:33> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N095.t179. PUTARG_REG }
N097 ( 3, 2) [000046] ------------- * LCL_VAR int V15 rat0 NA (last use) REG NA <l:$2c1, c:$2c0>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N095.t179. PUTARG_REG }
N099 (???,???) [000182] ------------- * PUTARG_REG int REG r2
<RefPosition #95 @99 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #96 @99 RefTypeUse <Ivl:12 V15> LCL_VAR BB02 regmask=[r2] minReg=1 last fixed>
Interval 34: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #97 @100 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #98 @100 RefTypeDef <Ivl:34> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N095.t179. PUTARG_REG; N099.t182. PUTARG_REG }
N101 (???,???) [000171] ------------- * LCL_VAR int V16 rat1 NA (last use) REG NA
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N095.t179. PUTARG_REG; N099.t182. PUTARG_REG }
N103 (???,???) [000183] ------------- * PUTARG_REG int REG r3
<RefPosition #99 @103 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #100 @103 RefTypeUse <Ivl:13 V16> LCL_VAR BB02 regmask=[r3] minReg=1 last fixed>
Interval 35: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #101 @104 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #102 @104 RefTypeDef <Ivl:35> PUTARG_REG BB02 regmask=[r3] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N095.t179. PUTARG_REG; N099.t182. PUTARG_REG; N103.t183. PUTARG_REG }
N105 (???,???) [000180] Hc----------- * FIELD_LIST int int at offset 0 REG NA
Contained
DefList: { N095.t179. PUTARG_REG; N099.t182. PUTARG_REG; N103.t183. PUTARG_REG }
N107 ( 3, 2) [000062] ------------- * LCL_VAR int V10 tmp2 u:3 NA (last use) REG NA $283
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N095.t179. PUTARG_REG; N099.t182. PUTARG_REG; N103.t183. PUTARG_REG }
N109 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
<RefPosition #103 @109 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #104 @109 RefTypeUse <Ivl:33> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #105 @109 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #106 @109 RefTypeUse <Ivl:34> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #107 @109 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #108 @109 RefTypeUse <Ivl:35> BB02 regmask=[r3] minReg=1 last fixed>
<RefPosition #109 @109 RefTypeUse <Ivl:7 V10> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #110 @110 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #111 @110 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #112 @110 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #113 @110 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #114 @110 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1>
<RefPosition #115 @110 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1>
+<TreeNodeInfo 0=4 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 4 produce=0
DefList: { }
N111 ( 6, 10) [000070] ------------- * IL_OFFSET void IL offset: 0x21 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N113 ( 6, 10) [000065] ----G-------- * CLS_VAR_ADDR byref Hnd=0x9247d8 REG NA
Interval 36: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #116 @114 RefTypeDef <Ivl:36> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N113.t65. CLS_VAR_ADDR }
N115 (???,???) [000151] ----G-------- * IND ref REG NA
<RefPosition #117 @115 RefTypeUse <Ivl:36> BB02 regmask=[allInt] minReg=1 last>
Interval 37: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #118 @116 RefTypeDef <Ivl:37> IND BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N115.t151. IND }
N117 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3 NA REG NA
<RefPosition #119 @117 RefTypeUse <Ivl:37> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L8> to <I37>
<RefPosition #120 @118 RefTypeDef <Ivl:8 V11> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N119 ( 1, 1) [000072] ------------- * LCL_VAR ref V11 tmp3 u:3 NA REG NA <l:$34b, c:$388>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N121 (???,???) [000184] ------------- * PUTARG_REG ref REG r0
<RefPosition #121 @121 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #122 @121 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
Setting putarg_reg as a pass-through of a non-last use lclVar
Interval 38: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #123 @122 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #124 @122 RefTypeDef <Ivl:38> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
Assigning related <L8> to <I38>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N121.t184. PUTARG_REG }
N123 ( 3, 7) [000073] ------------- * CNS_INT(h) int 0x924994 token REG NA $244
Interval 39: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #125 @124 RefTypeDef <Ivl:39> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N121.t184. PUTARG_REG; N123.t73. CNS_INT }
N125 (???,???) [000185] ------------- * PUTARG_REG int REG r1
<RefPosition #126 @125 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #127 @125 RefTypeUse <Ivl:39> BB02 regmask=[r1] minReg=1 last fixed>
Interval 40: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #128 @126 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #129 @126 RefTypeDef <Ivl:40> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N121.t184. PUTARG_REG; N125.t185. PUTARG_REG }
N127 ( 3, 7) [000074] ------------- * CNS_INT(h) int 0x924B74 token REG NA $246
Interval 41: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #130 @128 RefTypeDef <Ivl:41> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N121.t184. PUTARG_REG; N125.t185. PUTARG_REG; N127.t74. CNS_INT }
N129 (???,???) [000186] ------------- * PUTARG_REG int REG r2
<RefPosition #131 @129 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #132 @129 RefTypeUse <Ivl:41> BB02 regmask=[r2] minReg=1 last fixed>
Interval 42: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #133 @130 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #134 @130 RefTypeDef <Ivl:42> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N121.t184. PUTARG_REG; N125.t185. PUTARG_REG; N129.t186. PUTARG_REG }
N131 ( 3, 7) [000187] ------------- * CNS_INT(h) int 0xFDA55A0 ftn REG NA
Interval 43: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #135 @132 RefTypeDef <Ivl:43> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N121.t184. PUTARG_REG; N125.t185. PUTARG_REG; N129.t186. PUTARG_REG; N131.t187. CNS_INT }
N133 ( 23, 28) [000078] --CXG-------- * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
<RefPosition #136 @133 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #137 @133 RefTypeUse <Ivl:38> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #138 @133 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #139 @133 RefTypeUse <Ivl:40> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #140 @133 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #141 @133 RefTypeUse <Ivl:42> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #142 @133 RefTypeUse <Ivl:43> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #143 @134 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #144 @134 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #145 @134 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #146 @134 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #147 @134 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1>
<RefPosition #148 @134 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1>
<RefPosition #149 @134 RefTypeKill <Reg:f0 > BB02 regmask=[f0] minReg=1>
<RefPosition #150 @134 RefTypeKill <Reg:f1 > BB02 regmask=[f1] minReg=1>
<RefPosition #151 @134 RefTypeKill <Reg:f2 > BB02 regmask=[f2] minReg=1>
<RefPosition #152 @134 RefTypeKill <Reg:f3 > BB02 regmask=[f3] minReg=1>
<RefPosition #153 @134 RefTypeKill <Reg:f4 > BB02 regmask=[f4] minReg=1>
<RefPosition #154 @134 RefTypeKill <Reg:f5 > BB02 regmask=[f5] minReg=1>
<RefPosition #155 @134 RefTypeKill <Reg:f6 > BB02 regmask=[f6] minReg=1>
<RefPosition #156 @134 RefTypeKill <Reg:f7 > BB02 regmask=[f7] minReg=1>
<RefPosition #157 @134 RefTypeKill <Reg:f8 > BB02 regmask=[f8] minReg=1>
<RefPosition #158 @134 RefTypeKill <Reg:f9 > BB02 regmask=[f9] minReg=1>
<RefPosition #159 @134 RefTypeKill <Reg:f10> BB02 regmask=[f10] minReg=1>
<RefPosition #160 @134 RefTypeKill <Reg:f11> BB02 regmask=[f11] minReg=1>
<RefPosition #161 @134 RefTypeKill <Reg:f12> BB02 regmask=[f12] minReg=1>
<RefPosition #162 @134 RefTypeKill <Reg:f13> BB02 regmask=[f13] minReg=1>
<RefPosition #163 @134 RefTypeKill <Reg:f14> BB02 regmask=[f14] minReg=1>
<RefPosition #164 @134 RefTypeKill <Reg:f15> BB02 regmask=[f15] minReg=1>
Interval 44: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #165 @134 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #166 @134 RefTypeDef <Ivl:44> CALL BB02 regmask=[r0] minReg=1 fixed>
+<TreeNodeInfo 1=4 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 4 produce=1
DefList: { N133.t78. CALL }
N135 ( 27, 31) [000080] DA-XG-------- * STORE_LCL_VAR int V12 tmp4 d:3 NA REG NA
<RefPosition #167 @135 RefTypeUse <Ivl:44> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L9> to <I44>
<RefPosition #168 @136 RefTypeDef <Ivl:9 V12> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N137 ( 1, 1) [000071] ------------- * LCL_VAR ref V11 tmp3 u:3 NA (last use) REG NA <l:$34b, c:$388>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N139 (???,???) [000188] ------------- * PUTARG_REG ref REG r0
<RefPosition #169 @139 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #170 @139 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
Interval 45: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #171 @140 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #172 @140 RefTypeDef <Ivl:45> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N139.t188. PUTARG_REG }
N141 ( 2, 2) [000066] ------------- * LCL_VAR int V02 arg2 u:3 NA (last use) REG NA <l:$203, c:$4c0>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N139.t188. PUTARG_REG }
N143 (???,???) [000189] ------------- * PUTARG_REG int REG r1
<RefPosition #173 @143 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #174 @143 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[r1] minReg=1 last fixed>
Interval 46: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #175 @144 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #176 @144 RefTypeDef <Ivl:46> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N139.t188. PUTARG_REG; N143.t189. PUTARG_REG }
N145 ( 3, 2) [000082] ------------- * LCL_VAR int V12 tmp4 u:3 NA (last use) REG NA $287
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N139.t188. PUTARG_REG; N143.t189. PUTARG_REG }
N147 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
<RefPosition #177 @147 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #178 @147 RefTypeUse <Ivl:45> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #179 @147 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #180 @147 RefTypeUse <Ivl:46> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #181 @147 RefTypeUse <Ivl:9 V12> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #182 @148 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #183 @148 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #184 @148 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #185 @148 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #186 @148 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1>
<RefPosition #187 @148 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1>
+<TreeNodeInfo 0=3 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 3 produce=0
CHECKING LAST USES for block 2, liveout={V00 V01 V03 V05 V14}
==============================
use: {}
def: {V02 V09 V10 V11 V12 V13 V15 V16 V17}
NEW BLOCK BB03
Setting BB03 as the predecessor for determining incoming variable registers of BB01
<RefPosition #188 @149 RefTypeBB BB03 regmask=[] minReg=1>
DefList: { }
N151 ( 5, 5) [000011] ------------- * IL_OFFSET void IL offset: 0x2c REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N153 ( 1, 1) [000146] ------------- * LCL_VAR int V14 cse0 NA (last use) REG NA $200
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N155 ( 1, 1) [000008] -c----------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N157 ( 3, 3) [000009] J------N--S-- * NE void REG NA $207
<RefPosition #189 @157 RefTypeUse <Ivl:11 V14> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N159 ( 5, 5) [000010] ------------- * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 3, liveout={V00 V01 V03 V05}
==============================
use: {V14}
def: {}
NEW BLOCK BB04
Setting BB04 as the predecessor for determining incoming variable registers of BB03
<RefPosition #190 @161 RefTypeBB BB04 regmask=[] minReg=1>
DefList: { }
N163 ( 13, 14) [000028] ------------- * IL_OFFSET void IL offset: 0x30 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N165 ( 1, 1) [000024] ------------- * CNS_INT int 0 REG NA $40
Interval 47: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #191 @166 RefTypeDef <Ivl:47> CNS_INT BB04 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N165.t24. CNS_INT }
N167 ( 1, 1) [000023] ------------- * LCL_VAR ref V00 arg0 u:2 NA (last use) REG NA $80
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N165.t24. CNS_INT }
N169 (???,???) [000190] -c----------- * LEA(b+4) byref REG NA
Contained
DefList: { N165.t24. CNS_INT }
N171 ( 3, 3) [000123] ---X--------- * IND int REG NA $3c2
<RefPosition #192 @171 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
Interval 48: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #193 @172 RefTypeDef <Ivl:48> IND BB04 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N165.t24. CNS_INT; N171.t123. IND }
N173 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
<RefPosition #194 @173 RefTypeUse <Ivl:47> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #195 @173 RefTypeUse <Ivl:48> BB04 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=0
CHECKING LAST USES for block 4, liveout={V01 V03 V05}
==============================
use: {V00}
def: {}
NEW BLOCK BB05
Setting BB05 as the predecessor for determining incoming variable registers of BB03
<RefPosition #196 @175 RefTypeBB BB05 regmask=[] minReg=1>
DefList: { }
N177 ( 16, 17) [000018] ------------- * IL_OFFSET void IL offset: 0x34 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N179 ( 1, 1) [000014] ------------- * CNS_INT int 0 REG NA $40
Interval 49: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #197 @180 RefTypeDef <Ivl:49> CNS_INT BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N179.t14. CNS_INT }
N181 ( 1, 1) [000013] ------------- * LCL_VAR ref V05 arg5 u:2 NA REG NA $81
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N179.t14. CNS_INT }
N183 (???,???) [000192] -c----------- * LEA(b+4) byref REG NA
Contained
DefList: { N179.t14. CNS_INT }
N185 ( 3, 3) [000134] ---X--------- * IND int REG NA $3c3
<RefPosition #198 @185 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 50: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #199 @186 RefTypeDef <Ivl:50> IND BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N179.t14. CNS_INT; N185.t134. IND }
N187 ( 8, 11) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
<RefPosition #200 @187 RefTypeUse <Ivl:49> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #201 @187 RefTypeUse <Ivl:50> BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=0
DefList: { }
N189 ( 1, 1) [000132] ------------- * LCL_VAR ref V05 arg5 u:2 NA (last use) REG NA $81
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N191 (???,???) [000193] -c----------- * LEA(b+8) byref REG NA
Contained
DefList: { }
N193 ( 2, 2) [000015] ------------- * LCL_VAR int V03 arg3 u:2 NA (last use) REG NA $100
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N195 (???,???) [000152] -A-XGO------- * STOREIND byte REG NA
<RefPosition #202 @195 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #203 @195 RefTypeUse <Ivl:3 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=0
DefList: { }
N197 ( 4, 4) [000021] ------------- * IL_OFFSET void IL offset: 0x39 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N199 ( 2, 2) [000019] ------------- * LCL_VAR int V01 arg1 u:2 NA (last use) REG NA $c0
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N201 ( 3, 3) [000141] ------------- * CAST int <- ushort <- int REG NA $20c
<RefPosition #204 @201 RefTypeUse <Ivl:1 V01> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 51: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #205 @202 RefTypeDef <Ivl:51> CAST BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N201.t141. CAST }
N203 ( 4, 4) [000020] ------------- * RETURN int REG NA $28a
<RefPosition #206 @203 RefTypeFixedReg <Reg:r0 > BB05 regmask=[r0] minReg=1>
<RefPosition #207 @203 RefTypeUse <Ivl:51> BB05 regmask=[r0] minReg=1 last fixed>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
CHECKING LAST USES for block 5, liveout={}
==============================
use: {V01 V03 V05}
def: {}
NEW BLOCK BB06
No allocated predecessor;
Setting BB06 as the predecessor for determining incoming variable registers of BB05
<RefPosition #208 @205 RefTypeBB BB06 regmask=[] minReg=1>
DefList: { }
N207 ( 3, 7) [000194] ------------- * CNS_INT(h) int 0xFDA7BB0 ftn REG NA
Interval 52: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #209 @208 RefTypeDef <Ivl:52> CNS_INT BB06 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N207.t194. CNS_INT }
N209 ( 16, 10) [000155] --CXG-------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
<RefPosition #210 @209 RefTypeUse <Ivl:52> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #211 @210 RefTypeKill <Reg:r0 > BB06 regmask=[r0] minReg=1>
<RefPosition #212 @210 RefTypeKill <Reg:r1 > BB06 regmask=[r1] minReg=1>
<RefPosition #213 @210 RefTypeKill <Reg:r2 > BB06 regmask=[r2] minReg=1>
<RefPosition #214 @210 RefTypeKill <Reg:r3 > BB06 regmask=[r3] minReg=1>
<RefPosition #215 @210 RefTypeKill <Reg:r12> BB06 regmask=[r12] minReg=1>
<RefPosition #216 @210 RefTypeKill <Reg:lr > BB06 regmask=[lr] minReg=1>
<RefPosition #217 @210 RefTypeKill <Reg:f0 > BB06 regmask=[f0] minReg=1>
<RefPosition #218 @210 RefTypeKill <Reg:f1 > BB06 regmask=[f1] minReg=1>
<RefPosition #219 @210 RefTypeKill <Reg:f2 > BB06 regmask=[f2] minReg=1>
<RefPosition #220 @210 RefTypeKill <Reg:f3 > BB06 regmask=[f3] minReg=1>
<RefPosition #221 @210 RefTypeKill <Reg:f4 > BB06 regmask=[f4] minReg=1>
<RefPosition #222 @210 RefTypeKill <Reg:f5 > BB06 regmask=[f5] minReg=1>
<RefPosition #223 @210 RefTypeKill <Reg:f6 > BB06 regmask=[f6] minReg=1>
<RefPosition #224 @210 RefTypeKill <Reg:f7 > BB06 regmask=[f7] minReg=1>
<RefPosition #225 @210 RefTypeKill <Reg:f8 > BB06 regmask=[f8] minReg=1>
<RefPosition #226 @210 RefTypeKill <Reg:f9 > BB06 regmask=[f9] minReg=1>
<RefPosition #227 @210 RefTypeKill <Reg:f10> BB06 regmask=[f10] minReg=1>
<RefPosition #228 @210 RefTypeKill <Reg:f11> BB06 regmask=[f11] minReg=1>
<RefPosition #229 @210 RefTypeKill <Reg:f12> BB06 regmask=[f12] minReg=1>
<RefPosition #230 @210 RefTypeKill <Reg:f13> BB06 regmask=[f13] minReg=1>
<RefPosition #231 @210 RefTypeKill <Reg:f14> BB06 regmask=[f14] minReg=1>
<RefPosition #232 @210 RefTypeKill <Reg:f15> BB06 regmask=[f15] minReg=1>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
CHECKING LAST USES for block 6, liveout={}
==============================
use: {}
def: {}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) RefPositions {#0@0 #192@171} physReg:r0 Preferences=[r4-r10]
Interval 1: (V01) RefPositions {#3@0 #204@201} physReg:r1 Preferences=[r4-r10]
Interval 2: (V02) RefPositions {#2@0 #37@66 #174@143} physReg:r2 Preferences=[r4-r10]
Interval 3: (V03) RefPositions {#1@0 #203@195} physReg:r3 Preferences=[r4-r10]
Interval 4: (V04) RefPositions {#5@0 #7@7} physReg:NA Preferences=[allInt]
Interval 5: (V05) RefPositions {#4@0 #198@185 #202@195} physReg:NA Preferences=[r4-r10]
Interval 6: (V09) RefPositions {#42@74 #44@77 #92@95} physReg:NA Preferences=[r4-r10]
Interval 7: (V10) RefPositions {#90@92 #109@109} physReg:NA Preferences=[allInt]
Interval 8: (V11) RefPositions {#120@118 #122@121 #170@139} physReg:NA Preferences=[r4-r10]
Interval 9: (V12) RefPositions {#168@136 #181@147} physReg:NA Preferences=[allInt]
Interval 10: (V13) RefPositions {#28@48 #30@55 #34@63} physReg:NA Preferences=[allInt]
Interval 11: (V14) RefPositions {#10@10 #11@15 #189@157} physReg:NA Preferences=[r4-r10]
Interval 12: (V15) (struct) RefPositions {#21@38 #96@99} physReg:NA Preferences=[r4-r10]
Interval 13: (V16) (struct) RefPositions {#23@40 #100@103} physReg:NA Preferences=[r4-r10]
Interval 14: (V17) RefPositions {#17@28 #18@35 #20@37} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#8@8 #9@9} physReg:NA Preferences=[allInt] RelatedInterval <L11>[008D0934]
Interval 16: RefPositions {#13@24 #14@25} physReg:NA Preferences=[allInt]
Interval 17: RefPositions {#15@26 #16@27} physReg:NA Preferences=[allInt] RelatedInterval <L14>[008D09DC]
Interval 18: RefPositions {#19@36 #22@39} physReg:NA Preferences=[allInt] RelatedInterval <L13>[008D09A4]
Interval 19: RefPositions {#24@44 #25@45} physReg:NA Preferences=[allInt]
Interval 20: RefPositions {#26@46 #27@47} physReg:NA Preferences=[allInt] RelatedInterval <L10>[008D08FC]
Interval 21: (constant) RefPositions {#29@50 #32@57} physReg:NA Preferences=[allInt]
Interval 22: RefPositions {#31@56 #33@57} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#35@64 #36@65} physReg:NA Preferences=[allInt] RelatedInterval <L2>[008D073C]
Interval 24: RefPositions {#38@70 #39@71} physReg:NA Preferences=[allInt]
Interval 25: RefPositions {#40@72 #41@73} physReg:NA Preferences=[allInt] RelatedInterval <L6>[008D081C]
Interval 26: (specialPutArg) RefPositions {#46@78 #59@89} physReg:NA Preferences=[r0] RelatedInterval <L6>[008D081C]
Interval 27: (constant) RefPositions {#47@80 #49@81} physReg:NA Preferences=[r1]
Interval 28: RefPositions {#51@82 #61@89} physReg:NA Preferences=[r1]
Interval 29: (constant) RefPositions {#52@84 #54@85} physReg:NA Preferences=[r2]
Interval 30: RefPositions {#56@86 #63@89} physReg:NA Preferences=[r2]
Interval 31: (constant) RefPositions {#57@88 #64@89} physReg:NA Preferences=[allInt]
Interval 32: RefPositions {#88@90 #89@91} physReg:NA Preferences=[r0] RelatedInterval <L7>[008D0854]
Interval 33: RefPositions {#94@96 #104@109} physReg:NA Preferences=[r0]
Interval 34: RefPositions {#98@100 #106@109} physReg:NA Preferences=[r2]
Interval 35: RefPositions {#102@104 #108@109} physReg:NA Preferences=[r3]
Interval 36: RefPositions {#116@114 #117@115} physReg:NA Preferences=[allInt]
Interval 37: RefPositions {#118@116 #119@117} physReg:NA Preferences=[allInt] RelatedInterval <L8>[008D088C]
Interval 38: (specialPutArg) RefPositions {#124@122 #137@133} physReg:NA Preferences=[r0] RelatedInterval <L8>[008D088C]
Interval 39: (constant) RefPositions {#125@124 #127@125} physReg:NA Preferences=[r1]
Interval 40: RefPositions {#129@126 #139@133} physReg:NA Preferences=[r1]
Interval 41: (constant) RefPositions {#130@128 #132@129} physReg:NA Preferences=[r2]
Interval 42: RefPositions {#134@130 #141@133} physReg:NA Preferences=[r2]
Interval 43: (constant) RefPositions {#135@132 #142@133} physReg:NA Preferences=[allInt]
Interval 44: RefPositions {#166@134 #167@135} physReg:NA Preferences=[r0] RelatedInterval <L9>[008D08C4]
Interval 45: RefPositions {#172@140 #178@147} physReg:NA Preferences=[r0]
Interval 46: RefPositions {#176@144 #180@147} physReg:NA Preferences=[r1]
Interval 47: (constant) RefPositions {#191@166 #194@173} physReg:NA Preferences=[allInt]
Interval 48: RefPositions {#193@172 #195@173} physReg:NA Preferences=[allInt]
Interval 49: (constant) RefPositions {#197@180 #200@187} physReg:NA Preferences=[allInt]
Interval 50: RefPositions {#199@186 #201@187} physReg:NA Preferences=[allInt]
Interval 51: RefPositions {#205@202 #207@203} physReg:NA Preferences=[r0]
Interval 52: (constant) RefPositions {#209@208 #210@209} physReg:NA Preferences=[allInt]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[r0] minReg=1 fixed>
<RefPosition #1 @0 RefTypeParamDef <Ivl:3 V03> BB00 regmask=[r3] minReg=1 fixed>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r2] minReg=1 fixed>
<RefPosition #3 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[r1] minReg=1 fixed>
<RefPosition #4 @0 RefTypeParamDef <Ivl:5 V05> BB00 regmask=[allInt] minReg=1>
<RefPosition #5 @0 RefTypeParamDef <Ivl:4 V04> BB00 regmask=[allInt] minReg=1>
<RefPosition #6 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #7 @7 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @8 RefTypeDef <Ivl:15> CAST BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @9 RefTypeUse <Ivl:15> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #10 @10 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @15 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #12 @19 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #13 @24 RefTypeDef <Ivl:16> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
<RefPosition #14 @25 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #15 @26 RefTypeDef <Ivl:17> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #16 @27 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #17 @28 RefTypeDef <Ivl:14 V17> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #18 @35 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #19 @36 RefTypeDef <Ivl:18> RSH BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @37 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @38 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #22 @39 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @40 RefTypeDef <Ivl:13 V16> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @44 RefTypeDef <Ivl:19> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
<RefPosition #25 @45 RefTypeUse <Ivl:19> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #26 @46 RefTypeDef <Ivl:20> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @47 RefTypeUse <Ivl:20> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #28 @48 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #29 @50 RefTypeDef <Ivl:21> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #30 @55 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #31 @56 RefTypeDef <Ivl:22> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @57 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #33 @57 RefTypeUse <Ivl:22> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #34 @63 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #35 @64 RefTypeDef <Ivl:23> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #36 @65 RefTypeUse <Ivl:23> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #37 @66 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #38 @70 RefTypeDef <Ivl:24> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
<RefPosition #39 @71 RefTypeUse <Ivl:24> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #40 @72 RefTypeDef <Ivl:25> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #41 @73 RefTypeUse <Ivl:25> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #42 @74 RefTypeDef <Ivl:6 V09> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #43 @77 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #44 @77 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #45 @78 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #46 @78 RefTypeDef <Ivl:26> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #47 @80 RefTypeDef <Ivl:27> CNS_INT BB02 regmask=[r1] minReg=1>
<RefPosition #48 @81 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #49 @81 RefTypeUse <Ivl:27> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #50 @82 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #51 @82 RefTypeDef <Ivl:28> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
<RefPosition #52 @84 RefTypeDef <Ivl:29> CNS_INT BB02 regmask=[r2] minReg=1>
<RefPosition #53 @85 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #54 @85 RefTypeUse <Ivl:29> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #55 @86 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #56 @86 RefTypeDef <Ivl:30> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
<RefPosition #57 @88 RefTypeDef <Ivl:31> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #58 @89 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #59 @89 RefTypeUse <Ivl:26> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #60 @89 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #61 @89 RefTypeUse <Ivl:28> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #62 @89 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #63 @89 RefTypeUse <Ivl:30> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #64 @89 RefTypeUse <Ivl:31> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #65 @90 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #66 @90 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #67 @90 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #68 @90 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #69 @90 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #70 @90 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #71 @90 RefTypeKill <Reg:f0 > BB02 regmask=[f0] minReg=1 last>
<RefPosition #72 @90 RefTypeKill <Reg:f1 > BB02 regmask=[f1] minReg=1 last>
<RefPosition #73 @90 RefTypeKill <Reg:f2 > BB02 regmask=[f2] minReg=1 last>
<RefPosition #74 @90 RefTypeKill <Reg:f3 > BB02 regmask=[f3] minReg=1 last>
<RefPosition #75 @90 RefTypeKill <Reg:f4 > BB02 regmask=[f4] minReg=1 last>
<RefPosition #76 @90 RefTypeKill <Reg:f5 > BB02 regmask=[f5] minReg=1 last>
<RefPosition #77 @90 RefTypeKill <Reg:f6 > BB02 regmask=[f6] minReg=1 last>
<RefPosition #78 @90 RefTypeKill <Reg:f7 > BB02 regmask=[f7] minReg=1 last>
<RefPosition #79 @90 RefTypeKill <Reg:f8 > BB02 regmask=[f8] minReg=1 last>
<RefPosition #80 @90 RefTypeKill <Reg:f9 > BB02 regmask=[f9] minReg=1 last>
<RefPosition #81 @90 RefTypeKill <Reg:f10> BB02 regmask=[f10] minReg=1 last>
<RefPosition #82 @90 RefTypeKill <Reg:f11> BB02 regmask=[f11] minReg=1 last>
<RefPosition #83 @90 RefTypeKill <Reg:f12> BB02 regmask=[f12] minReg=1 last>
<RefPosition #84 @90 RefTypeKill <Reg:f13> BB02 regmask=[f13] minReg=1 last>
<RefPosition #85 @90 RefTypeKill <Reg:f14> BB02 regmask=[f14] minReg=1 last>
<RefPosition #86 @90 RefTypeKill <Reg:f15> BB02 regmask=[f15] minReg=1 last>
<RefPosition #87 @90 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #88 @90 RefTypeDef <Ivl:32> CALL BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #89 @91 RefTypeUse <Ivl:32> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #90 @92 RefTypeDef <Ivl:7 V10> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #91 @95 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #92 @95 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #93 @96 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #94 @96 RefTypeDef <Ivl:33> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #95 @99 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #96 @99 RefTypeUse <Ivl:12 V15> LCL_VAR BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #97 @100 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #98 @100 RefTypeDef <Ivl:34> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
<RefPosition #99 @103 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #100 @103 RefTypeUse <Ivl:13 V16> LCL_VAR BB02 regmask=[r3] minReg=1 last fixed>
<RefPosition #101 @104 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #102 @104 RefTypeDef <Ivl:35> PUTARG_REG BB02 regmask=[r3] minReg=1 fixed>
<RefPosition #103 @109 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #104 @109 RefTypeUse <Ivl:33> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #105 @109 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #106 @109 RefTypeUse <Ivl:34> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #107 @109 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #108 @109 RefTypeUse <Ivl:35> BB02 regmask=[r3] minReg=1 last fixed>
<RefPosition #109 @109 RefTypeUse <Ivl:7 V10> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #110 @110 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #111 @110 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #112 @110 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #113 @110 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #114 @110 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #115 @110 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #116 @114 RefTypeDef <Ivl:36> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
<RefPosition #117 @115 RefTypeUse <Ivl:36> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #118 @116 RefTypeDef <Ivl:37> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #119 @117 RefTypeUse <Ivl:37> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #120 @118 RefTypeDef <Ivl:8 V11> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #121 @121 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #122 @121 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #123 @122 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #124 @122 RefTypeDef <Ivl:38> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #125 @124 RefTypeDef <Ivl:39> CNS_INT BB02 regmask=[r1] minReg=1>
<RefPosition #126 @125 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #127 @125 RefTypeUse <Ivl:39> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #128 @126 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #129 @126 RefTypeDef <Ivl:40> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
<RefPosition #130 @128 RefTypeDef <Ivl:41> CNS_INT BB02 regmask=[r2] minReg=1>
<RefPosition #131 @129 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #132 @129 RefTypeUse <Ivl:41> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #133 @130 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #134 @130 RefTypeDef <Ivl:42> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
<RefPosition #135 @132 RefTypeDef <Ivl:43> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #136 @133 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #137 @133 RefTypeUse <Ivl:38> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #138 @133 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #139 @133 RefTypeUse <Ivl:40> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #140 @133 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #141 @133 RefTypeUse <Ivl:42> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #142 @133 RefTypeUse <Ivl:43> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #143 @134 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #144 @134 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #145 @134 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #146 @134 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #147 @134 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #148 @134 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #149 @134 RefTypeKill <Reg:f0 > BB02 regmask=[f0] minReg=1 last>
<RefPosition #150 @134 RefTypeKill <Reg:f1 > BB02 regmask=[f1] minReg=1 last>
<RefPosition #151 @134 RefTypeKill <Reg:f2 > BB02 regmask=[f2] minReg=1 last>
<RefPosition #152 @134 RefTypeKill <Reg:f3 > BB02 regmask=[f3] minReg=1 last>
<RefPosition #153 @134 RefTypeKill <Reg:f4 > BB02 regmask=[f4] minReg=1 last>
<RefPosition #154 @134 RefTypeKill <Reg:f5 > BB02 regmask=[f5] minReg=1 last>
<RefPosition #155 @134 RefTypeKill <Reg:f6 > BB02 regmask=[f6] minReg=1 last>
<RefPosition #156 @134 RefTypeKill <Reg:f7 > BB02 regmask=[f7] minReg=1 last>
<RefPosition #157 @134 RefTypeKill <Reg:f8 > BB02 regmask=[f8] minReg=1 last>
<RefPosition #158 @134 RefTypeKill <Reg:f9 > BB02 regmask=[f9] minReg=1 last>
<RefPosition #159 @134 RefTypeKill <Reg:f10> BB02 regmask=[f10] minReg=1 last>
<RefPosition #160 @134 RefTypeKill <Reg:f11> BB02 regmask=[f11] minReg=1 last>
<RefPosition #161 @134 RefTypeKill <Reg:f12> BB02 regmask=[f12] minReg=1 last>
<RefPosition #162 @134 RefTypeKill <Reg:f13> BB02 regmask=[f13] minReg=1 last>
<RefPosition #163 @134 RefTypeKill <Reg:f14> BB02 regmask=[f14] minReg=1 last>
<RefPosition #164 @134 RefTypeKill <Reg:f15> BB02 regmask=[f15] minReg=1 last>
<RefPosition #165 @134 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #166 @134 RefTypeDef <Ivl:44> CALL BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #167 @135 RefTypeUse <Ivl:44> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #168 @136 RefTypeDef <Ivl:9 V12> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #169 @139 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #170 @139 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #171 @140 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #172 @140 RefTypeDef <Ivl:45> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #173 @143 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #174 @143 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #175 @144 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #176 @144 RefTypeDef <Ivl:46> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
<RefPosition #177 @147 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #178 @147 RefTypeUse <Ivl:45> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #179 @147 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #180 @147 RefTypeUse <Ivl:46> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #181 @147 RefTypeUse <Ivl:9 V12> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #182 @148 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #183 @148 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #184 @148 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #185 @148 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #186 @148 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #187 @148 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #188 @149 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #189 @157 RefTypeUse <Ivl:11 V14> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
<RefPosition #190 @161 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #191 @166 RefTypeDef <Ivl:47> CNS_INT BB04 regmask=[allInt] minReg=1>
<RefPosition #192 @171 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #193 @172 RefTypeDef <Ivl:48> IND BB04 regmask=[allInt] minReg=1>
<RefPosition #194 @173 RefTypeUse <Ivl:47> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #195 @173 RefTypeUse <Ivl:48> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #196 @175 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #197 @180 RefTypeDef <Ivl:49> CNS_INT BB05 regmask=[allInt] minReg=1>
<RefPosition #198 @185 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #199 @186 RefTypeDef <Ivl:50> IND BB05 regmask=[allInt] minReg=1>
<RefPosition #200 @187 RefTypeUse <Ivl:49> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #201 @187 RefTypeUse <Ivl:50> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #202 @195 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #203 @195 RefTypeUse <Ivl:3 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #204 @201 RefTypeUse <Ivl:1 V01> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #205 @202 RefTypeDef <Ivl:51> CAST BB05 regmask=[r0] minReg=1>
<RefPosition #206 @203 RefTypeFixedReg <Reg:r0 > BB05 regmask=[r0] minReg=1>
<RefPosition #207 @203 RefTypeUse <Ivl:51> BB05 regmask=[r0] minReg=1 last fixed>
<RefPosition #208 @205 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #209 @208 RefTypeDef <Ivl:52> CNS_INT BB06 regmask=[allInt] minReg=1>
<RefPosition #210 @209 RefTypeUse <Ivl:52> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #211 @210 RefTypeKill <Reg:r0 > BB06 regmask=[r0] minReg=1 last>
<RefPosition #212 @210 RefTypeKill <Reg:r1 > BB06 regmask=[r1] minReg=1 last>
<RefPosition #213 @210 RefTypeKill <Reg:r2 > BB06 regmask=[r2] minReg=1 last>
<RefPosition #214 @210 RefTypeKill <Reg:r3 > BB06 regmask=[r3] minReg=1 last>
<RefPosition #215 @210 RefTypeKill <Reg:r12> BB06 regmask=[r12] minReg=1 last>
<RefPosition #216 @210 RefTypeKill <Reg:lr > BB06 regmask=[lr] minReg=1 last>
<RefPosition #217 @210 RefTypeKill <Reg:f0 > BB06 regmask=[f0] minReg=1 last>
<RefPosition #218 @210 RefTypeKill <Reg:f1 > BB06 regmask=[f1] minReg=1 last>
<RefPosition #219 @210 RefTypeKill <Reg:f2 > BB06 regmask=[f2] minReg=1 last>
<RefPosition #220 @210 RefTypeKill <Reg:f3 > BB06 regmask=[f3] minReg=1 last>
<RefPosition #221 @210 RefTypeKill <Reg:f4 > BB06 regmask=[f4] minReg=1 last>
<RefPosition #222 @210 RefTypeKill <Reg:f5 > BB06 regmask=[f5] minReg=1 last>
<RefPosition #223 @210 RefTypeKill <Reg:f6 > BB06 regmask=[f6] minReg=1 last>
<RefPosition #224 @210 RefTypeKill <Reg:f7 > BB06 regmask=[f7] minReg=1 last>
<RefPosition #225 @210 RefTypeKill <Reg:f8 > BB06 regmask=[f8] minReg=1 last>
<RefPosition #226 @210 RefTypeKill <Reg:f9 > BB06 regmask=[f9] minReg=1 last>
<RefPosition #227 @210 RefTypeKill <Reg:f10> BB06 regmask=[f10] minReg=1 last>
<RefPosition #228 @210 RefTypeKill <Reg:f11> BB06 regmask=[f11] minReg=1 last>
<RefPosition #229 @210 RefTypeKill <Reg:f12> BB06 regmask=[f12] minReg=1 last>
<RefPosition #230 @210 RefTypeKill <Reg:f13> BB06 regmask=[f13] minReg=1 last>
<RefPosition #231 @210 RefTypeKill <Reg:f14> BB06 regmask=[f14] minReg=1 last>
<RefPosition #232 @210 RefTypeKill <Reg:f15> BB06 regmask=[f15] minReg=1 last>
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[r0] minReg=1 fixed>
<RefPosition #192 @171 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #28 @48 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #30 @55 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #34 @63 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #10 @10 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @15 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #189 @157 RefTypeUse <Ivl:11 V14> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #1 @0 RefTypeParamDef <Ivl:3 V03> BB00 regmask=[r3] minReg=1 fixed>
<RefPosition #203 @195 RefTypeUse <Ivl:3 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r2] minReg=1 fixed>
<RefPosition #37 @66 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #174 @143 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[r1] minReg=1 last fixed>
-----------------
<RefPosition #3 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[r1] minReg=1 fixed>
<RefPosition #204 @201 RefTypeUse <Ivl:1 V01> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #4 @0 RefTypeParamDef <Ivl:5 V05> BB00 regmask=[allInt] minReg=1>
<RefPosition #198 @185 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #202 @195 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #42 @74 RefTypeDef <Ivl:6 V09> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #44 @77 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #92 @95 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
-----------------
<RefPosition #120 @118 RefTypeDef <Ivl:8 V11> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #122 @121 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #170 @139 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
-----------------
<RefPosition #17 @28 RefTypeDef <Ivl:14 V17> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #18 @35 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @37 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #5 @0 RefTypeParamDef <Ivl:4 V04> BB00 regmask=[allInt] minReg=1>
<RefPosition #7 @7 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #90 @92 RefTypeDef <Ivl:7 V10> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #109 @109 RefTypeUse <Ivl:7 V10> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #168 @136 RefTypeDef <Ivl:9 V12> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #181 @147 RefTypeUse <Ivl:9 V12> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #21 @38 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #96 @99 RefTypeUse <Ivl:12 V15> LCL_VAR BB02 regmask=[r2] minReg=1 last fixed>
-----------------
<RefPosition #23 @40 RefTypeDef <Ivl:13 V16> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #100 @103 RefTypeUse <Ivl:13 V16> LCL_VAR BB02 regmask=[r3] minReg=1 last fixed>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00 V03 V02 V01 V05 V04
BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N003. IL_OFFSET IL offset: 0x0 REG NA
N005. V04(L4)
N007. CAST
Use:<L4>(#7) *
Def:<I15>(#8) Pref:<L11>
N009. V14(L11)
Use:<I15>(#9) *
Def:<L11>(#10)
N011. V14(L11)
N013. CNS_INT 0 REG NA
N015. EQ
Use:<L11>(#11)
N017. JTRUE
BB02 [004..02C), preds={BB01} succs={BB03}
=====
N021. IL_OFFSET IL offset: 0x4 REG NA
N023. CLS_VAR_ADDR Hnd=0x9247f8 REG NA
Def:<I16>(#13)
N025. IND
Use:<I16>(#14) *
Def:<I17>(#15) Pref:<L14>
N027. V17(L14)
Use:<I17>(#16) *
Def:<L14>(#17)
N029. V17(L14)
N031. V17(L14)
N033. CNS_INT 31 REG NA
N035. RSH
Use:<L14>(#18)
Def:<I18>(#19) Pref:<L13>
N037. V15(L12)
Use:<L14>(#20) *
Def:<L12>(#21)
N039. V16(L13)
Use:<I18>(#22) *
Def:<L13>(#23)
N041. IL_OFFSET IL offset: 0xb REG NA
N043. CLS_VAR_ADDR Hnd=0x924808 REG NA
Def:<I19>(#24)
N045. IND
Use:<I19>(#25) *
Def:<I20>(#26) Pref:<L10>
N047. V13(L10)
Use:<I20>(#27) *
Def:<L10>(#28)
N049. CNS_INT 0 REG NA
Def:<I21>(#29)
N051. V13(L10)
N053. LEA(b+4)
N055. IND
Use:<L10>(#30)
Def:<I22>(#31)
N057. ARR_BOUNDS_CHECK_Rng
Use:<I21>(#32) *
Use:<I22>(#33) *
N059. V13(L10)
N061. LEA(b+8)
N063. IND
Use:<L10>(#34) *
Def:<I23>(#35) Pref:<L2>
N065. V02(L2)
Use:<I23>(#36) *
Def:<L2>(#37)
N067. IL_OFFSET IL offset: 0x16 REG NA
N069. CLS_VAR_ADDR Hnd=0x9247d8 REG NA
Def:<I24>(#38)
N071. IND
Use:<I24>(#39) *
Def:<I25>(#40) Pref:<L6>
N073. V09(L6)
Use:<I25>(#41) *
Def:<L6>(#42)
N075. V09(L6)
N077. PUTARG_REG
Use:<L6>(#44) Fixed:r0(#43)
Def:<I26>(#46) r0 Pref:<L6>
N079. CNS_INT(h) 0x924994 token REG NA
Def:<I27>(#47)
N081. PUTARG_REG
Use:<I27>(#49) Fixed:r1(#48) *
Def:<I28>(#51) r1
N083. CNS_INT(h) 0x924B10 token REG NA
Def:<I29>(#52)
N085. PUTARG_REG
Use:<I29>(#54) Fixed:r2(#53) *
Def:<I30>(#56) r2
N087. CNS_INT(h) 0xFDA55A0 ftn REG NA
Def:<I31>(#57)
N089. CALL help
Use:<I26>(#59) Fixed:r0(#58) *
Use:<I28>(#61) Fixed:r1(#60) *
Use:<I30>(#63) Fixed:r2(#62) *
Use:<I31>(#64) *
Kill: r0 r1 r2 r3 r12 lr f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15
Def:<I32>(#88) r0 Pref:<L7>
N091. V10(L7)
Use:<I32>(#89) *
Def:<L7>(#90)
N093. V09(L6)
N095. PUTARG_REG
Use:<L6>(#92) Fixed:r0(#91) *
Def:<I33>(#94) r0
N097. V15(L12)
N099. PUTARG_REG
Use:<L12>(#96) Fixed:r2(#95) *
Def:<I34>(#98) r2
N101. V16(L13)
N103. PUTARG_REG
Use:<L13>(#100) Fixed:r3(#99) *
Def:<I35>(#102) r3
N105. FIELD_LIST
N107. V10(L7)
N109. CALL ind
Use:<I33>(#104) Fixed:r0(#103) *
Use:<I34>(#106) Fixed:r2(#105) *
Use:<I35>(#108) Fixed:r3(#107) *
Use:<L7>(#109) *
Kill: r0 r1 r2 r3 r12 lr
N111. IL_OFFSET IL offset: 0x21 REG NA
N113. CLS_VAR_ADDR Hnd=0x9247d8 REG NA
Def:<I36>(#116)
N115. IND
Use:<I36>(#117) *
Def:<I37>(#118) Pref:<L8>
N117. V11(L8)
Use:<I37>(#119) *
Def:<L8>(#120)
N119. V11(L8)
N121. PUTARG_REG
Use:<L8>(#122) Fixed:r0(#121)
Def:<I38>(#124) r0 Pref:<L8>
N123. CNS_INT(h) 0x924994 token REG NA
Def:<I39>(#125)
N125. PUTARG_REG
Use:<I39>(#127) Fixed:r1(#126) *
Def:<I40>(#129) r1
N127. CNS_INT(h) 0x924B74 token REG NA
Def:<I41>(#130)
N129. PUTARG_REG
Use:<I41>(#132) Fixed:r2(#131) *
Def:<I42>(#134) r2
N131. CNS_INT(h) 0xFDA55A0 ftn REG NA
Def:<I43>(#135)
N133. CALL help
Use:<I38>(#137) Fixed:r0(#136) *
Use:<I40>(#139) Fixed:r1(#138) *
Use:<I42>(#141) Fixed:r2(#140) *
Use:<I43>(#142) *
Kill: r0 r1 r2 r3 r12 lr f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15
Def:<I44>(#166) r0 Pref:<L9>
N135. V12(L9)
Use:<I44>(#167) *
Def:<L9>(#168)
N137. V11(L8)
N139. PUTARG_REG
Use:<L8>(#170) Fixed:r0(#169) *
Def:<I45>(#172) r0
N141. V02(L2)
N143. PUTARG_REG
Use:<L2>(#174) Fixed:r1(#173) *
Def:<I46>(#176) r1
N145. V12(L9)
N147. CALL ind
Use:<I45>(#178) Fixed:r0(#177) *
Use:<I46>(#180) Fixed:r1(#179) *
Use:<L9>(#181) *
Kill: r0 r1 r2 r3 r12 lr
BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
=====
N151. IL_OFFSET IL offset: 0x2c REG NA
N153. V14(L11)
N155. CNS_INT 0 REG NA
N157. NE
Use:<L11>(#189) *
N159. JTRUE
BB04 [030..034), preds={BB03} succs={BB05}
=====
N163. IL_OFFSET IL offset: 0x30 REG NA
N165. CNS_INT 0 REG NA
Def:<I47>(#191)
N167. V00(L0)
N169. LEA(b+4)
N171. IND
Use:<L0>(#192) *
Def:<I48>(#193)
N173. ARR_BOUNDS_CHECK_Rng
Use:<I47>(#194) *
Use:<I48>(#195) *
BB05 [034..03B) (return), preds={BB03,BB04} succs={}
=====
N177. IL_OFFSET IL offset: 0x34 REG NA
N179. CNS_INT 0 REG NA
Def:<I49>(#197)
N181. V05(L5)
N183. LEA(b+4)
N185. IND
Use:<L5>(#198)
Def:<I50>(#199)
N187. ARR_BOUNDS_CHECK_Rng
Use:<I49>(#200) *
Use:<I50>(#201) *
N189. V05(L5)
N191. LEA(b+8)
N193. V03(L3)
N195. STOREIND
Use:<L5>(#202) *
Use:<L3>(#203) *
N197. IL_OFFSET IL offset: 0x39 REG NA
N199. V01(L1)
N201. CAST
Use:<L1>(#204) *
Def:<I51>(#205)
N203. RETURN
Use:<I51>(#207) Fixed:r0(#206) *
BB06 [???..???) (throw), preds={} succs={}
=====
N207. CNS_INT(h) 0xFDA7BB0 ftn REG NA
Def:<I52>(#209)
N209. CALL help
Use:<I52>(#210) *
Kill: r0 r1 r2 r3 r12 lr f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15
Linear scan intervals after buildIntervals:
Interval 0: (V00) RefPositions {#0@0 #192@171} physReg:r0 Preferences=[r4-r10]
Interval 1: (V01) RefPositions {#3@0 #204@201} physReg:r1 Preferences=[r4-r10]
Interval 2: (V02) RefPositions {#2@0 #37@66 #174@143} physReg:r2 Preferences=[r4-r10]
Interval 3: (V03) RefPositions {#1@0 #203@195} physReg:r3 Preferences=[r4-r10]
Interval 4: (V04) RefPositions {#5@0 #7@7} physReg:NA Preferences=[allInt]
Interval 5: (V05) RefPositions {#4@0 #198@185 #202@195} physReg:NA Preferences=[r4-r10]
Interval 6: (V09) RefPositions {#42@74 #44@77 #92@95} physReg:NA Preferences=[r4-r10]
Interval 7: (V10) RefPositions {#90@92 #109@109} physReg:NA Preferences=[allInt]
Interval 8: (V11) RefPositions {#120@118 #122@121 #170@139} physReg:NA Preferences=[r4-r10]
Interval 9: (V12) RefPositions {#168@136 #181@147} physReg:NA Preferences=[allInt]
Interval 10: (V13) RefPositions {#28@48 #30@55 #34@63} physReg:NA Preferences=[allInt]
Interval 11: (V14) RefPositions {#10@10 #11@15 #189@157} physReg:NA Preferences=[r4-r10]
Interval 12: (V15) (struct) RefPositions {#21@38 #96@99} physReg:NA Preferences=[r4-r10]
Interval 13: (V16) (struct) RefPositions {#23@40 #100@103} physReg:NA Preferences=[r4-r10]
Interval 14: (V17) RefPositions {#17@28 #18@35 #20@37} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#8@8 #9@9} physReg:NA Preferences=[allInt] RelatedInterval <L11>[008D0934]
Interval 16: RefPositions {#13@24 #14@25} physReg:NA Preferences=[allInt]
Interval 17: RefPositions {#15@26 #16@27} physReg:NA Preferences=[allInt] RelatedInterval <L14>[008D09DC]
Interval 18: RefPositions {#19@36 #22@39} physReg:NA Preferences=[allInt] RelatedInterval <L13>[008D09A4]
Interval 19: RefPositions {#24@44 #25@45} physReg:NA Preferences=[allInt]
Interval 20: RefPositions {#26@46 #27@47} physReg:NA Preferences=[allInt] RelatedInterval <L10>[008D08FC]
Interval 21: (constant) RefPositions {#29@50 #32@57} physReg:NA Preferences=[allInt]
Interval 22: RefPositions {#31@56 #33@57} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#35@64 #36@65} physReg:NA Preferences=[allInt] RelatedInterval <L2>[008D073C]
Interval 24: RefPositions {#38@70 #39@71} physReg:NA Preferences=[allInt]
Interval 25: RefPositions {#40@72 #41@73} physReg:NA Preferences=[allInt] RelatedInterval <L6>[008D081C]
Interval 26: (specialPutArg) RefPositions {#46@78 #59@89} physReg:NA Preferences=[r0] RelatedInterval <L6>[008D081C]
Interval 27: (constant) RefPositions {#47@80 #49@81} physReg:NA Preferences=[r1]
Interval 28: RefPositions {#51@82 #61@89} physReg:NA Preferences=[r1]
Interval 29: (constant) RefPositions {#52@84 #54@85} physReg:NA Preferences=[r2]
Interval 30: RefPositions {#56@86 #63@89} physReg:NA Preferences=[r2]
Interval 31: (constant) RefPositions {#57@88 #64@89} physReg:NA Preferences=[allInt]
Interval 32: RefPositions {#88@90 #89@91} physReg:NA Preferences=[r0] RelatedInterval <L7>[008D0854]
Interval 33: RefPositions {#94@96 #104@109} physReg:NA Preferences=[r0]
Interval 34: RefPositions {#98@100 #106@109} physReg:NA Preferences=[r2]
Interval 35: RefPositions {#102@104 #108@109} physReg:NA Preferences=[r3]
Interval 36: RefPositions {#116@114 #117@115} physReg:NA Preferences=[allInt]
Interval 37: RefPositions {#118@116 #119@117} physReg:NA Preferences=[allInt] RelatedInterval <L8>[008D088C]
Interval 38: (specialPutArg) RefPositions {#124@122 #137@133} physReg:NA Preferences=[r0] RelatedInterval <L8>[008D088C]
Interval 39: (constant) RefPositions {#125@124 #127@125} physReg:NA Preferences=[r1]
Interval 40: RefPositions {#129@126 #139@133} physReg:NA Preferences=[r1]
Interval 41: (constant) RefPositions {#130@128 #132@129} physReg:NA Preferences=[r2]
Interval 42: RefPositions {#134@130 #141@133} physReg:NA Preferences=[r2]
Interval 43: (constant) RefPositions {#135@132 #142@133} physReg:NA Preferences=[allInt]
Interval 44: RefPositions {#166@134 #167@135} physReg:NA Preferences=[r0] RelatedInterval <L9>[008D08C4]
Interval 45: RefPositions {#172@140 #178@147} physReg:NA Preferences=[r0]
Interval 46: RefPositions {#176@144 #180@147} physReg:NA Preferences=[r1]
Interval 47: (constant) RefPositions {#191@166 #194@173} physReg:NA Preferences=[allInt]
Interval 48: RefPositions {#193@172 #195@173} physReg:NA Preferences=[allInt]
Interval 49: (constant) RefPositions {#197@180 #200@187} physReg:NA Preferences=[allInt]
Interval 50: RefPositions {#199@186 #201@187} physReg:NA Preferences=[allInt]
Interval 51: RefPositions {#205@202 #207@203} physReg:NA Preferences=[r0]
Interval 52: (constant) RefPositions {#209@208 #210@209} physReg:NA Preferences=[allInt]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) RefPositions {#0@0 #192@171} physReg:r0 Preferences=[r4-r10]
Interval 1: (V01) RefPositions {#3@0 #204@201} physReg:r1 Preferences=[r4-r10]
Interval 2: (V02) RefPositions {#2@0 #37@66 #174@143} physReg:r2 Preferences=[r4-r10]
Interval 3: (V03) RefPositions {#1@0 #203@195} physReg:r3 Preferences=[r4-r10]
Interval 4: (V04) RefPositions {#5@0 #7@7} physReg:NA Preferences=[allInt]
Interval 5: (V05) RefPositions {#4@0 #198@185 #202@195} physReg:NA Preferences=[r4-r10]
Interval 6: (V09) RefPositions {#42@74 #44@77 #92@95} physReg:NA Preferences=[r4-r10]
Interval 7: (V10) RefPositions {#90@92 #109@109} physReg:NA Preferences=[allInt]
Interval 8: (V11) RefPositions {#120@118 #122@121 #170@139} physReg:NA Preferences=[r4-r10]
Interval 9: (V12) RefPositions {#168@136 #181@147} physReg:NA Preferences=[allInt]
Interval 10: (V13) RefPositions {#28@48 #30@55 #34@63} physReg:NA Preferences=[allInt]
Interval 11: (V14) RefPositions {#10@10 #11@15 #189@157} physReg:NA Preferences=[r4-r10]
Interval 12: (V15) (struct) RefPositions {#21@38 #96@99} physReg:NA Preferences=[r4-r10]
Interval 13: (V16) (struct) RefPositions {#23@40 #100@103} physReg:NA Preferences=[r4-r10]
Interval 14: (V17) RefPositions {#17@28 #18@35 #20@37} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#8@8 #9@9} physReg:NA Preferences=[allInt] RelatedInterval <L11>[008D0934]
Interval 16: RefPositions {#13@24 #14@25} physReg:NA Preferences=[allInt]
Interval 17: RefPositions {#15@26 #16@27} physReg:NA Preferences=[allInt] RelatedInterval <L14>[008D09DC]
Interval 18: RefPositions {#19@36 #22@39} physReg:NA Preferences=[allInt] RelatedInterval <L13>[008D09A4]
Interval 19: RefPositions {#24@44 #25@45} physReg:NA Preferences=[allInt]
Interval 20: RefPositions {#26@46 #27@47} physReg:NA Preferences=[allInt] RelatedInterval <L10>[008D08FC]
Interval 21: (constant) RefPositions {#29@50 #32@57} physReg:NA Preferences=[allInt]
Interval 22: RefPositions {#31@56 #33@57} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#35@64 #36@65} physReg:NA Preferences=[allInt] RelatedInterval <L2>[008D073C]
Interval 24: RefPositions {#38@70 #39@71} physReg:NA Preferences=[allInt]
Interval 25: RefPositions {#40@72 #41@73} physReg:NA Preferences=[allInt] RelatedInterval <L6>[008D081C]
Interval 26: (specialPutArg) RefPositions {#46@78 #59@89} physReg:NA Preferences=[r0] RelatedInterval <L6>[008D081C]
Interval 27: (constant) RefPositions {#47@80 #49@81} physReg:NA Preferences=[r1]
Interval 28: RefPositions {#51@82 #61@89} physReg:NA Preferences=[r1]
Interval 29: (constant) RefPositions {#52@84 #54@85} physReg:NA Preferences=[r2]
Interval 30: RefPositions {#56@86 #63@89} physReg:NA Preferences=[r2]
Interval 31: (constant) RefPositions {#57@88 #64@89} physReg:NA Preferences=[allInt]
Interval 32: RefPositions {#88@90 #89@91} physReg:NA Preferences=[r0] RelatedInterval <L7>[008D0854]
Interval 33: RefPositions {#94@96 #104@109} physReg:NA Preferences=[r0]
Interval 34: RefPositions {#98@100 #106@109} physReg:NA Preferences=[r2]
Interval 35: RefPositions {#102@104 #108@109} physReg:NA Preferences=[r3]
Interval 36: RefPositions {#116@114 #117@115} physReg:NA Preferences=[allInt]
Interval 37: RefPositions {#118@116 #119@117} physReg:NA Preferences=[allInt] RelatedInterval <L8>[008D088C]
Interval 38: (specialPutArg) RefPositions {#124@122 #137@133} physReg:NA Preferences=[r0] RelatedInterval <L8>[008D088C]
Interval 39: (constant) RefPositions {#125@124 #127@125} physReg:NA Preferences=[r1]
Interval 40: RefPositions {#129@126 #139@133} physReg:NA Preferences=[r1]
Interval 41: (constant) RefPositions {#130@128 #132@129} physReg:NA Preferences=[r2]
Interval 42: RefPositions {#134@130 #141@133} physReg:NA Preferences=[r2]
Interval 43: (constant) RefPositions {#135@132 #142@133} physReg:NA Preferences=[allInt]
Interval 44: RefPositions {#166@134 #167@135} physReg:NA Preferences=[r0] RelatedInterval <L9>[008D08C4]
Interval 45: RefPositions {#172@140 #178@147} physReg:NA Preferences=[r0]
Interval 46: RefPositions {#176@144 #180@147} physReg:NA Preferences=[r1]
Interval 47: (constant) RefPositions {#191@166 #194@173} physReg:NA Preferences=[allInt]
Interval 48: RefPositions {#193@172 #195@173} physReg:NA Preferences=[allInt]
Interval 49: (constant) RefPositions {#197@180 #200@187} physReg:NA Preferences=[allInt]
Interval 50: RefPositions {#199@186 #201@187} physReg:NA Preferences=[allInt]
Interval 51: RefPositions {#205@202 #207@203} physReg:NA Preferences=[r0]
Interval 52: (constant) RefPositions {#209@208 #210@209} physReg:NA Preferences=[allInt]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[r0] minReg=1 fixed>
<RefPosition #1 @0 RefTypeParamDef <Ivl:3 V03> BB00 regmask=[r3] minReg=1 fixed>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r2] minReg=1 fixed>
<RefPosition #3 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[r1] minReg=1 fixed>
<RefPosition #4 @0 RefTypeParamDef <Ivl:5 V05> BB00 regmask=[allInt] minReg=1>
<RefPosition #5 @0 RefTypeParamDef <Ivl:4 V04> BB00 regmask=[allInt] minReg=1>
<RefPosition #6 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #7 @7 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @8 RefTypeDef <Ivl:15> CAST BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @9 RefTypeUse <Ivl:15> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #10 @10 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @15 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #12 @19 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #13 @24 RefTypeDef <Ivl:16> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
<RefPosition #14 @25 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #15 @26 RefTypeDef <Ivl:17> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #16 @27 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #17 @28 RefTypeDef <Ivl:14 V17> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #18 @35 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #19 @36 RefTypeDef <Ivl:18> RSH BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @37 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @38 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #22 @39 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @40 RefTypeDef <Ivl:13 V16> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @44 RefTypeDef <Ivl:19> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
<RefPosition #25 @45 RefTypeUse <Ivl:19> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #26 @46 RefTypeDef <Ivl:20> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @47 RefTypeUse <Ivl:20> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #28 @48 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #29 @50 RefTypeDef <Ivl:21> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #30 @55 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #31 @56 RefTypeDef <Ivl:22> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @57 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #33 @57 RefTypeUse <Ivl:22> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #34 @63 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #35 @64 RefTypeDef <Ivl:23> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #36 @65 RefTypeUse <Ivl:23> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #37 @66 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #38 @70 RefTypeDef <Ivl:24> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
<RefPosition #39 @71 RefTypeUse <Ivl:24> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #40 @72 RefTypeDef <Ivl:25> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #41 @73 RefTypeUse <Ivl:25> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #42 @74 RefTypeDef <Ivl:6 V09> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #43 @77 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #44 @77 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #45 @78 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #46 @78 RefTypeDef <Ivl:26> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #47 @80 RefTypeDef <Ivl:27> CNS_INT BB02 regmask=[r1] minReg=1>
<RefPosition #48 @81 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #49 @81 RefTypeUse <Ivl:27> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #50 @82 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #51 @82 RefTypeDef <Ivl:28> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
<RefPosition #52 @84 RefTypeDef <Ivl:29> CNS_INT BB02 regmask=[r2] minReg=1>
<RefPosition #53 @85 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #54 @85 RefTypeUse <Ivl:29> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #55 @86 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #56 @86 RefTypeDef <Ivl:30> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
<RefPosition #57 @88 RefTypeDef <Ivl:31> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #58 @89 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #59 @89 RefTypeUse <Ivl:26> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #60 @89 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #61 @89 RefTypeUse <Ivl:28> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #62 @89 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #63 @89 RefTypeUse <Ivl:30> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #64 @89 RefTypeUse <Ivl:31> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #65 @90 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #66 @90 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #67 @90 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #68 @90 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #69 @90 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #70 @90 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #71 @90 RefTypeKill <Reg:f0 > BB02 regmask=[f0] minReg=1 last>
<RefPosition #72 @90 RefTypeKill <Reg:f1 > BB02 regmask=[f1] minReg=1 last>
<RefPosition #73 @90 RefTypeKill <Reg:f2 > BB02 regmask=[f2] minReg=1 last>
<RefPosition #74 @90 RefTypeKill <Reg:f3 > BB02 regmask=[f3] minReg=1 last>
<RefPosition #75 @90 RefTypeKill <Reg:f4 > BB02 regmask=[f4] minReg=1 last>
<RefPosition #76 @90 RefTypeKill <Reg:f5 > BB02 regmask=[f5] minReg=1 last>
<RefPosition #77 @90 RefTypeKill <Reg:f6 > BB02 regmask=[f6] minReg=1 last>
<RefPosition #78 @90 RefTypeKill <Reg:f7 > BB02 regmask=[f7] minReg=1 last>
<RefPosition #79 @90 RefTypeKill <Reg:f8 > BB02 regmask=[f8] minReg=1 last>
<RefPosition #80 @90 RefTypeKill <Reg:f9 > BB02 regmask=[f9] minReg=1 last>
<RefPosition #81 @90 RefTypeKill <Reg:f10> BB02 regmask=[f10] minReg=1 last>
<RefPosition #82 @90 RefTypeKill <Reg:f11> BB02 regmask=[f11] minReg=1 last>
<RefPosition #83 @90 RefTypeKill <Reg:f12> BB02 regmask=[f12] minReg=1 last>
<RefPosition #84 @90 RefTypeKill <Reg:f13> BB02 regmask=[f13] minReg=1 last>
<RefPosition #85 @90 RefTypeKill <Reg:f14> BB02 regmask=[f14] minReg=1 last>
<RefPosition #86 @90 RefTypeKill <Reg:f15> BB02 regmask=[f15] minReg=1 last>
<RefPosition #87 @90 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #88 @90 RefTypeDef <Ivl:32> CALL BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #89 @91 RefTypeUse <Ivl:32> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #90 @92 RefTypeDef <Ivl:7 V10> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #91 @95 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #92 @95 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #93 @96 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #94 @96 RefTypeDef <Ivl:33> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #95 @99 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #96 @99 RefTypeUse <Ivl:12 V15> LCL_VAR BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #97 @100 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #98 @100 RefTypeDef <Ivl:34> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
<RefPosition #99 @103 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #100 @103 RefTypeUse <Ivl:13 V16> LCL_VAR BB02 regmask=[r3] minReg=1 last fixed>
<RefPosition #101 @104 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #102 @104 RefTypeDef <Ivl:35> PUTARG_REG BB02 regmask=[r3] minReg=1 fixed>
<RefPosition #103 @109 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #104 @109 RefTypeUse <Ivl:33> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #105 @109 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #106 @109 RefTypeUse <Ivl:34> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #107 @109 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #108 @109 RefTypeUse <Ivl:35> BB02 regmask=[r3] minReg=1 last fixed>
<RefPosition #109 @109 RefTypeUse <Ivl:7 V10> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #110 @110 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #111 @110 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #112 @110 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #113 @110 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #114 @110 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #115 @110 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #116 @114 RefTypeDef <Ivl:36> CLS_VAR_ADDR BB02 regmask=[allInt] minReg=1>
<RefPosition #117 @115 RefTypeUse <Ivl:36> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #118 @116 RefTypeDef <Ivl:37> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #119 @117 RefTypeUse <Ivl:37> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #120 @118 RefTypeDef <Ivl:8 V11> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #121 @121 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #122 @121 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #123 @122 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #124 @122 RefTypeDef <Ivl:38> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #125 @124 RefTypeDef <Ivl:39> CNS_INT BB02 regmask=[r1] minReg=1>
<RefPosition #126 @125 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #127 @125 RefTypeUse <Ivl:39> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #128 @126 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #129 @126 RefTypeDef <Ivl:40> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
<RefPosition #130 @128 RefTypeDef <Ivl:41> CNS_INT BB02 regmask=[r2] minReg=1>
<RefPosition #131 @129 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #132 @129 RefTypeUse <Ivl:41> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #133 @130 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #134 @130 RefTypeDef <Ivl:42> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
<RefPosition #135 @132 RefTypeDef <Ivl:43> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #136 @133 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #137 @133 RefTypeUse <Ivl:38> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #138 @133 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #139 @133 RefTypeUse <Ivl:40> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #140 @133 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #141 @133 RefTypeUse <Ivl:42> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #142 @133 RefTypeUse <Ivl:43> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #143 @134 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #144 @134 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #145 @134 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #146 @134 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #147 @134 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #148 @134 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #149 @134 RefTypeKill <Reg:f0 > BB02 regmask=[f0] minReg=1 last>
<RefPosition #150 @134 RefTypeKill <Reg:f1 > BB02 regmask=[f1] minReg=1 last>
<RefPosition #151 @134 RefTypeKill <Reg:f2 > BB02 regmask=[f2] minReg=1 last>
<RefPosition #152 @134 RefTypeKill <Reg:f3 > BB02 regmask=[f3] minReg=1 last>
<RefPosition #153 @134 RefTypeKill <Reg:f4 > BB02 regmask=[f4] minReg=1 last>
<RefPosition #154 @134 RefTypeKill <Reg:f5 > BB02 regmask=[f5] minReg=1 last>
<RefPosition #155 @134 RefTypeKill <Reg:f6 > BB02 regmask=[f6] minReg=1 last>
<RefPosition #156 @134 RefTypeKill <Reg:f7 > BB02 regmask=[f7] minReg=1 last>
<RefPosition #157 @134 RefTypeKill <Reg:f8 > BB02 regmask=[f8] minReg=1 last>
<RefPosition #158 @134 RefTypeKill <Reg:f9 > BB02 regmask=[f9] minReg=1 last>
<RefPosition #159 @134 RefTypeKill <Reg:f10> BB02 regmask=[f10] minReg=1 last>
<RefPosition #160 @134 RefTypeKill <Reg:f11> BB02 regmask=[f11] minReg=1 last>
<RefPosition #161 @134 RefTypeKill <Reg:f12> BB02 regmask=[f12] minReg=1 last>
<RefPosition #162 @134 RefTypeKill <Reg:f13> BB02 regmask=[f13] minReg=1 last>
<RefPosition #163 @134 RefTypeKill <Reg:f14> BB02 regmask=[f14] minReg=1 last>
<RefPosition #164 @134 RefTypeKill <Reg:f15> BB02 regmask=[f15] minReg=1 last>
<RefPosition #165 @134 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #166 @134 RefTypeDef <Ivl:44> CALL BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #167 @135 RefTypeUse <Ivl:44> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #168 @136 RefTypeDef <Ivl:9 V12> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #169 @139 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #170 @139 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #171 @140 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #172 @140 RefTypeDef <Ivl:45> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #173 @143 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #174 @143 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #175 @144 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #176 @144 RefTypeDef <Ivl:46> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
<RefPosition #177 @147 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #178 @147 RefTypeUse <Ivl:45> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #179 @147 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #180 @147 RefTypeUse <Ivl:46> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #181 @147 RefTypeUse <Ivl:9 V12> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #182 @148 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #183 @148 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #184 @148 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #185 @148 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #186 @148 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #187 @148 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #188 @149 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #189 @157 RefTypeUse <Ivl:11 V14> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
<RefPosition #190 @161 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #191 @166 RefTypeDef <Ivl:47> CNS_INT BB04 regmask=[allInt] minReg=1>
<RefPosition #192 @171 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #193 @172 RefTypeDef <Ivl:48> IND BB04 regmask=[allInt] minReg=1>
<RefPosition #194 @173 RefTypeUse <Ivl:47> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #195 @173 RefTypeUse <Ivl:48> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #196 @175 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #197 @180 RefTypeDef <Ivl:49> CNS_INT BB05 regmask=[allInt] minReg=1>
<RefPosition #198 @185 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #199 @186 RefTypeDef <Ivl:50> IND BB05 regmask=[allInt] minReg=1>
<RefPosition #200 @187 RefTypeUse <Ivl:49> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #201 @187 RefTypeUse <Ivl:50> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #202 @195 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #203 @195 RefTypeUse <Ivl:3 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #204 @201 RefTypeUse <Ivl:1 V01> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #205 @202 RefTypeDef <Ivl:51> CAST BB05 regmask=[r0] minReg=1>
<RefPosition #206 @203 RefTypeFixedReg <Reg:r0 > BB05 regmask=[r0] minReg=1>
<RefPosition #207 @203 RefTypeUse <Ivl:51> BB05 regmask=[r0] minReg=1 last fixed>
<RefPosition #208 @205 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #209 @208 RefTypeDef <Ivl:52> CNS_INT BB06 regmask=[allInt] minReg=1>
<RefPosition #210 @209 RefTypeUse <Ivl:52> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #211 @210 RefTypeKill <Reg:r0 > BB06 regmask=[r0] minReg=1 last>
<RefPosition #212 @210 RefTypeKill <Reg:r1 > BB06 regmask=[r1] minReg=1 last>
<RefPosition #213 @210 RefTypeKill <Reg:r2 > BB06 regmask=[r2] minReg=1 last>
<RefPosition #214 @210 RefTypeKill <Reg:r3 > BB06 regmask=[r3] minReg=1 last>
<RefPosition #215 @210 RefTypeKill <Reg:r12> BB06 regmask=[r12] minReg=1 last>
<RefPosition #216 @210 RefTypeKill <Reg:lr > BB06 regmask=[lr] minReg=1 last>
<RefPosition #217 @210 RefTypeKill <Reg:f0 > BB06 regmask=[f0] minReg=1 last>
<RefPosition #218 @210 RefTypeKill <Reg:f1 > BB06 regmask=[f1] minReg=1 last>
<RefPosition #219 @210 RefTypeKill <Reg:f2 > BB06 regmask=[f2] minReg=1 last>
<RefPosition #220 @210 RefTypeKill <Reg:f3 > BB06 regmask=[f3] minReg=1 last>
<RefPosition #221 @210 RefTypeKill <Reg:f4 > BB06 regmask=[f4] minReg=1 last>
<RefPosition #222 @210 RefTypeKill <Reg:f5 > BB06 regmask=[f5] minReg=1 last>
<RefPosition #223 @210 RefTypeKill <Reg:f6 > BB06 regmask=[f6] minReg=1 last>
<RefPosition #224 @210 RefTypeKill <Reg:f7 > BB06 regmask=[f7] minReg=1 last>
<RefPosition #225 @210 RefTypeKill <Reg:f8 > BB06 regmask=[f8] minReg=1 last>
<RefPosition #226 @210 RefTypeKill <Reg:f9 > BB06 regmask=[f9] minReg=1 last>
<RefPosition #227 @210 RefTypeKill <Reg:f10> BB06 regmask=[f10] minReg=1 last>
<RefPosition #228 @210 RefTypeKill <Reg:f11> BB06 regmask=[f11] minReg=1 last>
<RefPosition #229 @210 RefTypeKill <Reg:f12> BB06 regmask=[f12] minReg=1 last>
<RefPosition #230 @210 RefTypeKill <Reg:f13> BB06 regmask=[f13] minReg=1 last>
<RefPosition #231 @210 RefTypeKill <Reg:f14> BB06 regmask=[f14] minReg=1 last>
<RefPosition #232 @210 RefTypeKill <Reg:f15> BB06 regmask=[f15] minReg=1 last>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[r0] minReg=1 fixed>
<RefPosition #192 @171 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
--- V01
<RefPosition #3 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[r1] minReg=1 fixed>
<RefPosition #204 @201 RefTypeUse <Ivl:1 V01> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
--- V02
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r2] minReg=1 fixed>
<RefPosition #37 @66 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #174 @143 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[r1] minReg=1 last fixed>
--- V03
<RefPosition #1 @0 RefTypeParamDef <Ivl:3 V03> BB00 regmask=[r3] minReg=1 fixed>
<RefPosition #203 @195 RefTypeUse <Ivl:3 V03> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
--- V04
<RefPosition #5 @0 RefTypeParamDef <Ivl:4 V04> BB00 regmask=[allInt] minReg=1>
<RefPosition #7 @7 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
--- V05
<RefPosition #4 @0 RefTypeParamDef <Ivl:5 V05> BB00 regmask=[allInt] minReg=1>
<RefPosition #198 @185 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #202 @195 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
--- V06
--- V07
--- V08
--- V09
<RefPosition #42 @74 RefTypeDef <Ivl:6 V09> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #44 @77 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #92 @95 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
--- V10
<RefPosition #90 @92 RefTypeDef <Ivl:7 V10> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #109 @109 RefTypeUse <Ivl:7 V10> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
--- V11
<RefPosition #120 @118 RefTypeDef <Ivl:8 V11> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #122 @121 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #170 @139 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 last fixed>
--- V12
<RefPosition #168 @136 RefTypeDef <Ivl:9 V12> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #181 @147 RefTypeUse <Ivl:9 V12> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
--- V13
<RefPosition #28 @48 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #30 @55 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #34 @63 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
--- V14
<RefPosition #10 @10 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @15 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #189 @157 RefTypeUse <Ivl:11 V14> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
--- V15
<RefPosition #21 @38 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #96 @99 RefTypeUse <Ivl:12 V15> LCL_VAR BB02 regmask=[r2] minReg=1 last fixed>
--- V16
<RefPosition #23 @40 RefTypeDef <Ivl:13 V16> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #100 @103 RefTypeUse <Ivl:13 V16> LCL_VAR BB02 regmask=[r3] minReg=1 last fixed>
--- V17
<RefPosition #17 @28 RefTypeDef <Ivl:14 V17> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #18 @35 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @37 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
--------------------------------+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |
--------------------------------+----+----+----+----+----+----+
|V0 a|V1 a|V2 a|V3 a| | |
0.#0 V0 Parm Alloc r4 | |V1 a|V2 a|V3 a|V0 a| |
0.#1 V3 Parm Alloc r5 | |V1 a|V2 a| |V0 a|V3 a|
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |
--------------------------------+----+----+----+----+----+----+----+
0.#2 V2 Parm Alloc r6 | |V1 a| | |V0 a|V3 a|V2 a|
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |
--------------------------------+----+----+----+----+----+----+----+----+
0.#3 V1 Parm Alloc r7 | | | | |V0 a|V3 a|V2 a|V1 a|
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |
--------------------------------+----+----+----+----+----+----+----+----+----+
0.#4 V5 Parm Alloc r8 | | | | |V0 a|V3 a|V2 a|V1 a|V5 a|
0.#5 V4 Parm Alloc r0 |V4 a| | | |V0 a|V3 a|V2 a|V1 a|V5 a|
1.#6 BB1 PredBB0 |V4 a| | | |V0 a|V3 a|V2 a|V1 a|V5 a|
7.#7 V4 Use * Keep r0 |V4 a| | | |V0 a|V3 a|V2 a|V1 a|V5 a|
--------------------------------+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+
8.#8 I15 Def Alloc r9 | | | | |V0 a|V3 a|V2 a|V1 a|V5 a|I15a|
9.#9 I15 Use * Keep r9 | | | | |V0 a|V3 a|V2 a|V1 a|V5 a|I15a|
10.#10 V14 Def Alloc r9 | | | | |V0 a|V3 a|V2 a|V1 a|V5 a|V14a|
15.#11 V14 Use Keep r9 | | | | |V0 a|V3 a|V2 a|V1 a|V5 a|V14a|
--------------------------------+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+
19.#12 BB2 PredBB1 | | | | |V0 a|V3 a|V2 i|V1 a|V5 a|V14a|
24.#13 I16 Def Alloc r0 |I16a| | | |V0 a|V3 a|V2 i|V1 a|V5 a|V14a|
25.#14 I16 Use * Keep r0 |I16a| | | |V0 a|V3 a|V2 i|V1 a|V5 a|V14a|
26.#15 I17 Def Alloc r0 |I17a| | | |V0 a|V3 a|V2 i|V1 a|V5 a|V14a|
27.#16 I17 Use * Keep r0 |I17a| | | |V0 a|V3 a|V2 i|V1 a|V5 a|V14a|
28.#17 V17 Def Alloc r0 |V17a| | | |V0 a|V3 a|V2 i|V1 a|V5 a|V14a|
35.#18 V17 Use Keep r0 |V17a| | | |V0 a|V3 a|V2 i|V1 a|V5 a|V14a|
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+
36.#19 I18 Def Alloc r10 |V17a| | | |V0 a|V3 a|V2 i|V1 a|V5 a|V14a|I18a|
37.#20 V17 Use * Keep r0 |V17a| | | |V0 a|V3 a|V2 i|V1 a|V5 a|V14a|I18a|
38.#21 V15 Def Alloc r6 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|I18a|
39.#22 I18 Use * Keep r10 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|I18a|
40.#23 V16 Def Alloc r10 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
44.#24 I19 Def Alloc r0 |I19a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
45.#25 I19 Use * Keep r0 |I19a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
46.#26 I20 Def Alloc r0 |I20a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
47.#27 I20 Use * Keep r0 |I20a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
48.#28 V13 Def Alloc r0 |V13a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
50.#29 C21 Def Alloc r1 |V13a|C21a| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
55.#30 V13 Use Keep r0 |V13a|C21a| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
56.#31 I22 Def Alloc r2 |V13a|C21a|I22a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
57.#32 C21 Use * Keep r1 |V13a|C21a|I22a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
57.#33 I22 Use * Keep r2 |V13a|C21a|I22a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
63.#34 V13 Use * Keep r0 |V13a|C21i| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
64.#35 I23 Def Alloc r0 |I23a|C21i| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
65.#36 I23 Use * Keep r0 |I23a|C21i| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
66.#37 V2 Def Alloc r3 | |C21i| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
70.#38 I24 Def Alloc r0 |I24a|C21i| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
71.#39 I24 Use * Keep r0 |I24a|C21i| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+
72.#40 I25 Def Alloc lr | |C21i| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|I25a|
73.#41 I25 Use * Keep lr | |C21i| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|I25a|
74.#42 V9 Def Alloc lr | |C21i| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
77.#43 r0 Fixd Keep r0 | |C21i| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
77.#44 V9 Use Copy r0 |V9 a|C21i| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
78.#45 r0 Fixd Keep r0 |V9 a|C21i| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
78.#46 I26 Def Alloc r0 |I26a|C21i| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
80.#47 C27 Def Alloc r1 |I26a|C27a| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
81.#48 r1 Fixd Keep r1 |I26a|C27a| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
81.#49 C27 Use * Keep r1 |I26a|C27a| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
82.#50 r1 Fixd Keep r1 |I26a| | |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
82.#51 I28 Def Alloc r1 |I26a|I28a| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
84.#52 C29 Def Alloc r2 |I26a|I28a|C29a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
85.#53 r2 Fixd Keep r2 |I26a|I28a|C29a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
85.#54 C29 Use * Keep r2 |I26a|I28a|C29a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
86.#55 r2 Fixd Keep r2 |I26a|I28a| |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
86.#56 I30 Def Alloc r2 |I26a|I28a|I30a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|V9 a|
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
88.#57 C31 Def Alloc r12 |I26a|I28a|I30a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a|V9 a|
89.#58 r0 Fixd Keep r0 |I26a|I28a|I30a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a|V9 a|
89.#59 I26 Use * Keep r0 |I26a|I28a|I30a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a|V9 a|
89.#60 r1 Fixd Keep r1 |I26a|I28a|I30a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a|V9 a|
89.#61 I28 Use * Keep r1 |I26a|I28a|I30a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a|V9 a|
89.#62 r2 Fixd Keep r2 |I26a|I28a|I30a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a|V9 a|
89.#63 I30 Use * Keep r2 |I26a|I28a|I30a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a|V9 a|
89.#64 C31 Use * Keep r12 |I26a|I28a|I30a|V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a|V9 a|
90.#65 r0 Kill Keep r0 | | | |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31i|V9 a|
90.#66 r1 Kill Keep r1 | | | |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31i|V9 a|
90.#67 r2 Kill Keep r2 | | | |V2 a|V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31i|V9 a|
90.#68 r3 Kill Spill r3 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31i|V9 a|
Keep r3 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31i|V9 a|
90.#69 r12 Kill Keep r12 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| |V9 a|
90.#70 lr Kill Spill lr | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
Keep lr | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#71 f0 Kill Keep f0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#72 f1 Kill Keep f1 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#73 f2 Kill Keep f2 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#74 f3 Kill Keep f3 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#75 f4 Kill Keep f4 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#76 f5 Kill Keep f5 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#77 f6 Kill Keep f6 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#78 f7 Kill Keep f7 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#79 f8 Kill Keep f8 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#80 f9 Kill Keep f9 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#81 f10 Kill Keep f10 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#82 f11 Kill Keep f11 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#83 f12 Kill Keep f12 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#84 f13 Kill Keep f13 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#85 f14 Kill Keep f14 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#86 f15 Kill Keep f15 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#87 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#88 I32 Def Alloc r0 |I32a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
91.#89 I32 Use * Keep r0 |I32a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
92.#90 V10 Def Alloc r0 |V10a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
95.#91 r0 Fixd Keep r0 |V10a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
95.#92 V9 Use * ReLod NA |V10a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
Spill r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
Steal r0 |V9 a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
96.#93 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
96.#94 I33 Def Alloc r0 |I33a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
99.#95 r2 Fixd Keep r2 |I33a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
99.#96 V15 Use * Copy r2 |I33a| |V15a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
100.#97 r2 Fixd Keep r2 |I33a| | | |V0 a|V3 a| |V1 a|V5 a|V14a|V16a| | |
100.#98 I34 Def Alloc r2 |I33a| |I34a| |V0 a|V3 a| |V1 a|V5 a|V14a|V16a| | |
103.#99 r3 Fixd Keep r3 |I33a| |I34a| |V0 a|V3 a| |V1 a|V5 a|V14a|V16a| | |
103.#100 V16 Use * Copy r3 |I33a| |I34a|V16a|V0 a|V3 a| |V1 a|V5 a|V14a|V16a| | |
104.#101 r3 Fixd Keep r3 |I33a| |I34a| |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
104.#102 I35 Def Alloc r3 |I33a| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#103 r0 Fixd Keep r0 |I33a| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
109.#104 I33 Use * Keep r0 |I33a| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#105 r2 Fixd Keep r2 |I33a| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#106 I34 Use * Keep r2 |I33a| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#107 r3 Fixd Keep r3 |I33a| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#108 I35 Use * Keep r3 |I33a| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#109 V10 Use * ReLod NA |I33a| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
Alloc r1 |I33a|V10a|I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#110 r0 Kill Keep r0 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#111 r1 Kill Keep r1 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#112 r2 Kill Keep r2 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#113 r3 Kill Keep r3 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#114 r12 Kill Keep r12 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#115 lr Kill Keep lr | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
114.#116 I36 Def Alloc r0 |I36a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
115.#117 I36 Use * Keep r0 |I36a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
116.#118 I37 Def Alloc r6 | | | | |V0 a|V3 a|I37a|V1 a|V5 a|V14a| | | |
117.#119 I37 Use * Keep r6 | | | | |V0 a|V3 a|I37a|V1 a|V5 a|V14a| | | |
118.#120 V11 Def Alloc r6 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
121.#121 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
121.#122 V11 Use Copy r0 |V11a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
122.#123 r0 Fixd Keep r0 |V11a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
122.#124 I38 Def Alloc r0 |I38a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
124.#125 C39 Def Alloc r1 |I38a|C39a| | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
125.#126 r1 Fixd Keep r1 |I38a|C39a| | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
125.#127 C39 Use * Keep r1 |I38a|C39a| | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
126.#128 r1 Fixd Keep r1 |I38a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
126.#129 I40 Def Alloc r1 |I38a|I40a| | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
128.#130 C41 Def Alloc r2 |I38a|I40a|C41a| |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
129.#131 r2 Fixd Keep r2 |I38a|I40a|C41a| |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
129.#132 C41 Use * Keep r2 |I38a|I40a|C41a| |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
130.#133 r2 Fixd Keep r2 |I38a|I40a| | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
130.#134 I42 Def Alloc r2 |I38a|I40a|I42a| |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
132.#135 C43 Def Alloc r3 |I38a|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#136 r0 Fixd Keep r0 |I38a|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#137 I38 Use * Keep r0 |I38a|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#138 r1 Fixd Keep r1 |I38a|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#139 I40 Use * Keep r1 |I38a|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#140 r2 Fixd Keep r2 |I38a|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#141 I42 Use * Keep r2 |I38a|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#142 C43 Use * Keep r3 |I38a|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#143 r0 Kill Keep r0 | | | |C43i|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#144 r1 Kill Keep r1 | | | |C43i|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#145 r2 Kill Keep r2 | | | |C43i|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#146 r3 Kill Keep r3 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#147 r12 Kill Keep r12 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#148 lr Kill Keep lr | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#149 f0 Kill Keep f0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#150 f1 Kill Keep f1 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#151 f2 Kill Keep f2 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#152 f3 Kill Keep f3 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#153 f4 Kill Keep f4 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#154 f5 Kill Keep f5 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#155 f6 Kill Keep f6 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#156 f7 Kill Keep f7 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#157 f8 Kill Keep f8 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#158 f9 Kill Keep f9 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#159 f10 Kill Keep f10 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#160 f11 Kill Keep f11 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#161 f12 Kill Keep f12 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#162 f13 Kill Keep f13 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#163 f14 Kill Keep f14 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#164 f15 Kill Keep f15 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#165 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
134.#166 I44 Def Alloc r0 |I44a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
135.#167 I44 Use * Keep r0 |I44a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
136.#168 V12 Def Alloc r0 |V12a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
139.#169 r0 Fixd Keep r0 |V12a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
139.#170 V11 Use * Spill r0 | | | | |V0 a|V3 a|V11i|V1 a|V5 a|V14a| | | |
Copy r0 |V11a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
140.#171 r0 Fixd Keep r0 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
140.#172 I45 Def Alloc r0 |I45a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
143.#173 r1 Fixd Keep r1 |I45a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
143.#174 V2 Use * ReLod NA |I45a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
Alloc r1 |I45a|V2 a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
144.#175 r1 Fixd Keep r1 |I45a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
144.#176 I46 Def Alloc r1 |I45a|I46a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
147.#177 r0 Fixd Keep r0 |I45a|I46a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
147.#178 I45 Use * Keep r0 |I45a|I46a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
147.#179 r1 Fixd Keep r1 |I45a|I46a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
147.#180 I46 Use * Keep r1 |I45a|I46a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
147.#181 V12 Use * ReLod NA |I45a|I46a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
Alloc r3 |I45a|I46a| |V12a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#182 r0 Kill Keep r0 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#183 r1 Kill Keep r1 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#184 r2 Kill Keep r2 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#185 r3 Kill Keep r3 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#186 r12 Kill Keep r12 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#187 lr Kill Keep lr | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
149.#188 BB3 PredBB1 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
157.#189 V14 Use * Keep r9 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
161.#190 BB4 PredBB3 | | | | |V0 a|V3 a| |V1 a|V5 a| | | | |
166.#191 C47 Def Alloc r0 |C47a| | | |V0 a|V3 a| |V1 a|V5 a| | | | |
171.#192 V0 Use * Keep r4 |C47a| | | |V0 a|V3 a| |V1 a|V5 a| | | | |
172.#193 I48 Def Alloc r3 |C47a| | |I48a| |V3 a| |V1 a|V5 a| | | | |
173.#194 C47 Use * Keep r0 |C47a| | |I48a| |V3 a| |V1 a|V5 a| | | | |
173.#195 I48 Use * Keep r3 |C47a| | |I48a| |V3 a| |V1 a|V5 a| | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
175.#196 BB5 PredBB3 | | | | | |V3 a| |V1 a|V5 a| | | | |
180.#197 C49 Def Alloc r0 |C49a| | | | |V3 a| |V1 a|V5 a| | | | |
185.#198 V5 Use Keep r8 |C49a| | | | |V3 a| |V1 a|V5 a| | | | |
186.#199 I50 Def Alloc r3 |C49a| | |I50a| |V3 a| |V1 a|V5 a| | | | |
187.#200 C49 Use * Keep r0 |C49a| | |I50a| |V3 a| |V1 a|V5 a| | | | |
187.#201 I50 Use * Keep r3 |C49a| | |I50a| |V3 a| |V1 a|V5 a| | | | |
195.#202 V5 Use * Keep r8 |C49i| | | | |V3 a| |V1 a|V5 a| | | | |
195.#203 V3 Use * Keep r5 |C49i| | | | |V3 a| |V1 a|V5 a| | | | |
201.#204 V1 Use * Keep r7 |C49i| | | | | | |V1 a| | | | | |
202.#205 I51 Def Alloc r0 |I51a| | | | | | | | | | | | |
203.#206 r0 Fixd Keep r0 |I51a| | | | | | | | | | | | |
203.#207 I51 Use * Keep r0 |I51a| | | | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
205.#208 BB6 PredBB5 | | | | | | | | | | | | | |
208.#209 C52 Def Alloc r3 | | | |C52a| | | | | | | | | |
209.#210 C52 Use * Keep r3 | | | |C52a| | | | | | | | | |
210.#211 r0 Kill Keep r0 | | | |C52i| | | | | | | | | |
210.#212 r1 Kill Keep r1 | | | |C52i| | | | | | | | | |
210.#213 r2 Kill Keep r2 | | | |C52i| | | | | | | | | |
210.#214 r3 Kill Keep r3 | | | | | | | | | | | | | |
210.#215 r12 Kill Keep r12 | | | | | | | | | | | | | |
210.#216 lr Kill Keep lr | | | | | | | | | | | | | |
210.#217 f0 Kill Keep f0 | | | | | | | | | | | | | |
210.#218 f1 Kill Keep f1 | | | | | | | | | | | | | |
210.#219 f2 Kill Keep f2 | | | | | | | | | | | | | |
210.#220 f3 Kill Keep f3 | | | | | | | | | | | | | |
210.#221 f4 Kill Keep f4 | | | | | | | | | | | | | |
210.#222 f5 Kill Keep f5 | | | | | | | | | | | | | |
210.#223 f6 Kill Keep f6 | | | | | | | | | | | | | |
210.#224 f7 Kill Keep f7 | | | | | | | | | | | | | |
210.#225 f8 Kill Keep f8 | | | | | | | | | | | | | |
210.#226 f9 Kill Keep f9 | | | | | | | | | | | | | |
210.#227 f10 Kill Keep f10 | | | | | | | | | | | | | |
210.#228 f11 Kill Keep f11 | | | | | | | | | | | | | |
210.#229 f12 Kill Keep f12 | | | | | | | | | | | | | |
210.#230 f13 Kill Keep f13 | | | | | | | | | | | | | |
210.#231 f14 Kill Keep f14 | | | | | | | | | | | | | |
210.#232 f15 Kill Keep f15 | | | | | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[r4] minReg=1 fixed>
<RefPosition #1 @0 RefTypeParamDef <Ivl:3 V03> BB00 regmask=[r5] minReg=1 fixed>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r6] minReg=1 fixed>
<RefPosition #3 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[r7] minReg=1 fixed>
<RefPosition #4 @0 RefTypeParamDef <Ivl:5 V05> BB00 regmask=[r8] minReg=1>
<RefPosition #5 @0 RefTypeParamDef <Ivl:4 V04> BB00 regmask=[r0] minReg=1>
<RefPosition #6 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #7 @7 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[r0] minReg=1 last>
<RefPosition #8 @8 RefTypeDef <Ivl:15> CAST BB01 regmask=[r9] minReg=1>
<RefPosition #9 @9 RefTypeUse <Ivl:15> BB01 regmask=[r9] minReg=1 last>
<RefPosition #10 @10 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[r9] minReg=1>
<RefPosition #11 @15 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[r9] minReg=1>
<RefPosition #12 @19 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #13 @24 RefTypeDef <Ivl:16> CLS_VAR_ADDR BB02 regmask=[r0] minReg=1>
<RefPosition #14 @25 RefTypeUse <Ivl:16> BB02 regmask=[r0] minReg=1 last>
<RefPosition #15 @26 RefTypeDef <Ivl:17> IND BB02 regmask=[r0] minReg=1>
<RefPosition #16 @27 RefTypeUse <Ivl:17> BB02 regmask=[r0] minReg=1 last>
<RefPosition #17 @28 RefTypeDef <Ivl:14 V17> STORE_LCL_VAR BB02 regmask=[r0] minReg=1>
<RefPosition #18 @35 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[r0] minReg=1>
<RefPosition #19 @36 RefTypeDef <Ivl:18> RSH BB02 regmask=[r10] minReg=1>
<RefPosition #20 @37 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[r0] minReg=1 last>
<RefPosition #21 @38 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB02 regmask=[r6] minReg=1>
<RefPosition #22 @39 RefTypeUse <Ivl:18> BB02 regmask=[r10] minReg=1 last>
<RefPosition #23 @40 RefTypeDef <Ivl:13 V16> STORE_LCL_VAR BB02 regmask=[r10] minReg=1>
<RefPosition #24 @44 RefTypeDef <Ivl:19> CLS_VAR_ADDR BB02 regmask=[r0] minReg=1>
<RefPosition #25 @45 RefTypeUse <Ivl:19> BB02 regmask=[r0] minReg=1 last>
<RefPosition #26 @46 RefTypeDef <Ivl:20> IND BB02 regmask=[r0] minReg=1>
<RefPosition #27 @47 RefTypeUse <Ivl:20> BB02 regmask=[r0] minReg=1 last>
<RefPosition #28 @48 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB02 regmask=[r0] minReg=1>
<RefPosition #29 @50 RefTypeDef <Ivl:21> CNS_INT BB02 regmask=[r1] minReg=1>
<RefPosition #30 @55 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[r0] minReg=1>
<RefPosition #31 @56 RefTypeDef <Ivl:22> IND BB02 regmask=[r2] minReg=1>
<RefPosition #32 @57 RefTypeUse <Ivl:21> BB02 regmask=[r1] minReg=1 last>
<RefPosition #33 @57 RefTypeUse <Ivl:22> BB02 regmask=[r2] minReg=1 last>
<RefPosition #34 @63 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[r0] minReg=1 last>
<RefPosition #35 @64 RefTypeDef <Ivl:23> IND BB02 regmask=[r0] minReg=1>
<RefPosition #36 @65 RefTypeUse <Ivl:23> BB02 regmask=[r0] minReg=1 last>
<RefPosition #37 @66 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB02 regmask=[r3] minReg=1 spillAfter>
<RefPosition #38 @70 RefTypeDef <Ivl:24> CLS_VAR_ADDR BB02 regmask=[r0] minReg=1>
<RefPosition #39 @71 RefTypeUse <Ivl:24> BB02 regmask=[r0] minReg=1 last>
<RefPosition #40 @72 RefTypeDef <Ivl:25> IND BB02 regmask=[lr] minReg=1>
<RefPosition #41 @73 RefTypeUse <Ivl:25> BB02 regmask=[lr] minReg=1 last>
<RefPosition #42 @74 RefTypeDef <Ivl:6 V09> STORE_LCL_VAR BB02 regmask=[lr] minReg=1>
<RefPosition #43 @77 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #44 @77 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 spillAfter copy fixed>
<RefPosition #45 @78 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #46 @78 RefTypeDef <Ivl:26> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #47 @80 RefTypeDef <Ivl:27> CNS_INT BB02 regmask=[r1] minReg=1>
<RefPosition #48 @81 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #49 @81 RefTypeUse <Ivl:27> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #50 @82 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #51 @82 RefTypeDef <Ivl:28> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
<RefPosition #52 @84 RefTypeDef <Ivl:29> CNS_INT BB02 regmask=[r2] minReg=1>
<RefPosition #53 @85 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #54 @85 RefTypeUse <Ivl:29> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #55 @86 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #56 @86 RefTypeDef <Ivl:30> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
<RefPosition #57 @88 RefTypeDef <Ivl:31> CNS_INT BB02 regmask=[r12] minReg=1>
<RefPosition #58 @89 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #59 @89 RefTypeUse <Ivl:26> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #60 @89 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #61 @89 RefTypeUse <Ivl:28> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #62 @89 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #63 @89 RefTypeUse <Ivl:30> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #64 @89 RefTypeUse <Ivl:31> BB02 regmask=[r12] minReg=1 last>
<RefPosition #65 @90 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #66 @90 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #67 @90 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #68 @90 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #69 @90 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #70 @90 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #71 @90 RefTypeKill <Reg:f0 > BB02 regmask=[f0] minReg=1 last>
<RefPosition #72 @90 RefTypeKill <Reg:f1 > BB02 regmask=[f1] minReg=1 last>
<RefPosition #73 @90 RefTypeKill <Reg:f2 > BB02 regmask=[f2] minReg=1 last>
<RefPosition #74 @90 RefTypeKill <Reg:f3 > BB02 regmask=[f3] minReg=1 last>
<RefPosition #75 @90 RefTypeKill <Reg:f4 > BB02 regmask=[f4] minReg=1 last>
<RefPosition #76 @90 RefTypeKill <Reg:f5 > BB02 regmask=[f5] minReg=1 last>
<RefPosition #77 @90 RefTypeKill <Reg:f6 > BB02 regmask=[f6] minReg=1 last>
<RefPosition #78 @90 RefTypeKill <Reg:f7 > BB02 regmask=[f7] minReg=1 last>
<RefPosition #79 @90 RefTypeKill <Reg:f8 > BB02 regmask=[f8] minReg=1 last>
<RefPosition #80 @90 RefTypeKill <Reg:f9 > BB02 regmask=[f9] minReg=1 last>
<RefPosition #81 @90 RefTypeKill <Reg:f10> BB02 regmask=[f10] minReg=1 last>
<RefPosition #82 @90 RefTypeKill <Reg:f11> BB02 regmask=[f11] minReg=1 last>
<RefPosition #83 @90 RefTypeKill <Reg:f12> BB02 regmask=[f12] minReg=1 last>
<RefPosition #84 @90 RefTypeKill <Reg:f13> BB02 regmask=[f13] minReg=1 last>
<RefPosition #85 @90 RefTypeKill <Reg:f14> BB02 regmask=[f14] minReg=1 last>
<RefPosition #86 @90 RefTypeKill <Reg:f15> BB02 regmask=[f15] minReg=1 last>
<RefPosition #87 @90 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #88 @90 RefTypeDef <Ivl:32> CALL BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #89 @91 RefTypeUse <Ivl:32> BB02 regmask=[r0] minReg=1 last>
<RefPosition #90 @92 RefTypeDef <Ivl:7 V10> STORE_LCL_VAR BB02 regmask=[r0] minReg=1 spillAfter>
<RefPosition #91 @95 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #92 @95 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 last reload fixed>
<RefPosition #93 @96 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #94 @96 RefTypeDef <Ivl:33> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #95 @99 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #96 @99 RefTypeUse <Ivl:12 V15> LCL_VAR BB02 regmask=[r2] minReg=1 last copy fixed>
<RefPosition #97 @100 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #98 @100 RefTypeDef <Ivl:34> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
<RefPosition #99 @103 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #100 @103 RefTypeUse <Ivl:13 V16> LCL_VAR BB02 regmask=[r3] minReg=1 last copy fixed>
<RefPosition #101 @104 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #102 @104 RefTypeDef <Ivl:35> PUTARG_REG BB02 regmask=[r3] minReg=1 fixed>
<RefPosition #103 @109 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #104 @109 RefTypeUse <Ivl:33> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #105 @109 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #106 @109 RefTypeUse <Ivl:34> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #107 @109 RefTypeFixedReg <Reg:r3 > BB02 regmask=[r3] minReg=1>
<RefPosition #108 @109 RefTypeUse <Ivl:35> BB02 regmask=[r3] minReg=1 last fixed>
<RefPosition #109 @109 RefTypeUse <Ivl:7 V10> LCL_VAR BB02 regmask=[r1] minReg=1 last reload>
<RefPosition #110 @110 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #111 @110 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #112 @110 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #113 @110 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #114 @110 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #115 @110 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #116 @114 RefTypeDef <Ivl:36> CLS_VAR_ADDR BB02 regmask=[r0] minReg=1>
<RefPosition #117 @115 RefTypeUse <Ivl:36> BB02 regmask=[r0] minReg=1 last>
<RefPosition #118 @116 RefTypeDef <Ivl:37> IND BB02 regmask=[r6] minReg=1>
<RefPosition #119 @117 RefTypeUse <Ivl:37> BB02 regmask=[r6] minReg=1 last>
<RefPosition #120 @118 RefTypeDef <Ivl:8 V11> STORE_LCL_VAR BB02 regmask=[r6] minReg=1>
<RefPosition #121 @121 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #122 @121 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 copy fixed>
<RefPosition #123 @122 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #124 @122 RefTypeDef <Ivl:38> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #125 @124 RefTypeDef <Ivl:39> CNS_INT BB02 regmask=[r1] minReg=1>
<RefPosition #126 @125 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #127 @125 RefTypeUse <Ivl:39> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #128 @126 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #129 @126 RefTypeDef <Ivl:40> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
<RefPosition #130 @128 RefTypeDef <Ivl:41> CNS_INT BB02 regmask=[r2] minReg=1>
<RefPosition #131 @129 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #132 @129 RefTypeUse <Ivl:41> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #133 @130 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #134 @130 RefTypeDef <Ivl:42> PUTARG_REG BB02 regmask=[r2] minReg=1 fixed>
<RefPosition #135 @132 RefTypeDef <Ivl:43> CNS_INT BB02 regmask=[r3] minReg=1>
<RefPosition #136 @133 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #137 @133 RefTypeUse <Ivl:38> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #138 @133 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #139 @133 RefTypeUse <Ivl:40> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #140 @133 RefTypeFixedReg <Reg:r2 > BB02 regmask=[r2] minReg=1>
<RefPosition #141 @133 RefTypeUse <Ivl:42> BB02 regmask=[r2] minReg=1 last fixed>
<RefPosition #142 @133 RefTypeUse <Ivl:43> BB02 regmask=[r3] minReg=1 last>
<RefPosition #143 @134 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #144 @134 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #145 @134 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #146 @134 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #147 @134 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #148 @134 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #149 @134 RefTypeKill <Reg:f0 > BB02 regmask=[f0] minReg=1 last>
<RefPosition #150 @134 RefTypeKill <Reg:f1 > BB02 regmask=[f1] minReg=1 last>
<RefPosition #151 @134 RefTypeKill <Reg:f2 > BB02 regmask=[f2] minReg=1 last>
<RefPosition #152 @134 RefTypeKill <Reg:f3 > BB02 regmask=[f3] minReg=1 last>
<RefPosition #153 @134 RefTypeKill <Reg:f4 > BB02 regmask=[f4] minReg=1 last>
<RefPosition #154 @134 RefTypeKill <Reg:f5 > BB02 regmask=[f5] minReg=1 last>
<RefPosition #155 @134 RefTypeKill <Reg:f6 > BB02 regmask=[f6] minReg=1 last>
<RefPosition #156 @134 RefTypeKill <Reg:f7 > BB02 regmask=[f7] minReg=1 last>
<RefPosition #157 @134 RefTypeKill <Reg:f8 > BB02 regmask=[f8] minReg=1 last>
<RefPosition #158 @134 RefTypeKill <Reg:f9 > BB02 regmask=[f9] minReg=1 last>
<RefPosition #159 @134 RefTypeKill <Reg:f10> BB02 regmask=[f10] minReg=1 last>
<RefPosition #160 @134 RefTypeKill <Reg:f11> BB02 regmask=[f11] minReg=1 last>
<RefPosition #161 @134 RefTypeKill <Reg:f12> BB02 regmask=[f12] minReg=1 last>
<RefPosition #162 @134 RefTypeKill <Reg:f13> BB02 regmask=[f13] minReg=1 last>
<RefPosition #163 @134 RefTypeKill <Reg:f14> BB02 regmask=[f14] minReg=1 last>
<RefPosition #164 @134 RefTypeKill <Reg:f15> BB02 regmask=[f15] minReg=1 last>
<RefPosition #165 @134 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #166 @134 RefTypeDef <Ivl:44> CALL BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #167 @135 RefTypeUse <Ivl:44> BB02 regmask=[r0] minReg=1 last>
<RefPosition #168 @136 RefTypeDef <Ivl:9 V12> STORE_LCL_VAR BB02 regmask=[r0] minReg=1 spillAfter>
<RefPosition #169 @139 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #170 @139 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 last copy fixed>
<RefPosition #171 @140 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #172 @140 RefTypeDef <Ivl:45> PUTARG_REG BB02 regmask=[r0] minReg=1 fixed>
<RefPosition #173 @143 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #174 @143 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[r1] minReg=1 last reload fixed>
<RefPosition #175 @144 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #176 @144 RefTypeDef <Ivl:46> PUTARG_REG BB02 regmask=[r1] minReg=1 fixed>
<RefPosition #177 @147 RefTypeFixedReg <Reg:r0 > BB02 regmask=[r0] minReg=1>
<RefPosition #178 @147 RefTypeUse <Ivl:45> BB02 regmask=[r0] minReg=1 last fixed>
<RefPosition #179 @147 RefTypeFixedReg <Reg:r1 > BB02 regmask=[r1] minReg=1>
<RefPosition #180 @147 RefTypeUse <Ivl:46> BB02 regmask=[r1] minReg=1 last fixed>
<RefPosition #181 @147 RefTypeUse <Ivl:9 V12> LCL_VAR BB02 regmask=[r3] minReg=1 last reload>
<RefPosition #182 @148 RefTypeKill <Reg:r0 > BB02 regmask=[r0] minReg=1 last>
<RefPosition #183 @148 RefTypeKill <Reg:r1 > BB02 regmask=[r1] minReg=1 last>
<RefPosition #184 @148 RefTypeKill <Reg:r2 > BB02 regmask=[r2] minReg=1 last>
<RefPosition #185 @148 RefTypeKill <Reg:r3 > BB02 regmask=[r3] minReg=1 last>
<RefPosition #186 @148 RefTypeKill <Reg:r12> BB02 regmask=[r12] minReg=1 last>
<RefPosition #187 @148 RefTypeKill <Reg:lr > BB02 regmask=[lr] minReg=1 last>
<RefPosition #188 @149 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #189 @157 RefTypeUse <Ivl:11 V14> LCL_VAR BB03 regmask=[r9] minReg=1 last>
<RefPosition #190 @161 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #191 @166 RefTypeDef <Ivl:47> CNS_INT BB04 regmask=[r0] minReg=1>
<RefPosition #192 @171 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[r4] minReg=1 last>
<RefPosition #193 @172 RefTypeDef <Ivl:48> IND BB04 regmask=[r3] minReg=1>
<RefPosition #194 @173 RefTypeUse <Ivl:47> BB04 regmask=[r0] minReg=1 last>
<RefPosition #195 @173 RefTypeUse <Ivl:48> BB04 regmask=[r3] minReg=1 last>
<RefPosition #196 @175 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #197 @180 RefTypeDef <Ivl:49> CNS_INT BB05 regmask=[r0] minReg=1>
<RefPosition #198 @185 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[r8] minReg=1>
<RefPosition #199 @186 RefTypeDef <Ivl:50> IND BB05 regmask=[r3] minReg=1>
<RefPosition #200 @187 RefTypeUse <Ivl:49> BB05 regmask=[r0] minReg=1 last>
<RefPosition #201 @187 RefTypeUse <Ivl:50> BB05 regmask=[r3] minReg=1 last>
<RefPosition #202 @195 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[r8] minReg=1 last>
<RefPosition #203 @195 RefTypeUse <Ivl:3 V03> LCL_VAR BB05 regmask=[r5] minReg=1 last>
<RefPosition #204 @201 RefTypeUse <Ivl:1 V01> LCL_VAR BB05 regmask=[r7] minReg=1 last>
<RefPosition #205 @202 RefTypeDef <Ivl:51> CAST BB05 regmask=[r0] minReg=1>
<RefPosition #206 @203 RefTypeFixedReg <Reg:r0 > BB05 regmask=[r0] minReg=1>
<RefPosition #207 @203 RefTypeUse <Ivl:51> BB05 regmask=[r0] minReg=1 last fixed>
<RefPosition #208 @205 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #209 @208 RefTypeDef <Ivl:52> CNS_INT BB06 regmask=[r3] minReg=1>
<RefPosition #210 @209 RefTypeUse <Ivl:52> BB06 regmask=[r3] minReg=1 last>
<RefPosition #211 @210 RefTypeKill <Reg:r0 > BB06 regmask=[r0] minReg=1 last>
<RefPosition #212 @210 RefTypeKill <Reg:r1 > BB06 regmask=[r1] minReg=1 last>
<RefPosition #213 @210 RefTypeKill <Reg:r2 > BB06 regmask=[r2] minReg=1 last>
<RefPosition #214 @210 RefTypeKill <Reg:r3 > BB06 regmask=[r3] minReg=1 last>
<RefPosition #215 @210 RefTypeKill <Reg:r12> BB06 regmask=[r12] minReg=1 last>
<RefPosition #216 @210 RefTypeKill <Reg:lr > BB06 regmask=[lr] minReg=1 last>
<RefPosition #217 @210 RefTypeKill <Reg:f0 > BB06 regmask=[f0] minReg=1 last>
<RefPosition #218 @210 RefTypeKill <Reg:f1 > BB06 regmask=[f1] minReg=1 last>
<RefPosition #219 @210 RefTypeKill <Reg:f2 > BB06 regmask=[f2] minReg=1 last>
<RefPosition #220 @210 RefTypeKill <Reg:f3 > BB06 regmask=[f3] minReg=1 last>
<RefPosition #221 @210 RefTypeKill <Reg:f4 > BB06 regmask=[f4] minReg=1 last>
<RefPosition #222 @210 RefTypeKill <Reg:f5 > BB06 regmask=[f5] minReg=1 last>
<RefPosition #223 @210 RefTypeKill <Reg:f6 > BB06 regmask=[f6] minReg=1 last>
<RefPosition #224 @210 RefTypeKill <Reg:f7 > BB06 regmask=[f7] minReg=1 last>
<RefPosition #225 @210 RefTypeKill <Reg:f8 > BB06 regmask=[f8] minReg=1 last>
<RefPosition #226 @210 RefTypeKill <Reg:f9 > BB06 regmask=[f9] minReg=1 last>
<RefPosition #227 @210 RefTypeKill <Reg:f10> BB06 regmask=[f10] minReg=1 last>
<RefPosition #228 @210 RefTypeKill <Reg:f11> BB06 regmask=[f11] minReg=1 last>
<RefPosition #229 @210 RefTypeKill <Reg:f12> BB06 regmask=[f12] minReg=1 last>
<RefPosition #230 @210 RefTypeKill <Reg:f13> BB06 regmask=[f13] minReg=1 last>
<RefPosition #231 @210 RefTypeKill <Reg:f14> BB06 regmask=[f14] minReg=1 last>
<RefPosition #232 @210 RefTypeKill <Reg:f15> BB06 regmask=[f15] minReg=1 last>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[r4] minReg=1 fixed>
<RefPosition #192 @171 RefTypeUse <Ivl:0 V00> LCL_VAR BB04 regmask=[r4] minReg=1 last>
--- V01
<RefPosition #3 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[r7] minReg=1 fixed>
<RefPosition #204 @201 RefTypeUse <Ivl:1 V01> LCL_VAR BB05 regmask=[r7] minReg=1 last>
--- V02
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[r6] minReg=1 fixed>
<RefPosition #37 @66 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB02 regmask=[r3] minReg=1 spillAfter>
<RefPosition #174 @143 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[r1] minReg=1 last reload fixed>
--- V03
<RefPosition #1 @0 RefTypeParamDef <Ivl:3 V03> BB00 regmask=[r5] minReg=1 fixed>
<RefPosition #203 @195 RefTypeUse <Ivl:3 V03> LCL_VAR BB05 regmask=[r5] minReg=1 last>
--- V04
<RefPosition #5 @0 RefTypeParamDef <Ivl:4 V04> BB00 regmask=[r0] minReg=1>
<RefPosition #7 @7 RefTypeUse <Ivl:4 V04> LCL_VAR BB01 regmask=[r0] minReg=1 last>
--- V05
<RefPosition #4 @0 RefTypeParamDef <Ivl:5 V05> BB00 regmask=[r8] minReg=1>
<RefPosition #198 @185 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[r8] minReg=1>
<RefPosition #202 @195 RefTypeUse <Ivl:5 V05> LCL_VAR BB05 regmask=[r8] minReg=1 last>
--- V06
--- V07
--- V08
--- V09
<RefPosition #42 @74 RefTypeDef <Ivl:6 V09> STORE_LCL_VAR BB02 regmask=[lr] minReg=1>
<RefPosition #44 @77 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 spillAfter copy fixed>
<RefPosition #92 @95 RefTypeUse <Ivl:6 V09> LCL_VAR BB02 regmask=[r0] minReg=1 last reload fixed>
--- V10
<RefPosition #90 @92 RefTypeDef <Ivl:7 V10> STORE_LCL_VAR BB02 regmask=[r0] minReg=1 spillAfter>
<RefPosition #109 @109 RefTypeUse <Ivl:7 V10> LCL_VAR BB02 regmask=[r1] minReg=1 last reload>
--- V11
<RefPosition #120 @118 RefTypeDef <Ivl:8 V11> STORE_LCL_VAR BB02 regmask=[r6] minReg=1>
<RefPosition #122 @121 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 copy fixed>
<RefPosition #170 @139 RefTypeUse <Ivl:8 V11> LCL_VAR BB02 regmask=[r0] minReg=1 last copy fixed>
--- V12
<RefPosition #168 @136 RefTypeDef <Ivl:9 V12> STORE_LCL_VAR BB02 regmask=[r0] minReg=1 spillAfter>
<RefPosition #181 @147 RefTypeUse <Ivl:9 V12> LCL_VAR BB02 regmask=[r3] minReg=1 last reload>
--- V13
<RefPosition #28 @48 RefTypeDef <Ivl:10 V13> STORE_LCL_VAR BB02 regmask=[r0] minReg=1>
<RefPosition #30 @55 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[r0] minReg=1>
<RefPosition #34 @63 RefTypeUse <Ivl:10 V13> LCL_VAR BB02 regmask=[r0] minReg=1 last>
--- V14
<RefPosition #10 @10 RefTypeDef <Ivl:11 V14> STORE_LCL_VAR BB01 regmask=[r9] minReg=1>
<RefPosition #11 @15 RefTypeUse <Ivl:11 V14> LCL_VAR BB01 regmask=[r9] minReg=1>
<RefPosition #189 @157 RefTypeUse <Ivl:11 V14> LCL_VAR BB03 regmask=[r9] minReg=1 last>
--- V15
<RefPosition #21 @38 RefTypeDef <Ivl:12 V15> STORE_LCL_VAR BB02 regmask=[r6] minReg=1>
<RefPosition #96 @99 RefTypeUse <Ivl:12 V15> LCL_VAR BB02 regmask=[r2] minReg=1 last copy fixed>
--- V16
<RefPosition #23 @40 RefTypeDef <Ivl:13 V16> STORE_LCL_VAR BB02 regmask=[r10] minReg=1>
<RefPosition #100 @103 RefTypeUse <Ivl:13 V16> LCL_VAR BB02 regmask=[r3] minReg=1 last copy fixed>
--- V17
<RefPosition #17 @28 RefTypeDef <Ivl:14 V17> STORE_LCL_VAR BB02 regmask=[r0] minReg=1>
<RefPosition #18 @35 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[r0] minReg=1>
<RefPosition #20 @37 RefTypeUse <Ivl:14 V17> LCL_VAR BB02 regmask=[r0] minReg=1 last>
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V01 V03 V04 V05 V14}
Has Critical Edges
Prior to Resolution
BB01 use def in out
{V04}
{V14}
{V00 V01 V03 V04 V05}
{V00 V01 V03 V05 V14}
Var=Reg beg of BB01: V00=r4 V03=r5 V02=r6 V01=r7 V05=r8 V04=r0
Var=Reg end of BB01: V00=r4 V14=r9 V03=r5 V01=r7 V05=r8
BB02 use def in out
{}
{V02 V09 V10 V11 V12 V13 V15 V16 V17}
{V00 V01 V03 V05 V14}
{V00 V01 V03 V05 V14}
Var=Reg beg of BB02: V00=r4 V14=r9 V03=r5 V01=r7 V05=r8
Var=Reg end of BB02: V00=r4 V14=r9 V03=r5 V01=r7 V05=r8
BB03 use def in out
{V14}
{}
{V00 V01 V03 V05 V14}
{V00 V01 V03 V05}
Var=Reg beg of BB03: V00=r4 V14=r9 V03=r5 V01=r7 V05=r8
Var=Reg end of BB03: V00=r4 V03=r5 V01=r7 V05=r8
BB04 use def in out
{V00}
{}
{V00 V01 V03 V05}
{V01 V03 V05}
Var=Reg beg of BB04: V00=r4 V03=r5 V01=r7 V05=r8
Var=Reg end of BB04: V03=r5 V01=r7 V05=r8
BB05 use def in out
{V01 V03 V05}
{}
{V01 V03 V05}
{}
Var=Reg beg of BB05: V03=r5 V01=r7 V05=r8
Var=Reg end of BB05: none
BB06 use def in out
{}
{}
{}
{}
Var=Reg beg of BB06: none
Var=Reg end of BB06: none
RESOLVING EDGES
Set V00 argument initial register to r4
Set V01 argument initial register to r7
Set V02 argument initial register to r6
Set V03 argument initial register to r5
Set V04 argument initial register to r0
Set V05 argument initial register to r8
Trees after linear scan register allocator (LSRA)
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
BB06 [0005] 0 0 [???..???) (throw ) keep i internal rare label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
N003 ( 8, 8) [000005] ------------- IL_OFFSET void IL offset: 0x0 REG NA
N005 ( 2, 2) [000001] ------------- t1 = LCL_VAR int V04 arg4 u:2 r0 (last use) REG r0 $140
/--* t1 int
N007 ( 3, 3) [000085] ----------S-- t85 = * CAST int <- bool <- int REG r9 $200
/--* t85 int
N009 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0 r9 REG r9
N011 ( 1, 1) [000144] ------------- t144 = LCL_VAR int V14 cse0 r9 REG r9 $200
N013 ( 1, 1) [000002] -c----------- t2 = CNS_INT int 0 REG NA $40
/--* t144 int
+--* t2 int
N015 ( 6, 6) [000003] J------N--S-- * EQ void REG NA $201
N017 ( 8, 8) [000004] ------------- * JTRUE void REG NA
------------ BB02 [004..02C), preds={BB01} succs={BB03}
N021 ( 14, 17) [000034] ------------- IL_OFFSET void IL offset: 0x4 REG NA
N023 ( 6, 10) [000030] ----G-------- t30 = CLS_VAR_ADDR byref Hnd=0x9247f8 REG r0
/--* t30 byref
N025 (???,???) [000148] ----G-------- t148 = * IND int REG r0
/--* t148 int
N027 (???,???) [000164] DA--G-------- * STORE_LCL_VAR int V17 rat2 r0 REG r0
N029 (???,???) [000165] ------------- t165 = LCL_VAR int V17 rat2 r0 (last use) REG r0
N031 (???,???) [000166] ------------- t166 = LCL_VAR int V17 rat2 r0 REG r0
N033 (???,???) [000167] -c----------- t167 = CNS_INT int 31 REG NA
/--* t166 int
+--* t167 int
N035 (???,???) [000168] ------------- t168 = * RSH int REG r10
/--* t165 int
N037 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR int V15 rat0 r6 REG r6
/--* t168 int
N039 (???,???) [000170] D------------ * STORE_LCL_VAR int V16 rat1 r10 REG r10
N041 ( 19, 24) [000040] ------------- IL_OFFSET void IL offset: 0xb REG NA
N043 ( 6, 10) [000035] ----G-------- t35 = CLS_VAR_ADDR byref Hnd=0x924808 REG r0
/--* t35 byref
N045 (???,???) [000149] ----G-------- t149 = * IND ref REG r0
/--* t149 ref
N047 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3 r0 REG r0
N049 ( 1, 1) [000036] ------------- t36 = CNS_INT int 0 REG r1 $40
N051 ( 1, 1) [000088] ------------- t88 = LCL_VAR ref V13 tmp5 u:3 r0 REG r0 <l:$340, c:$380>
/--* t88 ref
N053 (???,???) [000173] -c----------- t173 = * LEA(b+4) byref REG NA
/--* t173 byref
N055 ( 3, 3) [000091] ---X--------- t91 = * IND int REG r2 <l:$3c1, c:$3c0>
/--* t36 int
+--* t91 int
N057 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
N059 ( 1, 1) [000089] ------------- t89 = LCL_VAR ref V13 tmp5 u:3 r0 (last use) REG r0 <l:$340, c:$380>
/--* t89 ref
N061 (???,???) [000174] -c----------- t174 = * LEA(b+8) byref REG NA
/--* t174 byref
N063 ( 5, 3) [000037] a---GO------- t37 = * IND ushort REG r0 <l:$203, c:$4c0>
/--* t37 ushort
N065 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3 NA REG NA
N067 ( 6, 10) [000050] ------------- IL_OFFSET void IL offset: 0x16 REG NA
N069 ( 6, 10) [000045] ----G-------- t45 = CLS_VAR_ADDR byref Hnd=0x9247d8 REG r0
/--* t45 byref
N071 (???,???) [000150] ----G-------- t150 = * IND ref REG lr
/--* t150 ref
N073 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3 lr REG lr
N075 ( 1, 1) [000052] ------------Z t52 = LCL_VAR ref V09 tmp1 u:3 lr REG lr <l:$349, c:$382>
/--* t52 ref
N077 (???,???) [000175] ------------- t175 = * PUTARG_REG ref REG r0
N079 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token REG r1 $244
/--* t53 int
N081 (???,???) [000176] ------------- t176 = * PUTARG_REG int REG r1
N083 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token REG r2 $245
/--* t54 int
N085 (???,???) [000177] ------------- t177 = * PUTARG_REG int REG r2
N087 ( 3, 7) [000178] ------------- t178 = CNS_INT(h) int 0xFDA55A0 ftn REG r12
/--* t175 ref arg0 in r0
+--* t176 int arg1 in r1
+--* t177 int arg2 in r2
+--* t178 int control expr
N089 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
/--* t58 int
N091 ( 27, 31) [000060] DA-XG-------- * STORE_LCL_VAR int V10 tmp2 d:3 NA REG NA
N093 ( 1, 1) [000051] ------------z t51 = LCL_VAR ref V09 tmp1 u:3 r0 (last use) REG r0 <l:$349, c:$382>
/--* t51 ref
N095 (???,???) [000179] ------------- t179 = * PUTARG_REG ref REG r0
N097 ( 3, 2) [000046] ------------- t46 = LCL_VAR int V15 rat0 r6 (last use) REG r6 <l:$2c1, c:$2c0>
/--* t46 int
N099 (???,???) [000182] ------------- t182 = * PUTARG_REG int REG r2
N101 (???,???) [000171] ------------- t171 = LCL_VAR int V16 rat1 r10 (last use) REG r10
/--* t171 int
N103 (???,???) [000183] ------------- t183 = * PUTARG_REG int REG r3
/--* t182 int
+--* t183 int
N105 (???,???) [000180] Hc----------- t180 = * FIELD_LIST int int at offset 0 REG NA
N107 ( 3, 2) [000062] ------------z t62 = LCL_VAR int V10 tmp2 u:3 r1 (last use) REG r1 $283
/--* t179 ref this in r0
+--* t180 int arg1 r2,r3
+--* t62 int calli tgt
N109 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
N111 ( 6, 10) [000070] ------------- IL_OFFSET void IL offset: 0x21 REG NA
N113 ( 6, 10) [000065] ----G-------- t65 = CLS_VAR_ADDR byref Hnd=0x9247d8 REG r0
/--* t65 byref
N115 (???,???) [000151] ----G-------- t151 = * IND ref REG r6
/--* t151 ref
N117 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3 r6 REG r6
N119 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 r6 REG r6 <l:$34b, c:$388>
/--* t72 ref
N121 (???,???) [000184] ------------- t184 = * PUTARG_REG ref REG r0
N123 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token REG r1 $244
/--* t73 int
N125 (???,???) [000185] ------------- t185 = * PUTARG_REG int REG r1
N127 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token REG r2 $246
/--* t74 int
N129 (???,???) [000186] ------------- t186 = * PUTARG_REG int REG r2
N131 ( 3, 7) [000187] ------------- t187 = CNS_INT(h) int 0xFDA55A0 ftn REG r3
/--* t184 ref arg0 in r0
+--* t185 int arg1 in r1
+--* t186 int arg2 in r2
+--* t187 int control expr
N133 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
/--* t78 int
N135 ( 27, 31) [000080] DA-XG-------- * STORE_LCL_VAR int V12 tmp4 d:3 NA REG NA
N137 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 r6 (last use) REG r6 <l:$34b, c:$388>
/--* t71 ref
N139 (???,???) [000188] ------------- t188 = * PUTARG_REG ref REG r0
N141 ( 2, 2) [000066] ------------z t66 = LCL_VAR int V02 arg2 u:3 r1 (last use) REG r1 <l:$203, c:$4c0>
/--* t66 int
N143 (???,???) [000189] ------------- t189 = * PUTARG_REG int REG r1
N145 ( 3, 2) [000082] ------------z t82 = LCL_VAR int V12 tmp4 u:3 r3 (last use) REG r3 $287
/--* t188 ref this in r0
+--* t189 int arg1 in r1
+--* t82 int calli tgt
N147 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
------------ BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N151 ( 5, 5) [000011] ------------- IL_OFFSET void IL offset: 0x2c REG NA
N153 ( 1, 1) [000146] ------------- t146 = LCL_VAR int V14 cse0 r9 (last use) REG r9 $200
N155 ( 1, 1) [000008] -c----------- t8 = CNS_INT int 0 REG NA $40
/--* t146 int
+--* t8 int
N157 ( 3, 3) [000009] J------N--S-- * NE void REG NA $207
N159 ( 5, 5) [000010] ------------- * JTRUE void REG NA
------------ BB04 [030..034), preds={BB03} succs={BB05}
N163 ( 13, 14) [000028] ------------- IL_OFFSET void IL offset: 0x30 REG NA
N165 ( 1, 1) [000024] ------------- t24 = CNS_INT int 0 REG r0 $40
N167 ( 1, 1) [000023] ------------- t23 = LCL_VAR ref V00 arg0 u:2 r4 (last use) REG r4 $80
/--* t23 ref
N169 (???,???) [000190] -c----------- t190 = * LEA(b+4) byref REG NA
/--* t190 byref
N171 ( 3, 3) [000123] ---X--------- t123 = * IND int REG r3 $3c2
/--* t24 int
+--* t123 int
N173 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
------------ BB05 [034..03B) (return), preds={BB03,BB04} succs={}
N177 ( 16, 17) [000018] ------------- IL_OFFSET void IL offset: 0x34 REG NA
N179 ( 1, 1) [000014] ------------- t14 = CNS_INT int 0 REG r0 $40
N181 ( 1, 1) [000013] ------------- t13 = LCL_VAR ref V05 arg5 u:2 r8 REG r8 $81
/--* t13 ref
N183 (???,???) [000192] -c----------- t192 = * LEA(b+4) byref REG NA
/--* t192 byref
N185 ( 3, 3) [000134] ---X--------- t134 = * IND int REG r3 $3c3
/--* t14 int
+--* t134 int
N187 ( 8, 11) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
N189 ( 1, 1) [000132] ------------- t132 = LCL_VAR ref V05 arg5 u:2 r8 (last use) REG r8 $81
/--* t132 ref
N191 (???,???) [000193] -c----------- t193 = * LEA(b+8) byref REG NA
N193 ( 2, 2) [000015] ------------- t15 = LCL_VAR int V03 arg3 u:2 r5 (last use) REG r5 $100
/--* t193 byref
+--* t15 int
N195 (???,???) [000152] -A-XGO------- * STOREIND byte REG NA
N197 ( 4, 4) [000021] ------------- IL_OFFSET void IL offset: 0x39 REG NA
N199 ( 2, 2) [000019] ------------- t19 = LCL_VAR int V01 arg1 u:2 r7 (last use) REG r7 $c0
/--* t19 int
N201 ( 3, 3) [000141] ------------- t141 = * CAST int <- ushort <- int REG r0 $20c
/--* t141 int
N203 ( 4, 4) [000020] ------------- * RETURN int REG NA $28a
------------ BB06 [???..???) (throw), preds={} succs={}
N207 ( 3, 7) [000194] ------------- t194 = CNS_INT(h) int 0xFDA7BB0 ftn REG r3
/--* t194 int control expr
N209 ( 16, 10) [000155] --CXG-------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
-------------------------------------------------------------------------------------------------------------------
Final allocation
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
0.#0 V0 Parm Alloc r4 | | | | |V0 a| | | | | | | | |
0.#1 V3 Parm Alloc r5 | | | | |V0 a|V3 a| | | | | | | |
0.#2 V2 Parm Alloc r6 | | | | |V0 a|V3 a|V2 a| | | | | | |
0.#3 V1 Parm Alloc r7 | | | | |V0 a|V3 a|V2 a|V1 a| | | | | |
0.#4 V5 Parm Alloc r8 | | | | |V0 a|V3 a|V2 a|V1 a|V5 a| | | | |
0.#5 V4 Parm Alloc r0 |V4 a| | | |V0 a|V3 a|V2 a|V1 a|V5 a| | | | |
1.#6 BB1 PredBB0 |V4 a| | | |V0 a|V3 a|V2 a|V1 a|V5 a| | | | |
7.#7 V4 Use * Keep r0 |V4 i| | | |V0 a|V3 a|V2 a|V1 a|V5 a| | | | |
8.#8 I15 Def Alloc r9 | | | | |V0 a|V3 a|V2 a|V1 a|V5 a|I15a| | | |
9.#9 I15 Use * Keep r9 | | | | |V0 a|V3 a|V2 a|V1 a|V5 a|I15i| | | |
10.#10 V14 Def Alloc r9 | | | | |V0 a|V3 a|V2 a|V1 a|V5 a|V14a| | | |
15.#11 V14 Use Keep r9 | | | | |V0 a|V3 a|V2 a|V1 a|V5 a|V14a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
19.#12 BB2 PredBB1 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
24.#13 I16 Def Alloc r0 |I16a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
25.#14 I16 Use * Keep r0 |I16i| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
26.#15 I17 Def Alloc r0 |I17a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
27.#16 I17 Use * Keep r0 |I17i| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
28.#17 V17 Def Alloc r0 |V17a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
35.#18 V17 Use Keep r0 |V17a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
36.#19 I18 Def Alloc r10 |V17a| | | |V0 a|V3 a| |V1 a|V5 a|V14a|I18a| | |
37.#20 V17 Use * Keep r0 |V17i| | | |V0 a|V3 a| |V1 a|V5 a|V14a|I18a| | |
38.#21 V15 Def Alloc r6 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|I18a| | |
39.#22 I18 Use * Keep r10 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|I18i| | |
40.#23 V16 Def Alloc r10 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
44.#24 I19 Def Alloc r0 |I19a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
45.#25 I19 Use * Keep r0 |I19i| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
46.#26 I20 Def Alloc r0 |I20a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
47.#27 I20 Use * Keep r0 |I20i| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
48.#28 V13 Def Alloc r0 |V13a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
50.#29 C21 Def Alloc r1 |V13a|C21a| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
55.#30 V13 Use Keep r0 |V13a|C21a| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
56.#31 I22 Def Alloc r2 |V13a|C21a|I22a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
57.#32 C21 Use * Keep r1 |V13a|C21i|I22a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
57.#33 I22 Use * Keep r2 |V13a| |I22i| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
63.#34 V13 Use * Keep r0 |V13i| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
64.#35 I23 Def Alloc r0 |I23a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
65.#36 I23 Use * Keep r0 |I23i| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
66.#37 V2 Def Alloc r3 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
Spill r3 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
70.#38 I24 Def Alloc r0 |I24a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
71.#39 I24 Use * Keep r0 |I24i| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
72.#40 I25 Def Alloc lr | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| |I25a|
73.#41 I25 Use * Keep lr | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| |I25i|
74.#42 V9 Def Alloc lr | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| |V9 a|
77.#43 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| |V9 a|
77.#44 V9 Use Copy r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| |V9 i|
Spill lr | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| |V9 i|
78.#45 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
78.#46 I26 Def Alloc r0 |I26a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
80.#47 C27 Def Alloc r1 |I26a|C27a| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
81.#48 r1 Fixd Keep r1 |I26a|C27a| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
81.#49 C27 Use * Keep r1 |I26a|C27i| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
82.#50 r1 Fixd Keep r1 |I26a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
82.#51 I28 Def Alloc r1 |I26a|I28a| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
84.#52 C29 Def Alloc r2 |I26a|I28a|C29a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
85.#53 r2 Fixd Keep r2 |I26a|I28a|C29a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
85.#54 C29 Use * Keep r2 |I26a|I28a|C29i| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
86.#55 r2 Fixd Keep r2 |I26a|I28a| | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
86.#56 I30 Def Alloc r2 |I26a|I28a|I30a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
88.#57 C31 Def Alloc r12 |I26a|I28a|I30a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a| |
89.#58 r0 Fixd Keep r0 |I26a|I28a|I30a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a| |
89.#59 I26 Use * Keep r0 |I26i|I28a|I30a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a| |
89.#60 r1 Fixd Keep r1 | |I28a|I30a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a| |
89.#61 I28 Use * Keep r1 | |I28i|I30a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a| |
89.#62 r2 Fixd Keep r2 | | |I30a| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a| |
89.#63 I30 Use * Keep r2 | | |I30i| |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31a| |
89.#64 C31 Use * Keep r12 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a|C31i| |
90.#65 r0 Kill Keep r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#66 r1 Kill Keep r1 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#67 r2 Kill Keep r2 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#68 r3 Kill Keep r3 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#69 r12 Kill Keep r12 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#70 lr Kill Keep lr | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#71 f0 Kill Keep f0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#72 f1 Kill Keep f1 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#73 f2 Kill Keep f2 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#74 f3 Kill Keep f3 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#75 f4 Kill Keep f4 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#76 f5 Kill Keep f5 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#77 f6 Kill Keep f6 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#78 f7 Kill Keep f7 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#79 f8 Kill Keep f8 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#80 f9 Kill Keep f9 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#81 f10 Kill Keep f10 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#82 f11 Kill Keep f11 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#83 f12 Kill Keep f12 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#84 f13 Kill Keep f13 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#85 f14 Kill Keep f14 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#86 f15 Kill Keep f15 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#87 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
90.#88 I32 Def Alloc r0 |I32a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
91.#89 I32 Use * Keep r0 |I32i| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
92.#90 V10 Def Alloc r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
Spill r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
95.#91 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
95.#92 V9 Use * ReLod r0 |V9 a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
Keep r0 |V9 i| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
96.#93 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
96.#94 I33 Def Alloc r0 |I33a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
99.#95 r2 Fixd Keep r2 |I33a| | | |V0 a|V3 a|V15a|V1 a|V5 a|V14a|V16a| | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
99.#96 V15 Use * Copy r2 |I33a| |V15i| |V0 a|V3 a|V15i|V1 a|V5 a|V14a|V16a| | |
100.#97 r2 Fixd Keep r2 |I33a| | | |V0 a|V3 a| |V1 a|V5 a|V14a|V16a| | |
100.#98 I34 Def Alloc r2 |I33a| |I34a| |V0 a|V3 a| |V1 a|V5 a|V14a|V16a| | |
103.#99 r3 Fixd Keep r3 |I33a| |I34a| |V0 a|V3 a| |V1 a|V5 a|V14a|V16a| | |
103.#100 V16 Use * Copy r3 |I33a| |I34a|V16i|V0 a|V3 a| |V1 a|V5 a|V14a|V16i| | |
104.#101 r3 Fixd Keep r3 |I33a| |I34a| |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
104.#102 I35 Def Alloc r3 |I33a| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#103 r0 Fixd Keep r0 |I33a| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#104 I33 Use * Keep r0 |I33i| |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#105 r2 Fixd Keep r2 | | |I34a|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#106 I34 Use * Keep r2 | | |I34i|I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#107 r3 Fixd Keep r3 | | | |I35a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#108 I35 Use * Keep r3 | | | |I35i|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
109.#109 V10 Use * ReLod r1 | |V10a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
Keep r1 | |V10i| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#110 r0 Kill Keep r0 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#111 r1 Kill Keep r1 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#112 r2 Kill Keep r2 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#113 r3 Kill Keep r3 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#114 r12 Kill Keep r12 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
110.#115 lr Kill Keep lr | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
114.#116 I36 Def Alloc r0 |I36a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
115.#117 I36 Use * Keep r0 |I36i| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
116.#118 I37 Def Alloc r6 | | | | |V0 a|V3 a|I37a|V1 a|V5 a|V14a| | | |
117.#119 I37 Use * Keep r6 | | | | |V0 a|V3 a|I37i|V1 a|V5 a|V14a| | | |
118.#120 V11 Def Alloc r6 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
121.#121 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
121.#122 V11 Use Copy r0 |V11a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
122.#123 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
122.#124 I38 Def Alloc r0 |I38a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
124.#125 C39 Def Alloc r1 |I38a|C39a| | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
125.#126 r1 Fixd Keep r1 |I38a|C39a| | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
125.#127 C39 Use * Keep r1 |I38a|C39i| | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
126.#128 r1 Fixd Keep r1 |I38a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
126.#129 I40 Def Alloc r1 |I38a|I40a| | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
128.#130 C41 Def Alloc r2 |I38a|I40a|C41a| |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
129.#131 r2 Fixd Keep r2 |I38a|I40a|C41a| |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
129.#132 C41 Use * Keep r2 |I38a|I40a|C41i| |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
130.#133 r2 Fixd Keep r2 |I38a|I40a| | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
130.#134 I42 Def Alloc r2 |I38a|I40a|I42a| |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
132.#135 C43 Def Alloc r3 |I38a|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#136 r0 Fixd Keep r0 |I38a|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#137 I38 Use * Keep r0 |I38i|I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#138 r1 Fixd Keep r1 | |I40a|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#139 I40 Use * Keep r1 | |I40i|I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#140 r2 Fixd Keep r2 | | |I42a|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#141 I42 Use * Keep r2 | | |I42i|C43a|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
133.#142 C43 Use * Keep r3 | | | |C43i|V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#143 r0 Kill Keep r0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#144 r1 Kill Keep r1 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#145 r2 Kill Keep r2 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#146 r3 Kill Keep r3 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#147 r12 Kill Keep r12 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#148 lr Kill Keep lr | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#149 f0 Kill Keep f0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#150 f1 Kill Keep f1 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#151 f2 Kill Keep f2 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#152 f3 Kill Keep f3 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#153 f4 Kill Keep f4 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#154 f5 Kill Keep f5 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#155 f6 Kill Keep f6 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#156 f7 Kill Keep f7 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#157 f8 Kill Keep f8 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#158 f9 Kill Keep f9 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#159 f10 Kill Keep f10 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#160 f11 Kill Keep f11 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#161 f12 Kill Keep f12 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#162 f13 Kill Keep f13 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#163 f14 Kill Keep f14 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#164 f15 Kill Keep f15 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#165 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
134.#166 I44 Def Alloc r0 |I44a| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
135.#167 I44 Use * Keep r0 |I44i| | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
136.#168 V12 Def Alloc r0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
Spill r0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
139.#169 r0 Fixd Keep r0 | | | | |V0 a|V3 a|V11a|V1 a|V5 a|V14a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
139.#170 V11 Use * Copy r0 |V11i| | | |V0 a|V3 a|V11i|V1 a|V5 a|V14a| | | |
140.#171 r0 Fixd Keep r0 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
140.#172 I45 Def Alloc r0 |I45a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
143.#173 r1 Fixd Keep r1 |I45a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
143.#174 V2 Use * ReLod r1 |I45a|V2 a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
Keep r1 |I45a|V2 i| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
144.#175 r1 Fixd Keep r1 |I45a| | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
144.#176 I46 Def Alloc r1 |I45a|I46a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
147.#177 r0 Fixd Keep r0 |I45a|I46a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
147.#178 I45 Use * Keep r0 |I45i|I46a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
147.#179 r1 Fixd Keep r1 | |I46a| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
147.#180 I46 Use * Keep r1 | |I46i| | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
147.#181 V12 Use * ReLod r3 | | | |V12a|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
Keep r3 | | | |V12i|V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#182 r0 Kill Keep r0 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#183 r1 Kill Keep r1 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#184 r2 Kill Keep r2 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#185 r3 Kill Keep r3 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#186 r12 Kill Keep r12 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
148.#187 lr Kill Keep lr | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
149.#188 BB3 PredBB1 | | | | |V0 a|V3 a| |V1 a|V5 a|V14a| | | |
157.#189 V14 Use * Keep r9 | | | | |V0 a|V3 a| |V1 a|V5 a|V14i| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
161.#190 BB4 PredBB3 | | | | |V0 a|V3 a| |V1 a|V5 a| | | | |
166.#191 C47 Def Alloc r0 |C47a| | | |V0 a|V3 a| |V1 a|V5 a| | | | |
171.#192 V0 Use * Keep r4 |C47a| | | |V0 i|V3 a| |V1 a|V5 a| | | | |
172.#193 I48 Def Alloc r3 |C47a| | |I48a| |V3 a| |V1 a|V5 a| | | | |
173.#194 C47 Use * Keep r0 |C47i| | |I48a| |V3 a| |V1 a|V5 a| | | | |
173.#195 I48 Use * Keep r3 | | | |I48i| |V3 a| |V1 a|V5 a| | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
175.#196 BB5 PredBB3 | | | | | |V3 a| |V1 a|V5 a| | | | |
180.#197 C49 Def Alloc r0 |C49a| | | | |V3 a| |V1 a|V5 a| | | | |
185.#198 V5 Use Keep r8 |C49a| | | | |V3 a| |V1 a|V5 a| | | | |
186.#199 I50 Def Alloc r3 |C49a| | |I50a| |V3 a| |V1 a|V5 a| | | | |
187.#200 C49 Use * Keep r0 |C49i| | |I50a| |V3 a| |V1 a|V5 a| | | | |
187.#201 I50 Use * Keep r3 | | | |I50i| |V3 a| |V1 a|V5 a| | | | |
195.#202 V5 Use * Keep r8 | | | | | |V3 a| |V1 a|V5 i| | | | |
195.#203 V3 Use * Keep r5 | | | | | |V3 i| |V1 a| | | | | |
201.#204 V1 Use * Keep r7 | | | | | | | |V1 i| | | | | |
202.#205 I51 Def Alloc r0 |I51a| | | | | | | | | | | | |
203.#206 r0 Fixd Keep r0 |I51a| | | | | | | | | | | | |
203.#207 I51 Use * Keep r0 |I51i| | | | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |r0 |r1 |r2 |r3 |r4 |r5 |r6 |r7 |r8 |r9 |r10 |r12 |lr |
--------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+
205.#208 BB6 PredBB5 | | | | | | | | | | | | | |
208.#209 C52 Def Alloc r3 | | | |C52a| | | | | | | | | |
209.#210 C52 Use * Keep r3 | | | |C52i| | | | | | | | | |
210.#211 r0 Kill Keep r0 | | | | | | | | | | | | | |
210.#212 r1 Kill Keep r1 | | | | | | | | | | | | | |
210.#213 r2 Kill Keep r2 | | | | | | | | | | | | | |
210.#214 r3 Kill Keep r3 | | | | | | | | | | | | | |
210.#215 r12 Kill Keep r12 | | | | | | | | | | | | | |
210.#216 lr Kill Keep lr | | | | | | | | | | | | | |
210.#217 f0 Kill Keep f0 | | | | | | | | | | | | | |
210.#218 f1 Kill Keep f1 | | | | | | | | | | | | | |
210.#219 f2 Kill Keep f2 | | | | | | | | | | | | | |
210.#220 f3 Kill Keep f3 | | | | | | | | | | | | | |
210.#221 f4 Kill Keep f4 | | | | | | | | | | | | | |
210.#222 f5 Kill Keep f5 | | | | | | | | | | | | | |
210.#223 f6 Kill Keep f6 | | | | | | | | | | | | | |
210.#224 f7 Kill Keep f7 | | | | | | | | | | | | | |
210.#225 f8 Kill Keep f8 | | | | | | | | | | | | | |
210.#226 f9 Kill Keep f9 | | | | | | | | | | | | | |
210.#227 f10 Kill Keep f10 | | | | | | | | | | | | | |
210.#228 f11 Kill Keep f11 | | | | | | | | | | | | | |
210.#229 f12 Kill Keep f12 | | | | | | | | | | | | | |
210.#230 f13 Kill Keep f13 | | | | | | | | | | | | | |
210.#231 f14 Kill Keep f14 | | | | | | | | | | | | | |
210.#232 f15 Kill Keep f15 | | | | | | | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
BB02 [ 50]: SpillCount = 4, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0
Total Tracked Vars: 15
Total Reg Cand Vars: 15
Total number of Intervals: 52
Total number of RefPositions: 232
Total Spill Count: 4 Weighted: 200
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(r0=>r4) V03(r3=>r5) V02(r2=>r6) V01(r1=>r7) V05(STK=>r8) V04(STK=>r0)
BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N003. IL_OFFSET IL offset: 0x0 REG NA
N005. V04(r0*)
N007. r9 = CAST ; r0*
* N009. V14(r9); r9
N011. V14(r9)
N013. CNS_INT 0 REG NA
N015. EQ ; r9
N017. JTRUE
Var=Reg end of BB01: V00=r4 V14=r9 V03=r5 V01=r7 V05=r8
BB02 [004..02C), preds={BB01} succs={BB03}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: V00=r4 V14=r9 V03=r5 V01=r7 V05=r8
N021. IL_OFFSET IL offset: 0x4 REG NA
N023. r0 = CLS_VAR_ADDR Hnd=0x9247f8 REG r0
N025. r0 = IND ; r0
* N027. V17(r0); r0
N029. V17(r0*)
N031. V17(r0)
N033. CNS_INT 31 REG NA
N035. r10 = RSH ; r0
* N037. V15(r6); r0*
* N039. V16(r10); r10
N041. IL_OFFSET IL offset: 0xb REG NA
N043. r0 = CLS_VAR_ADDR Hnd=0x924808 REG r0
N045. r0 = IND ; r0
* N047. V13(r0); r0
N049. r1 = CNS_INT 0 REG r1
N051. V13(r0)
N053. STK = LEA(b+4) ; r0
N055. r2 = IND ; STK
N057. ARR_BOUNDS_CHECK_Rng; r1,r2
N059. V13(r0*)
N061. STK = LEA(b+8) ; r0*
N063. r0 = IND ; STK
N065. V02(STK); r0
N067. IL_OFFSET IL offset: 0x16 REG NA
N069. r0 = CLS_VAR_ADDR Hnd=0x9247d8 REG r0
N071. lr = IND ; r0
* N073. V09(lr); lr
S N075. V09(lr)
N077. r0 = PUTARG_REG; lr
N079. r1 = CNS_INT(h) 0x924994 token REG r1
N081. r1 = PUTARG_REG; r1
N083. r2 = CNS_INT(h) 0x924B10 token REG r2
N085. r2 = PUTARG_REG; r2
N087. r12 = CNS_INT(h) 0xFDA55A0 ftn REG r12
N089. r0 = CALL help; r0,r1,r2,r12
N091. V10(STK); r0
N093. V09(r0*)R
N095. r0 = PUTARG_REG; r0*
N097. V15(r6*)
N099. r2 = PUTARG_REG; r6*
N101. V16(r10*)
N103. r3 = PUTARG_REG; r10*
N105. STK = FIELD_LIST; r2,r3
N107. V10(r1*)R
N109. CALL ind ; r0,STK,STK,r1*
N111. IL_OFFSET IL offset: 0x21 REG NA
N113. r0 = CLS_VAR_ADDR Hnd=0x9247d8 REG r0
N115. r6 = IND ; r0
* N117. V11(r6); r6
N119. V11(r6)
N121. r0 = PUTARG_REG; r6
N123. r1 = CNS_INT(h) 0x924994 token REG r1
N125. r1 = PUTARG_REG; r1
N127. r2 = CNS_INT(h) 0x924B74 token REG r2
N129. r2 = PUTARG_REG; r2
N131. r3 = CNS_INT(h) 0xFDA55A0 ftn REG r3
N133. r0 = CALL help; r0,r1,r2,r3
N135. V12(STK); r0
N137. V11(r6*)
N139. r0 = PUTARG_REG; r6*
N141. V02(r1*)R
N143. r1 = PUTARG_REG; r1*
N145. V12(r3*)R
N147. CALL ind ; r0,r1,r3*
Var=Reg end of BB02: V00=r4 V14=r9 V03=r5 V01=r7 V05=r8
BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB03: V00=r4 V14=r9 V03=r5 V01=r7 V05=r8
N151. IL_OFFSET IL offset: 0x2c REG NA
N153. V14(r9*)
N155. CNS_INT 0 REG NA
N157. NE ; r9*
N159. JTRUE
Var=Reg end of BB03: V00=r4 V03=r5 V01=r7 V05=r8
BB04 [030..034), preds={BB03} succs={BB05}
=====
Predecessor for variable locations: BB03
Var=Reg beg of BB04: V00=r4 V03=r5 V01=r7 V05=r8
N163. IL_OFFSET IL offset: 0x30 REG NA
N165. r0 = CNS_INT 0 REG r0
N167. V00(r4*)
N169. STK = LEA(b+4) ; r4*
N171. r3 = IND ; STK
N173. ARR_BOUNDS_CHECK_Rng; r0,r3
Var=Reg end of BB04: V03=r5 V01=r7 V05=r8
BB05 [034..03B) (return), preds={BB03,BB04} succs={}
=====
Predecessor for variable locations: BB03
Var=Reg beg of BB05: V03=r5 V01=r7 V05=r8
N177. IL_OFFSET IL offset: 0x34 REG NA
N179. r0 = CNS_INT 0 REG r0
N181. V05(r8)
N183. STK = LEA(b+4) ; r8
N185. r3 = IND ; STK
N187. ARR_BOUNDS_CHECK_Rng; r0,r3
N189. V05(r8*)
N191. STK = LEA(b+8) ; r8*
N193. V03(r5*)
N195. STOREIND ; STK,r5*
N197. IL_OFFSET IL offset: 0x39 REG NA
N199. V01(r7*)
N201. r0 = CAST ; r7*
N203. RETURN ; r0
Var=Reg end of BB05: none
BB06 [???..???) (throw), preds={} succs={}
=====
Predecessor for variable locations: BB05
Var=Reg beg of BB06: none
N207. r3 = CNS_INT(h) 0xFDA7BB0 ftn REG r3
N209. CALL help; r3
Var=Reg end of BB06: none
*************** In genGenerateCode()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 0.50 [004..02C) i gcsafe LIR
BB03 [0002] 2 BB01,BB02 1 [02C..030)-> BB05 ( cond ) i label target LIR
BB04 [0003] 1 BB03 0.50 [030..034) i idxlen LIR
BB05 [0004] 2 BB03,BB04 1 [034..03B) (return) i label target idxlen LIR
BB06 [0005] 0 0 [???..???) (throw ) keep i internal rare label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(r4) V03(r5) V01(r7) V05(r8) V04(r0)
Modified regs: [r0-r10 r12 lr f0-f15]
Callee-saved registers pushed: 9 [r4-r11 lr]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V02 arg2, size=4, stkOffs=-0x2c
Assign V10 tmp2, size=4, stkOffs=-0x30
Assign V12 tmp4, size=4, stkOffs=-0x34
Assign V09 tmp1, size=4, stkOffs=-0x38
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 5, 3.50) ref -> r4 class-hnd
; V01 arg1 [V01,T05] ( 3, 3 ) ushort -> r7
; V02 arg2 [V02,T04] ( 5, 3.50) ushort -> [sp+0x0C]
; V03 arg3 [V03,T03] ( 4, 4 ) ubyte -> r5
; V04 arg4 [V04,T10] ( 2, 2 ) bool -> r0
; V05 arg5 [V05,T06] ( 4, 4 ) ref -> r8 class-hnd
;* V06 loc0 [V06 ] ( 0, 0 ) long -> zero-ref
;* V07 loc1 [V07 ] ( 0, 0 ) ushort -> zero-ref
;# V08 OutArgs [V08 ] ( 1, 1 ) lclBlk ( 0) [sp+0x00]
; V09 tmp1 [V09,T07] ( 3, 3 ) ref -> [sp+0x00]
; V10 tmp2 [V10,T11] ( 2, 2 ) int -> [sp+0x08]
; V11 tmp3 [V11,T08] ( 3, 3 ) ref -> r6
; V12 tmp4 [V12,T12] ( 2, 2 ) int -> [sp+0x04]
; V13 tmp5 [V13,T01] ( 6, 6 ) ref -> r0
; V14 cse0 [V14,T02] ( 6, 6 ) int -> r9
; V15 rat0 [V15,T13] ( 2, 1 ) int -> r6 V06.lo(offs=0x00)
; V16 rat1 [V16,T14] ( 2, 1 ) int -> r10 V06.hi(offs=0x04)
; V17 rat2 [V17,T09] ( 3, 3 ) int -> r0
;
; Lcl frame size = 20
=============== Generating BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} flags=0x00000000.40030020: i label target LIR
BB01 IN (5)={V00 V03 V01 V05 V04} + ByrefExposed + GcHeap
OUT(5)={V00 V14 V03 V01 V05 } + ByrefExposed + GcHeap
Recording Var Locations at start of BB01
V00(r4) V03(r5) V01(r7) V05(r8) V04(r0)
Change life 00000000 {} -> 00000469 {V00 V01 V03 V04 V05}
V00 in reg r4 is becoming live [------]
Live regs: 0000 {} => 0010 {r4}
V03 in reg r5 is becoming live [------]
Live regs: 0010 {r4} => 0030 {r4 r5}
V01 in reg r7 is becoming live [------]
Live regs: 0030 {r4 r5} => 00B0 {r4 r5 r7}
V05 in reg r8 is becoming live [------]
Live regs: 00B0 {r4 r5 r7} => 01B0 {r4 r5 r7 r8}
V04 in reg r0 is becoming live [------]
Live regs: 01B0 {r4 r5 r7 r8} => 01B1 {r0 r4 r5 r7 r8}
Live regs: (unchanged) 01B1 {r0 r4 r5 r7 r8}
GC regs: (unchanged) 0110 {r4 r8}
Byref regs: (unchanged) 0000 {}
L_M58754_BB01:
Label: IG02, GCvars=00000000 {}, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}
Setting stack level from -572662307 to 0
Scope info: begin block BB01, IL range [000..004)
Scope info: open scopes =
0 (V00 arg0) [000..03B)
3 (V03 arg3) [000..03B)
1 (V01 arg1) [000..03B)
5 (V05 arg5) [000..03B)
4 (V04 arg4) [000..03B)
Added IP mapping: 0x0000 STACK_EMPTY (G_M58754_IG02,ins#0,ofs#0) label
Generating: N003 ( 8, 8) [000005] ------------- IL_OFFSET void IL offset: 0x0 REG NA
Generating: N005 ( 2, 2) [000001] ------------- t1 = LCL_VAR int V04 arg4 u:2 r0 (last use) REG r0 $140
/--* t1 int
Generating: N007 ( 3, 3) [000085] ----------S-- t85 = * CAST int <- bool <- int REG r9 $200
V04 in reg r0 is becoming dead [000001]
Live regs: 01B1 {r0 r4 r5 r7 r8} => 01B0 {r4 r5 r7 r8}
Live vars: {V00 V01 V03 V04 V05} => {V00 V01 V03 V05}
IN0001: uxtb r9, r0
/--* t85 int
Generating: N009 ( 3, 3) [000143] DA----------- * STORE_LCL_VAR int V14 cse0 r9 REG r9
V14 in reg r9 is becoming live [000143]
Live regs: 01B0 {r4 r5 r7 r8} => 03B0 {r4 r5 r7 r8 r9}
Live vars: {V00 V01 V03 V05} => {V00 V01 V03 V05 V14}
Generating: N011 ( 1, 1) [000144] ------------- t144 = LCL_VAR int V14 cse0 r9 REG r9 $200
Generating: N013 ( 1, 1) [000002] -c----------- t2 = CNS_INT int 0 REG NA $40
/--* t144 int
+--* t2 int
Generating: N015 ( 6, 6) [000003] J------N--S-- * EQ void REG NA $201
IN0002: cmp r9, 0
Generating: N017 ( 8, 8) [000004] ------------- * JTRUE void REG NA
IN0003: beq L_M58754_BB03
Scope info: end block BB01, IL range [000..004)
Scope info: open scopes =
0 (V00 arg0) [000..03B)
3 (V03 arg3) [000..03B)
1 (V01 arg1) [000..03B)
5 (V05 arg5) [000..03B)
=============== Generating BB02 [004..02C), preds={BB01} succs={BB03} flags=0x00000000.40080020: i gcsafe LIR
BB02 IN (5)={V00 V14 V03 V01 V05} + ByrefExposed + GcHeap
OUT(5)={V00 V14 V03 V01 V05} + ByrefExposed + GcHeap
Recording Var Locations at start of BB02
V00(r4) V14(r9) V03(r5) V01(r7) V05(r8)
Liveness not changing: 0000006D {V00 V01 V03 V05 V14}
Live regs: 0000 {} => 03B0 {r4 r5 r7 r8 r9}
GC regs: 0000 {} => 0110 {r4 r8}
Byref regs: (unchanged) 0000 {}
L_M58754_BB02:
Scope info: begin block BB02, IL range [004..02C)
Scope info: open scopes =
0 (V00 arg0) [000..03B)
3 (V03 arg3) [000..03B)
1 (V01 arg1) [000..03B)
5 (V05 arg5) [000..03B)
Added IP mapping: 0x0004 STACK_EMPTY (G_M58754_IG02,ins#3,ofs#14) label
Generating: N021 ( 14, 17) [000034] ------------- IL_OFFSET void IL offset: 0x4 REG NA
Generating: N023 ( 6, 10) [000030] ----G-------- t30 = CLS_VAR_ADDR byref Hnd=0x9247f8 REG r0
IN0004: movw r0, 0x408c
IN0005: movt r0, 0x92
Byref regs: 0000 {} => 0001 {r0}
/--* t30 byref
Generating: N025 (???,???) [000148] ----G-------- t148 = * IND int REG r0
Byref regs: 0001 {r0} => 0000 {}
IN0006: ldr r0, [r0]
/--* t148 int
Generating: N027 (???,???) [000164] DA--G-------- * STORE_LCL_VAR int V17 rat2 r0 REG r0
V17 in reg r0 is becoming live [000164]
Live regs: 03B0 {r4 r5 r7 r8 r9} => 03B1 {r0 r4 r5 r7 r8 r9}
Live vars: {V00 V01 V03 V05 V14} => {V00 V01 V03 V05 V14 V17}
Generating: N029 (???,???) [000165] ------------- t165 = LCL_VAR int V17 rat2 r0 (last use) REG r0
Generating: N031 (???,???) [000166] ------------- t166 = LCL_VAR int V17 rat2 r0 REG r0
Generating: N033 (???,???) [000167] -c----------- t167 = CNS_INT int 31 REG NA
/--* t166 int
+--* t167 int
Generating: N035 (???,???) [000168] ------------- t168 = * RSH int REG r10
IN0007: asr r10, r0, 31
/--* t165 int
Generating: N037 ( 14, 17) [000033] DA--G-------- * STORE_LCL_VAR int V15 rat0 r6 REG r6
V17 in reg r0 is becoming dead [000165]
Live regs: 03B1 {r0 r4 r5 r7 r8 r9} => 03B0 {r4 r5 r7 r8 r9}
Live vars: {V00 V01 V03 V05 V14 V17} => {V00 V01 V03 V05 V14}
IN0008: mov r6, r0
V15 in reg r6 is becoming live [000033]
Live regs: 03B0 {r4 r5 r7 r8 r9} => 03F0 {r4 r5 r6 r7 r8 r9}
Live vars: {V00 V01 V03 V05 V14} => {V00 V01 V03 V05 V14 V15}
/--* t168 int
Generating: N039 (???,???) [000170] D------------ * STORE_LCL_VAR int V16 rat1 r10 REG r10
V16 in reg r10 is becoming live [000170]
Live regs: 03F0 {r4 r5 r6 r7 r8 r9} => 07F0 {r4 r5 r6 r7 r8 r9 r10}
Live vars: {V00 V01 V03 V05 V14 V15} => {V00 V01 V03 V05 V14 V15 V16}
Added IP mapping: 0x000B STACK_EMPTY (G_M58754_IG02,ins#8,ofs#30)
Generating: N041 ( 19, 24) [000040] ------------- IL_OFFSET void IL offset: 0xb REG NA
Generating: N043 ( 6, 10) [000035] ----G-------- t35 = CLS_VAR_ADDR byref Hnd=0x924808 REG r0
IN0009: movw r0, 0x1cb4
IN000a: movt r0, 0x5fd
Byref regs: 0000 {} => 0001 {r0}
/--* t35 byref
Generating: N045 (???,???) [000149] ----G-------- t149 = * IND ref REG r0
Byref regs: 0001 {r0} => 0000 {}
IN000b: ldr r0, [r0]
GC regs: 0110 {r4 r8} => 0111 {r0 r4 r8}
/--* t149 ref
Generating: N047 ( 6, 10) [000087] DA--G-------- * STORE_LCL_VAR ref V13 tmp5 d:3 r0 REG r0
GC regs: 0111 {r0 r4 r8} => 0110 {r4 r8}
V13 in reg r0 is becoming live [000087]
Live regs: 07F0 {r4 r5 r6 r7 r8 r9 r10} => 07F1 {r0 r4 r5 r6 r7 r8 r9 r10}
Live vars: {V00 V01 V03 V05 V14 V15 V16} => {V00 V01 V03 V05 V13 V14 V15 V16}
GC regs: 0110 {r4 r8} => 0111 {r0 r4 r8}
Generating: N049 ( 1, 1) [000036] ------------- t36 = CNS_INT int 0 REG r1 $40
IN000c: movs r1, 0
Generating: N051 ( 1, 1) [000088] ------------- t88 = LCL_VAR ref V13 tmp5 u:3 r0 REG r0 <l:$340, c:$380>
/--* t88 ref
Generating: N053 (???,???) [000173] -c----------- t173 = * LEA(b+4) byref REG NA
/--* t173 byref
Generating: N055 ( 3, 3) [000091] ---X--------- t91 = * IND int REG r2 <l:$3c1, c:$3c0>
IN000d: ldr r2, [r0+4]
/--* t36 int
+--* t91 int
Generating: N057 ( 8, 11) [000092] ---X--------- * ARR_BOUNDS_CHECK_Rng void <l:$346, c:$345>
IN000e: cmp r1, r2
IN000f: bhs L_M58754_BB06
Generating: N059 ( 1, 1) [000089] ------------- t89 = LCL_VAR ref V13 tmp5 u:3 r0 (last use) REG r0 <l:$340, c:$380>
/--* t89 ref
Generating: N061 (???,???) [000174] -c----------- t174 = * LEA(b+8) byref REG NA
/--* t174 byref
Generating: N063 ( 5, 3) [000037] a---GO------- t37 = * IND ushort REG r0 <l:$203, c:$4c0>
V13 in reg r0 is becoming dead [000089]
Live regs: 07F1 {r0 r4 r5 r6 r7 r8 r9 r10} => 07F0 {r4 r5 r6 r7 r8 r9 r10}
Live vars: {V00 V01 V03 V05 V13 V14 V15 V16} => {V00 V01 V03 V05 V14 V15 V16}
GC regs: 0111 {r0 r4 r8} => 0110 {r4 r8}
IN0010: ldrh r0, [r0+8]
/--* t37 ushort
Generating: N065 ( 19, 24) [000039] DA-XGO------- * STORE_LCL_VAR ushort V02 arg2 d:3 NA REG NA
IN0011: strh r0, [sp+0x0c] // [V02 arg2]
Live vars: {V00 V01 V03 V05 V14 V15 V16} => {V00 V01 V02 V03 V05 V14 V15 V16}
Added IP mapping: 0x0016 STACK_EMPTY (G_M58754_IG02,ins#17,ofs#58)
Generating: N067 ( 6, 10) [000050] ------------- IL_OFFSET void IL offset: 0x16 REG NA
Generating: N069 ( 6, 10) [000045] ----G-------- t45 = CLS_VAR_ADDR byref Hnd=0x9247d8 REG r0
IN0012: movw r0, 0x1cac
IN0013: movt r0, 0x5fd
Byref regs: 0000 {} => 0001 {r0}
/--* t45 byref
Generating: N071 (???,???) [000150] ----G-------- t150 = * IND ref REG lr
Byref regs: 0001 {r0} => 0000 {}
IN0014: ldr lr, [r0]
GC regs: 0110 {r4 r8} => 4110 {r4 r8 lr}
/--* t150 ref
Generating: N073 ( 6, 10) [000049] DA--G-------- * STORE_LCL_VAR ref V09 tmp1 d:3 lr REG lr
GC regs: 4110 {r4 r8 lr} => 0110 {r4 r8}
V09 in reg lr is becoming live [000049]
Live regs: 07F0 {r4 r5 r6 r7 r8 r9 r10} => 47F0 {r4 r5 r6 r7 r8 r9 r10 lr}
Live vars: {V00 V01 V02 V03 V05 V14 V15 V16} => {V00 V01 V02 V03 V05 V09 V14 V15 V16}
GC regs: 0110 {r4 r8} => 4110 {r4 r8 lr}
Generating: N075 ( 1, 1) [000052] ------------Z t52 = LCL_VAR ref V09 tmp1 u:3 lr REG lr <l:$349, c:$382>
/--* t52 ref
Generating: N077 (???,???) [000175] ------------- t175 = * PUTARG_REG ref REG r0
IN0015: str lr, [sp] // [V09 tmp1]
V09 in reg lr is becoming dead [000052]
Live regs: 47F0 {r4 r5 r6 r7 r8 r9 r10 lr} => 07F0 {r4 r5 r6 r7 r8 r9 r10}
GC regs: 4110 {r4 r8 lr} => 0110 {r4 r8}
Var V09 becoming live
IN0016: mov r0, lr
GC regs: 0110 {r4 r8} => 0111 {r0 r4 r8}
Generating: N079 ( 3, 7) [000053] ------------- t53 = CNS_INT(h) int 0x924994 token REG r1 $244
IN0017: movw r1, 0x4994
IN0018: movt r1, 0x92
/--* t53 int
Generating: N081 (???,???) [000176] ------------- t176 = * PUTARG_REG int REG r1
Generating: N083 ( 3, 7) [000054] ------------- t54 = CNS_INT(h) int 0x924B10 token REG r2 $245
IN0019: movw r2, 0x4b10
IN001a: movt r2, 0x92
/--* t54 int
Generating: N085 (???,???) [000177] ------------- t177 = * PUTARG_REG int REG r2
Generating: N087 ( 3, 7) [000178] ------------- t178 = CNS_INT(h) int 0xFDA55A0 ftn REG r12
IN001b: movw r12, 0x55a0
IN001c: movt r12, 0xfda
/--* t175 ref arg0 in r0
+--* t176 int arg1 in r1
+--* t177 int arg2 in r2
+--* t178 int control expr
Generating: N089 ( 23, 28) [000058] --CXG-------- t58 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $205
GC regs: 0111 {r0 r4 r8} => 0110 {r4 r8}
Call: GCvars=00000080 {V09}, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}
[29] Rec call GC vars = 00000080
IN001d: blx r12 // CORINFO_HELP_VIRTUAL_FUNC_PTR
/--* t58 int
Generating: N091 ( 27, 31) [000060] DA-XG-------- * STORE_LCL_VAR int V10 tmp2 d:3 NA REG NA
IN001e: str r0, [sp+0x08] // [V10 tmp2]
Live vars: {V00 V01 V02 V03 V05 V09 V14 V15 V16} => {V00 V01 V02 V03 V05 V09 V10 V14 V15 V16}
Generating: N093 ( 1, 1) [000051] ------------z t51 = LCL_VAR ref V09 tmp1 u:3 r0 (last use) REG r0 <l:$349, c:$382>
/--* t51 ref
Generating: N095 (???,???) [000179] ------------- t179 = * PUTARG_REG ref REG r0
IN001f: ldr r0, [sp] // [V09 tmp1]
Removing V09 from gcVarPtrSetCur
V09 in reg r0 is becoming live [000051]
Live regs: 07F0 {r4 r5 r6 r7 r8 r9 r10} => 07F1 {r0 r4 r5 r6 r7 r8 r9 r10}
GC regs: 0110 {r4 r8} => 0111 {r0 r4 r8}
V09 in reg r0 is becoming dead [000051]
Live regs: 07F1 {r0 r4 r5 r6 r7 r8 r9 r10} => 07F0 {r4 r5 r6 r7 r8 r9 r10}
Live vars: {V00 V01 V02 V03 V05 V09 V10 V14 V15 V16} => {V00 V01 V02 V03 V05 V10 V14 V15 V16}
GC regs: 0111 {r0 r4 r8} => 0110 {r4 r8}
GC regs: 0110 {r4 r8} => 0111 {r0 r4 r8}
Generating: N097 ( 3, 2) [000046] ------------- t46 = LCL_VAR int V15 rat0 r6 (last use) REG r6 <l:$2c1, c:$2c0>
/--* t46 int
Generating: N099 (???,???) [000182] ------------- t182 = * PUTARG_REG int REG r2
V15 in reg r6 is becoming dead [000046]
Live regs: 07F0 {r4 r5 r6 r7 r8 r9 r10} => 07B0 {r4 r5 r7 r8 r9 r10}
Live vars: {V00 V01 V02 V03 V05 V10 V14 V15 V16} => {V00 V01 V02 V03 V05 V10 V14 V16}
IN0020: mov r2, r6
Generating: N101 (???,???) [000171] ------------- t171 = LCL_VAR int V16 rat1 r10 (last use) REG r10
/--* t171 int
Generating: N103 (???,???) [000183] ------------- t183 = * PUTARG_REG int REG r3
V16 in reg r10 is becoming dead [000171]
Live regs: 07B0 {r4 r5 r7 r8 r9 r10} => 03B0 {r4 r5 r7 r8 r9}
Live vars: {V00 V01 V02 V03 V05 V10 V14 V16} => {V00 V01 V02 V03 V05 V10 V14}
IN0021: mov r3, r10
/--* t182 int
+--* t183 int
Generating: N105 (???,???) [000180] Hc----------- t180 = * FIELD_LIST int int at offset 0 REG NA
Generating: N107 ( 3, 2) [000062] ------------z t62 = LCL_VAR int V10 tmp2 u:3 r1 (last use) REG r1 $283
/--* t179 ref this in r0
+--* t180 int arg1 r2,r3
+--* t62 int calli tgt
Generating: N109 ( 24, 10) [000063] --CXG-------- * CALL ind void $VN.Void
GC regs: 0111 {r0 r4 r8} => 0110 {r4 r8}
IN0022: ldr r1, [sp+0x08] // [V10 tmp2]
V10 in reg r1 is becoming live [000062]
Live regs: 03B0 {r4 r5 r7 r8 r9} => 03B2 {r1 r4 r5 r7 r8 r9}
V10 in reg r1 is becoming dead [000062]
Live regs: 03B2 {r1 r4 r5 r7 r8 r9} => 03B0 {r4 r5 r7 r8 r9}
Live vars: {V00 V01 V02 V03 V05 V10 V14} => {V00 V01 V02 V03 V05 V14}
Call: GCvars=00000000 {}, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}
IN0023: blx r1
Added IP mapping: 0x0021 STACK_EMPTY (G_M58754_IG02,ins#35,ofs#114)
Generating: N111 ( 6, 10) [000070] ------------- IL_OFFSET void IL offset: 0x21 REG NA
Generating: N113 ( 6, 10) [000065] ----G-------- t65 = CLS_VAR_ADDR byref Hnd=0x9247d8 REG r0
IN0024: movw r0, 0x1cac
IN0025: movt r0, 0x5fd
Byref regs: 0000 {} => 0001 {r0}
/--* t65 byref
Generating: N115 (???,???) [000151] ----G-------- t151 = * IND ref REG r6
Byref regs: 0001 {r0} => 0000 {}
IN0026: ldr r6, [r0]
GC regs: 0110 {r4 r8} => 0150 {r4 r6 r8}
/--* t151 ref
Generating: N117 ( 6, 10) [000069] DA--G-------- * STORE_LCL_VAR ref V11 tmp3 d:3 r6 REG r6
GC regs: 0150 {r4 r6 r8} => 0110 {r4 r8}
V11 in reg r6 is becoming live [000069]
Live regs: 03B0 {r4 r5 r7 r8 r9} => 03F0 {r4 r5 r6 r7 r8 r9}
Live vars: {V00 V01 V02 V03 V05 V14} => {V00 V01 V02 V03 V05 V11 V14}
GC regs: 0110 {r4 r8} => 0150 {r4 r6 r8}
Generating: N119 ( 1, 1) [000072] ------------- t72 = LCL_VAR ref V11 tmp3 u:3 r6 REG r6 <l:$34b, c:$388>
/--* t72 ref
Generating: N121 (???,???) [000184] ------------- t184 = * PUTARG_REG ref REG r0
IN0027: mov r0, r6
GC regs: 0150 {r4 r6 r8} => 0151 {r0 r4 r6 r8}
Generating: N123 ( 3, 7) [000073] ------------- t73 = CNS_INT(h) int 0x924994 token REG r1 $244
IN0028: movw r1, 0x4994
IN0029: movt r1, 0x92
/--* t73 int
Generating: N125 (???,???) [000185] ------------- t185 = * PUTARG_REG int REG r1
Generating: N127 ( 3, 7) [000074] ------------- t74 = CNS_INT(h) int 0x924B74 token REG r2 $246
IN002a: movw r2, 0x4b74
IN002b: movt r2, 0x92
/--* t74 int
Generating: N129 (???,???) [000186] ------------- t186 = * PUTARG_REG int REG r2
Generating: N131 ( 3, 7) [000187] ------------- t187 = CNS_INT(h) int 0xFDA55A0 ftn REG r3
IN002c: movw r3, 0x55a0
IN002d: movt r3, 0xfda
/--* t184 ref arg0 in r0
+--* t185 int arg1 in r1
+--* t186 int arg2 in r2
+--* t187 int control expr
Generating: N133 ( 23, 28) [000078] --CXG-------- t78 = * CALL help int HELPER.CORINFO_HELP_VIRTUAL_FUNC_PTR $206
GC regs: 0151 {r0 r4 r6 r8} => 0150 {r4 r6 r8}
Call: GCvars=00000000 {}, gcrefRegs=0150 {r4 r6 r8}, byrefRegs=0000 {}
IN002e: blx r3 // CORINFO_HELP_VIRTUAL_FUNC_PTR
/--* t78 int
Generating: N135 ( 27, 31) [000080] DA-XG-------- * STORE_LCL_VAR int V12 tmp4 d:3 NA REG NA
IN002f: str r0, [sp+0x04] // [V12 tmp4]
Live vars: {V00 V01 V02 V03 V05 V11 V14} => {V00 V01 V02 V03 V05 V11 V12 V14}
Generating: N137 ( 1, 1) [000071] ------------- t71 = LCL_VAR ref V11 tmp3 u:3 r6 (last use) REG r6 <l:$34b, c:$388>
/--* t71 ref
Generating: N139 (???,???) [000188] ------------- t188 = * PUTARG_REG ref REG r0
V11 in reg r6 is becoming dead [000071]
Live regs: 03F0 {r4 r5 r6 r7 r8 r9} => 03B0 {r4 r5 r7 r8 r9}
Live vars: {V00 V01 V02 V03 V05 V11 V12 V14} => {V00 V01 V02 V03 V05 V12 V14}
GC regs: 0150 {r4 r6 r8} => 0110 {r4 r8}
IN0030: mov r0, r6
GC regs: 0110 {r4 r8} => 0111 {r0 r4 r8}
Generating: N141 ( 2, 2) [000066] ------------z t66 = LCL_VAR int V02 arg2 u:3 r1 (last use) REG r1 <l:$203, c:$4c0>
/--* t66 int
Generating: N143 (???,???) [000189] ------------- t189 = * PUTARG_REG int REG r1
IN0031: ldr r1, [sp+0x0c] // [V02 arg2]
V02 in reg r1 is becoming live [000066]
Live regs: 03B0 {r4 r5 r7 r8 r9} => 03B2 {r1 r4 r5 r7 r8 r9}
V02 in reg r1 is becoming dead [000066]
Live regs: 03B2 {r1 r4 r5 r7 r8 r9} => 03B0 {r4 r5 r7 r8 r9}
Live vars: {V00 V01 V02 V03 V05 V12 V14} => {V00 V01 V03 V05 V12 V14}
Generating: N145 ( 3, 2) [000082] ------------z t82 = LCL_VAR int V12 tmp4 u:3 r3 (last use) REG r3 $287
/--* t188 ref this in r0
+--* t189 int arg1 in r1
+--* t82 int calli tgt
Generating: N147 ( 23, 10) [000083] --CXG-------- * CALL ind void $VN.Void
GC regs: 0111 {r0 r4 r8} => 0110 {r4 r8}
IN0032: ldr r3, [sp+0x04] // [V12 tmp4]
V12 in reg r3 is becoming live [000082]
Live regs: 03B0 {r4 r5 r7 r8 r9} => 03B8 {r3 r4 r5 r7 r8 r9}
V12 in reg r3 is becoming dead [000082]
Live regs: 03B8 {r3 r4 r5 r7 r8 r9} => 03B0 {r4 r5 r7 r8 r9}
Live vars: {V00 V01 V03 V05 V12 V14} => {V00 V01 V03 V05 V14}
Call: GCvars=00000000 {}, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}
IN0033: blx r3
Scope info: end block BB02, IL range [004..02C)
Scope info: open scopes =
0 (V00 arg0) [000..03B)
3 (V03 arg3) [000..03B)
1 (V01 arg1) [000..03B)
5 (V05 arg5) [000..03B)
=============== Generating BB03 [02C..030) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05} flags=0x00000000.40030020: i label target LIR
BB03 IN (5)={V00 V14 V03 V01 V05} + ByrefExposed + GcHeap
OUT(4)={V00 V03 V01 V05} + ByrefExposed + GcHeap
Recording Var Locations at start of BB03
V00(r4) V14(r9) V03(r5) V01(r7) V05(r8)
Liveness not changing: 0000006D {V00 V01 V03 V05 V14}
Live regs: 0000 {} => 03B0 {r4 r5 r7 r8 r9}
GC regs: 0000 {} => 0110 {r4 r8}
Byref regs: (unchanged) 0000 {}
L_M58754_BB03:
G_M58754_IG02: ; offs=000000H, funclet=00
Label: IG03, GCvars=00000000 {}, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}
Scope info: begin block BB03, IL range [02C..030)
Scope info: open scopes =
0 (V00 arg0) [000..03B)
3 (V03 arg3) [000..03B)
1 (V01 arg1) [000..03B)
5 (V05 arg5) [000..03B)
Added IP mapping: 0x002C STACK_EMPTY (G_M58754_IG03,ins#0,ofs#0) label
Generating: N151 ( 5, 5) [000011] ------------- IL_OFFSET void IL offset: 0x2c REG NA
Generating: N153 ( 1, 1) [000146] ------------- t146 = LCL_VAR int V14 cse0 r9 (last use) REG r9 $200
Generating: N155 ( 1, 1) [000008] -c----------- t8 = CNS_INT int 0 REG NA $40
/--* t146 int
+--* t8 int
Generating: N157 ( 3, 3) [000009] J------N--S-- * NE void REG NA $207
V14 in reg r9 is becoming dead [000146]
Live regs: 03B0 {r4 r5 r7 r8 r9} => 01B0 {r4 r5 r7 r8}
Live vars: {V00 V01 V03 V05 V14} => {V00 V01 V03 V05}
IN0034: cmp r9, 0
Generating: N159 ( 5, 5) [000010] ------------- * JTRUE void REG NA
IN0035: bne L_M58754_BB05
Scope info: end block BB03, IL range [02C..030)
Scope info: open scopes =
0 (V00 arg0) [000..03B)
3 (V03 arg3) [000..03B)
1 (V01 arg1) [000..03B)
5 (V05 arg5) [000..03B)
=============== Generating BB04 [030..034), preds={BB03} succs={BB05} flags=0x00000000.40200020: i idxlen LIR
BB04 IN (4)={V00 V03 V01 V05} + ByrefExposed + GcHeap
OUT(3)={ V03 V01 V05} + ByrefExposed + GcHeap
Recording Var Locations at start of BB04
V00(r4) V03(r5) V01(r7) V05(r8)
Liveness not changing: 00000069 {V00 V01 V03 V05}
Live regs: 0000 {} => 01B0 {r4 r5 r7 r8}
GC regs: 0000 {} => 0110 {r4 r8}
Byref regs: (unchanged) 0000 {}
L_M58754_BB04:
Scope info: begin block BB04, IL range [030..034)
Scope info: open scopes =
0 (V00 arg0) [000..03B)
3 (V03 arg3) [000..03B)
1 (V01 arg1) [000..03B)
5 (V05 arg5) [000..03B)
Added IP mapping: 0x0030 STACK_EMPTY (G_M58754_IG03,ins#2,ofs#10) label
Generating: N163 ( 13, 14) [000028] ------------- IL_OFFSET void IL offset: 0x30 REG NA
Generating: N165 ( 1, 1) [000024] ------------- t24 = CNS_INT int 0 REG r0 $40
IN0036: movs r0, 0
Generating: N167 ( 1, 1) [000023] ------------- t23 = LCL_VAR ref V00 arg0 u:2 r4 (last use) REG r4 $80
/--* t23 ref
Generating: N169 (???,???) [000190] -c----------- t190 = * LEA(b+4) byref REG NA
/--* t190 byref
Generating: N171 ( 3, 3) [000123] ---X--------- t123 = * IND int REG r3 $3c2
V00 in reg r4 is becoming dead [000023]
Live regs: 01B0 {r4 r5 r7 r8} => 01A0 {r5 r7 r8}
Live vars: {V00 V01 V03 V05} => {V01 V03 V05}
GC regs: 0110 {r4 r8} => 0100 {r8}
IN0037: ldr r3, [r4+4]
/--* t24 int
+--* t123 int
Generating: N173 ( 8, 11) [000124] ---X--------- * ARR_BOUNDS_CHECK_Rng void $350
IN0038: cmp r0, r3
IN0039: bhs L_M58754_BB06
Scope info: end block BB04, IL range [030..034)
Scope info: open scopes =
3 (V03 arg3) [000..03B)
1 (V01 arg1) [000..03B)
5 (V05 arg5) [000..03B)
=============== Generating BB05 [034..03B) (return), preds={BB03,BB04} succs={} flags=0x00000000.40230020: i label target idxlen LIR
BB05 IN (3)={V03 V01 V05} + ByrefExposed + GcHeap
OUT(0)={ }
Recording Var Locations at start of BB05
V03(r5) V01(r7) V05(r8)
Liveness not changing: 00000068 {V01 V03 V05}
Live regs: 0000 {} => 01A0 {r5 r7 r8}
GC regs: 0000 {} => 0100 {r8}
Byref regs: (unchanged) 0000 {}
L_M58754_BB05:
G_M58754_IG03: ; offs=0000A2H, funclet=00
Label: IG04, GCvars=00000000 {}, gcrefRegs=0100 {r8}, byrefRegs=0000 {}
Scope info: begin block BB05, IL range [034..03B)
Scope info: open scopes =
3 (V03 arg3) [000..03B)
1 (V01 arg1) [000..03B)
5 (V05 arg5) [000..03B)
Added IP mapping: 0x0034 STACK_EMPTY (G_M58754_IG04,ins#0,ofs#0) label
Generating: N177 ( 16, 17) [000018] ------------- IL_OFFSET void IL offset: 0x34 REG NA
Generating: N179 ( 1, 1) [000014] ------------- t14 = CNS_INT int 0 REG r0 $40
IN003a: movs r0, 0
Generating: N181 ( 1, 1) [000013] ------------- t13 = LCL_VAR ref V05 arg5 u:2 r8 REG r8 $81
/--* t13 ref
Generating: N183 (???,???) [000192] -c----------- t192 = * LEA(b+4) byref REG NA
/--* t192 byref
Generating: N185 ( 3, 3) [000134] ---X--------- t134 = * IND int REG r3 $3c3
IN003b: ldr r3, [r8+4]
/--* t14 int
+--* t134 int
Generating: N187 ( 8, 11) [000135] ---X--------- * ARR_BOUNDS_CHECK_Rng void $356
IN003c: cmp r0, r3
IN003d: bhs L_M58754_BB06
Generating: N189 ( 1, 1) [000132] ------------- t132 = LCL_VAR ref V05 arg5 u:2 r8 (last use) REG r8 $81
/--* t132 ref
Generating: N191 (???,???) [000193] -c----------- t193 = * LEA(b+8) byref REG NA
Generating: N193 ( 2, 2) [000015] ------------- t15 = LCL_VAR int V03 arg3 u:2 r5 (last use) REG r5 $100
/--* t193 byref
+--* t15 int
Generating: N195 (???,???) [000152] -A-XGO------- * STOREIND byte REG NA
V05 in reg r8 is becoming dead [000132]
Live regs: 01A0 {r5 r7 r8} => 00A0 {r5 r7}
Live vars: {V01 V03 V05} => {V01 V03}
GC regs: 0100 {r8} => 0000 {}
V03 in reg r5 is becoming dead [000015]
Live regs: 00A0 {r5 r7} => 0080 {r7}
Live vars: {V01 V03} => {V01}
IN003e: strb r5, [r8+8]
Added IP mapping: 0x0039 STACK_EMPTY (G_M58754_IG04,ins#5,ofs#18)
Generating: N197 ( 4, 4) [000021] ------------- IL_OFFSET void IL offset: 0x39 REG NA
Generating: N199 ( 2, 2) [000019] ------------- t19 = LCL_VAR int V01 arg1 u:2 r7 (last use) REG r7 $c0
/--* t19 int
Generating: N201 ( 3, 3) [000141] ------------- t141 = * CAST int <- ushort <- int REG r0 $20c
V01 in reg r7 is becoming dead [000019]
Live regs: 0080 {r7} => 0000 {}
Live vars: {V01} => {}
IN003f: uxth r0, r7
/--* t141 int
Generating: N203 ( 4, 4) [000020] ------------- * RETURN int REG NA $28a
Scope info: end block BB05, IL range [034..03B)
Scope info: ending scope, LVnum=1 [000..03B)
Scope info: ending scope, LVnum=2 [000..03B)
Scope info: ending scope, LVnum=3 [000..03B)
Scope info: ending scope, LVnum=4 [000..03B)
Scope info: ending scope, LVnum=5 [000..03B)
Scope info: ending scope, LVnum=6 [000..03B)
Scope info: ending scope, LVnum=7 [000..03B)
Scope info: ending scope, LVnum=0 [000..03B)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M58754_IG04,ins#6,ofs#20) label
Reserving epilog IG for block BB05
G_M58754_IG04: ; offs=0000B8H, funclet=00
*************** After placeholder IG creation
G_M58754_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=0000 {} <-- Prolog IG
G_M58754_IG02: ; offs=000000H, size=00A2H, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}, byref
G_M58754_IG03: ; offs=0000A2H, size=0016H, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}, byref
G_M58754_IG04: ; offs=0000B8H, size=0014H, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, byref
G_M58754_IG05: ; epilog placeholder, next placeholder=<END>, BB05 [0004], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=0110 {r4 r8}, PrevByrefRegs=0000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=0100 {r8}, InitByrefRegs=0000 {}
G_M58754_IG06: ; offs=0001CCH, size=0000H, gcrefRegs=0000 {} <-- Current IG
=============== Generating BB06 [???..???) (throw), preds={} succs={} flags=0x00000000.40031070: keep i internal rare label target LIR
BB06 IN (0)={}
OUT(0)={}
Recording Var Locations at start of BB06
<none>
Liveness not changing: 00000000 {}
Live regs: (unchanged) 0000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M58754_BB06:
Label: IG06, GCvars=00000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB06, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP STACK_EMPTY (G_M58754_IG06,ins#0,ofs#0) label
Generating: N207 ( 3, 7) [000194] ------------- t194 = CNS_INT(h) int 0xFDA7BB0 ftn REG r3
IN0040: movw r3, 0x7bb0
IN0041: movt r3, 0xfda
/--* t194 int control expr
Generating: N209 ( 16, 10) [000155] --CXG-------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL
Call: GCvars=00000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0042: blx r3 // CORINFO_HELP_RNGCHKFAIL
Scope info: end block BB06, IL range [???..???)
Scope info: ignoring block end
IN0043: bkpt
Liveness not changing: 00000000 {}
# compCycleEstimate = 192, compSizeEstimate = 191 Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort
; Final local variable assignments
;
; V00 arg0 [V00,T00] ( 5, 3.50) ref -> r4 class-hnd
; V01 arg1 [V01,T05] ( 3, 3 ) ushort -> r7
; V02 arg2 [V02,T04] ( 5, 3.50) ushort -> [sp+0x0C]
; V03 arg3 [V03,T03] ( 4, 4 ) ubyte -> r5
; V04 arg4 [V04,T10] ( 2, 2 ) bool -> r0
; V05 arg5 [V05,T06] ( 4, 4 ) ref -> r8 class-hnd
;* V06 loc0 [V06 ] ( 0, 0 ) long -> zero-ref
;* V07 loc1 [V07 ] ( 0, 0 ) ushort -> zero-ref
;# V08 OutArgs [V08 ] ( 1, 1 ) lclBlk ( 0) [sp+0x00]
; V09 tmp1 [V09,T07] ( 3, 3 ) ref -> [sp+0x00]
; V10 tmp2 [V10,T11] ( 2, 2 ) int -> [sp+0x08]
; V11 tmp3 [V11,T08] ( 3, 3 ) ref -> r6
; V12 tmp4 [V12,T12] ( 2, 2 ) int -> [sp+0x04]
; V13 tmp5 [V13,T01] ( 6, 6 ) ref -> r0
; V14 cse0 [V14,T02] ( 6, 6 ) int -> r9
; V15 rat0 [V15,T13] ( 2, 1 ) int -> r6 V06.lo(offs=0x00)
; V16 rat1 [V16,T14] ( 2, 1 ) int -> r10 V06.hi(offs=0x04)
; V17 rat2 [V17,T09] ( 3, 3 ) int -> r0
;
; Lcl frame size = 20
*************** Before prolog / epilog generation
G_M58754_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=0000 {} <-- Prolog IG
G_M58754_IG02: ; offs=000000H, size=00A2H, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}, byref
G_M58754_IG03: ; offs=0000A2H, size=0016H, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}, byref
G_M58754_IG04: ; offs=0000B8H, size=0014H, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, byref
G_M58754_IG05: ; epilog placeholder, next placeholder=<END>, BB05 [0004], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=0110 {r4 r8}, PrevByrefRegs=0000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=0100 {r8}, InitByrefRegs=0000 {}
G_M58754_IG06: ; offs=0001CCH, size=0000H, gcrefRegs=0000 {} <-- Current IG
Recording Var Locations at start of BB01
V00(r4) V03(r5) V01(r7) V05(r8) V04(r0)
G_M58754_IG06: ; offs=0001CCH, funclet=00
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M58754_IG01,ins#0,ofs#0) label
__prolog:
IN0044: push {r4,r5,r6,r7,r8,r9,r10,r11,lr}
IN0045: sub sp, 20
IN0046: add r11, sp, 48
*************** In genFnPrologCalleeRegArgs() for int regs
IN0047: mov r4, r0
IN0048: mov r7, r1
IN0049: mov r6, r2
IN004a: mov r5, r3
*************** In genEnregisterIncomingStackArgs()
IN004b: ldr r0, [sp+0x38] // [V04 arg4]
IN004c: ldr r8, [sp+0x3c] // [V05 arg5]
1 tracked GC refs are at stack offsets -0030 ... -002C
G_M58754_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=00000000 {}, gcRegGCrefSetCur=0100 {r8}, gcRegByrefSetCur=0000 {}
IN004d: add sp, 20
IN004e: pop {r4,r5,r6,r7,r8,r9,r10,r11,pc}
G_M58754_IG05: ; offs=0000CCH, funclet=00
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M58754_IG01: ; func=00, offs=000000H, size=0018H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M58754_IG02: ; offs=000018H, size=00A2H, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}, byref
G_M58754_IG03: ; offs=0000BAH, size=0016H, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}, byref
G_M58754_IG04: ; offs=0000D0H, size=0014H, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, byref
G_M58754_IG05: ; offs=0000E4H, size=0006H, epilog, nogc, emitadd
G_M58754_IG06: ; offs=0000EAH, size=000CH, gcVars=00000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref
*************** In emitJumpDistBind()
Binding: IN0003: beq L_M58754_BB03
Binding L_M58754_BB03 to G_M58754_IG03
Estimate of fwd jump [008D69E0/003]: 0020 -> 00BA = 0096
Shrinking jump [008D69E0/003]
Binding: IN000f: bhs L_M58754_BB06
Binding L_M58754_BB06 to G_M58754_IG06
Estimate of fwd jump [008D6A8C/015]: 0042 -> 00E6 = 00A0
Shrinking jump [008D6A8C/015]
Adjusted offset of block 03 from 00BA to 00B2
Binding: IN0035: bne L_M58754_BB05
Binding L_M58754_BB05 to G_M58754_IG04
Estimate of fwd jump [008D6DF4/053]: 00B6 -> 00C8 = 000E
Shrinking jump [008D6DF4/053]
Binding: IN0039: bhs L_M58754_BB06
Binding L_M58754_BB06 to G_M58754_IG06
Estimate of fwd jump [008D6E38/057]: 00BE -> 00DE = 001C
Shrinking jump [008D6E38/057]
Adjusted offset of block 04 from 00D0 to 00C0
Binding: IN003d: bhs L_M58754_BB06
Binding L_M58754_BB06 to G_M58754_IG06
Estimate of fwd jump [008D6F84/061]: 00C8 -> 00DA = 000E
Shrinking jump [008D6F84/061]
Adjusted offset of block 05 from 00E4 to 00D0
Adjusted offset of block 06 from 00EA to 00D6
Total shrinkage = 20, min extra short jump size = 4294967295, min extra medium jump size = 4294967295
Hot code size = 0xE2 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0xc)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M58754_IG01: ; func=00, offs=000000H, size=0018H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0044: 000000 E92D 4FF0 push {r4,r5,r6,r7,r8,r9,r10,r11,lr}
IN0045: 000004 B085 sub sp, 20
IN0046: 000006 F10D 0B30 add r11, sp, 48
gcrReg +[r4]
IN0047: 00000A 4604 mov r4, r0
IN0048: 00000C 460F mov r7, r1
IN0049: 00000E 4616 mov r6, r2
IN004a: 000010 461D mov r5, r3
IN004b: 000012 980E ldr r0, [sp+0x38] // [V04 arg4]
gcrReg +[r8]
IN004c: 000014 F8DD 803C ldr r8, [sp+0x3c] // [V05 arg5]
G_M58754_IG02: ; func=00, offs=000018H, size=009AH, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}, byref, isz
IN0001: 000018 FA5F F980 uxtb r9, r0
IN0002: 00001C F1B9 0F00 cmp r9, 0
IN0003: 000020 D047 beq SHORT G_M58754_IG03
IN0004: 000022 F244 008C movw r0, 0x408c
IN0005: 000026 F2C0 0092 movt r0, 0x92
IN0006: 00002A 6800 ldr r0, [r0]
IN0007: 00002C EA4F 7AE0 asr r10, r0, 31
IN0008: 000030 4606 mov r6, r0
IN0009: 000032 F641 40B4 movw r0, 0x1cb4
IN000a: 000036 F2C0 50FD movt r0, 0x5fd
gcrReg +[r0]
IN000b: 00003A 6800 ldr r0, [r0]
IN000c: 00003C 2100 movs r1, 0
IN000d: 00003E 6842 ldr r2, [r0+4]
IN000e: 000040 4291 cmp r1, r2
IN000f: 000042 D248 bhs SHORT G_M58754_IG06
gcrReg -[r0]
IN0010: 000044 8900 ldrh r0, [r0+8]
IN0011: 000046 F8AD 000C strh r0, [sp+0x0c] // [V02 arg2]
IN0012: 00004A F641 40AC movw r0, 0x1cac
IN0013: 00004E F2C0 50FD movt r0, 0x5fd
gcrReg +[lr]
IN0014: 000052 F8D0 E000 ldr lr, [r0]
[008D747C] gcr var born at [r11-30H]
IN0015: 000056 F8CD E000 str lr, [sp] // [V09 tmp1]
gcrReg +[r0]
IN0016: 00005A 4670 mov r0, lr
IN0017: 00005C F644 1194 movw r1, 0x4994
IN0018: 000060 F2C0 0192 movt r1, 0x92
IN0019: 000064 F644 3210 movw r2, 0x4b10
IN001a: 000068 F2C0 0292 movt r2, 0x92
IN001b: 00006C F245 5CA0 movw r12, 0x55a0
IN001c: 000070 F6C0 7CDA movt r12, 0xfda
New GC ref live vars=00000080 {V09}
New gcrReg live regs=0110 {r4 r8}
; Call at 0074 [stk=0], GCvars=[r11-30H], gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}
IN001d: 000074 47E0 blx r12 // CORINFO_HELP_VIRTUAL_FUNC_PTR
IN001e: 000076 9002 str r0, [sp+0x08] // [V10 tmp2]
gcrReg +[r0]
IN001f: 000078 9800 ldr r0, [sp] // [V09 tmp1]
IN0020: 00007A 4632 mov r2, r6
IN0021: 00007C 4653 mov r3, r10
IN0022: 00007E 9902 ldr r1, [sp+0x08] // [V10 tmp2]
New GC ref live vars=00000000 {}
[008D747C] gcr var died at [r11-30H]
New gcrReg live regs=0110 {r4 r8}
; Call at 0080 [stk=0], GCvars=none, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}
IN0023: 000080 4788 blx r1
IN0024: 000082 F641 40AC movw r0, 0x1cac
IN0025: 000086 F2C0 50FD movt r0, 0x5fd
gcrReg +[r6]
IN0026: 00008A 6806 ldr r6, [r0]
gcrReg +[r0]
IN0027: 00008C 4630 mov r0, r6
IN0028: 00008E F644 1194 movw r1, 0x4994
IN0029: 000092 F2C0 0192 movt r1, 0x92
IN002a: 000096 F644 3274 movw r2, 0x4b74
IN002b: 00009A F2C0 0292 movt r2, 0x92
IN002c: 00009E F245 53A0 movw r3, 0x55a0
IN002d: 0000A2 F6C0 73DA movt r3, 0xfda
New gcrReg live regs=0150 {r4 r6 r8}
; Call at 00A6 [stk=0], GCvars=none, gcrefRegs=0150 {r4 r6 r8}, byrefRegs=0000 {}
IN002e: 0000A6 4798 blx r3 // CORINFO_HELP_VIRTUAL_FUNC_PTR
IN002f: 0000A8 9001 str r0, [sp+0x04] // [V12 tmp4]
gcrReg +[r0]
IN0030: 0000AA 4630 mov r0, r6
IN0031: 0000AC 9903 ldr r1, [sp+0x0c] // [V02 arg2]
IN0032: 0000AE 9B01 ldr r3, [sp+0x04] // [V12 tmp4]
New gcrReg live regs=0110 {r4 r8}
; Call at 00B0 [stk=0], GCvars=none, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}
IN0033: 0000B0 4798 blx r3
G_M58754_IG03: ; func=00, offs=0000B2H, size=000EH, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}, byref, isz
IN0034: 0000B2 F1B9 0F00 cmp r9, 0
IN0035: 0000B6 D103 bne SHORT G_M58754_IG04
IN0036: 0000B8 2000 movs r0, 0
IN0037: 0000BA 6863 ldr r3, [r4+4]
IN0038: 0000BC 4298 cmp r0, r3
IN0039: 0000BE D20A bhs SHORT G_M58754_IG06
G_M58754_IG04: ; func=00, offs=0000C0H, size=0010H, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, byref, isz
New gcrReg live regs=0100 {r8}
IN003a: 0000C0 2000 movs r0, 0
IN003b: 0000C2 F8D8 3004 ldr r3, [r8+4]
IN003c: 0000C6 4298 cmp r0, r3
IN003d: 0000C8 D205 bhs SHORT G_M58754_IG06
IN003e: 0000CA F888 5008 strb r5, [r8+8]
IN003f: 0000CE B2B8 uxth r0, r7
G_M58754_IG05: ; func=00, offs=0000D0H, size=0006H, epilog, nogc, emitadd
IN004d: 0000D0 B005 add sp, 20
IN004e: 0000D2 E8BD 8FF0 pop {r4,r5,r6,r7,r8,r9,r10,r11,pc}
G_M58754_IG06: ; func=00, offs=0000D6H, size=000CH, gcVars=00000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref
New gcrReg live regs=0000 {}
IN0040: 0000D6 F647 33B0 movw r3, 0x7bb0
IN0041: 0000DA F6C0 73DA movt r3, 0xfda
; Call at 00DE [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0042: 0000DE 4798 blx r3 // CORINFO_HELP_RNGCHKFAIL
IN0043: 0000E0 DEFE bkpt
Allocated method code size = 226 , actual size = 226
*************** After end code gen, before unwindEmit()
G_M58754_IG01: ; func=00, offs=000000H, size=0018H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0044: 000000 push {r4,r5,r6,r7,r8,r9,r10,r11,lr}
IN0045: 000004 sub sp, 20
IN0046: 000006 add r11, sp, 48
IN0047: 00000A mov r4, r0
IN0048: 00000C mov r7, r1
IN0049: 00000E mov r6, r2
IN004a: 000010 mov r5, r3
IN004b: 000012 ldr r0, [sp+0x38] // [V04 arg4]
IN004c: 000014 ldr r8, [sp+0x3c] // [V05 arg5]
G_M58754_IG02: ; offs=000018H, size=009AH, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}, byref, isz
IN0001: 000018 uxtb r9, r0
IN0002: 00001C cmp r9, 0
IN0003: 000020 beq SHORT G_M58754_IG03
IN0004: 000022 movw r0, 0x408c
IN0005: 000026 movt r0, 0x92
IN0006: 00002A ldr r0, [r0]
IN0007: 00002C asr r10, r0, 31
IN0008: 000030 mov r6, r0
IN0009: 000032 movw r0, 0x1cb4
IN000a: 000036 movt r0, 0x5fd
IN000b: 00003A ldr r0, [r0]
IN000c: 00003C movs r1, 0
IN000d: 00003E ldr r2, [r0+4]
IN000e: 000040 cmp r1, r2
IN000f: 000042 bhs SHORT G_M58754_IG06
IN0010: 000044 ldrh r0, [r0+8]
IN0011: 000046 strh r0, [sp+0x0c] // [V02 arg2]
IN0012: 00004A movw r0, 0x1cac
IN0013: 00004E movt r0, 0x5fd
IN0014: 000052 ldr lr, [r0]
IN0015: 000056 str lr, [sp] // [V09 tmp1]
IN0016: 00005A mov r0, lr
IN0017: 00005C movw r1, 0x4994
IN0018: 000060 movt r1, 0x92
IN0019: 000064 movw r2, 0x4b10
IN001a: 000068 movt r2, 0x92
IN001b: 00006C movw r12, 0x55a0
IN001c: 000070 movt r12, 0xfda
IN001d: 000074 blx r12 // CORINFO_HELP_VIRTUAL_FUNC_PTR
IN001e: 000076 str r0, [sp+0x08] // [V10 tmp2]
IN001f: 000078 ldr r0, [sp] // [V09 tmp1]
IN0020: 00007A mov r2, r6
IN0021: 00007C mov r3, r10
IN0022: 00007E ldr r1, [sp+0x08] // [V10 tmp2]
IN0023: 000080 blx r1
IN0024: 000082 movw r0, 0x1cac
IN0025: 000086 movt r0, 0x5fd
IN0026: 00008A ldr r6, [r0]
IN0027: 00008C mov r0, r6
IN0028: 00008E movw r1, 0x4994
IN0029: 000092 movt r1, 0x92
IN002a: 000096 movw r2, 0x4b74
IN002b: 00009A movt r2, 0x92
IN002c: 00009E movw r3, 0x55a0
IN002d: 0000A2 movt r3, 0xfda
IN002e: 0000A6 blx r3 // CORINFO_HELP_VIRTUAL_FUNC_PTR
IN002f: 0000A8 str r0, [sp+0x04] // [V12 tmp4]
IN0030: 0000AA mov r0, r6
IN0031: 0000AC ldr r1, [sp+0x0c] // [V02 arg2]
IN0032: 0000AE ldr r3, [sp+0x04] // [V12 tmp4]
IN0033: 0000B0 blx r3
G_M58754_IG03: ; offs=0000B2H, size=000EH, gcrefRegs=0110 {r4 r8}, byrefRegs=0000 {}, byref, isz
IN0034: 0000B2 cmp r9, 0
IN0035: 0000B6 bne SHORT G_M58754_IG04
IN0036: 0000B8 movs r0, 0
IN0037: 0000BA ldr r3, [r4+4]
IN0038: 0000BC cmp r0, r3
IN0039: 0000BE bhs SHORT G_M58754_IG06
G_M58754_IG04: ; offs=0000C0H, size=0010H, gcrefRegs=0100 {r8}, byrefRegs=0000 {}, byref, isz
IN003a: 0000C0 movs r0, 0
IN003b: 0000C2 ldr r3, [r8+4]
IN003c: 0000C6 cmp r0, r3
IN003d: 0000C8 bhs SHORT G_M58754_IG06
IN003e: 0000CA strb r5, [r8+8]
IN003f: 0000CE uxth r0, r7
G_M58754_IG05: ; offs=0000D0H, size=0006H, epilog, nogc, emitadd
IN004d: 0000D0 add sp, 20
IN004e: 0000D2 pop {r4,r5,r6,r7,r8,r9,r10,r11,pc}
G_M58754_IG06: ; offs=0000D6H, size=000CH, gcVars=00000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref
IN0040: 0000D6 movw r3, 0x7bb0
IN0041: 0000DA movt r3, 0xfda
IN0042: 0000DE blx r3 // CORINFO_HELP_RNGCHKFAIL
IN0043: 0000E0 bkpt
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x0000e2 (not in unwind data)
Code Words : 1
Epilog Count : 1
F bit : 0
E bit : 0
X bit : 0
Vers : 0
Function Length : 113 (0x00071) Actual length = 226 (0x0000e2)
---- Epilog scopes ----
---- Scope 0
Epilog Start Offset : 104 (0x00068) Actual offset = 208 (0x0000d0) Offset from main function begin = 208 (0x0000d0)
Condition : 14 (0xe) (always)
Epilog Start Index : 0 (0x00)
---- Unwind codes ----
---- Epilog start at index 0 ----
05 add sp, sp, #20 ; opsize 16
DF pop {r4,r5,r6,r7,r8,r9,r10,r11,lr} ; opsize 32
FF end
FF end
allocUnwindInfo(pHotCode=0x00F82280, pColdCode=0x00000000, startOffset=0x0, endOffset=0xe2, unwindSize=0xc, pUnwindBlock=0x00886CAE, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 12
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000018 ( STACK_EMPTY )
IL offs 0x0004 : 0x00000022 ( STACK_EMPTY )
IL offs 0x000B : 0x00000032 ( STACK_EMPTY )
IL offs 0x0016 : 0x0000004A ( STACK_EMPTY )
IL offs 0x0021 : 0x00000082 ( STACK_EMPTY )
IL offs 0x002C : 0x000000B2 ( STACK_EMPTY )
IL offs 0x0030 : 0x000000B8 ( STACK_EMPTY )
IL offs 0x0034 : 0x000000C0 ( STACK_EMPTY )
IL offs 0x0039 : 0x000000CE ( STACK_EMPTY )
IL offs EPILOG : 0x000000D0 ( STACK_EMPTY )
IL offs NO_MAP : 0x000000D6 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 10
*************** Variable debug info
10 vars
1( UNKNOWN) : From 00000000h to 00000018h, in r1
2( UNKNOWN) : From 00000000h to 00000018h, in r2
3( UNKNOWN) : From 00000000h to 00000018h, in r3
4( UNKNOWN) : From 00000000h to 00000018h, in sp[4] (1 slot)
5( UNKNOWN) : From 00000000h to 00000018h, in sp[8] (1 slot)
0( UNKNOWN) : From 00000000h to 00000018h, in r0
0( UNKNOWN) : From 00000018h to 000000BAh, in r4
5( UNKNOWN) : From 00000018h to 000000CAh, in r8
3( UNKNOWN) : From 00000018h to 000000CAh, in r5
1( UNKNOWN) : From 00000018h to 000000CEh, in r7
*************** In gcInfoBlockHdrSave()
Set code length to 226.
Set ReturnKind to Scalar.
Set stack base register to r11.
Set Outgoing stack arg area size to 0.
Stack slot id for offset -48 (0xffffffd0) (frame) = 0.
Register slot id for reg r4 = 1.
Register slot id for reg r8 = 2.
Register slot id for reg r6 = 3.
Set state of slot 0 at instr offset 0x5a to Live.
Set state of slot 0 at instr offset 0x80 to Dead.
Set state of slot 1 at instr offset 0x74 to Live.
Set state of slot 2 at instr offset 0x74 to Live.
Set state of slot 1 at instr offset 0x76 to Dead.
Set state of slot 2 at instr offset 0x76 to Dead.
Set state of slot 1 at instr offset 0x80 to Live.
Set state of slot 2 at instr offset 0x80 to Live.
Set state of slot 1 at instr offset 0x82 to Dead.
Set state of slot 2 at instr offset 0x82 to Dead.
Set state of slot 1 at instr offset 0xa6 to Live.
Set state of slot 3 at instr offset 0xa6 to Live.
Set state of slot 2 at instr offset 0xa6 to Live.
Set state of slot 1 at instr offset 0xa8 to Dead.
Set state of slot 3 at instr offset 0xa8 to Dead.
Set state of slot 2 at instr offset 0xa8 to Dead.
Set state of slot 1 at instr offset 0xb0 to Live.
Set state of slot 2 at instr offset 0xb0 to Live.
Set state of slot 1 at instr offset 0xb2 to Dead.
Set state of slot 2 at instr offset 0xb2 to Dead.
Defining 5 call sites:
Offset 0x74, size 2.
Offset 0x80, size 2.
Offset 0xa6, size 2.
Offset 0xb0, size 2.
Offset 0xde, size 2.
Method code size: 226
Allocations for Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort (MethodHash=c9f11a7d)
count: 2025, size: 121761, max = 2600
allocateMemory: 131072, nraUsed: 123356
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 5412 | 4.44%
ASTNode | 19880 | 16.33%
InstDesc | 5236 | 4.30%
ImpStack | 192 | 0.16%
BasicBlock | 1332 | 1.09%
fgArgInfo | 440 | 0.36%
fgArgInfoPtrArr | 40 | 0.03%
FlowList | 120 | 0.10%
TreeStatementList | 32 | 0.03%
SiScope | 524 | 0.43%
FlatFPStateX87 | 0 | 0.00%
DominatorMemory | 128 | 0.11%
LSRA | 2908 | 2.39%
LSRA_Interval | 2968 | 2.44%
LSRA_RefPosition | 13048 | 10.72%
Reachability | 8 | 0.01%
SSA | 1516 | 1.25%
ValueNumber | 20550 | 16.88%
LvaTable | 6440 | 5.29%
UnwindInfo | 16 | 0.01%
hashBv | 100 | 0.08%
bitset | 1132 | 0.93%
FixedBitVect | 0 | 0.00%
Generic | 1818 | 1.49%
IndirAssignMap | 0 | 0.00%
FieldSeqStore | 168 | 0.14%
ZeroOffsetFieldMap | 28 | 0.02%
ArrayInfoMap | 164 | 0.13%
MemoryPhiArg | 16 | 0.01%
CSE | 1196 | 0.98%
GC | 2385 | 1.96%
CorSig | 104 | 0.09%
Inlining | 636 | 0.52%
ArrayStack | 0 | 0.00%
DebugInfo | 464 | 0.38%
DebugOnly | 29820 | 24.49%
Codegen | 752 | 0.62%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 388 | 0.32%
RangeCheck | 680 | 0.56%
CopyProp | 1120 | 0.92%
****** DONE compiling Program:M11(ref,ushort,ushort,ubyte,bool,ref):ushort
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