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jaytaph/gist:8d4b56ba47008398789ca8d2da4fe363

Last active December 30, 2016 09:47
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6526 tests
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gistfile1.txt
Ports A and B each consist of an 8-bit Peripheral
Data Register (PR) and an 8-bit Data Direction Register
(DDR).
If a bit in the DDR is set to the corresponding bit
in the PR is an output, if a DDR bit is set to a zero, the
corresponding PR bit is defined as an input.
On a READ, the PR reflects the information present on the
actual port pins (PA0-PA7, PBOPB7) for both input and
output bits.
Situatie 1:
PA0 0000 1111
Schrijf DDRA: 1101 0100 (1 = output, o = input)
Lees PRA: 0000 1111
Situatie 2:
PA0 0000 1111
Schrijf DDRA: 1101 0100 (1 = output, o = input)
Schrijf PRA: 0000 1111
naar PA0: 00?0 ?1??
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