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jborza/lcd1602.vhd

Created Oct 4, 2020
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LCD1602 IS
PORT (
CLK : IN std_logic; --clock
Reset : IN std_logic;
LCD_RS : OUT std_logic; --LCD Reset
LCD_RW : OUT std_logic; --LCD Read / Write
LCD_EN : OUT std_logic; --LCD Enable
LCD_Data : OUT std_logic_vector(7 DOWNTO 0)); --8-bit LCD data
END LCD1602;
ARCHITECTURE Behavioral OF LCD1602 IS
TYPE state IS (set_dlnf, set_cursor, set_dcb, set_cgram, write_cgram, set_ddram, write_LCD_Data);
SIGNAL Current_State : state;
TYPE ram1 IS ARRAY(0 TO 30) OF std_logic_vector(7 DOWNTO 0);
TYPE ram2 IS ARRAY(0 TO 30) OF std_logic_vector(7 DOWNTO 0);
TYPE ram3 IS ARRAY(0 TO 30) OF std_logic_vector(7 DOWNTO 0);
--Wazzup my boi? Let's partay !!!
CONSTANT cgram1 : ram1 := (x"6a",x"62",x"6f",x"72",x"7a",x"61",x"2e",x"63",x"6f",x"6d",x"20",x"20",x"20",x"20",x"20",x"20",x"4c",x"43",x"44",x"31",x"36",x"30",x"32",x"20",x"64",x"65",x"6d",x"6f",x"20",x"20",x"20");
--jborza.com LCD1602 demo
CONSTANT cgram3 : ram3 := (x"4c",x"43",x"44",x"31",x"36",x"30",x"32",x"20",x"64",x"65",x"6d",x"6f",x"20",x"20",x"68",x"74",x"74",x"70",x"3a",x"2f",x"2f",x"6a",x"62",x"6f",x"72",x"7a",x"61",x"2e",x"63",x"6f",x"6d");
--Hello World Hello World Hello
CONSTANT cgram2 : ram2 := (x"48",x"65",x"6c",x"6c",x"6f",x"20",x"57",x"6f",x"72",x"6c",x"64",x"20",x"48",x"65",x"6c",x"6c",x"6f",x"20",x"57",x"6f",x"72",x"6c",x"64",x"20",x"48",x"65",x"6c",x"6c",x"6f",x"20",x"57");
SIGNAL CLK1 : std_logic;
SIGNAL Clk_Out : std_logic;
SIGNAL LCD_Clk : std_logic;
SIGNAL m : std_logic_vector(1 DOWNTO 0);
BEGIN
LCD_EN <= Clk_Out;
LCD_RW <= '0';
PROCESS (CLK)
VARIABLE n1 : INTEGER RANGE 0 TO 19999;
BEGIN
IF rising_edge(CLK) THEN
IF n1 < 19999 THEN
n1 := n1 + 1;
ELSE
n1 := 0;
Clk_Out <= NOT Clk_Out;
END IF;
END IF;
END PROCESS;
LCD_Clk <= Clk_Out;
PROCESS (Clk_Out)
VARIABLE n2 : INTEGER RANGE 0 TO 499;
BEGIN
IF rising_edge(Clk_Out) THEN
IF n2 < 499 THEN
n2 := n2 + 1;
ELSE
n2 := 0;
Clk1 <= NOT Clk1;
END IF;
END IF;
END PROCESS;
PROCESS (Clk1)
VARIABLE n3 : INTEGER RANGE 0 TO 14;
BEGIN
IF rising_edge(Clk1) THEN
n3 := n3 + 1;
IF n3 <= 4 THEN
m <= "00";
ELSIF n3 <= 9 AND n3 > 4 THEN
m <= "01";
ELSE
m <= "10";
END IF;
END IF;
END PROCESS;
PROCESS (LCD_Clk, Reset, Current_State)
VARIABLE cnt1 : std_logic_vector(4 DOWNTO 0);
BEGIN
IF Reset = '0'THEN
Current_State <= set_dlnf;
cnt1 := "11110";
LCD_RS <= '0';
ELSIF rising_edge(LCD_Clk) THEN
Current_State <= Current_State;
LCD_RS <= '0';
CASE Current_State IS
WHEN set_dlnf =>
cnt1 := "00000";
LCD_Data <= "00000001"; -- /*ÇĺłýĎÔĘž*/
Current_State <= set_cursor;
WHEN set_cursor =>
LCD_Data <= "00111000"; --/*ÉčÖĂ8Îť¸ńĘ˝,2ĐĐ,5*7*/
Current_State <= set_dcb;
WHEN set_dcb =>
LCD_Data <= "00001100"; --/*ŐűĚĺĎÔĘž,šŘšâąę,˛ťÉÁ˸*/
Current_State <= set_cgram;
WHEN set_cgram =>
LCD_Data <= "00000110";
Current_State <= write_cgram;
WHEN write_cgram =>
LCD_RS <= '1';
IF m = "00" THEN
LCD_Data <= cgram1(conv_integer(cnt1));
ELSIF m = "01"THEN
LCD_Data <= cgram2(conv_integer(cnt1));
ELSE
LCD_Data <= cgram3(conv_integer(cnt1));
END IF;
Current_State <= set_ddram;
WHEN set_ddram =>
IF cnt1 < "11110" THEN
cnt1 := cnt1 + 1;
ELSE
cnt1 := "00000";
END IF;
IF cnt1 <= "01111" THEN
LCD_Data <= "10000000" + cnt1;--80H
ELSE
LCD_Data <= "11000000" + cnt1 - "10000";--80H
END IF;
Current_State <= write_LCD_Data;
WHEN write_LCD_Data =>
LCD_Data <= "00000000";
Current_State <= set_cursor;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END Behavioral;
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