Noriaki Chiba
translated by Joe Groff
Fujitsu's FM personal computer series began with 1981's FM8. In the following year, it was split into a hobby model (FM7) and business model (FM11). The FM7 was an especially big hit, contributing to the FM series' popularity. From there, the hobby line evolved into the FM77 (1984), equipped with a 3.5" floppy drive, and with the dawn of the multimedia era, the FM77AV (1985). All of these hobby computers were 8-bit machines, but in 1989, under the slogan "The personal computer is changing. TOWNS is changing it!", the FM TOWNS came out, making one big leap to a 32-bit CPU. The power of the typical CPU had become insufficient for the massive amount of data processing needed for audio and video content, making the need for a massive change obvious. To that end, a bold new computer line was imagined, equipped with things like a CD-ROM drive capable of playing music CDs and dedicated hardware designed for high-speed graphics. Unfortunately, there wasn't enough introductory material available for this new hardware, which was much more complex than what came before, so developers wanting to make full use of the TOWNS were unable to.
That is why the author wrote this book, to serve as an essential manual for enthusiasts, systems developers, and software developers. Typical computer manuals do not adequately cover technical specifications, so users tend to have a hard time understanding the hardware. We have an opportunity to thoroughly break through this barrier, and with this new hardware architecture being a milestone in the FM series, it feels like the perfect time to try. Hardware manuals up to this point have typically only explained the consequences of the hardware design without explaining its fundamentals. By contrast, this book describes the hardware design of the TOWNS from its foundations. Since even expert systems developers can feel like amateurs when working with devices outside of their repertoire, this book focuses on explaining those foundations. This is especially necessary for the FM TOWNS, since it features so many new devices, including a 80386 CPU and a CD-ROM drive.
One particularly special feature of this book is that, thanks to the contributions of our anonymous analysis team, it details the memory address map and hardware map, things the manufacturer has never released. Since this information is essential not only for systems and application developers but also enthusiasts, we achieved this regardless of the cost. Please understand though that this goes beyond anything the manufacturer guarantees, and future models may change without prior notice.
Also, in part II of this book, we describe the BIOS available under TOWNS OS. Generally, controlling the computer by setting every individual register is difficult, and using the BIOS is simpler. The appendices at the end of this book further describe the new abilities that every revision of the hardware has added on top of the first TOWNS generation. We also describe the most current update of the BIOS, so please be aware that we include things that cannot be used in previous versions of the BIOS.
With this book as a guide, if it encourages the development of software and expansion cards that make full use of the FM TOWNS' capability, nothing would make the author happier.
Finally, from the bottom of my heart, I would like to thank everyone at ASCII Press's Third Editing Department, who approved the plan for this book and did the hard work of editing it, as well as everyone on the analysis team for their contributions.
Noriaki Chiba, Author
May 1994
- In Part I of this book, we describe the FM TOWNS (Model 1 and Model 2) hardware. Appendices G-O describe the specification changes of newly-released models.
- In Part II of this book, we describe the newest BIOS that can be used under TOWNS OS (both the FM TOWNS' unique BIOS, and the FMR-50 compatibility BIOS).
- Consider that the FM TOWNS' hardware specification changes with each model, but compatibility is maintained at the BIOS level. For this reason, when making programs for distribution, although directly accessing I/O devices is possible, it is best avoided, and using things like the BIOS and the C programming language is recommended.
- We aim to make the contents of this book as accurate as possible, but the reality is that under particular situations, there are cases where the hardware does not behave exactly as described. When writing hardware and software, please take sufficient care.
- In this book, we refer to the 386 as 80386, and the 486 as 80486.
In this chapter, we describe the appearance and specifications of the FM TOWNS main unit and attached peripherals, and we outline the memory map and I/O interface. For details on each component, please consult the subsequent chapters.
The FM TOWNS main unit's appearance and components are named in diagram I-1-1, and the specifications are described in table I-1-1.
[diagram I-1-1]
| Item | Specification | ||
| Model 1 | Model 2 | ||
| CPU | 80386 (16MHz) | ||
| Math Coprocessor | Optional (80387) | ||
| System ROM | 256KB | ||
| OS ROM | 512KB | ||
| ROM Card Slot | 1 Slot | ||
| Main RAM | 1MB (32 bit) | 2MB (32 bit) | |
| VRAM | 512KB (32 bit) | 512KB (32 bit) | |
| Sprite RAM | 128KB (16 bit) | 128KB (16 bit) | |
| Graphics | 640x480 pixels, 256/16.7M colors with 1 screen or 16/4096 colors with 2 screens
320x240 pixels, 32,768 colors with 2 screens 360x240 pixels, 32,768 colors with 2 screens etc. |
||
| Kanji ROM | JIS level 1 and 2, 256KB | ||
| Dictionary ROM | 512KB | ||
| CMOS RAM | 8KB, battery-backed | ||
| PCM wavetable RAM | 64KB | ||
| Sound sources | OPLL (FM sound source with 6 voices)
PCM (8 voices) |
||
| Internal modem | Optional | ||
| Clock | Battery-backed | ||
| Interfaces | CRT | Analog RGB built-in | |
| Floppy drive | Built-in | ||
| TOWNS mouse | Built-in | ||
| TOWNS gamepad | Built-in | ||
| RS-232C | 1 connection built-in | ||
| Centronics | 1 connection built-in | ||
| SCSI | Optional | ||
| Video card slot | 1 slot | ||
| Keyboard | Optional (thumb shift or JIS) | ||
| TOWNS mouse | Included standard | ||
| TOWNS gamepad | Included standard | ||
| Storage | 3.5" floppy drive | 1x double high density drive | 2x double high density drives |
| CD-ROM | 1 internal drive | ||
| Hard drive | Externally connected by SCSI interface | ||
| Expansion connector | I/O expansion unit connector | ||
Diagram I-1-2 describes the structure of the computer, and diagram I-1-3 provides a block diagram. The following three chapters describe in detail each kind of controller.
In order to strengthen its multimedia capabilities, the FM TOWNS uses a 16MHz 80386, which can handle large amounts of data at high speed. Additionally, when the computer is equipped with the optional 80387 math coprocessor, it can perform floating-point computations at high speed. The 80387 is installed into the computer's internal math coprocessor slot.
As shipped, the Model 1 provides 1MB of main RAM for user programs, and the Model 2 provides 2MB. Beyond that, there is 512KB of VRAM, 128KB of sprite RAM, and 64KB of wavetable RAM for the PCM sound generator. Also, using optional RAM modules (expansion memory), which can be installed into the internal RAM module slots, the computer can be expanded to up to 6MB of RAM.
The system comes with 256KB of system ROM and 512KB of OS ROM. Additionally, there is 256KB of Kanji ROM, 512KB of dictionary ROM, and 8KB of battery-backed CMOS RAM. In the ROM slot on top of the computer, a ROM card written with a program to automatically launch at boot can be inserted.
For the keyboard, there are options for a JIS keyboard or thumb-shift keyboard, each having the choice of with or without a 10-key keypad. The keyboard uses a serial interface, and is compatible with the FMR-50.
For input devices, a gamepad and intelligent mouse are provided standard. Since they use a different specification from the FMR series, these are called the TOWNS gamepad and TOWNS mouse.
The computer uses 3.5" floppy drives that support both two-sided high density and two-sided double density formats. The Model 2 is equipped with two drives. The Model 1 is equipped with one drive, but an optional second drive can be connected. Furthermore, a single 5.25" two-sided high density/two-sided double density drive can be externally attached.
An internal CD-ROM drive is equipped for read-only storage. A CD-ROM disk has 540MB of storage. The drive can also be used as a standard audio CD player. When used this way, the audio output can be routed to the computer's speakers.
[Translator's note: the book consistently refers to CD-ROM capacity as 540MB, although a standard CD-ROM can store at least 650MB.]
To handle the high-end graphics system, which supports high-speed sprites and modes with either 32,768 simultaneous colors or 256 colors out of 16,777,216 possible colors (henceforth abbreviated in this book as 16.77 million colors), the TOWNS uses an analog RGB display.
For audio sources, the computer provides PCM (8 simultaneous voices in stereo) and FM (6 simultaneous voices in stereo). Various input connectors are also provided, so that electronic instruments and AV equipment can be connected. Mixed output is possible, with software controlling the volumes of the internal audio sources and input signals.
The computer is equipped with a microphone, providing monaural audio input.
A microphone connector is provided to connect an external microphone. A stereo microphone can be used, but since the input path only has one channel, the left and right channels of the input will be combined into a monaural signal.
One internal monitor speaker is provided. Sound playback through the internal speaker combines the left and right channels.
With both left and right channel audio output, a set of headphones can be connected for stereo listening.
An amplifier, cassette deck, video recorder, electronic instrument, or other audio equipment can be connected.
This is a standard computer interface primarily used to connect printers. This port provides an 8-bit parallel, output-only interface.
A standard RS-232C computer interface port is provided. RS-232C is a serial interface that supports bidirectional communication. The FM TOWNS also has a dedicated slot for installing a modem card, but it uses the same signal sources as the RS-232C port, so only one can be used at the same time.
On the back of the FM TOWNS are dedicated slots for installing a modem card, video card, and SCSI card. The top also has a dedicated slot for a ROM card.
- SCSI card: This card can connect to hard disks and other devices with SCSI interfaces.
- Modem card: By installing the modem card into its dedicated slot, an internal modem becomes available, enabling the sending and receiving of communication signals over telephone lines.
- Video card: By providing video input and output connectors, the video card makes it possible to connect devices like video cameras and VCRs. This card can be used to do things like digitize video and generate captions.
The FM TOWNS system can be further extended with its expansion unit, which provides three expansion slots into which expansion cards can be installed. Cards such as the RS-232C card (for when the internal RS-232C port alone is not enough) or a MIDI card can be installed.
Here, we will take a first look at the FM TOWNS' memory map and I/O address map.
Diagram I-1-4 shows the memory map.
[diagram I-1-4]
I/O interfaces serve as intermediaries between the CPU and I/O devices (such as the CRT, keyboard, or CD-ROM drive) when data is passed between them. The CPU cannot directly read from or write to I/O devices, so when data is to be read or written to an I/O device, it is done via that device's respective I/O interface.
For each kind of I/O device, various control ICs are provided. Writing to an I/O interface involves writing to these control ICs' registers.
Two ways to connect a CPU to an I/O interface are memory-mapped I/O and isolated I/O.
Specific addresses within memory act as I/O addresses. Computers such as 8-bit machines using the 6809 CPU (including the hobby FM series) use this technique.
I/O addresses are established in a separate address space outside of memory, so that I/O and memory are independent. CPUs such as the 8086, 80286, and 80386 use this technique.
The FM TOWNS fundamentally uses isolated I/O, though some parts of it do use memory-mapped I/O. Diagram I-1-5 shows the isolated I/O address map. Table I-1-2 further details the I/O address map.
Memory-mapped I/O regions include the 0x000C_FF80 - 0x000C_FFDF region within the 32KB IO/CVRAM (I/O character VRAM) region (diagram I-1-6). Also, 1GB out of the 4GB address space is assigned for use by the I/O expansion slots, so this address space can be used for memory-mapped I/O when an expansion card is present.
Table I-1-3 shows the contents of the memory-mapped IO regions.
[diagram I-1-6]
[table I-1-2]
[table I-1-3]
In this chapter, we give an overview of the 80386 CPU used by the FM TOWNS. The 80386 is a high-speed CPU with a huge memory address space. It was also designed with multitasking operating systems in mind, so compared to typical CPUs, it offers greatly expanded capabilities when writing an OS.
In the first half of this chapter, we describe the 80386's software-accessible registers, including their various types and characteristics.
In the second half, we cover the 80386's special address organization and memory protection system. This section's contents are mainly related to OS development, so it is mostly irrelevant when developing application programs that run on top of an OS, but we think it is helpful for understanding how TOWNS OS, the FM TOWNS' standard OS, handles the CPU.
However, the 80386 is an extremely powerful CPU, and the entire subject cannot be covered in detail in this book. If more detailed information is needed, please consult the 80386 reference manual.
In this section, we summarize various characteristics of the 80386 CPU.
The 80386 CPU has 32-bit general purpose registers and data bus. This bit count indicates the amount of data that can be accessed at one time, meaning that four bytes of data can be read or written on each access. Therefore, operations that would typically take several steps can be completed in one step, allowing for high-speed processing.
The 80386's predecessors include the 8086, 80186, and 80286 CPUs, each of which was a 16-bit CPU, only half the data bus width of the 80386. Those CPUs were based on an architecture with a 1MB address space, organized into 64KB segments, which became an obstacle in situations like high-speed graphics display or audio data manipulation that require a lot of memory. The 80386 eliminates this obstacle, while still including all of the capabilities of previous CPUs.
The 80386 can realize a continuous 4GB (gigabytes) of address space, eliminating the previously-mentioned obstacles. Furthermore, when using virtual addressing, it becomes possible to access 64TB (terabytes) of address space. (Virtual addressing has been available since the 80286, but the 80286 virtual address space is only 1GB.)
[Translator's note: this 64TB figure is gotten by counting the 14 selector bits of the segment register as independent virtual address bits, giving 46 total address bits, although segments cannot address memory beyond the fundamental 32 bit linear address space. Likewise for the 80286, with 16-bit offsets, counting the segment register address bits independently would give a total of 30 address bits (hence the 1GB figure) even though its linear address space is only 24 bits.]
However, when using virtual addressing, the physical address space of the address bus cannot be expanded. When multiple programs share the address space, caution is necessary to ensure they work together in separate parts of the address space. The second half of this chapter goes into this in detail.
The 80386 provides the ability for several programs to run simultaneously, making it suitable for implementing a time-sharing system that multitasks by running each program in its own timeslice.
Multitasking gives the appearance of several programs executing at the same time, but in reality, the CPU is executing by switching from program to program in sequence. The 80386 provides hardware that can rapidly switch between tasks.
When multitasking, running several programs in parallel is insufficient; each program also needs to be able to run independently. In other words, if a program goes out of control or does something else invalid, trouble could arise if it ended up influencing other programs.
For this reason, in order to prevent tasks' memory spaces from being violated, the 80386 enacts memory protection (task address space protection). Tasks are divided into four access levels; for example, the OS can run in level 0 (the highest access level), and other permissions can be divided among the other access levels 1 through 3, so that a task in a lower access level is forbidden from accessing the memory of a task in a higher access level (ring protection). There are also operations which cannot be performed except from access level 0 (privileged operations). A higher-level program has to be able to manage lower levels, so invalid operations from lower levels cannot be allowed to influence higher levels.
The CPU's internal functions are separated into several units, each in charge of one stage of instruction execution. The result of each unit's processing is passed on to the next unit as it continues processing the next instruction. Because of this pipeline processing method, each unit can operate without stopping, accelerating processing speed.
Furthermore, with cache, the contents of accessed memory blocks is stored inside of the CPU, so the CPU can operate with fewer memory accesses.
The CPU is equipped with functionality necessary for debugging. Single-step execution and up to four breakpoints can be configured. Breakpoints can be set not only on instructions, but also on data.
The 80386 has three operating modes: the most fundamental mode "protected mode" ("native mode"), as well as "real mode" and "virtual 8086 mode" to preserve compatibility with the 8086 and other processors. The relationships between these modes is shown in diagram I-2-1.
[diagram I-2-1]
At reset, the 80386 initializes in real mode. This mode is 8086 compatible. However, it doesn't support virtual memory, memory protection, or multitasking operation.
When the FM TOWNS power is turned on (or reset), TOWNS OS is booted, first into real mode, shifting later into protected mode.
Protected mode is the mode that exhibits the full functionality of the 80386. To transfer from real mode to protected mode, a flag in a control register (described below) is switched. Normally, the OS handles this. Protected mode supports virtual memory, memory protection, and multitasking. This mode includes everything from 80286 protected mode, so 80286 programs can run as well.
In TOWNS OS, user programs execute in this mode.
In protected mode, several tasks can be executing, and some of them can execute as 8086 programs.
Virtual 8086 mode is a mode for executing 8086 programs under protected mode. Other kinds of protected mode tasks (80286 and 80386 programs) can coexist with this mode. Multiple virtual 8086 mode tasks can also execute. This mode is placed at protected mode's lowest privilege level (access level 3, described below), so 8086 and 80186 software can run without modification.
Since TOWNS OS is a fundamentally single-tasking OS, it does not use this mode.
In order to maintain compatibility with the 8086/88, 80186/188, and 80286, the 80386's internal registers are laid out as an extension of those processors' registers.
In this section, we describe the structure of those registers and each of their capabilities.
Diagram I-2-2 shows all of the 80386's registers.
The shaded parts of the diagram distinguish the register parts that are shared with the 8086 CPU from the 80386 extensions. Many of the registers have been extended from 16 to 32 bits. The 80386 also adds a group of registers called "system registers". Those registers are normally used by the OS to manage the system.
The registers related to application programming are the general-purpose registers, segment registers, instruction pointer, and flags register.
Below, we describe each type of register.
The 80386 has eight 32-bit general-purpose registers. Diagram I-2-3 shows the format of the general-purpose registers.
On CPUs like the 8086 and 80286, there were the 16-bit registers AX, CX, DX, BX, SP, BP, SI, and DI. Correspondingly, the 80386 has 32-bit registers EAX, ECX, EDX, EBX, ESP, EBP, ESI, and EDI. Note that each register's name begins with "E".
To manipulate 32 bits with these registers, call them by their full name "Exx". By leaving out the "E" and using only the remaining two registers in the name (AX, DI, etc.), they can be accessed as 16-bit registers.
[diagram I-2-2]
The AX, CX, DX, and BX registers can also be accessed as 8 bits. For instance, the top 8 bits of AX can be accessed as AH, and the bottom 8 bits as AL.
By the way, even though previous CPUs called these "general purpose registers", in reality they were assigned individual roles and could not be used beyond their specific uses. By contrast, the 80386's extended 32-bit registers are literally general purpose, and can all be used for arithmetic or as the address of a memory pointer.
[diagram I-2-3]
The 80386 has six 16-bit segment registers. Diagram I-2-4 shows the format of the segment registers.
There are three kinds of segment, with corresponding segment registers as follows:
- Code segments: CS
- Stack segments: SS
- Data segments: DS, ES, FS, GS
A stack segment can also contain data, so it is reasonable to use the same value as both a data and stack segment.
The FS and GS segment registers for data segment use were added by the 80386. Because of this, the 80386 can manipulate four data regions simultaneously.
The behavior of segment registers changes depending on the operating mode of the 80386.
In real mode or virtual 8086 mode, the value inside of a segment register is multiplied by 16 (shifted left four bits), and the offset given by the instruction operand or other source is added in order to give the true address. Diagram I-2-5 shows this.
In protected mode, a segment register holds the value of a selector, which points to an entry describing a segment in the "segment descriptor table", described below.
The instruction pointer EIP points at the next instruction to execute. Diagram I-2-6 shows the format of the instruction pointer.
As with the general purpose registers, bits 0-15 of the instruction pointer are handled as in previous generation CPUs. This part by itself is called IP.
The flags register combines bits that indicate and/or configure things like the results of arithmetic operations and the CPU's status. Diagram I-2-7 shows the format of the flags register, and table I-2-1 describes the meaning of each flag.
[diagram I-2-7]
| Bit position | Name | Function |
|---|---|---|
| 0 | CF | Carry flag: Set when a carry or borrow occurred in the highest bit of a calculation result. |
| 2 | PF | Parity flag: Set when the lowest eight bits of a calculation result has an even number of 1 bits. |
| 4 | AF | Auxiliary carry flag: Set when a carry or borrow occurred in bit 3 of a calculation result. |
| 6 | ZF | Zero flag: Set when a calculation result is zero. |
| 7 | SF | Sign flag: Indicates the highest bit of the calculation result. (0 if the result is positive, 1 if negative) |
| 8 | TF | Single step flag: Each time this is set, a single step exception is triggered after each instruction is executed. TF is cleared by interrupts. |
| 9 | IF | Interrupt flag: When set, and a maskable interrupt occurs, the CPU transfers control to the address indicated by the interrupt vector. |
| 10 | DF | Direction flag: Selects whether string instructions automatically increase or decrease their corresponding index registers while executing. Decrements when set, increments when clear. |
| 11 | OF | Overflow flag: Set when an overflow occurs in a signed calculation, in other words, when the result cannot be stored in the destination. |
| 12-13 | IOPL | I/O permission level: Sets the protection level allowed to operate I/O devices. |
| 14 | NT | Nested task flag: Set when the current task is nested under another task. |
| 16 | RF | Resume flag: Indicates whether an instruction has completed executing, and is set when execution is incomplete because of a page fault. |
| 17 | VM | Virtual mode flag: This flag is used for transitioning into virtual 8086 mode. When set in protected mode or page protected mode, transitions to virtual 8086 mode. Can be set by executing an IRET instruction or a protected mode task switch. Automatically cleared by an interrupt or exception. |
Control registers exist to let the OS control the CPU's execution mode and paging mechanism. The 80386 has four 32-bit control registers (CR0-CR3). CR0 controls the execution mode, as well as the type of math coprocessor and whether it is communicated with, while CR2 and CR3 are used to control paging. CR1 is currently unused.
Diagram I-2-8 shows the format of the control registers. Parts of the diagram marked "reserved" cannot be accessed by the user, and their behavior has not been specified.
Table I-2-2 describes the meaning of each bit in CR0.
[diagram I-2-8]
| Name | Meaning |
| PG | Enable/disable paging.
|
| TS | Indicates whether a task switch has occurred.
|
| EM | Determines whether an ESC instruction causes a trap or is sent to the
coprocessor.
|
| MP | Used in conjunction with the TS bit, when MP = 1 and TS = 1, both ESC instructions and the WAIT instruction cause a trap 7. |
| PE | Enable/disable segment-based protection functionality.
|
The CPU's operation is determined by the combination of the PG and PE bits. Table I-2-3 describes the combinations. When both bits are 0, the processor is in real mode (boot time), and when both bits are 1, the 80386 exhibits its full capabilities. Protected mode can be used without paging (PG = 0, PE = 1), but real mode cannot be used with paging (PG = 1, PE = 0).
The CR2 and CR3 registers handle paging.
In CR2, when a page fault occurs, the linear address of the routine that caused the fault is stored. This is useful to paging error handlers.
CR3 holds the page directory table base address used for managing paging. On the 80386, one page is fixed at 4KB, so the lowest 12 bits of this register are always zero.
In regards to paging, section 2.5.2, "Managing virtual memory and physical address translation", has more details.
| PG | PE | Operation mode |
|---|---|---|
| 0 | 0 | Real mode |
| 0 | 1 | Protected mode (no paging) |
| 1 | 0 | Cannot be used |
| 1 | 1 | Protected mode (paging) |
Four system address registers are used for segmented address generation and task switching.
The format of the system address registers is shown in diagram I-2-9.
When the 80386 generates an address using segmentation, it consults a data table called a descriptor table. Each entry in this table is called a "descriptor" and includes a segment's attributes, size, and base address. Section 2.5.2, "Managing virtual memory and physical address translation", has more information about descriptors and segments.
The "selector" indicated in the diagram is a number that selects an entry from the table. The "base" is the segment's beginning address, and "limit" is the segment's size.
Each register behaves as follows:
- GDTR contains the GDT (global descriptor table)'s base address and limit. The GDT contains descriptors that can be referenced from any task.
- LDTR holds the selector number of the LDT (local descriptor table). The LDT contains each task's own descriptors, which other tasks cannot reference.
- IDTR contains the IDT (interrupt descriptor table)'s base address and limit. The IDT contains descriptors that are referenced when an interrupt or exception occurs.
- TR sets the selector number of the TSS (task state segment). The TSS preserves state such as registers when task switching and restores the state when the task regains control.
The TSS is a structure that holds private data for each task, such as the task's attributes and registers. There is one for every task.
By the way, TSS standing for "task state segment" is an Intel neologism. Please note that it does not mean the more widely used "time sharing system".
[diagram I-2-9]
The 80386 is equipped with hardware debug facilities. There are 8 debug registers (DR0-DR7). Up to four breakpoint addresses can be set, using registers DR0-DR3.
The 80386 is equipped with a cache (the TLB) to accelerate paging, and provides registers to examine its state. There are seven test registers (TR0-TR7), but TR0-TR5 are reserved according to Intel. TR6 is used as a test register, and TR7 as a test data register.
Here, for the benefit of readers used to the 6809 CPU from the FM-7 and other computers, we describe how bits are handled on the 80386 data bus.
On the 6809 and other Motorola CPUs, the handling of each bit value in the data bus and registers is perfectly straightforward, but in the case of Intel CPUs, each 8 bit (1 byte) unit is stored in reverse order. Diagram I-2-10 illustrates this situation.
We think this is because, after Intel released the 4004 CPU, when they expanded to 8 bits, they added the expansion bits after the existing bits, and this became an unfortunate habit.
For this reason, the 80386 outputs 32-bit data onto the bus as indicated in diagram I-2-11.
[diagram I-2-10]
[diagram I-2-11]
Typically, when one says "virtual memory" from the perspective of application programming, we tend to think of a technique for expanding the bus address space. Certainly during the 8-bit CPU era, virtual memory was frequently used with this goal. However, it means something a bit different on the 80386, where it largely has to do with multitasking and memory protection.
When several programs are executing in parallel, the address at which a program is loaded into memory is influenced by the state of the system at load time. Specifically, the address depends on the size of the other programs executing at the same time. As a result, each program must be able to execute without depending on its load address.
Also, since programs should generally be able to execute mutually independently, they can exit at different times. The address space used by an exiting program must be released and made available to other programs. Therefore, it is important that memory management be simple.
Diagram I-2-12 illustrates the 80386's approach to virtual memory.
[diagram I-2-12]
Typically on the 80386, each program has a base address chosen for its address space during initialization. Then, at the execution stage, the segment register (containing 14 bits of address information) is used as a program index, and in conjunction with a 32-bit offset, a 46-bit virtual address is formed. This technique is called "segmentation". This way, even when each program's addresses start from offset 0, its virtual address space is entirely separate, so there is no worry of collisions. As a result, even though the logical address space appears vast, it is in reality full of gaps.
At first glance, this process may seem troublesome, but it allows programs to exist in memory without knowing their true load address.
However, this address space is a thoroughly fictitious thing. In reality, the CPU's directly accessible address space on the address bus is limited to 32 bits, so all memory must fit within 4GB.
To that end, virtual addresses are converted into the bus's physical address space by referencing a table based on the virtual address. Before consulting the table, each 46-bit virtual address value is condensed into a 32-bit value. The 32-bit address value at this stage is called the "intermediate linear address".
The top 20 bits of the intermediate linear address are then separated from the bottom 12 bits. Those top bits are used to reference the table, and the result after replacement by the converted value is output onto the address bus. The address space is "rearranged", so to speak. The bottom bits are output onto the address bus as is.
This transformation is called "paging". The address range accessible via the low 12 bits is 4KB, so by taking the top 20 bits as a page position, each page position can be exchanged with the position of an arbitrary block (4KB) according to the page-to-physical address mapping controlled by the table. In short, the 4GB address space can be allocated in 4KB units.
Using the aforementioned technique, when it comes time to load a new program into the space formerly used by exited programs, the free space can be handled as if it were contiguous even when scattered, since the top 20 bits of the linear addresses can be rearranged.
If the contents of memory are to be saved to/loaded from disk, then it is also possible to restore the same blocks in different physical address arrangements.
Here, we describe how the 80386 converts logical addresses to physical addresses. At the same time as addresses are formed, the CPU also performs checks in order to prevent access to inappropriate addresses. Thus, address formation and memory protection are closely integrated. However, in this section, we first focus only on discussing address formation. Memory protection functionality is covered in the next section.
On the 80386, with its 32-bit linear addressing, up to 4GB (gigabytes) of physical addresses can be directly accessed. Furthermore, if virtual memory management is used, up to 64TB of logical address space can be set up. However, logical addresses are entirely internal to CPU. The total size of bus-accessible addresses (32 bits) is the actual size of the effective memory region.
Diagram I-2-13 shows an outline of the address generation flow.
A logical address is converted into an "intermediate linear address" according to the CPU's "segmentation system". During the conversion, conversion tables (the GDT or LDT) are used. The width of an intermediate linear address is 32 bits.
An intermediate linear address is finally converted into a "physical address" according to the "paging system". During this conversion, two conversion tables (the page directory, and the page table) are used.
TOWNS OS uses both the segmentation and paging system.
System software can also turn off the paging system, so it is also possible to use only the segmentation system. In this situation, the intermediate linear address directly becomes the physical address.
[diagram I-2-13]
An address in a program is indicated by a "segment" and "offset". These are first processed by the segmentation system. The behavior of this system differs according to the operating mode of the CPU, but here we describe how it behaves in protected mode, the mode TOWNS OS operates in.
In protected mode, segments are managed according to tables called "descriptor tables". A descriptor table stores the "descriptors" that manage each segment. The contents of a segment register is an index that indicate which descriptor in the table to use, and is called a "selector".
Diagram I-2-14 outlines this process.
Diagram I-2-15 illustrates the structure of a selector.
Diagram I-2-16 describes the structure of a descriptor. A grouping of these descriptors is called a descriptor table. There are two types of descriptor table, the global descriptor table (GDT) and local descriptor table (LDT), but their structure is the same.
The base address and limit are stored in a scattered format to preserve 80286 compatibility.
Only one GDT can exist in the system. Various kinds of OS service routines and interrupt handlers can be placed in segments managed by the GDT.
[diagram I-2-14]
[diagram I-2-15]
[diagram I-2-16]
The address of the GDT is stored in a CPU system register called the GDTR. The value of the GDTR is set by the OS at boot time.
There is an LDT used by every task, and when the CPU switches tasks, it also switches LDTs. The LDT's own segment is stored in the GDT.
Each task accesses segments through its own LDT. Therefore, segments that aren't stored there cannot be accessed.
The LDT's position within the GDT is indicated by a CPU system register called the LDTR.
Segment handling requires referencing the descriptor tables, but if frequent lookups are performed, then there could be too many memory accesses, slowing execution speed. Therefore, for each segment register, the 80386 provides 4 bytes of cache, so that the descriptor (4 bytes) can be stored inside of the CPU. Because of this, as long as the cached descriptor is not cleared by being replaced, additional memory accesses are unnecessary.
The paging system manages logical address space by separating it into fixed-sized "pages". Logical address space can be formed by densely assigning physical address space in fixed page size units without any waste.
As handled by the 80386, the size of a page is 4KB, and there is 64TB of logical address space, divided into 16 million pages. These pages are managed by two types of table, called the page table directory and page table.
The intermediate linear address generated by the segmentation system is translated into the final physical address via the paging system. Diagram I-2-17 provides a schematic that illustrates this process.
Paging separates the aforementioned intermediate linear address (32 bits) into 10 + 10 + 12 bit parts, and the following three-stage process occurs:
-
First, using the top 10 bits of the linear address as an index, the page table directory (diagram I-2-18) is referenced to obtain the base address of the page table used in the next step.
The physical address of the page table directory is stored in the top 20 bits of the CR3 register. 20 bits is established by the size of a page being 4KB. Since the page table directory is the foundational table for managing all pages, by necessity, it must exist in physical memory.
Each element in the page table directory has a size of 32 bits.
-
Second, the page table, which uses the same format as the page table directory, is referenced. The location of the page address is read from the page table according to the middle 10 bits of the intermediate linear address.
-
Finally, the bottom 12 bits of the intermediate linear address are added as an offset to the chosen page's base address. This gives the final physical address.
[diagram I-2-17]
[diagram I-2-18]
Since the 64TB accessible as virtual memory is divided into 4KB pages, there are 220 pages. Since each page needs 4 bytes of data to manage, page management requires up to a maximum of 4MB of data. Keeping this amount of metadata in physical memory is not practical.
For this reason, page metadata is split into two kinds of table, page directories and page tables. The first kind of table (page directories) must exist in physical memory, but the second kind (page tables) are themselves paged, so do not necessarily need to be present in physical memory.
To determine whether a requested page or page table is present in physical memory or not, the page directory's P bit is tested.
If P = 0, the page (or page table) is not present in physical memory, so the CPU triggers a page fault exception. The OS handles this by moving the page contents from permanent storage (like a hard disk) into physical memory or something similar.
Using this technique, a region of address space can be used as a view of a region on disk, but this unavoidably leads to lower input/output performance.
If P = 1, the CPU sets the A bit then advances to the next instruction.
With the way paging works, two tables must be referenced to resolve an address, each in physical memory; performing these successive reads on every address lookup would reduce speed. Therefore, in order to improve performance, the 80386 provides an internal buffer for use by paging. This is called the translation lookaside buffer (TLB), and it stores up to 32 of the most recently accessed page table entries.
Diagram I-2-19 gives an overview of paging including the TLB.
For memory protection, the 80386 implements both "ring protection" with four access levels, and "task protection" to prevent tasks from influencing each other. The former provides protection between upper and lower levels, while the latter provides lateral protection within a level.
Ring protection is a protection method that assigns an "access level" to each task and limits memory access, what instructions can execute, and other things according to this access level.
Diagram I-2-20 provides an overview of ring protection.
The 80386 has four access levels. Access level 0 is the highest, and access level 3 is the lowest level. Lower-level memory can be accessed from higher levels, but not vice versa. This check occurs at the same time that the CPU generates a physical address from a logical address.
Ring protection not only consists of memory access related protection, but also limits the execution of "privileged instructions".
Privileged instructions are instructions that only access level 0 is permitted to use. These important instructions, which do things like control the CPU, should only be permitted for the OS to execute, and lower-level programs should not be able to use them, preventing them from performing operations that could possibly influence other tasks.
Ring protection is essential functionality for a multitasking OS. The design ensures that programs that do not have as high an access level as the OS cannot access essential system data such as the management tables for other tasks' alloted memory, so that even if normal programs (user programs, application programs, etc.) run amok, major damage to the system cannot occur.
Also, although the CPU provides four access levels, it is not necessary to use all of them, depending on how the OS is designed. With the OS at level 0, and normal programs at level 3, a useful OS can exist using only two levels. If an OS is single-tasking, even a design that only uses access level 0 can be considered.
[diagram I-2-20]
Task protection ensures that a task cannot be influenced by other tasks, not even by a task of the same access level. In other words, ring protection provides vertical protection, whereas task protection provides horizontal protection.
Task protection works via each task's individual LDT. Diagram I-2-21 provides an overview. The descriptors in the LDT control segments and store the size of each segments, so the memory regions of other tasks' segments cannot be invaded since accesses that go past a segment's limit (size) are prevented.
This check also occurs at the same time as the CPU forms an address.
Using these memory protection techniques, trouble in one task or segment can be prevented from entangling other tasks or higher-access-level segments while multitasking.
[diagram I-2-21]
In order to limit accesses to segments and pages within the same task, the 80386 offers "access right" protection functionality. Access rights can be configured as described below. If these rights are violated, a protection error occurs, which generally returns control to the OS.
- Segments: - Code segment: reading allowed/disallowed - Data segment: reading allowed/disallowed
- Pages (access level 3 only): - Read-only/read-write permission
In access levels 0 through 2, page access rights are always read-write.
While using ring protection and/or task switching, in situations where a lower- access-level program requests a service from the higher-access-level OS (OS system request), there needs to be a mechanism for switching access levels. However, normal jump and call instructions cannot transfer control to a program of a different access level.
| Type | Classification |
|---|---|
| 0 | Unused |
| 1 | 286 TSS in waiting state |
| 2 | Local descriptor table |
| 3 | 286 TSS currently executing |
| 4 | 286 call gate |
| 5 | Task gate |
| 6 | 286 interrupt gate |
| 7 | 286 trap gate |
| 8 | Unused |
| 9 | 386 TSS in waiting state |
| 10 | Unused |
| 11 | 386 TSS currently executing |
| 12 | 386 call gate |
| 13 | Unused |
| 14 | 386 interrupt gate |
| 15 | 386 trap gate |
The 80386 provides "gates" as a mechanism for crossing ring and task boundaries. A gate is a special kind of descriptor. Table I-2-4 lists all of the 80386's special descriptor kinds.
There are four kinds of gate:
- Call gate: shifts to a higher access level
- Task gate: shifts to a different task
- Interrupt gate: shifts to an interrupt handler
- Trap gate: shifts to an exception handler
Call gates are the gate kind used to shift access level.
A task can even be composed of multiple programs with different access levels.
A gate is used by executing a call instruction whose selector refers to a call gate, which calls out to the destination procedure. In other words, it calls out to the call gate's internal jump destination address (procedure entry point).
To understand this from the point of view of shifting access levels, see diagram I-2-22, and for a description of how the jump destination address is formed, see diagram I-2-23.
The 80386 provides a stack for each access level. When changing access levels, data is transferred across the access levels via these stacks. At switch time, the values of registers related to the former access level's stack (SS, ESP) are saved to the stack on the new access level's side. Furthermore, a number of parameter words are copied from the former access level's stack to the new access level's stack, as indicated by the call gate's attributes. Finally, the former access level's EIP is saved. Diagram I-2-24 illustrates how the stack is formed.
[diagram I-2-22]
With the stack set up this way, the task can be restored when returning to the original access level.
At return time, a RET n instruction (n being the number of parameter bytes) is used, which discards any remaining parameter values in the new access level's stack and then returns from the procedure. At this time, EIP is restored to its original value, the stack pointer (SS, ESP) is restored, and the parameters on the former access level's stack are discarded. By restoring EIP, execution resumes at the instruction after the call instruction.
[diagram I-2-23]
[diagram I-2-24]
When switching tasks in a multitasking environment, if information about each task such as register values were not preserved, then those tasks could not resume execution.
The 80386 keeps a "task state segment" (TSS) for storing execution information about every task. In the TSS, task attributes, register values, and back links are preserved. Diagram I-2-25 illustrates the layout of the TSS.
To switch tasks, a "task gate" is used. When a TSS descriptor is referenced by a task gate, the task switches to the one selected by the new TSS. Diagram I-2-26 gives an overview of this.
A task gate is triggered by a jump or call instruction. Diagram I-2-27 illustrates this. When this happens, the former task's registers are saved inside of the former task's TSS. Then, from the newly-selected TSS, each register's contents are loaded, and the new task begins execution at the position indicated by EIP.
[diagram I-2-25]
There is a faster way to switch tasks: executing a jump or call instruction that uses a selector directly referencing a TSS descriptor. However, when using this method, the destination of the task switch is limited.
Whichever method is used, since task switching is done by hardware, it occurs with minimal time loss. Particularly when using the latter method without a task gate, the time needed to complete a task switch is 17 microseconds.
[diagram I-2-26]
[diagram I-2-27]
"Interrupts" and "exceptions" interrupt the currently-executing task and trigger the launch of a different task. The distinction between the two is whether the cause comes from a peripheral device or from inside of the CPU. Interrupts occur when a peripheral device has a request to be handled by the CPU. Exceptions occur when something abnormal or particular conditions are detected during instruction execution. When either of these occur, the currently-executing task automatically stops, and after the cause is determined, a handler is invoked to clear up the abnormal condition.
When an interrupt or exception occurs, as indicated in table I-2-5, first a vector is chosen. If an external interrupt was triggered by INTR, the interrupt number from the 8259 (programmable interrupt controller) is used.
Exceptions can be categorized based on the following criteria, as indicated by the "classification" from table I-2-5:
- Fault: retrying is possible
- Trap: execution from the next instruction is possible
- Abort: fatal OS or hardware error, recovery is not possible
For a fault or trap, CS and EIP values are saved on the stack, for the current instruction in case of a fault, or for the following instruction in case of a trap. In case of an abort, outside of requesting a reset, there is no way to recover.
When a vector is determined, the 80386 uses this value as an index into the interrupt descriptor table (IDT), and the gate recorded in this table is invoked. Table I-2-6 describes the gates stored in the table. The IDT is at the address indicated by the IDTR register.
A program that handles interrupts and/or exceptions is called a "handler". Being gates, the process for invoking an interrupt handler or exception handler resembles that for a call gate.
"Interrupt gates" and "trap gates" resemble each other, but they differ in handling the interrupt flag (IF). An interrupt gate sets IF = 0 (interrupts disabled) when invoked, but a trap gate leaves IF unchanged.
One point in which these gates differ from call gates is that they do not support copying parameters to the stack. For things like interrupts and exceptions, it cannot be known when or under what conditions they occur, so providing parameters would be meaningless.
Also, when a handler is invoked via one of these gates, it executes inside of the current task. In other words, the handler can use the full extent of resources like memory that are available to the task from which the interrupt or exception occurred.
On the other hand, through a task gate, the interrupt flag is handled by taking the value of the IF flag from inside of the TSS. Therefore, a handler invoked through a task gate runs under a separate task. This makes it so the original task's memory and other resources cannot be referenced, so caution is necessary.
| Vector | Classification | Exception condition |
|---|---|---|
| 0 | Fault | Arithmetic error |
| 1 | Trap/Fault*1 | Debug exception |
| 2 | Interrupt | NMI interrupt |
| 3 | Trap | Software breakpoint |
| 4 | Fault | Overflow |
| 5 | Fault | Array bounds check |
| 6 | Fault | Invalid opcode |
| 7 | Fault | Coprocessor not available |
| 8 | Abort | System error |
| 10 | Fault | Invalid TSS |
| 11 | Fault | Segment not present |
| 12 | Fault | Stack overflow/underflow |
| 13 | Fault | General protection exception |
| 14 | Fault | Page not present |
| 16 | Fault | Coprocessor error |
| 17-255*2 | Interrupt | Interrupt via INTR |
*1: See 2.10, "Debug functionality".
*2: INTR vectors are typically requested from the 8259A. The vectors generated by the
8259A are programmable and set by software.
| Kind | Handler kind | Interrupts allowed/forbidden after entering gate |
|---|---|---|
| Interrupt gate | Procedure | Forbidden (IF = 0) |
| Trap gate | Procedure | Unchanged. IF value from before the interrupt/exception occurred is preserved. |
| Task gate | Task | Follows IF flag from TSS |
The 80386 is equipped with hardware single-stepping and breakpoint functionality for debugging.
The debug registers DR0-DR7 are related to debugging. Diagram I-2-28 shows the contents of the debug registers. It is necessary to be at access level 0 to access these registers.
[diagram I-2-28]
A debug exception handler uses a trap gate for when a vector 1 exception occurs. If a task gate were used, the task would be switched, and the target program's state would become unavailable. Also, if an interrupt gate were used, then there would be obstacles to handling peripheral devices and other interrupt-driven tasks.
With single-step debugging, a program can be fully monitored. To enable single-step execution, the TF (trace flag) in EFLAGS (the flags register) is set to 1. With this set, the CPU triggers an exception after executing every instruction. However, in the exception handler, instructions are executed continuously until it returns. If the exception handler were also single-stepped, then not only would control be lost, but the goal of single-step execution would be lost.
Up to four breakpoints can also be set.
Breakpoint addresses are set by storing their 32-bit linear addresses into DR0-DR3. The break condition for each breakpoint is set using the access type and monitor data length in DR7 (the debug control register).
One of the following access types can be chosen:
- Exception occurs only with instruction execution.
- Exception occurs only with data write.
- Exception occurs with data read or write.
The monitor data length indicates the extent of the breakpoint, or the breakpoint size. Starting from the breakpoint's set address, when memory is accessed within a range of 1, 2, or 4 bytes (as selected), an exception occurs.
When an exception occurs, the flag corresponding to the breakpoint is set in DR6 (the debug status register). The exception handler can determine which breakpoint caused the exception by consulting this register. DR6 also has a flag to notify when an exception occurred at the point of a task switch while single-stepping.
Also, in a multitasking environment, each task needs to be able to set its own breakpoints. When the debug flag in the TSS task attributes is set to 1, then an exception also occurs when the task is switched to. By handling this exception, at task switching time, the contents of the debug registers can be rewritten.
The 80386 has the ability to run 16-bit code even under protected mode. Specifically, when the code segment descriptor's attributes set the D bit to zero, 16 bit code execution is enabled. With D = 1, native 32-bit code is enabled.
Therefore, 16-bit and 32-bit code can both be selected using segmentation, and it is possible to mix them. Diagram I-2-29 shows this situation.
[diagram I-2-29]
However, in 80386 protected mode, since segment registers behave differently from the 8086, object-level compatibility with 8086 code cannot be achieved by 16 bit code segments alone. To solve this problem, the 80386 supports "virtual 8086 mode".
To switch from protected mode to virtual 8086 mode, the VM flag inside of EFLAGS (the flags register) is set to 1. To manipulate the VM flag, it is necessary to be at access level 0; it can be overwritten from an EFLAGS value waiting on the stack, or by the EFLAGS value inside of the TSS during a task switch. With the VM flag set to 1, 16-bit code begins executing.
Once virtual 8086 mode is entered, only the lowest 16 bits of the flags register (EFLAGS) can be accessed. Since VM is in the upper 16 bits of EFLAGS, a task in virtual 8086 mode by itself cannot change the VM flag and cannot return back to protected mode. [Translator's note: the original text erroneously refers to the only the lowest 8 bits of EFLAGS being accessible to 8086 code.]
However, because virtual 8086 mode executes as a part of protected mode, when exceptions or external interrupts occur, they automatically bring the CPU back to protected mode.
Virtual 8086 mode always runs at access level 3. Therefore, although object-level code is compatible with the 8086, using privileged I/O instructions will trigger an exception. It is necessary to have a handler for this exception at access level 0, so that it can simulate I/O management on the protected mode side.
In the vicinity of the FM TOWNS CPU, there are several devices that help interface between the CPU and peripheral equipment. Of these, this chapter explains the essential devices necessary for interrupts, DMA, timers and clocks. Also, at the end of this chapter, all of the registers provided for these CPU-adjacent devices are described.
In this section, we briefly describe the specification of each device. For more details, please reference the following sections.
Table I-3-1 lists the specifications of the FM TOWNS CPU-adjacent devices.
The CPU is an 80386, running at a clock speed of 16MHz.
A math coprocessor is optionally available by installing an 80387 coprocessor card.
Up to 6MB of RAM can be installed. From the factory, the FM TOWNS Model 1 is equipped with 1MB, and the Model 2 with 2MB. To add to this, expansion RAM modules are used. There are 1MB and 2MB modules which respectively add 1MB or 2MB of RAM.
The ROM region includes the boot program run at system startup and kanji ROM. Additionally, in the expansion ROM slot, a ROM card can be installed containing a program to run automatically immediately after system boot. When a ROM card is equipped, control is transferred to this ROM immediately after booting.
15 types of interrupt can be used. An 8259A-compatible module is used as the interrupt controller.
Furthermore, there is the mandatory interrupt, NMI, which cannot be masked (by disabling interrupts) like normal interrupts. The NMI can be triggered by the keyboard.
Transferring data over the bus without going through the CPU is called DMA. Floppy drives, printers, the SCSI interface, and the CD-ROM drive support DMA transfers, among other devices. A 71071 is used as the DMA controller.
The computer also has registers for controlling timers, the clock, and other devices. We also describe these in detail.
| Item | Specification | ||||||||||||||||||||||||||||||||
| CPU | 16MHz 80386 80387 math coprocessor can be used | ||||||||||||||||||||||||||||||||
| RAM | Built-in: 1MB (model 1), 2MB (model 2) Maximum 6MB (optional expansion) | ||||||||||||||||||||||||||||||||
| ROM | 1.5MB built-in | ||||||||||||||||||||||||||||||||
| Interrupts |
Two 8259-compatible modules
| ||||||||||||||||||||||||||||||||
| NMI | RAS functionality (keyboard) I/O expansion unit* | ||||||||||||||||||||||||||||||||
| DMAC | 71071
| ||||||||||||||||||||||||||||||||
| Expansion DMAC | 71071
|
* marked items differ from the FMR series.
Interrupts enable the CPU to stop its current job and perform another job when hardware detects that a special event has occurred.
When an interrupt occurs, the CPU stops its current job and transfers control to the interrupt handler.
In the FM TOWNS, a pair of 8259A compatible PIC (programmable interrupt controller) modules is used to control interrupts coming from peripheral equipment, supporting 15 types of interrupt.
In this section, we describe the structure of the PIC and interrupt system.
Diagram I-3-1 shows a block diagram of the 8259A-compatible PIC.
[diagram I-3-1]
One PIC has eight interrupt lines, enabling interrupt requests from eight types of peripheral devices.
On the FM TOWNS, two PICs are used in series. Of the 16 interrupt lines, one is used for connecting one PIC to the other, allowing a total of up to 15 interrupt lines.
Each PIC's eight interrupt lines is associated with a priority level. Each of the two PICs also has a priority level. The higher-priority PIC is called "primary", and the lower-priority PIC is called "secondary". This way, all 15 interrupt lines can be handled in priority order.
There are multiple ways to handle interrupts, but it is standard to handle interrupts in priority order. This is called interrupt priority mode (free nested mode). This is the mode that is set right after the PIC's initialization command word (ICW, described below) is sent.
Here we describe the PIC's interrupt control system under the most common mode, interrupt priority mode.
Inside of the PIC are registers essential to interrupt control: IRR (table I-3-2), ISR (table I-3-3), and IMR (table I-3-4).
Below, we describe each register's purpose and outline the block structure of the flow of interrupt handling.
Interrupts are handled according to the following mechanism:
[Translator note: The description in the following paragraph describes how an 8259 PIC behaves in 8080/8085 mode. For x86 processors, no CALL instruction is output onto the bus; the PIC sends the interrupt vector number to the CPU, and the CPU dispatches the interrupt natively.]
When an interrupt from a peripheral occurs, the corresponding bit in the IRR (interrupt request register) becomes 1. The PIC outputs the CPU's INT signal, notifying it that an interrupt occurred. In response, the CPU outputs the /INTA signal, acknowledging the interrupt request from the PIC. Then, the PIC outputs 0xCD (hexadecimal machine code for a CALL instruction). With the CPU continuously outputting /INTA, the PIC outputs the previously-stored address of the interrupt handler (interrupt service routine) to the data bus 8 bits at a time, transferring it to the CPU. At this point, the interrupt currently being serviced is stored to the ISR (in-service register). "In service" means that the interrupt is in the middle of being handled. In this way, the CPU ends up executing a CALL instruction to the interrupt handler.
While handling an interrupt, information about this interrupt is present in the IRR and ISR. When the PIC receives an EOI (end of interrupt) command from the interrupt handler, this is erased.
If another interrupt occurs while an interrupt is still being handled, it is recorded in the IRR. In this case, the current interrupt and new interrupt's priorities are compared, and if the new interrupt has higher priority, then the currently-executing interrupt handler is stopped, and the new interrupt's handler runs.
However, while handling an interrupt, it is possible to refuse other interrupt requests. To do this, a bit corresponding to each interrupt in the IMR (interrupt mask register) can be set to 1.
The priority resolver usually inspects the state of the IRR, ISR, and IMR, deciding which interrupt should be handled based on the levels of the currently-occurring interrupts (IRR) and the interrupts with ongoing handlers (ISR) alongside the mask condition (IMR).
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0000 | Interrupt request register (primary side) | R | IR7 (SINT) | IR6 (INT6) | IR5 (INT5) | IR4 (INT4) | IR3 (INT3) | IR2 (INT2) | IR1 (INT1) | IR0 (INT0) |
- IR0-7 (bit 0-7): When interrupt requests occur, the bits for SINT and INT0-6 corresponding to every requested interrupt level are set.
SINT indicates an interrupt from the secondary side. INT0-6 indicate hardware-triggered interrupts.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0010 | Interrupt request register (secondary side) | R | IR7 (INT15) | IR6 (INT14) | IR5 (INT13) | IR4 (INT12) | IR3 (INT11) | IR2 (INT10) | IR1 (INT9) | IR0 (INT8) |
- IR0-7 (bit 0-7): When interrupt requests occur, the bits for INT8-15 corresponding to every requested interrupt level are set.
INT8-15 indicate hardware-triggered interrupts.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0000 | In-service register (primary side) | R | IS7 (SINT) | IS6 (INT6) | IS5 (INT5) | IS4 (INT4) | IS3 (INT3) | IS2 (INT2) | IS1 (INT1) | IS0 (INT0) |
- IS0-7 (bit 0-7): The bits for SINT and INT0-6 corresponding to the interrupt levels currently being serviced are set.
SINT indicates an interrupt from the secondary side. INT0-6 indicate hardware-triggered interrupts.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0010 | In-service register (secondary side) | R | IS7 (INT15) | IS6 (INT14) | IS5 (INT13) | IS4 (INT12) | IS3 (INT11) | IS2 (INT10) | IS1 (INT9) | IS0 (INT8) |
- IS0-7 (bit 0-7): The bits for INT8-15 corresponding to the interrupt levels currently being serviced are set.
INT8-15 indicate hardware-triggered interrupts.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0002 | Interrupt mask register (primary side) | R | IR7 | IR6 | IR5 | IR4 | IR3 | IR2 | IR1 | IR0 |
| 0x0012 | Interrupt mask register (secondary side) | R | IR15 | IR14 | IR13 | IR12 | IR11 | IR10 | IR9 | IR8 |
- IR0-15: Indicates the interrupt mask state:
- 0 = allowed
- 1 = forbidden
To control the PIC, alongside the aforementioned IRR, ISR, and IMR, there are also the ICW (initialization control word) and OCW (operation command word).
Reading from the IRR, ISR, or IMR and writing to the ICW or OCW are done from the CPU via I/O addresses.
Writing to the IMR is done indirectly by writing to the OCW. The IRR and ISR are written when an interrupt occurs or when interrupts are completed.
Reading register contents and writing control words are the PIC's fundamental operations, and are done via the A1, D4, D3, /RD, /WR, and /CS signals. The relation between these signals and PIC operations is illustrated in table I-3-5.
| Operation mode | Contents | A1 | D4 | D3 | /RD | /WR | /CS |
| Reading | IRR, ISR --> data bus*1 | 0 | 0 | 1 | 0 | ||
| IMR --> data bus*1 | 1 | 0 | 1 | 0 | |||
| Writing | data bus --> OCW2 | 0 | 0 | 0 | 1 | 0 | 0 |
| data bus --> OCW3 | 0 | 0 | 1 | 1 | 0 | 0 | |
| data bus --> ICW1 | 0 | 1 | X | 1 | 0 | 0 | |
| data bus --> OCW1, ICW2*2, ICW3*2, ICW4*2 | 1 | X | X | 1 | 0 | 0 | |
| Disable | data bus disconnected | X | X | X | 1 | 1 | 0 |
| data bus disconnected | X | X | X | X | X | 1 |
- *1: Before a read operation, which of IRR or ISR to read is set by operation command word 3 (OCW3).
- *2: The order of initialization command words (ICW) is performed by the PIC's internal sequencing logic.
The value of A1 is connected to the I/O address. The relationship between the A1 value and the I/O addresses of the primary and secondary PIC is shown in table I-3-6.
| I/O address | 8259 A1 | |
| Primary | Secondary | |
| 0x0000 | 0x0010 | 0 |
| 0x0002 | 0x0012 | 1 |
Also, the value of /CS while accessing the corresponding PIC is 0.
Before using the PIC, the PIC must be initialized using the initialization command word (ICW).
An initialization command consists of ICW1 (table I-3-7), ICW2 (table I-3-8), ICW3 (table I-3-9), and ICW4 (table I-3-10).
In diagram I-3-2, the initialization process using these ICW commands is shown. The FM TOWNS is equipped with two PICs, so it uses ICW3 in addition to ICW1, ICW2, and ICW4.
In table I-3-10, the highest priority interrupt mode (special free nested mode) allows another higher-priority interrupt on the secondary PIC side to occur while already handling an interrupt on the secondary PIC. When setting this mode, ICW4 on only the primary side should have SFNM set to 1. Buffered mode is a mode that uses hardware buffer control, and the FM TOWNS always has it set to 1.
The initialization state changes based on the the values set for ICW1-ICW4.
It is necessary to set ICW1-ICW4 by writing them in order; an arbitrary individual ICW cannot be written. Therefore, when wanting to change any one ICW, all of ICW1 through ICW4 must be set.
Note that when ICW1 is written, IRR and ISR are cleared, and free nested mode is initialized. At this point, the IRR/ISR selector for register read commands is initialized to IRR.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0000 | Initialization command word 1 (primary side) | W | A7 (0) |
A6 (0) |
A5 (0) |
1 | LTIM (1) |
ADI (0) |
SNGL (0) |
IC4 (1) |
| 0x0010 | Initialization command word 1 (secondary side) | W |
- A5-A7 (bit 5-7): Ignored by the 80386.
- Fixed to 0.
- LTIM (bit 3): Sets the IR input trigger mode.
- 1 = Level trigger mode (fixed)
- ADI (bit 2): Ignored by the 80386.
- Fixed to 0.
- SNGL (bit 1): Selects whether a single PIC or several PICs (cascade mode)
are in use.
- 0 = Cascade mode (fixed)
- IC4 (bit 0): Sets whether ICW4 is necessary.
- 1 = Necessary (fixed)
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0002 | Initialization command word 2 (primary side) | W | A15/T7 | A14/T6 | A13/T5 | A12/T4 | A11/T3 | A10 (0) |
A9 (0) |
A8 (0) |
| 0x0012 | Initialization command word 2 (secondary side) | W |
- A11-A15/T3-T7 (bit 3-7): Sets the interrupt vector address.
- A8-A10 (bit 0-2): Ignored by the 80386.
- Fixed to 0.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0002 | Initialization command word 3 (primary side) | W | S7 (1) |
S6 (0) |
S5 (0) |
S4 (0) |
S3 (0) |
S2 (0) |
S1 (0) |
S0 (0) |
- S0-S7 (bit 0-7): Sets whether a secondary PIC is connected to the
corresponding IR input.
- 1 = Secondary PIC connected (fixed)
- 0 = Device connected (fixed)
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0012 | Initialization command word 3 (secondary side) | W | A7 (0) |
A6 (0) |
A5 (0) |
A4 (0) |
A3 (0) |
ID2 (1) |
ID1 (1) |
ID0 (1) |
- A3-A7 (bit 3-7): Ignored by the 80386.
- Fixed to 0.
- ID0-ID2 (bit 0-2): Secondary PIC identifier number (fixed at 7).
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0002 | Initialization command word 4 (primary side) | W | 0 | 0 | 0 | SFNM | BUF (1) |
P/S | AEOI | µPM (1) |
| 0x0012 | Initialization command word 4 (secondary side) | W |
- SFNM (bit 4): Sets special free nested mode.
- 0: Free nested mode
- 1: Special free nested mode
- BUF (bit 3): Sets buffered mode.
- 1: Buffered mode (fixed)
- P/S (bit 2): For buffered mode, sets whether the PIC is primary or
secondary.
- 0: Secondary
- 1: Primary
- AEOI (bit 1): Sets automatic end-of-interrupt mode.
- 0: Non-automatic EOI mode
- 1: Automatic EOI mode
- µPM (bit 0): Sets CPU mode.
- 1: 80386 mode (fixed)
[diagram I-3-2]
There are three kinds of OCW: OCW1 (table I-3-11), OCW2 (table I-3-12), and OCW3 (table I-3-13). The I/O address distinguishes which of OCW1-OCW3 to write with the D3 signal, so it is possible to write individually to the ones that need setting or changing. Note that the OCW descriptions mention modes that have not yet been explained, but these will be explained later.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0002 | Operation command word 1 (primary side) | W | M7 | M6 | M5 | M4 | M3 | M2 | M1 | M0 |
| 0x0012 | Operation command word 1 (secondary side) | W | M15 | M14 | M13 | M12 | M11 | M10 | M9 | M8 |
- M0-15 (bit 0-7): Sets whether the corresponding interrupt request is
allowed or forbidden.
- 0 = allowed
- 1 = forbidden
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0000 | Operation command word 2 (primary side) | W | R | SL | EOI | 0 | 0 | L2 | L1 | L0 |
| 0x0010 | Operation command word 2 (secondary side) | W |
-
R, SL, EOI (bit 5-7): Combines priority order rotation and end-of-interrupt mode.
R SL EOI Function 0 0 1 Use interrupt priority order mode with non-special EOI commands 0 1 1 Use interrupt priority order mode with special EOI commands* 0 0 0 Automatic EOI mode without rotation mode 1 0 1 Use automatic rotation mode with non-special EOI commands 1 1 1 Use automatic rotation mode with special EOI commands* 1 0 0 Use automatic rotation mode with automatic EOI mode 1 1 0 Set priority command* 0 1 0 No operation * indicates that the interrupt bits are set using L0-L2.
-
L0-L2 (bit 0-2): Selects the interrupt level affected by a special EOI command when the SL bit (bit 6) is 1.
Primary side:
L2 L1 L0 Interrupt level 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 (SINT) Secondary side:
L2 L1 L0 Interrupt level 0 0 0 8 0 0 1 9 0 1 0 10 0 1 1 11 1 0 0 12 1 0 1 13 1 1 0 14 1 1 1 15 SINT indicates an interrupt on the secondary side.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0000 | Operation command word 3 (primary side) | W | 0 | ESMM | SMM | 0 | 1 | P | PR | RIS |
| 0x0010 | Operation command word 3 (secondary side) | W |
-
ESMM, SMM (bits 5-6): Special mask mode is controlled by the combination of these two bits.
ESMM SMM Function 0 0 Do nothing (since ESMM is 0) 0 1 1 0 Disable special mask mode, return to normal mask mode 1 1 Select special mask mode -
P (bit 2): Select interrupt handling by software polling, without using hardware interrupts on the CPU.
Poll command mode stops CPU interrupts from being dispatched.
- 0: Do not use poll command mode.
- 1: Use poll command mode.
-
PR, RIS (bits 0-1): Which register is read is selected by the combination of these two bits.
PR RIS Function 0 0 Do nothing (since PR is 0) 0 1 1 0 Select IRR for reading 1 1 Select ISR for reading
For interrupt control, in addition to the interrupt priority order mode described up to this point, there are various other modes.
Right after the ICW is initialized, the PIC is in interrupt priority order mode. In this mode, IR0 has the highest priority, and IR1, IR2, etc. have decreasing priority as the number increases.
When an interrupt reaches the stage where the 80386 dispatches to the handler address, the corresponding bit in the ISR is set, but after handling the interrupt is complete, it is necessary to clear it (set it to zero). To do this, EOI must be set when the interrupt handler is complete by writing to OCW2 on the corresponding primary/secondary side. EOI (End of Interrupt) is the command that ends handling of an interrupt. There are special EOI and non-special EOI commands (described below), either of which can be used. Additionally, automatic EOI mode (also described below), in which an EOI command is unnecessary, can be used.
If it is desired to treat all priority levels equally, then automatic rotation mode can be used instead of interrupt priority mode. In this mode, the priority of a requested interrupt is reduced to the lowest priority after its interrupt handler is activated. Thus if successive requests for the same interrupt occur, those interrupts cannot be handled until other handlers are completed.
To handle completion of an interrupt in automatic rotation mode, either an EOI command (described below) or automatic EOI mode (also described below) can be used.
There are two kinds of EOI command behavior, based on the SL bit of OCW2:
- SL bit 0: Non-special EOI command
- SL bit 1: Special EOI command
A non-special EOI command clears the ISR bit corresponding to the highest-priority interrupt.
A special EOI command clears a bit specified by the L0-L2 bits.
In cases where the EOI command process is troublesome, automatic EOI mode can be used.
To use this mode, at initialization time, the AOEI bit (bit 1) of ICW4 is set to 1.
In automatic EOI mode, interrupts do not set their corresponding ISR bits, so an EOI command is unnecessary. However, it is possible for another interrupt to be requested while already handling an interrupt, so additional caution with timing is necessary. Note that only the primary PIC can use this mode; the secondary cannot use it.
Furthermore, the OCW2 priority command raises the priority of subsequent interrupts by dropping a completed interrupt's priority to the lowest level.
The IMR works as a mask for the IRR; if the bit corresponding to an interrupt is masked, that interrupt will not be handled. However, in special mask mode, the IMR instead acts as a mask for the ISR. Concretely, this makes it so that when even a lower-priority interrupt occurs while a masked interrupt is currently being handled, that other interrupt will be handled.
To use this mode, set the bits in the IMR corresponding to the interrupts whose corresponding ISR bits are set, then switch to special mask mode using OCW3.
In OCW3's poll command mode, CPU interrupts are not used, and the CPU must continuously observe the contents of the PIC, so it cannot practically be used on the FM TOWNS.
DMA (direct memory access) is the direct transfer of data between peripherals and memory without going through the CPU.
Memory access by the DMAC (DMA controller) and memory access by MOV instructions on the CPU can both be used to sequentially read data into memory from some devices (such as disk drives). Of course the CPU can handle this, but by instead having DMA carry out the monotonous process of transferring large amounts of data, the CPU can handle other business. Also, some peripheral devices transfer data at a higher speed than CPU processing can keep up with. In these situations, DMA transfer is used.
The FM TOWNS uses a 71071 DMAC.
In this section, we describe the structure of the DMAC and the process of DMA transfers.
The 71071 can run four independent DMA channels. However, at any one point in time, only one out of the DMAC's four channels or the CPU can use the bus. Each channel is assigned as shown in table I-3-1.
The 71071 has various uses, but when used in practice in a personal computer in an auxiliary role to the CPU, there are many limitations on its functionality. The FM TOWNS too forbids the use of parts of the 71071's functionality, so care is necessary in its configuration.
The DMAC is started by a DMA transfer request signal from the CPU or other device. From the source device (such as a disk drive), 1 byte (or 1 word) of data is read, and that data is then written to the destination device (such as memory), completing one batch. The transmitted data does not go through the CPU during this time.
The memory address to start the read/write from is set beforehand in the DMAC address register, and the number of bytes to transfer is set in the count register. The channel register selects which of the four DMA channels to use.
The configuration up to this point has been done using the CPU. The DMAC carries out the actual data transfer using the values of its internal registers. For example, for a 2-byte-at-a-time transfer, DMA transfers repeat up to the number set by the DMAC's internal count register, while the address register is increased by 2 with each transfer.
The I/O expansion unit supports an expansion DMAC. Its registers are assigned to I/O addresses 0x00B0-0x00BF, while the built-in DMAC uses addresses 0x00A0-0x00AF.
The DMAC has registers that are shared by all channels as well as ones that configure each individual channel.
The shared registers are as follows:
- Initialize register: Initializes the DMAC and selects the bus size
- Device control register: Sets DMAC operation mode
- Status register: Stores whether DMA is requested or completed
- Request register: Used by software to request DMA
- Mask register: Masks DMA requests from hardware
The channel-specific configuration registers are as follows:
- Channel register: selects which register to access
- Base/current count register: sets the DMA transfer count
- Base/current address register: sets the DMA transfer address
- Mode control register: sets each channel's mode
Aside from the registers mentioned above, the DMAC also has temporary registers, but they cannot be used on the FM TOWNS.
Below, we describe each register in detail.
When using the DMAC, the initialize register (table I-3-14) is set first, followed by the other registers.
Setting the initialize register both initializes the DMAC and determines the bus access size. This register is 8-bit writable.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00A0 | Initialize register | W | 0 | 0 | 0 | 0 | 0 | 0 | 16B (1) |
RES |
- 16B (bit 1): Sets the DMAC's I/O bus width. This must be set to 1 before
accessing any other DMAC registers.
- 1: 16-bit bus (fixed)
- RES (bit 0): Resets the DMAC. This bit is automatically cleared after
initialization.
- 1: Reset on
Next, the channel register (table I-3-15) is set. This selects which register of which channel is used in following accesses. Note that the write and read format of the channel register differ. A description of the BASE bit is provided in the section about the count and address registers.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00A1 | Channel register | W | 0 | 0 | 0 | 0 | 0 | BASE | SELCH | |
| SL1 | SL0 | |||||||||
-
BASE (bit 2): Selects which of the base register or current register is accessed by the address and count registers.
- 0: Read current register; write base register
- 1: Base register
This bit is normally set to 0.
-
SELCH (bit 0-1): Selects which channel to access. This must always be set when configuring the DMAC's mode/address/byte count.
SL1 SL0 Channel 0 0 Channel 0 0 1 Channel 1 1 0 Channel 2 1 1 Channel 3
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00A1 | Channel register | R | undefined | BASE | SELCH | |||||
| SEL3 | SEL2 | SEL1 | SEL0 | |||||||
-
BASE (bit 4): Indicates which of the base register or current register is the currently selected state of the address and count registers.
- 0: Read current register; write base register
- 1: Base register
-
SELCH (bit 0-3): Indicates which channel is currently selected. Bits 0-3 correspond to channels 0-3.
SELCH Channel SEL0 = 1 Channel 0 SEL1 = 1 Channel 1 SEL2 = 1 Channel 2 SEL3 = 1 Channel 3
The count register (table I-3-16) stores the number of times the DMA transfer repeats. Each channel has both a base count register and a current count register. When the CPU sets this register, it sets the base count register, storing the number of times to repeat the DMA transfer. The current count register is mainly used by the DMAC during a DMA transfer. With normal initialization (auto initialization), the base count register value is transferred to the current count register, and with each DMA transfer unit, the value is decreased by one, the operation completing when zero is reached. Which count register gets accessed from the CPU is selected by the BASE bit in the channel register.
The length of the count register is 2 bytes (16 bits), so a continuous DMA transfer of up to 64KB is possible.
The contents of these registers, both base and current, are both readable and writable. If a 16 bit bus size was chosen when the initialize register was set, then both bytes of the register can be accessed simultaneously.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00A2 | Count register (low) | R/W | C7 | C6 | C5 | C4 | C3 | C2 | C1 | C0 |
| 0x00A3 | Count register (high) | R/W | C15 | C14 | C13 | C12 | C11 | C10 | C9 | C8 |
- C0-15: Sets the byte count for a DMA transfer.
The address register (table I-3-17) stores the memory address at which to perform DMA transfers. Each channel has both a base address register and a current address register. When the CPU sets the register, it sets the base address register, storing the start address at which DMA transfers read from or write to memory. The current address register is mainly used by the DMAC during a DMA transfer, holding the address presently being read or written. Under normal initialization (auto initialization), the base address register is transferred to the current address register, and with each DMA transfer, it is increased or decreased automatically by +/-1 (in 8-bit mode) or +/-2 (in 16-bit mode). The 8-bit or 16-bit mode here is not the bus size but the data width selected by the mode control register, described below. Which address register gets accessed from the CPU is selected by the BASE bit in the channel register.
The length of the address register is 4 bytes (32 bits), so any address in the 4GB range can be selected. However, the address register's low 3 bytes are internal to the DMAC, and the highest byte is an externally-attached register. The low 3 bytes are incremented or decremented sequentially, but there is no carry from A23 to A24. Therefore, in order to transfer to addresses above 16MB, address carry (or borrow) must be performed in software. The contents of these registers, both base and current, are both readable and writable.
It is also necessary to be aware that there is only one address register for the highest byte, used for both the base and current address.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00A4 | Address register (low) | R/W | A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 |
| 0x00A5 | Address register (middle) | R/W | A15 | A14 | A13 | A12 | A11 | A10 | A9 | A8 |
| 0x00A6 | Address register (high) | R/W | A23 | A22 | A21 | A20 | A19 | A18 | A17 | A16 |
| 0x00A7 | Address register (highest) | R/W | A31 | A30 | A29 | A28 | A27 | A26 | A25 | A24 |
-
A0-A31: Sets the DMA transfer start address (4GB range).
A24-A31 is an externally-attached register, so carry from A23 to A24 does not occur. Therefore, be aware that a transfer straddling 16MB regions will wrap around.
The device control register (table I-3-18) makes general mode settings common to all channels.
Due to the FM TOWNS' implementation constraints, most of the bit values in this register are fixed. The only bit that can be set is DDMA, which controls whether DMA operation is allowed or forbidden.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00A8 | Device control register | R/W | AKL (0) |
RQL (0) |
EXW (1) |
ROT (0) |
CMP (0) |
DDMA | AHLD (0) |
MTM (0) |
- AKL (bit 7): Sets the DMAAK active level.
- 0: Active low (fixed)
- RQL (bit 6): Sets the DMARQ active level.
- 0: Active high (fixed)
- EXW (bit 5): Sets the mode when writing.
- 1: Extended write mode (fixed)
- ROT (bit 4): Sets the priority control method.
- 0: Fixed priority order (fixed)
- CMP (bit 3): Sets the DMA cycle timing control method.
- 0: Normal timing (fixed)
- DDMA (bit 2): Forbids DMA operation.
- 0: DMA operation allowed.
- 1: DMA operation forbidden.
- AHLD (bit 1): Fixes the channel 0 address when doing memory-to-memory transfers. Since memory-to-memory transfers are forbidden, this bit is fixed to 0.
- MTM (bit 0): Whether memory-to-memory transfers are allowed.
- 0: Memory-to-memory transfers forbidden (fixed)
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00A9 | Device control register | R | undefined | WEV (0) |
BHLD (0) |
|||||
| W | 0 | 0 | 0 | 0 | 0 | 0 | ||||
- WEV (bit 1): Sets whether WAIT is allowed while verifying a transfer.
- 0: WAIT disallowed (fixed)
- BHLD (bit 0): Sets the DMA transfer bus mode.
- 0: Bus release mode (fixed)
The mode control register (table I-3-19) selects each channel's operation mode.
The TMODE field in the mode control register switches between demand mode and single mode.
In demand mode, the DMAC continuously performs DMA transfers while a DMA request is being handled, and does not release the bus until the transfer is finished. Conversely, in single mode, the DMA transfer releases the bus after each byte (or two bytes) during the operation.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00AA | Mode control register | R | TMODE | ADIR | AUTI | TDIR | undefined | W/B | ||
| MD1 | MD0 | TD1 | TD0 | |||||||
| W | TMODE | TDIR | 0 | |||||||
| MD1 | MD0 | TD1 | TD0 | |||||||
-
TMODE (bit 6-7): Sets the DMA transfer mode.
MD1 MD0 Transfer mode 0 0 Demand mode 0 1 Single mode 1 0 Block mode (use not allowed) 1 1 Cascade mode (use not allowed) -
ADIR (bit 5): Sets the address counter increment/decrement.
- 0: Address increment
- 1: Address decrement
The status register (table I-3-20) stores whether the DMA request signal is active or whether the transfer has been completed on each channel.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00AB | Status register | R | REQUEST | TERMINAL COUNT | ||||||
| RQ3 | RQ2 | RQ1 | RQ0 | TC3 | TC2 | TC1 | TC0 | |||
- RQ0-3 (bit 4-7): Indicates the DMA request signal state. RQ0-3 correspond
to channels 0-3.
- 0: No DMA request
- 1: DMA request in progress
- TC0-3 (bit 0-3): Indicates whether the indicated DMA transfer has finished
its byte count. These bits are cleared when read. TC0-3 correspond to channels
0 through 3.
- 1: Terminal count state.
The temporary register (table I-3-21) is used as a relay during memory-to-memory transfers, but the FM TOWNS does not use this functionality.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00AC | Temporary register (low) | R | T7 | T6 | T5 | T4 | T3 | T2 | T1 | T0 |
| 0x00AD | Temporary register (high) | R | T15 | T14 | T13 | T12 | T11 | T10 | T9 | T8 |
- These registers are unused.
The request register (table I-3-22) is used to issue DMA requests from software. In short, when software sets the bit corresponding to a channel in this register, the DMAC issues the DMA request for that channel.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00AE | Request register | R | undefined | SRQ3 | SRQ2 | SRQ1 | SRQ0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
- SRQ0-3 (bit 0-3): DMA request from software. SRQ0-3 correspond to channels
0-3.
- 0: DMA request reset
- 1: DMA request set
The mask register (table I-3-23) sets whether to accept or reject DMA requests from hardware. If the bit corresponding to a channel is set, then the DMA request signal from hardware for that channel is masked.
Note that if the corresponding channel is not masked when the DMAC is set up, a malfunction can occur.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x00AF | Mask register | R | undefined | M3 | M2 | M1 | M0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
- M0-3 (bit 0-3): DMA request signal mask bits. M0-3 correspond to channels
0-3.
- 0: DMA request unmasked
- 1: DMA request signal masked
The programmable timer (PIT) is a counter that counts clock pulses at a given fixed frequency, and when the count value times out (reaches a specified value), it can trigger an interrupt and/or output a pulse.
The PIT can be used as an interval timer with its ability to trigger an interrupt at fixed intervals. Software can use this interrupt to implement things like task switching. Also, the PIT is used as a baud rate generator to control the RS-232C baud rate by generating a pulse at fixed intervals.
The FM TOWNS uses 8253-compatible modules for its PITs.
In this section, we describe the 8253's structure and operation.
One 8253 is equipped with three independent timers (counters), and the FM TOWNS uses two of these PITs. However, channels 3 and 5 are reserved, leaving four channels that can be used. Table I-3-24 describes each channel's purpose and input clock interval.
| Item | Specification | ||||||||||||||
| Timer | 8253 x 2 | ||||||||||||||
| Channel allocation |
|
||||||||||||||
| Count clock |
|
||||||||||||||
| Interrupts | Interrupts can be triggered only by channels 0 and 1 |
On the FM TOWNS, of the 8253's operating modes, channels 0, 2, and 3 use mode 3, and channel 1 uses mode 0. These mode settings are fixed by the hardware design, and cannot be changed.
Also, only channels 0 and 1 can be used to cause interrupts.
When accessing PIT1 and PIT2 one after the other, please wait at least 1.3us.
The count cannot be controlled by input to any gate.
On channel 0, at the configured time interval, the timeout flag (TMOUT0) of the interrupt reason register (described below) is set, so the interrupt handler routine has to reset this flag. To do so, please write 1 to TM0CLR in the interrupt control register (described below).
The PIT has the following registers:
- Timer count register: sets the count value (time)
- Control register: sets the PIT operation mode
- Interrupt control register: whether interrupts are enabled/disabled
- Interrupt reason register: interrupt condition
Next, we describe each register in detail.
The timer count registers (table I-3-25) for each channel set the channel's input clock count. Each timer count register is 16 bits.
The count advances until the value set to this register, and then a timeout occurs, potentially triggering an interrupt.
Channel 4 is used exclusively for the RS-232C baud rate generator, and the value to set is determined using the 8251's divider ratio setting and the desired baud rate. Table I-3-26 shows the values to use when setting the channel 4 timer count register. There is more detailed discussion of RS-232C in Part I Chapter 7.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0040 | Timer count register | R/W | Timer #0 | |||||||
| 0x0042 | Timer #1 | |||||||||
| 0x0044 | Timer #2 | |||||||||
| 0x0050 | Timer #3 | |||||||||
| 0x0052 | Timer #4 | |||||||||
| 0x0054 | Timer #5 | |||||||||
- Sets the count value for timer channels 0-5.
| Mode: | Synchronous | Asynchronous | Count value | |
|---|---|---|---|---|
| Divider ratio: | 1/1 | 1/16 | 1/64 | |
| Baud rate | 75 | 16,384 | ||
| 150 | 8,192 | |||
| 300 | 4,096 | |||
| 600 | 2,048 | |||
| 1,200 | 75 | 1,024 | ||
| 2,400 | 150 | 512 | ||
| 4,800 | 300 | 75 | 256 | |
| 9,600 | 600 | 150 | 128 | |
| 19,200 | 1,200 | 300 | 64 | |
| 2,400 | 600 | 32 | ||
| 4,800 | 1,200 | 16 | ||
| 9,600 | 2,400 | 8 | ||
| 19,200 | 4,800 | 4 | ||
The control registers (table I-3-27) configure the operating mode and other per-channel settings.
To select a channel, the SC0-1 bits are used, but please note that the I/O address changes depending on which of the two PITs to configure. Channels 0-2 are accessed via I/O address 0x0046, whereas channels 3-5 are accessed by I/O address 0x0056.
The RL0-1 bits control both the operation when reading the timer count value and also set the counter latch (preserved count value). The timer count value is two bytes, so using the same I/O address, only the top byte, only the bottom byte, or both bytes in sequence can be read.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0046 | Control register PIT1 (#0-#2) | W | SC1 | SC0 | RL1 | RL0 | M2 | M1 | M0 | BCD |
| 0x0056 | Control register PIT2 (#3-#5) |
-
SC0-1 (bit 6-7): Selects the timer.
I/O address SC1 SC0 Channel 0x0046
(PIT1)0 0 0 0 1 1 1 0 2 0x0056
(PIT2)0 0 3 0 1 4 1 0 5 -
RL0-1 (bit 4-5): Selects the count number to load via the count register and the byte length of the count data to read, or counter latch operation.
RL1 RL0 Function 0 0 Counter latch 0 1 Read/write low byte 1 0 Read/write high byte 1 1 Read/write low then high byte in sequence -
M0-M2 (bit 1-3): Selects the timer operating mode.
M2 M1 M0 Mode setting 0 0 0 Mode 0 0 0 1 Mode 1 x 1 0 Mode 2 x 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 -
BCD (bit 0): Selects the count format.
- 0: Binary counter (16 digits)
- 1: BCD counter (4 digits)
Bits M0-2 set the timer's operating mode. In the FM TOWNS, the mode for each channel is fixed, so fixed values must be always be set. Going into detail about each mode would take a long time, so we only summarize them in this book. If a detailed explanation is necessary, please consult the 8253 manual or equivalent.
The BCD bit sets the count format. Setting the bit to 0 enables a binary counter, whereas setting it to 1 uses binary-coded decimal (BCD). In BCD, four bit positions correspond to one decimal digit. By comparison with the binary counter, the BCD counter's maximum count value is much lower, so care is necessary.
The interrupt control register (table I-3-28), in addition to enabling or disabling interrupts for channel 0 and 1, also has the ability to clear the timeout flag for timer 0 in the interrupt reason register (TM0CLR).
TM0CLR is written with 1 to clear the timeout flag. After clearing, this bit is erased, so software does not have to set it back to zero.
Additionally, the SOUND bit in this register is used to turn sound output on or off.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0060 | Interrupt control register | W | TM0CLR | 0 | 0 | 0 | 0 | SOUND | TM1MSK | TM0MSK |
- TM0CLR (bit 7): Clears the timer #0 timeout flag (TMOUT0).
- 1 = Set TMOUT0 to zero. (Setting TM0CLR back to zero afterward is not necessary.)
- SOUND (bit 2): Controls sound output.
- 0: Sound output off.
- 1: Sound output on.
- TM1MSK (bit 1): Controls the timer #1 timeout interrupt.
- 0: Interrupts forbidden.
- 1: Interrupts allowed.
- TM0MSK (bit 0): Controls the timer #0 timeout interrupt.
- 0: Interrupts forbidden.
- 1: Interrupts allowed.
The interrupt reason register (table I-3-29) indicates timeout conditions alongside the settings from the interrupt control register.
SOUND, TM0MSK, and TM1MSK are reflected from their values in the interrupt control register.
TMOUT0 and TMOUT1 reflect the status of timers 0 and 1. Each of these bits indicate whether the corresponding timeout has occurred.
The method for clearing these bits is as follows:
For TMOUT0, write 1 to the TM0CLR bit as previously mentioned.
TMOUT1 is automatically cleared by writing a count value to timer count register #1. This is because the interval timer (channel 0) operates at a fixed time interval, but the I/O control timeout (channel 1) time setting varies depending on the device, so the timer count register needs to be rewritten with each use.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0060 | Interrupt reason register | R | undefined | SOUND | TM1MSK | TM0MSK | TMOUT1 | TMOUT0 | ||
-
SOUND (bit 4): Shows the SOUND bit value from the interrupt control register.
-
TM1MSK (bit 3): Shows the TM1MSK bit value from the interrupt control register.
-
TM0MSK (bit 2): Shows the TM0MSK bit value from the interrupt control register.
-
TMOUT1 (bit 1): Indicates a timeout on timer #1.
- 0: Count in progress
- 1: Timeout
When TMOUT1=1 as well as TM1MSK=1, an interrupt is triggered on the CPU. This bit is cleared by setting the count number.
-
TMOUT0 (bit 0): Indicates a timeout on timer #0.
When TMOUT0=1 as well as TM0MSK=1, an interrupt is triggered on the CPU. When TM0CLR is written with 1, this bit becomes 0.
The real-time clock (RTC) tracks both year-month-date and hour-minute-second time. In this section, we describe the structure and operation of the RTC.
Table I-3-30 describes the specifications for the real-time clock.
The FM TOWNS uses the same 58321B RTC as every previous model in the FM series. It is backed up by a NiCd battery, which from a full charge provides approximately 3 months of backup charge.
| Item | Specification |
|---|---|
| LSI | RTC58312B |
| Battery backup | NiCd battery available. 3 months backup from full charge |
| Data representation | Year-Month-Date Hour-Minute-Second |
Inside of the RTC is an address register as well as several 4-bit counters. The address register is used to select which counter is accessed from the CPU.
The counters correspond to time component values, holding the 1-second value, 10-second value, ..., 1-year value, and 10-year value. These counter values change moment-to-moment with the advancement of time. By writing to the data registers, the year-month-date and hour-minute-second values are set, and by reading them, the current time value can be acquired. Table I-3-31 describes the contents of these counters.
The RTC generates a clock pulse every second by counting clock intervals from a crystal oscillator through a division circuit. This division circuit and counter are shown in diagram I-3-3. The second clock advances the 1-second register, and when the 1-second value wraps around, it affects the minute, hour, date, day of week, month and year registers. The RTC updates the contents of these registers as needed immediately after each 1-second clock pulse, so the CPU does not need to be involved in updating the registers.
At the same time as the 1-second clock pulse, the RTC outputs a busy signal, as shown in diagram I-3-4. Writing to the RTC registers should begin after confirming the RTC is not in the busy state. If the RTC enters the busy state during a write, the write should be presumed faulty, and the write needs to be retried.
In order to be strictly correct after a busy state occurs in the middle of writing time data, one should start over and set all of the values again starting from the seconds value. For instance, in order to write "29 seconds", if a busy state occurs immediately after writing "9", then the 1-second value will incorrectly become "0", and if one continues writing the "2" to the 10-seconds place, the RTC will incorrectly contain "20 seconds".
If the update can be done while setting the lowest second value to 0 according to the time (and that is frequently the case in reality), there will not be much trouble.
| Internal counter | Address | Bit expression | Data | Count value | Notes | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| D3 | D2 | D1 | D0 | D3 | D2 | D1 | D0 | ||||||||||||||||||||||||
| S1 (seconds) | 0 | 0 | 0 | 0 | 0 | * | * | * | * | 0-9 | |||||||||||||||||||||
| S10 (10 seconds) | 1 | 0 | 0 | 0 | 1 | * | * | * | 0-5 | ||||||||||||||||||||||
| M11 (minutes) | 2 | 0 | 0 | 1 | 0 | * | * | * | * | 0-9 | |||||||||||||||||||||
| M110 (10 minutes) | 3 | 0 | 0 | 1 | 1 | * | * | * | 0-5 | ||||||||||||||||||||||
| H1 (hours) | 4 | 0 | 1 | 0 | 0 | * | * | * | * | 0-9 | |||||||||||||||||||||
| H10 (10 hours) | 5 | 0 | 1 | 0 | 1 | *1 | * | * | * | 0-1 / 0-2 |
D2 = 1 for PM, D2 = 0 for AM D3 = 1 for 24-hour time, D3 = 0 for 12-hour time When D3 = 1 is written, the IC internally resets D2 so that it is always zero. |
||||||||||||||||||||
| W (day of week) | 6 | 0 | 1 | 1 | 0 | * | * | * | 0-6 | ||||||||||||||||||||||
| D1 (days) | 7 | 0 | 1 | 1 | 1 | * | * | * | * | 0-9 | |||||||||||||||||||||
| D10 (10 days) | 8 | 1 | 0 | 0 | 0 | *2 | *2 | * | * | 0-3 | The D2 and D3 bits of the D10 column are used to select leap year.
|
||||||||||||||||||||
| M01 (months) | 9 | 1 | 0 | 0 | 1 | * | * | * | * | 0-9 | |||||||||||||||||||||
| M010 (10 months) | A | 1 | 0 | 1 | 0 | * | 0-1 | ||||||||||||||||||||||||
| Y1 (years) | B | 1 | 0 | 1 | 1 | * | * | * | * | 0-9 | |||||||||||||||||||||
| Y10 (10 years) | C | 1 | 1 | 0 | 0 | * | * | * | * | 0-9 | |||||||||||||||||||||
| D | 1 | 1 | 0 | 1 | Latch this code into the select and address registers in order to reset the five stages after the 1/215 divider and the busy circuit. The reset is triggered when 1 is written. | ||||||||||||||||||||||||||
| E-F | 1 | 1 | 1 | 0 / 1 | Latch this code into the select and address registers in order to acquire the reference signal. When a 1 is read, the reference signal is output on D0-D3. | ||||||||||||||||||||||||||
Notes:
- An empty data input column has no corresponding bit. When read, a 0 will be output, and since there is no bit, the value will not be saved during a write.
- The bit marked with *1 is used to select a 12 hour/24 hour clock. The bits marked with *2 are used to select the leap year. These three bits can be read and written.
- For address input, D0-D2 send the signals onto the bus lines, and when ADDRESS WRITE is sent, the address information is latched into the address register.
[diagram I-3-3]
[diagram I-3-4]
In order to handle leap years, the RTC provides the ability to represent February 29 once every four years. To determine whether the current year is a leap year, the remainder of dividing the year value by 4 is taken. Which of the 0-3 values indicates a leap year is selected by the D2 and D3 bits of the 10-day register value (which would otherwise be empty). This method is flexible enough to handle both western and Japanese calendars.
To use the western calendar, or the Heisei (平成) era, since leap years occur when the year remainder is 0, D2 and D3 are set to 00. For instance, Western years 1992, 1996, etc. CE, corresponding to 平成4, 8, etc. 年, are leap years. To use the Shouwa (昭和) era, in which leap years occurred with a year remainder of 3, D2 and D3 can be set to 10. [Translator's note: for the Reiwa (令和) era, current at the time of this translation, leap years occur with a year remainder of 2, corresponding to the 01 bit setting.] However, be aware that the RTC does not take into account the three times every 400 years there is a non-leap year.
To access the RTC's internal registers from the CPU, the RTC data register (table I-3-32) and RTC command register (table I-3-33) are used.
First, the address of the desired internal register is written to the RTC data register, and after that the internal register can be accessed. Afterward, read or write is selected via the RTC command register.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0070 | RTC data register | R | READY | undefined | D3 | D2 | D1 | D0 | ||
| W | 0 | 0 | 0 | 0 | ||||||
- READY (bit 7): This bit becomes 1 when the RTC is updating the time. The time is updated every second, and in this interval (approximately 430 microseconds) the RTC cannot be read.
- D0-D3 (bit 0-3): Sets the time data in the RTC's selected register. (write) Reads time data from the RTC. (read)
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0080 | RTC command register | W | CHIP SELECT | 0 | 0 | 0 | 0 | READ | WRITE | ADDRESS WRITE |
- CHIP SELECT (bit 7): This bit is set to 1 when reading or writing RTC registers or selecting the register number. When this bit is zero, the other commands have no effect.
- READ (bit 2): Reads data from the RTC register chosen by ADDRESS WRITE. Set this bit to 1 in order to read, then it should be set back to 0.
- WRITE (bit 1): Writes data to the RTC register chosen by ADDRESS WRITE. Set this bit to 1 then set it back to 0 in order to write data to the register selected by ADDRESS WRITE.
- ADDRESS WRITE (bit 0): Selects the RTC register. By setting this bit to 1 and then back to 0, the RTC register is selected according to the register number previously written to the data register.
A flow chart of the process for accessing an RTC internal register is shown in diagram I-3-5.
Below, we explain the access process following the flowchart.
-
Confirm the RTC's ready state by reading RTC data register bit 7. If this bit is 1, the RTC is ready to be accessed.
-
Write 0x80 to the RTC command register.
-
Write the RTC internal register address to the RTC data register.
Write 0x81 (ADDRESS WRITE) to the RTC command register (setting the RTC internal address register), then write 0x80. -
Access the RTC internal register.
When reading data from an RTC internal register, write 0x84 to the RTC command register, then after waiting at least 2 microseconds, read from the RTC data register. Afterward, write 0x00 to the RTC command register.When writing data to an RTC internal register, write the desired value to the RTC data register, then write 0x82 to the RTC command register, and after waiting at least 2 microseconds, write 0x80 to the RTC command register.
-
Repeat steps 3-4 to access multiple RTC internal registers. When finished, write 0x00 to the RTC command register.
By writing any data to RTC internal register 13 (0xD), the division circuit is reset back to zero. Afterward, the RTC will not enter the ready state for about 1 second. When writing data to the RTC, using this method can avoid write faults.
In this section, we describe auxiliary registers near the CPU. These registers are standalone, separate from the previously-mentioned devices.
When a reset occurs, the reset reason register (table I-3-34) indicates its cause. The system software consults this bit immediately after booting and uses it to be able to perform boot-time processing.
When main power is turned on, or when the system is reset by pressing the reset switch, every bit of this register is zero.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0020 | Reset reason register | R | undefined | SHUTDOWN | SOFT | |||||
- SHUTDOWN (bit 1): Indicates that reset was caused by a shutdown (abnormal
condition detected by the CPU). This bit is cleared by reading.
- 1: Shutdown reset
- SOFT (bit 0): Indicates that reset was caused by software. This bit is
cleared by reading.
- 1: Software reset
Shutdown resets and software resets both only reset the CPU and math coprocessor. At power on reset or system reset time, both flags are zero.
In the soft reset, NMI vector protect, and soft power control register (table I-3-35), the RST bit triggers a soft reset. By writing 1 to this bit, the CPU and math coprocessor are reset. Afterward, in order to begin the reset sequence and avoid malfunction, the CPU is expected to be put in standby state with a HALT instruction.
The WRPROT bit can be set to 1 in order to write-protect the contents of memory where the NMI interrupt vector is stored.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0020 | Soft reset, NMI vector protect, and soft power control | W | WRPROT | POWOFF | 0 | 0 | 0 | 0 | 0 | RST |
-
WRPROT (bit 7): Write-protects the memory address where the NMI vector is stored. [Translator's note: this refers to the location of the real mode interrupt vector table entry for INT 2, the four bytes starting at physical address 0x8.] This flag is 0 at power-on or system reset time.
- 0: NMI vector write enable
- 1: NMI vector write protect
-
POWOFF (bit 6): Turns power off from software.
- 1: Power off
-
RST (bit 0): Resets the CPU and math coprocessor from software.
- 1: Software reset on
The computer must not be reset during a DMA transfer. After resetting, 0 should always be written. When performing a reset, PIC interrupts should be forbidden beforehand, and a HALT instruction should be executed immediately after the reset.
The power control register (table I-3-36) is used by software to turn off power.
When turning off power is desired, write 1 to the POWOFF bit.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0022 | Power control register | W | 0 | POWOFF | 0 | 0 | 0 | 0 | 0 | 0 |
- POWOFF (bit 6): Turns power off from software.
- 1: Power off
The CPU identification register (table I-3-37) holds the machine model and CPU type.
It consists of a 13-bit MACHINE-ID code indicating the machine model, and a 3-bit CPU-ID code indicating the CPU type.
To correctly determine the FM TOWNS model, the program should first confirm that the ID3-7 bits are all zero, and then check that ID9-15 are zero and ID8 is one. Checking ID8-15 first might give an incorrect result because those bits are undefined on FMR models.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0030 | CPU identification register | R | MACHINE-ID | CPU-ID | ||||||
| ID7 | ID6 | ID5 | ID4 | ID3 | ID2 | ID1 | ID0 | |||
| 0x0031 | MACHINE-ID | |||||||||
| ID15 | ID14 | ID13 | ID12 | ID11 | ID10 | ID9 | ID8 | |||
-
MACHINE-ID (bit 15-3): Indicates the type of computer. Identify the computer according to the below bit configurations:
Computer ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 FMR-60/50 undefined 1 1 1 1 1 FMR-50S undefined 1 1 1 0 1 FMR-70 undefined 1 1 1 1 0 FM TOWNS 0 0 0 0 0 0 0 1 0 0 0 0 0 The FM TOWNS uses ID8-15 for MACHINE-ID, which are valid when ID3-7 are all zero.
-
CPU-ID (bit 0-2): Indicates the CPU type in use. Identify the CPU according to the below bit configurations:
ID2 ID1 ID0 CPU 0 0 0 80286 0 0 1 80386 0 1 0 reserved 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved
The serial ROM records things like the model name and production number. Reading and writing to the serial ROM control register (table I-3-38) will read this information through the ID DATA field one bit at a time.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0032 | Serial ROM control register | R | ID RESET | ID CLK | undefined | ID DATA | ||||
| W | CS ID | 0 | 0 | 0 | 0 | 0 | ||||
- ID RESET (bit 7): With chip select active, when the clock signal becomes 1, changing this bit 0-1-0 will reset the ROM's internal address to zero.
- ID CLK (bit 6): Clock signal for the serial ROM. With chip select active, when ID RESET is zero and this bit changes from zero to one, the serial ROM address advances by one.
- CS ID (bit 5): Serial ROM chip select.
- 0: Active
- 1: Inactive
- ID DATA (bit 0): The serial data indicated by the serial ROM's internal address.
The data in the 256 bits of serial ROM are written in the following format:
| 255…252 | 251 … 72 |
| 0 0 0 0 | FUJITSU …… (reserved) …… |
| 71 … 56 |
| Device type number (0x0101 hex) |
| 55 … 20 |
| Serial number (production number) |
| 19 … 0 |
| 0 …… 0 |
Data contents:
- address 255-252: One hexadecimal digit fixed at 0x0.
- address 251-72: Reserved (planned for future expansion). Addresses 251-224 contain "FUJITSU" (0x46 0x55 0x4A 0x49 0x54 0x53 0x55). Addresses 223-72 are all 0xF.
- address 71-56: Device type number as four hexadecimal digits (fixed 0x0101 for the FM TOWNS).
- address 55-20: Serial number as nine hexadecimal digits.
- address 19-0: Five hexadecimal digits fixed at 0x00000. (Indicates that information has been written.)
The system status registers (table I-3-39) can be used to read the display resolution and to set which type of memory is used as a DMA transfer destination.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0400 | System status register | R | undefined | Resolution | ||||||
- Resolution (bit 0): Indicates medium or high resolution.
- 0: Fixed (medium resolution)
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0404 | System status register | R | MAIN MEM | undefined | ||||||
| W | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
- MAIN MEM (bit 7): Selects main memory or VRAM. At reset time, this is
set to graphics VRAM.
- 0: VRAM
- 1: Main memory
The memory switch register (table I-3-40) selects whether RAM or ROM is presented in the address range 0xF8000-0xFFFFF, and whether main RAM or dictionary/learning RAM is used.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0480 | Memory switch register | R | undefined | RAM | Dictionary ROM | |||||
| W | 0 | 0 | 0 | 0 | 0 | 0 | ||||
- RAM (bit 1): Selects whether 0xF8000-0xFFFFF maps RAM (32KB) or ROM
(32KB).
- 0: Boot ROM
- 1: RAM
- Dictionary ROM (bit 0): Selects whether RAM or dictionary/learning RAM
is mapped.
- 0: RAM
- 1: Dictionary/learning RAM
The dictionary register (table I-3-41) selects the dictionary ROM bank.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0484 | Dictionary ROM | R | undefined | DBK3 | DBK2 | DBK1 | DBK0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
16 banks of 32KB (512KB total) ROM can be accessed:
| Bank | DBK3 | DBK2 | DBK1 | DBK0 |
|---|---|---|---|---|
| Bank 0, Dictionary ROM bank 0 | 0 | 0 | 0 | 0 |
| Bank 1, Dictionary ROM bank 1 | 0 | 0 | 0 | 1 |
| Bank 2, Dictionary ROM bank 2 | 0 | 0 | 1 | 0 |
| Bank 3, Dictionary ROM bank 3 | 0 | 0 | 1 | 1 |
| ⋮ | ⋮ | ⋮ | ⋮ | ⋮ |
| Bank 15, Dictionary ROM bank 15 | 1 | 1 | 1 | 1 |
The memory card status register (table I-3-42) observes when a memory card is ejected or inserted.
Specifically, the CD-0 and CD-1 bits indicate whether a card is currently present or not, and the CHANGE bit can be inspected in order to determine whether an insertion or ejection occurred. The CHANGE bit becomes 1 after an insertion or ejection, and is cleared to zero immediately after being read.
Also, the remaining backup battery power can be checked, with bits for these levels:
- RED: Backup not possible (backup data will not be preserved)
- YELLOW: Low power remaining (replacement needed)
If either bit becomes 1, other steps are necessary in addition to changing the battery to preserve the data. For instance, if the battery level is YELLOW and the battery needs to be replaced but the backup data isn't saved to somewhere like disk first, then it will be erased. There is software that can manage loading data back to the card after the battery is exchanged.
The WP bit can be inspected to check the memory card's write protect status. If the bit is 0, writing is possible.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x048A | Memory card status | R | CHANGE | undefined | RED | YELLOW | (RDY) | CD-0 | CD-1 | WP |
-
CHANGE (bit 7): Indicates that a memory card (such as a ROM card) was inserted or ejected. Becomes 0 when read.
- 1: Insertion or ejection occurred
-
RED, YELLOW (bit 5, 4): Indicates remaining backup battery energy.
- RED indicates that the backup battery cannot preserve data.
- 1: No battery energy
- YELLOW indicates that the backup battery needs replacement.
- 1: Battery replacement necessary
- RED indicates that the backup battery cannot preserve data.
-
CD-0, CD-1 (bit 2, 1): Indicates the presence of a card:
CD-1 CD-0 Function 0 0 Card present 0 1 Not inserted correctly 1 0 Not inserted correctly 1 1 No card -
WP (bit 0): Indicates that writing to the memory card unit is not allowed.
- 0: Writing allowed
- 1: Writing forbidden
-
(RDY) (bit 3): Not used. (If a memory card unit is equipped with EEPROM, indicates that the EEPROM is in a writable state.
- 0: Writing not possible
- 1: Writing possible)
The NMI mask register (table I-3-43) and NMI status register (table I-3-44) handle NMIs from the expansion bus.
The NMI mask register is used to mask (ignore) NMI requests from the expansion bus. When this register's BNMI bit is zero, NMIs from the expansion bus are masked. The intent of the hardware design allowing the non-maskable interrupt to be masked is that the expansion NMI should normally be masked and only enabled (accepted) when needed.
The NMI status register is used by an NMI handler to determine whether an NMI came from the expansion bus. This register's BNMI bit is set to 1 if an NMI comes from the expansion bus. If the expansion unit is not installed, it always holds 0.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x05C0 | NMI mask register | R | undefined | BNMI | undefined | |||||
| W | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
- BNMI (bit 3): Sets the expansion bus NMI mask.
- 0: Masked
- 1: Enabled
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x05C2 | NMI status register | R | undefined | BNMI | undefined | |||||
- BNMI (bit 3): Indicates an expansion bus NMI.
- 0: No
- 1: Yes
The TVRAM write register (table I-3-45), with the MD bit, indicates whether or not writes to the text VRAM region are carried out.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x05C8 | TVRAM write register | R | MD | undefined | ||||||
- MD (bit 7): Indicates the text VRAM state. Becomes 0 after being read.
- 0: Text VRAM has not been written to
- 1: Text VRAM was written to
The VSYNC interrupt trigger clear register (table I-3-46) is a dummy register used when a VSYNC interrupt occurs so that the interrupt handler can stop the VSYNC interrupt request.
There is no particular meaning to any of its bits; the interrupt request is terminated just by writing anything to this register.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x05CA | VSYNC interrupt trigger clear register | W | write to clear | |||||||
- The VSYNC interrupt trigger is cleared by a dummy write to this register.
Bit 7 of the FIRQ register (table I-3-47) serves as the light pen interrupt request flag, but the FM TOWNS does not support a light pen, so it is always zero.
| Memory address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x000C_FF84 | FIRQ register | R | 0 | undefined | ||||||
- bit 7: Light pen interrupt request flag. Unsupported on the FM TOWNS, so this bit is always 0.
The kanji character generator access register (table I-3-48) is used for read/write access to the kanji character generator's kanji font.
| Memory address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x000C_FF94 | Kanji character generator access register | R | L2CG | undefined | ||||||
| W | KC15 | KC14 | KC13 | KC12 | KC11 | KC10 | KC9 | KC8 | ||
| 0x000C_FF95 | W | KC7 | KC6 | KC5 | KC4 | KC3 | KC2 | KC1 | KC0 | |
| 0x000C_FF96 | R/W | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | |
| 0x000C_FF97 | R/W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
- L2CG (bit 7): Indicates whether a Level 2 Kanji character generator is present. This bit is always 1 (Level 2 Kanji are always available).
- KC0-15: Selects the code of the kanji to access using its JIS code.
- D0-15: Read/write kanji character data. The font data can be read or written row-by-row, with the row address incrementing when address FF97 is accessed. When address FF95 is accessed, the row address is cleared. The ROM's low four bits are counted with each read.
The buzzer control register (table I-3-49) is used to turn the buzzer on and off.
| Memory address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x000C_FF98 | Buzzer control register | R/W | read: on | |||||||
| write: off | ||||||||||
- Reading this register turns the buzzer on, and writing it turns the buzzer off.
The Kanji VRAM register (table I-3-50) determines which of the kanji VRAM or alpha-numeric-kana character generator can be accessed.
| Memory address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x000C_FF99 | Kanji VRAM register | W | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ANKCG |
- ANKCG (bit 0): Selects which of kanji VRAM or the alpha-numeric-kana
character generator to access.
- 0: Select kanji VRAM
- 1: Select the ANK character generator
The logical operation register (table I-3-51) is always fixed at zero.
| Memory address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x000C_FFA0 | Logical operation register | R | ESTART (0) |
undefined | ||||||
- ESTART (bit 7): The logical operation is always fixed at 0.
In this chapter, we explain various ways the FM TOWNS' complex video display hardware can be used. Specifically, the topics we cover include screen types, reading and writing to VRAM, the palette, sprites, display output, and scrolling system.
The FM TOWNS has superior video display capabilities, and is able to display various screen resolutions and color depths. There are 18 fundamental screen modes. Whether scrolling, digitization, superimpose, and/or sprites can be used depends on the screen mode. In this section, we give an overview of the video display. For more details on display capabilities, please consult the following sections.
Table I-4-1 arranges each screen mode with its video display capabilities.
There are 18 fundamental screen modes.
Setting any screen mode requires setting all of its register values. Please see "4.7.3: CRTC registers and their configuration" for details.
| Mode number | Virtual screen | Visible screen (effective pixel size) | Actual display area | Color depth | Palette | Layer count | Scrolling | CRT horizontal frequency | Sprites | Superimpose | Digitizer |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 640x400 | 640x400 | 640x400 noninterlaced (FMR-50 compatible) | 16 colors | 16/4,096 colors | 2 screens | None | 24.37KHz underscan | Unavailable | Unavailable | Unavailable |
| 2 | 640x200 | 640x200 noninterlaced (double read) | |||||||||
| 3 | 1024x512 | 640x480 (1:1 pixel aspect ratio) | 640x480 noninterlaced | Cylindrical (vertical only) | 31.47KHz underscan | ||||||
| 4 | 640x400 | 640x400 noninterlaced | 24.37KHz underscan | ||||||||
| 5 | 256x512 | 256x256 | 256x256 noninterlaced | 32,768 colors | None | 31.47KHz underscan | Available | ||||
| 6 | 256x256 | 256x256 noninterlaced | 24.37KHz underscan | ||||||||
| 7 | 256x240 | 230x216 interlaced | 15.73KHz overscan | Available | Available | ||||||
| 8 | 256x240 | 230x216 interlaced | |||||||||
| 9 | 512x256 | 360x240 | 324x216 interlaced | Spherical (unlimited) | Unavailable | ||||||
| 10 | 320x240 | 320x240 interlaced | 31.47KHz underscan | Unavailable | Unavailable | ||||||
| 11 | 320x240 | 288x216 interlaced | 15.73KHz overscan | Available | Available | ||||||
| 12 | 1024x512 | 640x480 (1:1 pixel aspect ratio) | 640x480 noninterlaced | 256 colors | 256/16.77 million colors | 1 screen | Cylindrical (vertical only) | 31.47KHz underscan | Unavailable | Unavailable | |
| 13 | 640x400 | 640x400 noninterlaced | 24.37KHz underscan | ||||||||
| 14 | 720x480 | 648x432 interlaced | 15.73KHz overscan | Available | |||||||
| 15 | 512x512 | 320x480 (2:1 pixel aspect ratio) | 320x480 noninterlaced | 32,768 colors | None | 31.47KHz underscan | Unavailable | ||||
| 16 | 320x480 (2:1 pixel aspect ratio) | 288x432 interlaced | 15.73KHz overscan | Available | Available | ||||||
| 17 | 512x480 | 512x480 noninterlaced | 31.47KHz underscan | Unavailable | Unavailable | ||||||
| 18 | 512x480 | 512x432 interlaced | 15.73KHz overscan | Available | Available |
The FM TOWNS uses a bitmapped display. A bitmap stores image data as pixel values in memory (VRAM). Text display on the TOWNS also uses this technique.
Furthermore, the hardware supports the screen concept at two levels, the virtual screen and visible screen. The virtual screen is what is directly stored in VRAM, and the part that is selected out of the full extent of the virtual screen to show on the display is called the visible screen. Diagram I-4-1 illustrates the relationship between the virtual and visible screens.
The display can be output to a CRT with either underscan or overscan. With underscan, the full extent of the visible screen is visible on the CRT, but with overscan, areas of the visible screen do not actually get displayed (diagram I-4-2). The extent of the visible screen area is called the effective pixel size.
To change what part of the virtual screen is displayed as the visible screen, the screen is scrolled. In addition to cylindrical scrolling, the FM TOWNS also supports spherical scrolling (described below). It is also possible to display two virtual screens stacked on top of each other.
The number of possible display colors can be chosen to suit the content being displayed.
For example, 32,768-color mode is suitable for displaying natural images. Alternatively, using the palette functionality, 16-color mode gives the choice of 16 out of 4,096 colors, and 256-color mode gives the choice of 256 out of 16.77 million colors, allowing for subtle color distinctions to be expressed.
Sprites are used to display quickly-moving patterns over the screen.
Sprites are displayed stacked in front of the normal screen, and they can be moved just by changing their display address without touching background screen data.
Up to 1,024 sprites can be displayed. Each sprite pixel color can be chosen out of 32,768 colors.
Superimpose functionality stacks the computer image on top of an image from an external video signal. An optional video card is necessary to use superimpose.
An external video signal can be transformed in real time into digital data and stored in VRAM. To use the digitizer, the optional video card is necessary.
The FM TOWNS is designed to allow the use of FMR-50 software. Even for screen output, its hardware was designed to provide outwardly equivalent behavior to an FMR-50.
The FMR-50 has both graphics VRAM, with framebuffer access, and text VRAM for text output. The FM TOWNS uses 8KB of RAM (4KB of text VRAM, and 4KB of kanji VRAM) to emulate text VRAM in order to implement the FMR-50 compatible display using the TOWNS' framebuffer graphics mode.
Here we explain some additional terminology used in table I-4-1.
Interlacing is a display method where the odd rasters (a raster being an emission line, corresponding to one horizontal row) and even rasters are separated and displayed alternately. This display method is generally used for televisions.
Please see "4.7.2: CRT display system" for a detailed explanation of interlacing.
Pixel aspect ratio refers to the height-to-width ratio of the display when a square is drawn with an equal number of vertical and horizontal pixels.
In this section, we provide an overview of the CRT controller, which performs essential screen management tasks.
The block diagram in Diagram I-4-3 describes how the screen is controlled.
The CRT controller carries the core responsibilities of controlling the display. The largest part of the CRT controller's operation is outputting data written in VRAM to the display.
The CRT controller output is in analog RGB format, which can be directly connected to a display. This output only includes the computer's image; unlike the video card's analog RGB output, it cannot show a superimposed image.
[diagram I-4-3]
The CRT controller is made up of four CRT-related controller components.
The VRAM access controller manages reading VRAM. The display controller manages display timing. The sprite I/O controller handles sprite display. The video output controller handles composing the displayed video signal.
Every controller is connected to VRAM, sprite pattern RAM, palette RAM, and/or the DAC.
There are various registers provided to control each chip, which are operated by I/O accesses from the CPU. Please consult the following sections regarding the structure and operation of each register, or consult "4.11: Video card" for information about the video card.
In this section, we describe how to read and write VRAM, along with topics related to addressing VRAM.
In order to show a still image on the display, it is necessary to continuously repeat the same video signal from the computer. Computers are equipped with memory to store this video signal as digital data for this purpose, called VRAM (video random access memory).
The FM TOWNS has 512KB of VRAM. This memory is presented in the same address space as main memory, so can be freely read from or written to by the CPU. Also, VRAM is equipped with two sets of address lines at separate access points, so VRAM can be read from and written to in parallel by the CPU and video controller at the same time, making high-speed drawing possible. This style of VRAM is called dual-ported VRAM.
VRAM can be used in its entirety for a single virtual screen, or it can be divided into two virtual screens (256KB each) or four virtual screens (128KB each).
For example, for a screen mode with a 1024x512 pixel virtual screen and 256 simultaneous colors, 512KB of memory is necessary for one screen, so the entirety of VRAM is used as one virtual screen. However, for a 1024x512 screen mode with 16 simultaneous colors, one screen only needs 256KB, so it is possible to use two virtual screens. (diagram I-4-3)
One screen in VRAM is called a page. When split into two parts, in increasing order starting from lower addresses, the pages are called page 0 and 1. When split into four parts, there are pages 0 through 3.
The size of VRAM needed for one virtual screen is the total pixel count times the number of VRAM bits per pixel, with the number of bits per pixel determined by the color depth as shown in table I-4-2.
| Color depth | VRAM bits per pixel |
|---|---|
| 16 | 4 bits (24) |
| 256 | 8 bits (28) |
| 32,768 | 16 bits (216) |
In 32,768 color mode, one out of the 16 bits is used for superimpose control, so 15 bits are used to determine the color.
The FM TOWNS uses a concept called screen layers in order to output values from VRAM to the display.
Two screen layers are provided, called screen layer 0 and 1. Screen output is performed with a VRAM page assigned to each of these layers (diagram I-4-4). Two screen layers can be displayed stacked on top of each other, with the higher-priority layer displayed in front.
[diagram I-4-4]
VRAM pages are associated with screen layers as follows.
When all of VRAM is used as one screen, page 0 must be assigned to screen layer 0. When VRAM is divided into two pages, page 0 must be associated with layer 0, and page 1 with layer 1 (diagram I-4-5).
When VRAM is divided into four pages (640x400 pixel mode), then screen layer 0 can be assigned to page 0 or page 1, and screen layer 1 to page 2 or 3. Thus only one out of page 0 or 1 is displayed with one out of page 2 or 3.
Various screen settings are possible for each screen layer, and screens with different screen modes can be combined.
When divided into four pages, which of page 0 or 1 is assigned to screen layer 0 (that is, which page is displayed) is determined by the VRAM display mode register (table I-4-41) described below. Also, the accessed page is switched using the graphics VRAM page select register (table I-4-44).
For screen layer 1, CRTC frame start address 1 is set to either page 2 or 3's start address, according to the chosen displayed page.
[diagram I-4-5]
When two screens are overlaid in the manner described above, which of the screen layers is shown in the foreground (priority order) is selected by the video output control priority register (table I-4-37), described below. When the PRI bit is 0, screen layer 0 is foreground, and when it is 1, screen layer 1 is foreground.
Using superimpose functionality, the computer screen can be composed with an external video signal. In this case, in addition to the two screen layers, a video screen layer is used for displaying the video signal. The video screen layer has lower priority than the screen layers, so the video image is always displayed in the background to the computer image.
For example, in diagram I-4-6, the page with the rocket drawing is assigned to the highest priority screen layer, the page with the planet drawing is assigned to the remaining screen layer, and the video screen layer shows an image of outer space and the moon. On the screen, it appears as if the rocket is flying through outer space near the planet.
Superimpose is also possible when the computer image is in a one screen layer mode.
Please consult "4.11: Video card" regarding superimpose.
[diagram I-4-6]
One of the screen colors can be used as a transparent color. When the color in a higher-priority screen layer is transparent, the color of the pixel at the same coordinates in a lower priority screen layer becomes visible.
The pixel data value used for the transparent color changes depending on the color depth, as shown in table I-4-3.
Diagram I-4-7 includes a video screen layer. Using transparency management, the colors of the pixels in the highest-priority screen layer are shown, excluding the transparent ones.
| Color depth | Transparent color pixel data |
|---|---|
| 32,768 (16 bit) | Highest bit (bit 15) is 1 |
| 256 (8 bit) | Bit pattern 0000_0000 |
| 16 (4 bit) | Bit pattern 0000 |
[diagram I-4-7]
The screen mode can be set independently for each screen layer. For example, a landscape photograph can be shown using screen layer 1 set to screen mode 5 (256x256 pixels, 32,768 colors), with screen layer 0 on top of that showing text in screen mode 3 (640x480 pixels, 16 colors).
For which screen modes support being overlaid, please see "4.7.3: CRTC registers and their configuration".
The contents of VRAM can be directly read from and written to by the CPU.
Here, we explain this system.
In the FM TOWNS, the data order in VRAM is suitable for 32-bit transfer instructions; regardless of the number of bits per pixel, the value stored to the register contains the pixels in opposite order from the pixel order on screen. Executing 32-bit transfer instructions is preferred.
By using this technique, pixel data can be transferred at high speed. The combination of several pixels into one 32-bit value is called packed pixels.
The correlation between CPU register and VRAM values with pixels on screen according to each color depth (bits per pixel) is shown in diagrams I-4-8, I-4-9, and I-4-10.
In summary, the order difference of the bits produced by register and memory transfers is corrected at display time.
[diagram I-4-8]
[diagram I-4-9]
[diagram I-4-10]
The FM TOWNS' 512KB of VRAM can be arranged in many different ways. Their addressing changes according to the screen modes used.
The VRAM address arrangement for each virtual screen format is shown in diagrams I-4-11, I-4-12, I-4-13, I-4-14, I-4-15, and I-4-16.
With four bits per pixel, the CPU can access eight pixels at once. VRAM addresses start from 0x8000_0000. Screen layer 0 can select page 0 or 1, and screen layer 1 can select page 2 or 3.
[diagram I-4-11]
With four bits per pixel, the CPU can access eight pixels at once. VRAM addresses start from 0x8000_0000. Pages 0 and 1 correspond to screen layers 0 and 1.
[diagram I-4-12]
With eight bits per pixel, the CPU can access four pixels at once. VRAM addresses start from 0x8010_0000. Only one screen is provided.
[diagram I-4-13]
With 16 bits per pixel, the CPU can access two pixels at once. VRAM addresses start from 0x8010_0000. Only one screen is provided.
[diagram I-4-14]
With 16 bits per pixel, the CPU can access two pixels at once. VRAM addresses start from 0x8000_0000. Pages 0 and 1 correspond to screen layers 0 and 1.
[diagram I-4-15]
[diagram I-4-16]
The following registers are related to VRAM read/write control:
- Packed pixel mask registers
- Mix register
- Graphics VRAM update mode register
- Graphics VRAM page select register
Of these, the latter three registers are related to FMR-50 compatibility mode, so are described in "4.9: FMR compatible screen display functionality". Here, we only describe the packed pixel mask registers.
The packed pixel mask registers (table I-4-4) are used to mask bit positions when VRAM is written to from the CPU. Each bit of these registers corresponds to the VRAM pixel bit layout and indicates whether the corresponding bit is masked (prevented from being written) or not. Masked bits are set to 0, and writable bits are set to 1. To write to one of these registers, the register's address is written to the VRAM access controller I/O register (table I-4-5) at I/O address 0x0458, and then the low and high byte of the mask data are written to addresses 0x045A and 0x045B respectively.
| Register number | Register name | Size |
|---|---|---|
| 0 0 | Packed pixel mask register 0 (low word) | W |
| 0 1 | Packed pixel mask register 1 (high word) | W |
- The selected bits become the target for writes during 8/16/32 bit packed pixel accesses. - 0: Masked (not written) - 1: Unmasked (written)
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0458 | Address register | R | undefined | RA1 | RA0 | |||||
| W | 0 | 0 | 0 | 0 | 0 | 0 | ||||
| 0x045A | Data register (low) | R/W | RD7 | RD6 | RD5 | RD4 | RD3 | RD2 | RD1 | RD0 |
| 0x045B | Data register (high) | R/W | RD15 | RD14 | RD13 | RD12 | RD11 | RD10 | RD9 | RD8 |
On the FM TOWNS, a virtual screen can be scrolled in order to move its displayed area. In addition to cylindrical scrolling, spherical scrolling is also possible. In this section, we describe the scrolling concept. In order to configure scrolling, there are registers for setting the display address. Please see "4.7.4: CRTC internal registers" for details.
When a typical computer text screen is completely filled with text, the entire screen will be pushed upward one line before showing the next line, removing the topmost line from display. This is called vertical scrolling.
In this situation, the memory for the top and bottom of the screen being scrolled may not be connected, but by logically connecting them, the data can appear on screen as if it is continuous. This is called cylindrical scrolling (diagrams I-4-17 and I-4-18).
On the FM TOWNS, the part of the virtual screen that is shown on the display (visible screen) is formed by cylindrical scrolling (except in the 640x400 pixel virtual screen mode).
[diagram I-4-17]
[diagram I-4-18]
The CRTC (CRT display controller) displays the screen by reading out the contents of VRAM. It implements vertical scrolling by incrementing the start address in the Y axis (vertical) direction such that when the address value reaches the lowest line (binary ...111), adding 1 while ignoring the carry makes the VRAM address in the vertical direction become zero, indicating the top of VRAM. This is the principle behind cylindrical scrolling (diagram I-4-19).
Furthermore, the FM TOWNS virtual screen also has an extent in the X axis (horizontal) direction, so even with only cylindrical scrolling, the visible screen can be horizontally scrolled within that extent.
Under cylindrical scrolling, horizontal scrolling has limitations, but if the address of both edges in the horizontal direction is also made continuous, then continuous scrolling becomes possible in all directions, which is called spherical scrolling (diagram I-4-20).
Spherical scrolling is possible in 512x256 pixel virtual screen modes.
Spherical scrolling works by incrementing the VRAM address in the X axis (horizontal) direction in the same manner as described above for the Y axis under cylindrical scrolling, so that continuous scrolling becomes possible in all directions (diagram I-4-21).
Using the FM TOWNS' palette functionality, either 256 out of 16.77 million colors or 16 out of 4,096 colors can be displayed. In this section, we describe how to use the palette.
On the FM TOWNS, there are situations when displaying colors where the palette is and isn't used.
When the palette is not used, 32,768 colors can be displayed at the same time. In this case, one pixel's data in the virtual screen corresponds 1:1 with 16 bits of VRAM data, so a color is displayed from every 16 bits of VRAM data.
When the palette is used, either 256 colors out of 16.77 million (RGB 8 bit) or 16 colors out of 4,096 can be displayed.
If, for example, 256 out of 16.77 million color display is being used, a memory region with room to store 256 colors needs to be provided. This is called the analog palette table. Each palette entry has 24 bits of storage, storing 8 bits each for red, green, and blue (giving 16.77 million total colors).
At display time, what is specified is not colors in and of themselves, but indices into this palette (0-255). This index is called a palette code. Therefore, while using a palette, the data stored in VRAM does not itself contain color numbers, but these palette codes.
A palette table is a memory region that stores a palette's color data. The FM TOWNS has an analog palette, used for the native FM TOWNS bitmap display, and a digital palette, used for FMR-50 compatibility. Here we describe how to use the analog palette. The digital palette registers are explained in "4.9.3: Setting the FMR-50 compatibility palette".
There are two types of analog palette, a 256-color palette which holds 256 colors chosen out of 16.77 million colors, or a 16-color palette which holds 16 colors chosen out of 4,096 colors.
Reading from and writing to the analog palette is performed through the analog palette registers (table I-4-6).
These registers handle both 256- and 16-color palettes. In order to read from or write to a color in the analog palette, there is an analog palette register for each of the analog palette code (the value written to VRAM), blue, red, and green values. Diagram I-4-22 shows the connection between the registers and the palette.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0xFD90 | Address register | R/W | P7* | P6* | P5* | P4* | P3 | P2 | P1 | P0 |
| 0xFD92 | Blue palette data | R/W | BL7 | BL6 | BL5 | BL4 | BL3* | BL2* | BL1* | BL0* |
| 0xFD94 | Red palette data | R/W | RL7 | RL6 | RL5 | RL4 | RL3* | RL2* | RL1* | RL0* |
| 0xFD96 | Green palette data | R/W | GL7 | GL6 | GL5 | GL4 | GL3* | GL2* | GL1* | GL0* |
- * When the PLT1 bit of the video output control register (0x0448/0x044A register #01) is 0, the marked bits are 0 on write, undefined on read. When the PLT1 bit is 1, all bits are readable and writable.
Diagram I-4-23 further illustrates the process of converting an analog palette code into a color to be displayed.
PLT1 in this diagram refers to the palette select bit from the priority register (described later in table I-4-36). If PLT1 = 1, then the 256-color palette is referenced, or if PLT1 = 0, then the 16-color palette is referenced.
[diagram I-4-22]
[diagram I-4-23]
When both screen layers use a 16 color palette, the composed image can display a maximum of 31 colors (counting all of each palettes' codes, minus one transparent color).
In this section, we describe the high-speed display and movement system for sprites.
Table I-4-7 shows the specifications for the FM TOWNS' sprites.
The size of one sprite pattern is 16x16 pixels, which is small, but larger patterns can be made by grouping many sprites together.
The sprite pattern can also be transformed while being rendered. This is performed rapidly by hardware.
| Item | Specification |
|---|---|
| Size | 16x16 pixels |
| Number of sprites that can be shown | 1024 |
| Number of colors that can be used | 32,768, or 16 out of 32,768 colors (each pixel position) |
| Number of pattern definitions | Maximum 896 (when only using 16-color sprites) 224 (when only using 32,768-color sprites) |
| Pattern overlap | Priority ordering possible |
| Render-time pattern transformations | Rotation (0, 90, 180, 270 degrees) Horizontal reflection Shrinking (independent horizontal and vertical 1x or 1/2x) |
When rendering sprites, the character data is not directly written to VRAM.
To prepare to render sprites, sprite patterns (their colors and shapes) are first defined in sprite memory (up to a maximum of 896 patterns). Afterward, each sprite (up to a maximum of 1024 sprites) is defined by its pattern number, display position, and whether it has any render-time transformations applied.
At render time, the hardware reads each sprite's data according to its sprite number (index number), which is then transferred to VRAM. Diagram I-4-24 illustrates the operation of sprite rendering.
VRAM page 1 (screen layer 1) of the 256x512 pixel virtual screen mode is used when rendering sprites. The page is divided into two 256x256 pixel parts, with each part alternatingly used as the sprite rendering buffer (double buffering). VRAM page 0 can be used as a background, in either a 256x512 or 512x256 virtual screen mode.
Diagram I-4-25 shows the connection between sprite rendering and double buffering. Specifically, while the contents of sprite pattern memory are being transferred to one buffer, the other buffer is displayed; when the transfer is done, the buffers are exchanged, and the newly-rendered buffer is displayed. This process then repeats.
If single-buffered rendering were performed, then data transfers would happen while the same data is being displayed, causing unsightly noise and flickering on the screen. Although data transfer could be forbidden during screen display (scan) in order to avoid this, having data transfer wait until the scan ends (blanking period) would make sprite rendering slower. Using double buffering enables high-speed, noise-free sprite rendering.
Note that page 1 (screen layer 1), to which sprites are rendered, must be set to the highest display priority.
[diagram I-4-24]
[diagram I-4-25]
Here, we explain the structure and operation of sprite pattern memory.
Sprite pattern memory, as shown in diagram I-4-26, is divided into three regions.
[diagram I-4-26]
For each sprite, its display position, pattern (shape and colors), attributes, color table number (palette colors), and other management information is stored. The index region has enough space to store information for 1,024 sprites (8 bytes per sprite). The 1,024 sprites are numbered from 0 to 1,023; this is called the index number. Higher index numbers are processed earlier, so when sprites overlap, the later-processed sprites remain and also get shown.
16-color sprites use colors from one of the color tables defined in this region, as set for the sprite in the index region.
The patterns in this region define the color of each pixel in a sprite.
Table I-4-8 shows the structure of the index region.
| Index number | Word 0 | Word 1 | Word 2 | Word 3 |
|---|---|---|---|---|
| #0 | X address (16 bit) |
Y address (16 bit) |
Attributes (16 bit) |
Color table index (16 bit) |
| #1 | X address (16 bit) |
Y address (16 bit) |
Attributes (16 bit) |
Color table index (16 bit) |
| #2 | X address (16 bit) |
Y address (16 bit) |
Attributes (16 bit) |
Color table index (16 bit) |
| ⋮ | ⋮ | ⋮ | ⋮ | ⋮ |
| #1022 | X address (16 bit) |
Y address (16 bit) |
Attributes (16 bit) |
Color table index (16 bit) |
| #1023 | X address (16 bit) |
Y address (16 bit) |
Attributes (16 bit) |
Color table index (16 bit) |
The index region's contents are stored as described below.
The structure of the coordinate address bits is as described in tables I-4-9 and I-4-10. The sprite's display coordinates are set here. These coordinates define the position of the sprite pattern's upper-left corner within the sprite coordinate space (ranged from 0-511 in both the X and Y directions).
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPX8 | SPX7 | SPX6 | SPX5 | SPX4 | SPX3 | SPX2 | SPX1 | SPX0 | |||||||
- SPX0-8 (bit 0-8): Indicates the sprite's address in the X direction.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPY8 | SPY7 | SPY6 | SPY5 | SPY4 | SPY3 | SPY2 | SPY1 | SPY0 | |||||||
- SPY0-8 (bit 0-8): Indicates the sprite's address in the Y direction.
The structure of the attribute bits is as described in table I-4-11.
In addition to selecting the sprite pattern, the attributes set whether render-time shrinking (in horizontal and/or vertical directions), rotation, and/or horizontal reflection are applied, as well as whether the offset address is added. Please see "4.6.9: Sprite I/O control" regarding the offset address.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFS | ROT2 | ROT1 | ROT0 | SUY | SUX | PAT9 | PAT8 | PAT7 | PAT6 | PAT5 | PAT4 | PAT3 | PAT2 | PAT1 | PAT0 |
- OFFS (bit 15): Whether to use the offset address.
- 0: No offset
- 1: Offset
- ROT0-2 (bit 12-14): Rotation/horizontal reflection.
- 000: 0 degrees, no reflection (F)
- 001: 180 degrees, reflection (F)
- 010: 0 degrees, reflection (F)
- 011: 180 degrees, no reflection (F)
- 100: 270 degrees, reflection (F)
- 101: 270 degrees, no reflection (F)
- 110: 90 degrees, no reflection (F)
- 111: 90 degrees, reflection (F)
- SUY (bit 11): Vertical shrinkage.
- 0: Normal size
- 1: 1/2 size
- SUX (bit 10): Horizontal shrinkage.
- 0: Normal size
- 1: 1/2 size
- PAT0-9 (bit 0-9): Pattern number. Between 128-1023.
Along with selecting whether the sprite is 16-color or 32,768-color, for 16-color sprites, this field selects which 16-color grouping (color table) to use for the sprite.
The structure of the color table number bits is as described in table I-4-12. A color grouping from the color table region is chosen from the range 256-511. The highest bit CTEN determines whether the color table is referenced or not; in other words, it determines whether the sprite has 16 or 32,768 colors.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CTEN | SPYS | DISP | COL11 | COL10 | COL9 | COL8 | COL7 | COL6 | COL5 | COL4 | COL3 | COL2 | COL1 | COL0 |
- CTEN (bit 15): Whether to reference the color table.
- 0: No color table (32,768 colors)
- 1: Color table (16 colors)
- SPYS (bit 14): Sprite superimpose bit.
- 0: Normal display
- 1: Superimpose
- DISP (bit 13): Sprite display flag.
- 0: Display
- 1: Do not display
- COL0-11 (bit 0-11): Color table number 256-511 (setting other values is forbidden).
The pattern region can store a mix of 16-color and 32,768-color pattern data.
Since storing the sprite pattern for one 16-color sprite takes 4 bits of memory per sprite pixel, 16*16*4/8 = 128 bytes of memory per sprite are necessary. The entire pattern region is 112KB (114,688 bytes), so when using only 16-color sprites, it can store 114,688/128 = 896 patterns.
The pattern region is divided into 896 blocks of 128 bytes, and one of 896 pattern data entries is stored in each respective block. The pattern indices used to refer to each pattern are not 0 through 895; they are 128 through 1,023. Since the part of sprite memory from the base up to the 16KB point (corresponding to 128 patterns) contains the index region and color table region, using these values as pattern indexes makes it convenient to compute an index relative to the beginning of sprite memory.
Using only 32,768-color sprites can be considered in a similar manner.
In this situation, there are 16 bits per pixel, so in order to store one sprite pattern, 512 bytes become necessary. Therefore, 224 patterns can be stored. These patterns are indexed from 128-1020 (using every fourth value).
The indices corresponding to each kind of pattern are as shown in table I-4-13.
| 16-color sprite | 32,768-color sprite |
| #128 | #128 |
| #129 | |
| #130 | |
| #131 | |
| #132 | #132 |
| #133 | |
| #134 | |
| #135 | |
| #136 | #136 |
| #137 | |
| #138 | |
| #139 | |
| ⋮ | ⋮ |
| #1020 | #1020 |
| #1021 | |
| #1022 | |
| #1023 |
Both kinds of sprite use the same memory region for patterns. When assigning pattern indices while combining both kinds, please be careful not to reuse the same memory. For reference, table I-4-14 shows examples of how many of each kind of pattern there can be when mixing both kinds of sprites.
Additionally, in the pattern region, patterns are stored starting from the top line followed by the lines below in order (diagram I-4-27).
| 32,768 color pattern count | 16 color pattern count | Total pattern count |
|---|---|---|
| 224 | 0 | 224 |
| 192 | 128 | 320 |
| 160 | 256 | 416 |
| 128 | 384 | 512 |
| 96 | 512 | 608 |
| 64 | 640 | 704 |
| 0 | 896 | 896 |
[diagram I-4-27]
16-color sprites use 16 selected out of 32,768 colors. In the color table, 256 groups of 16 colors each can be defined.
In order to store one group of 16 colors, 16 bits (32,768 colors) * 16 items / 8 = 32 bytes of memory are necessary, so storing 256 groups uses 8KB of memory.
Each of the 256 color groups is distinguished by an index (256-511). This is called the color table index. By assigning the numbers this way instead of using 0-255, computing the start address corresponding to a color table can be done by adding n*32 bytes (n being 256-511, the color table indices) to the beginning of sprite memory.
For example, to find color table number 256's start address, 256 * 32 = 8,192.
One group in the color table, as shown in diagram I-4-28, is stored as 16 color values, each using 16 bits (32,768 colors) of data.
How each 16-color index is converted into an physical color table address is shown in diagram I-4-29. The low 11 bits of the color table index from the index region indicate the start address within the color table region.
[diagram I-4-28]
[diagram I-4-29]
For sprite rendering, page 1 of the 256x512 pixel virtual display is divided into two parts, making the visible space 256x256 pixels. However, this space is narrower than the sprite's whole movement space. As shown in diagram I-4-30, the sprites' logical coordinate space has an extent of 512x512 pixels, so the coordinates in sprite memory's attribute region can be set to a value between 0 and 511. However, only the shaded area is used in actuality when a sprite is being rendered. The remaining area exists as logical space, but is physically meaningless. On the other hand, just by changing a sprite's logical position within this coordinate space, sprites can be partially or completely hidden. Futhermore, as shown in diagram I-4-31, within the 512x512 pixel coordinate space, sprite images move in the same manner as the screen's spherical scrolling.
[diagram I-4-30]
[diagram I-4-31]
The 1,024 sprites are handled in order of ascending index number. For this reason, when rendered sprites are made to overlap, the sprite with the lesser index number is rendered in the background (diagram I-4-32). However, smaller-indexed sprites' pixels can still show through by using masking.
The top bit of the 16 bits for each pixel in the pattern region is used for masking. A pixel with this bit set to 1 is interpreted as transparent so that pixels from lower-indexed sprites will be visible underneath it.
When all four bits for a pixel are zero, the pixel is interpreted as transparent, and pixels from lower-indexed sprites will be visible underneath it.
The sprite I/O controller manages sprites. The sprite I/O controller has internal registers as shown in table I-4-15. These internal registers are indirectly accessed via the sprite controller I/O register (table I-4-16). In order to write to an internal register, first write the register number to I/O address 0x0450, then write the value to address 0x0452.
| Register number | Register name | Word/Byte |
|---|---|---|
| 0 | Control register 0 | B |
| 1 | Control register 1 | B |
| 2 | Horizontal offset register 0 | B |
| 3 | Horizontal offset register 1 | B |
| 4 | Vertical offset register 0 | B |
| 5 | Vertical offset register 1 | B |
| 6 | Display page control register | B |
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0450 | Address register | R | undefined | RA2 | RA1 | RA0 | ||||
| W | 0 | 0 | 0 | 0 | 0 | |||||
| 0x0452 | Data register | R/W | RD7 | RD6 | RD5 | RD4 | RD3 | RD2 | RD1 | RD0 |
The ten bits IND0-9 in control registers 0 and 1 (table I-4-17) set the two's complement of the number of sprites to process. For example, in case it is desired to display only one sprite, the index number #1023 is set by storing the value 0x3FF to IND0-9 in the registers.
The SPEN bit sets whether sprite transfer (from sprite pattern memory to VRAM) occurs.
| Register number | Contents | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Control register 0 | IND7 | IND6 | IND5 | IND4 | IND3 | IND2 | IND1 | IND0 |
| 1 | Control register 1 | SPEN | IND9 | IND8 | |||||
-
SPEN (bit 7): Selects whether to perform sprite pattern transfer.
- 0: Sprite pattern transfer is disabled
- 1: Sprite pattern transfer is enabled
(Sprite pattern transfer is disabled at reset time.)
-
IND0-9: Sets the two's complement of the number of sprites to handle. (if set to 0, all 1,024 sprites are handled)
The horizontal and vertical offset registers 0 and 1 (table I-4-18) set an offset for the sprite display coordinates. The index region of sprite memory sets the coordinate values for each sprite, and this offset value further offsets the display position for every sprite that references it.
The nine bits OY0-8 set the offset in the vertical direction, and the nine bits OX0-9 set the offset in the horizontal direction.
The addition of this offset value is only performed on sprites whose OFFS value has a value of 1 in their index region attributes. The offset value is added to the coordinate values from the index region as shown in diagram I-4-33.
If the addition result overflows bit 8, the carry is ignored, so even if large values are added, the display coordinates stay in the range 0-511, and the sprite group moves in the manner of spherical scrolling.
| Register number | Contents | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 2 | Horizontal offset register 0 | OX7 | OX6 | OX5 | OX4 | OX3 | OX2 | OX1 | OX0 |
| 3 | Horizontal offset register 1 | OX8 | |||||||
| 4 | Vertical offset register 0 | OY7 | OY6 | OY5 | OY4 | OY3 | OY2 | OY1 | OY0 |
| 5 | Vertical offset register 1 | OY8 | |||||||
- The horizontal and vertical offset values both consist of nine bits.
[diagram I-4-33]
In the display page control register (table I-4-19), only the DP1 bit has meaning.
Sprites use VRAM screen layer 1 as a double buffer, and at any point in time, one or the other buffer is displayed. DP1 indicates which one to display when sprites are stopped.
Writing to this register selects which page to display, as shown in diagram I-4-34. When DP1 is written with zero, as in the diagram, then page 0 is shown, and when DP1 is written with one, then page 1 is shown. To write this bit, it is necessary to configure the CRTC so that VRAM page 0 is displayed and set the SPEN bit in the aforementioned control register 1 (table I-4-17) to zero (no transfer) in order to stop sprite pattern transfer. Note that the display page control register has no meaning outside of the 256x512 pixel virtual screen mode used by sprites. DP1 must always be set to 0 in those other modes.
Please note that here we refer to the first half of the double buffer (VRAM screen layer 1) as page 0, and the second half as page 1.
| Register number | Contents | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 6 | Display page control register | R | 0 | 0 | 0 | DP1 | 0 | 0 | 0 | 0 |
| W | DP1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
- DP1: Selects the page to display.
- 0: Page 0
- 1: Page 1
[diagram I-4-34]
The CRTC (cathode ray tube controller) is a video display controller IC.
In this section, we describe the CRTC and related hardware.
Diagram I-4-35 gives an overview of the CRTC and related hardware.
The CRTC performs the essential role of displaying VRAM data on a monitor. Writing to the CRTC registers controls things like display timing. Whatever data is written to VRAM, the CRTC registers must be set to suitable values for correct display to be possible.
In the vicinity of the CRTC, the video output control registers also provide additional controls.
[diagram I-4-35]
Before describing how to control the screen using the CRTC, we provide some background knowledge about the operation of a cathode ray tube display.
The display method used by the cathode ray tubes in computers and television displays is called raster scan.
If you caught a cathode ray tube's operation at an instant in time, actual light emission would only come from one point. This point is called the spot.
The spot moves horizontally, forming a raster (also called an emission line or scanline). The raster then moves from the top of the screen downward, and when it reaches the bottom, the operation repeats again from the top. This operation is called a scan (diagram I-4-36).
A screen is composed of rasters from the top of the screen to the bottom, but if the screen display frequency is too low, then flickering would become apparent, making eye exhaustion likely. On the other hand, increasing the display frequency requires increasing the rate of data processing, necessitating higher-speed hardware.
In the television broadcast standard, one screen is made of 486 scanlines, and the screen must be drawn 30 times per second. However, since this drawing speed would feel flickery, a technique is used to reduce flickering: every time the screen is drawn, the odd and even rasters (243 each) are separated, and alternatingly drawn 60 times per second. This is called interlacing.
The number of scanlines in a computer screen differs depending on things like the model and display mode. On the FM TOWNS, the number of scanlines is determined by the chosen vertical resolution.
Interlacing, as previously mentioned, is generally used for television, but can also be used for the FM TOWNS display. Diagram I-4-37 shows the interlaced raster drawing method used by a television.
As shown in this diagram, the horizontal display time for both the final odd raster and the first even raster is halved. For that reason, a pulse needs to be inserted at half the horizontal sync interval in place of the horizontal sync signal in order to get the timing right. This is called the equalization pulse. The timing for the equalization pulse is set using the vertical sync setting register.
When displaying an image on a CRT, aside from the video signal, horizontal and vertical sync signals are necessary to establish the horizontal and vertical scan timing.
[diagram I-4-36]
[diagram I-4-37]
The horizontal sync signal indicates the start of each scanline. The display equipment references this signal to stop the current horizontal scan and returns the spot to the left edge of the screen. The time period between horizontal sync pulses is determined by the horizontal frequency, and the amount of time needed for the sync is called the horizontal sync interval.
Furthermore, the vertical sync signal indicates the start of each screen scan. The display equipment references this signal to stop vertical scan and return the spot to the top position. The time between vertical syncs is the horizontal interval, multiplied by the number of scanlines, plus the vertical sync time interval, which is the amount of time the spot takes to return to the top of the screen. During the vertical sync time interval, some number of horizontal scans occur. There is no screen output during this time interval, but the horizontal sync signal continues to be output. This allows the horizontal sync signal to be stopped once and re-synchronize to the side of the screen in a short amount of time.
On the FM TOWNS, 15.73KHz, 24.37KHz, or 31.47KHz horizontal frequencies can be selected.
Underscan is when the extent of the display area is smaller than the monitor, and overscan is when part of the display area overflows the monitor and cannot be displayed. The difference is caused by the relationship between the number of scanlines and the display resolution.
Let's describe examples of both situations. First, in screen mode 1 (640x400 pixels), the number of scanlines on the FM TOWNS monitor is set to 440 (with 432 actually- visible scanlines). Since only 400 out of those 432 scanlines are used, underscan occurs.
Alternatively, in screen mode 11 (320x240 pixels), the number of screen scanlines is set to 262 (with 216 actually-visible scanlines). Not all lines can be shown on the screen, so overscan occurs.
By writing to the CRTC's internal registers, the following display-related settings can be configured:
- Horizontal and vertical sync period
- Visible screen size
- Actual display address in VRAM
- Scrolling
- Magnified display
- Virtual display type
- Color depth
Of these, the most essential is display VRAM address generation. The CRTC updates its VRAM address alongside the display scan.
Inside of the CRTC are many internal registers which manage screen display, listed in table I-4-20.
These registers can be individually set to independent values, but if all 32 registers aren't set to suitable values that work together perfectly, screen display can go out of control. For that reason, tables I-4-21 and I-4-22 give an overview of the screen modes with matching sets of standard settings for each CRTC register. In these tables, a register set number refers to a group of setting values for the registers. Table I-4-23 shows the register set numbers and their associated register values. Please note that the register setting values are different when using two screen modes at once.
Table I-4-23 also includes values for the video output registers. Please see "4.8: Video output controller related registers" for information regarding these.
Different register values also have to be used in order to perform superimpose and/or digitization. Please see "4.11: Video card" for information regarding these settings.
| Register number | Abbr. title | Register name | Purpose | Size |
| 00 | HSW1 | Horizontal sync width 1 | Sets horizontal sync signal | W |
| 01 | HSW2 | Horizontal sync width 2 | W | |
| 02 | reserved | |||
| 03 | reserved | |||
| 04 | HST | Horizontal sync time period | Sets horizontal sync period | W |
| 05 | VST1 | Vertical sync timing 1 | Sets vertical sync signal timing | W |
| 06 | VST2 | Vertical sync timing 2 | W | |
| 07 | EET | Equalization pulse effective time period | Sets equalization pulse waveform | W |
| 08 | VST | Vertical sync time period | Sets vertical sync period | W |
| 09 | HDS0 | Horizontal display start position 0 | Sets screen layer 0 horizontal display position | W |
| 0A | HDE0 | Horizontal display end position 0 | W | |
| 0B | HDS1 | Horizontal display start position 1 | Sets screen layer 1 horizontal display position | W |
| 0C | HDE1 | Horizontal display end position 1 | W | |
| 0D | VDS0 | Vertical display start position 0 | Sets screen layer 0 vertical display position | W |
| 0E | VDE0 | Vertical display end position 0 | W | |
| 0F | VDS1 | Vertical display start position 1 | Sets screen layer 1 vertical display position | W |
| 10 | VDE1 | Vertical display end position 1 | W | |
| 11 | FA0 | Frame start address 0 | Sets screen layer 0 scroll | W |
| 12 | HAJ0 | Horizontal adjust 0 | W | |
| 13 | FO0 | Field interval address offset 0 | Sets screen layer 0 interlace display | W |
| 14 | LO0 | Line interval address offset 0 | W | |
| 15 | FA1 | Frame start address 1 | Sets screen layer 1 scroll | W |
| 16 | HAJ1 | Horizontal adjust 1 | W | |
| 17 | FO1 | Field interval address offset 1 | Sets screen layer 1 interlace display | W |
| 18 | LO1 | Line interval address offset 1 | W | |
| 19 | EHAJ | External sync horizontal adjust | Sets position relative to external sync | W |
| 1A | EVAJ | External sync vertical adjust | W | |
| 1B | ZOOM | Horizontal and vertical zoom | Sets horizontal and vertical zoom ratio | W |
| 1C | CR0 | Control register 0 | Various controls | W |
| 1D | CR1 | Control register 1 | W | |
| 1E | FR | Dummy register | Dummy register | W |
| 1F | CR2 | Control register 2 | Vertical sync signal separation circuit register | W |
| Screen mode | Register set number |
|---|---|
| 12 | 1 |
| 15 | 4 |
| 17 | 31 |
| 13 | 2 |
| 14 | 3 |
| 16 | 5 |
| 18 | 32 |
| Screen layer 0 | ||||||||||||
| Screen layer 1 | Mode | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
| 1 | 6 | |||||||||||
| 2 | 8 | |||||||||||
| 3 | 9 | 19 | 27 | |||||||||
| 4 | R50 | 10 | 11 | |||||||||
| 5 | 22 | 20 | 29 | |||||||||
| 6 | 23 | 16 | ||||||||||
| 7 | 17 | 24 | ||||||||||
| 8 | 18 | 25 | ||||||||||
| 9 | 13 | 12 | ||||||||||
| 10 | 26 | 30 | 28 | |||||||||
| 11 | 15 | 14 | ||||||||||
| Register address | Register name | Register set number | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | R50 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 00 | HSW1 | 0060 | 0040 | 0086 | 0060 | 0074 | 0040 | unused reserved | 0040 | 0060 | 0040 | 0040 | 0086 | 0086 | 0074 | 0074 | 0040 | 0086 | 0074 | 0060 | 0060 | unused reserved | 0060 | 0040 | 0086 | 0074 | 0060 | 0060 | 0060 | 0060 | 0060 | 0060 | 0074 | 0040 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 01 | HSW2 | 02C0 | 0320 | 0610 | 02C0 | 0530 | 0320 | 0320 | 02C0 | 0320 | 0320 | 0610 | 0610 | 0530 | 0530 | 0320 | 0610 | 0530 | 02C0 | 02C0 | 02C0 | 0320 | 0610 | 0530 | 02C0 | 02C0 | 02C0 | 02C0 | 02C0 | 02C0 | 0530 | 0320 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 02 | ---- | ---- | ---- | ---- | ---- | ---- | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 03 | ---- | ---- | ---- | ---- | ---- | ---- | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 04 | HST | 031F | 035F | 071B | 031F | 0617 | 035F | 035F | 031F | 035F | 035F | 071B | 071B | 0617 | 0617 | 035F | 071B | 0617 | 031F | 031F | 031F | 035F | 071B | 0617 | 031F | 031F | 031F | 031F | 031F | 031F | 0617 | 035F | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 05 | VST1 | 0000 | 0000 | 0006 | 0000 | 0006 | 0000 | 0000 | 0000 | 0000 | 0000 | 0006 | 0006 | 0006 | 0006 | 0000 | 0006 | 0006 | 0000 | 0000 | 0000 | 0000 | 0006 | 0006 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0006 | 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 06 | VST2 | 0004 | 0010 | 000C | 0004 | 000C | 0010 | 0010 | 0004 | 0010 | 0010 | 000C | 000C | 000C | 000C | 0010 | 000C | 000C | 0004 | 0004 | 0004 | 0010 | 000C | 000C | 0004 | 0004 | 0004 | 0004 | 0004 | 0004 | 000C | 0010 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 07 | EET | 0000 | 0000 | 0012 | 0000 | 0012 | 0000 | 0000 | 0000 | 0000 | 0000 | 0012 | 0012 | 0012 | 0012 | 0000 | 0012 | 0012 | 0000 | 0000 | 0000 | 0000 | 0012 | 0012 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0012 | 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 08 | VST | 0419 | 036F | 020C | 0419 | 020C | 036F | 036F | 0419 | 036F | 036F | 020C | 020C | 0208 | 020B | 036F | 020C | 020B | 0419 | 0419 | 0419 | 036F | 020C | 020B | 0419 | 0419 | 0419 | 0419 | 0419 | 0419 | 020C | 036F | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 09 | HDS0 | 008A | 009C | 0129 | 008A | 00E7 | 009C | 009C | 008A | 009C | 009C | 0129 | 0129 | 00E7 | 00E7 | 009C | 0129 | 00E7 | 008A | 008A | 008A | 009C | 0129 | 00E7 | 008A | 008A | 008A | 008A | 008A | 00CA | 0167 | 009C | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0A | HDE0 | 030A | 031C | 06C9 | 030A | 05E7 | 031C | 031C | 030A | 031C | 019C | 06C9 | 0529 | 05E7 | 04E7 | 019C | 0529 | 04E7 | 018A | 018A | 030A | 031C | 06C9 | 05E7 | 030A | 01CA | 01CA | 01CA | 01CA | 02CA | 0567 | 031C | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0B | HDS1 | 008A | 009C | 0129 | 008A | 00E7 | 009C | 009C | 008A | 009C | 009C | 0129 | 0129 | 00E7 | 00E7 | 009C | 0129 | 00E7 | 008A | 008A | 008A | 009C | 0129 | 00E7 | 008A | 008A | 008A | 008A | 008A | 00CA | 0167 | 009C | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0C | HDE1 | 030A | 031C | 06C9 | 030A | 05E7 | 031C | 031C | 030A | 031C | 031C | 06C9 | 06C9 | 05E7 | 05E7 | 019C | 0529 | 04E7 | 030A | 018A | 018A | 019C | 0529 | 04E7 | 01CA | 030A | 01CA | 018A | 018A | 02CA | 0567 | 031C | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0D | VDS0 | 0046 | 0040 | 002A | 0046 | 002A | 0040 | 0040 | 0046 | 0040 | 0040 | 002A | 002A | 002A | 002A | 0040 | 002A | 002A | 0046 | 0046 | 0046 | 0040 | 002A | 002A | 0046 | 0046 | 0046 | 0046 | 0046 | 0046 | 002A | 0040 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0E | VDE0 | 0406 | 0360 | 020A | 0406 | 020A | 0360 | 0360 | 0406 | 0360 | 0240 | 020A | 020A | 020A | 020A | 0240 | 020A | 020A | 0246 | 0246 | 0406 | 0360 | 020A | 020A | 0406 | 0226 | 0226 | 0226 | 01E6 | 0406 | 020A | 0360 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0F | VDS1 | 0046 | 0040 | 002A | 0046 | 002A | 0040 | 0040 | 0046 | 0040 | 0040 | 002A | 002A | 002A | 002A | 0040 | 002A | 002A | 0046 | 0046 | 0046 | 0040 | 002A | 002A | 0046 | 0046 | 0046 | 0046 | 0046 | 0046 | 002A | 0040 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | VDE1 | 0406 | 0360 | 020A | 0406 | 020A | 0360 | 0360 | 0406 | 0360 | 0360 | 020A | 020A | 020A | 020A | 0240 | 020A | 020A | 0406 | 0246 | 0246 | 0240 | 020A | 020A | 0226 | 0406 | 0226 | 0246 | 0226 | 0406 | 020A | 0360 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | FA0 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | HAJ0 | 008A | 009C | 0129 | 008A | 00E7 | 009C | 009C | 008A | 009C | 009C | 0129 | 0129 | 00E7 | 00E7 | 009C | 0129 | 00E7 | 008A | 008A | 008A | 009C | 0129 | 00E7 | 008A | 008A | 008A | 008A | 008A | 00CA | 0167 | 009C | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | FO0 | 0000 | 0000 | 0080 | 0000 | 0080 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0080 | 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | LO0 | 0080 | 0080 | 0100 | 0080 | 0100 | 0050 | 0050 | 0080 | 0080 | 0080 | 0100 | 0080 | 0100 | 0080 | 0080 | 0080 | 0080 | 0080 | 0080 | 0080 | 0080 | 0100 | 0100 | 0080 | 0100 | 0100 | 0100 | 0080 | 0080 | 0100 | 0050 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | FA1 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | HAJ1 | 008A | 009C | 0129 | 008A | 00E7 | 009C | 009C | 008A | 009C | 009C | 0129 | 0129 | 00E7 | 00E7 | 009C | 0129 | 00E7 | 008A | 008A | 008A | 009C | 0129 | 00E7 | 008A | 008A | 008A | 008A | 008A | 00CA | 0167 | 009C | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | FO1 | 0000 | 0000 | 0080 | 0000 | 0080 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0080 | 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | LO1 | 0080 | 0080 | 0100 | 0080 | 0100 | 0050 | 0050 | 0080 | 0080 | 0080 | 0100 | 0100 | 0100 | 0100 | 0080 | 0080 | 0080 | 0080 | 0080 | 0080 | 0080 | 0080 | 0080 | 0100 | 0080 | 0100 | 0080 | 0100 | 0080 | 0100 | 0080 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | EHAJ | 0058 | 004A | 0064 | 0058 | 0056 | 004A | 004A | 0058 | 004A | 004A | 0064 | 0064 | 0056 | 0056 | 004A | 0064 | 0056 | 0058 | 0058 | 0058 | 004A | 0064 | 0056 | 0058 | 0058 | 0058 | 0058 | 0058 | 0058 | 0056 | 004A | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1A | EVAJ | 0001 | 0001 | 0007 | 0001 | 0007 | 0001 | 0001 | 0001 | 0001 | 0001 | 0007 | 0007 | 0007 | 0007 | 0001 | 0007 | 0007 | 0001 | 0001 | 0001 | 0001 | 0007 | 0007 | 0000 | 0000 | 0000 | 0000 | 0000 | 0001 | 0001 | 0001 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1B | ZOOM | 0000 | 0000 | 0101 | 0101 | 0303 | 0000 | 1010 | 0000 | 0000 | 0000 | 0303 | 0303 | 0303 | 0303 | 0000 | 0303 | 0303 | 0000 | 0000 | 0000 | 0000 | 0303 | 0303 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0101 | 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1C | CR0 | 000F | 000F | 000F | 000A | 000A | 003F | 003F | 000F | 000F | 000D | 0005 | 0005 | 0005 | 0005 | 0005 | 0005 | 0005 | 000D | 0005 | 0007 | 0007 | 0005 | 0005 | 0007 | 000D | 0005 | 0005 | 0005 | 000A | 000A | 001F | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1D | CR1 | 0002 | 0003 | 000C | 0002 | 0001 | 0003 | 0003 | 0002 | 0003 | 0003 | 000C | 000C | 0001 | 0001 | 0003 | 000C | 0001 | 0002 | 0002 | 0002 | 0003 | 000C | 0001 | 0002 | 0002 | 0002 | 0002 | 0002 | 0002 | 0001 | 0003 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1E | FR | 0000 | 0000 | 0003 | 0000 | 0002 | 0000 | 0000 | 0000 | 0000 | 0000 | 0003 | 0003 | 0002 | 0002 | 0000 | 0003 | 0002 | 0000 | 0000 | 0000 | 0000 | 0003 | 0002 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0002 | 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1F | CR2 | 0192 | 0150 | 01CA | 0192 | 0188 | 0150 | 0150 | 0192 | 0150 | 0150 | 01CA | 01CA | 0188 | 0188 | 0150 | 01CA | 0188 | 0192 | 0192 | 0192 | 0150 | 01CA | 0188 | 0192 | 0192 | 0192 | 0192 | 0192 | 0192 | 0188 | 0150 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| SHIFTER (video output control registers): | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 00 | CONTROL REGISTER | 0A | 0A | 0A | 0F | 0F | 15 | 15 | 15 | 15 | 17 | 1F | 1F | 1F | 1F | 1F | 1F | 1F | 17 | 1F | 1D | 1D | 1F | 1F | 1D | 17 | 1F | 1F | 1F | 0F | 0F | 15 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 01 | PRIORITY REGISTER | 18 | 18 | 18 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 08 | 09 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
- Things to note when using external sync:
- 32,768 color single layer mode:
- Superimpose: Screen layer 1 must be set to DISPLAY OFF. Superimpose does not occur if on.
- Digitizer: Screen layer 1 must be set to DISPLAY ON. Digitized data does not get written through if off.
- 256 color single layer mode:
- YS is always enabled and the setting cannot be changed.
- 32,768 color single layer mode:
Here, we explain the behavior of each CRTC internal register.
In order to read or write the CRTC's internal registers, the CRTC's I/O addresses are used (table I-4-24).
Address 0x0440 sets the internal register address to read from or write to, and then the data is written to addresses 0x0442-0x0443. The CRTC used by the FM TOWNS was designed with awareness of Intel CPUs, so reading from and writing to CRTC internal registers using word (16-bit) data transfer instructions is possible.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0440 | Address register | W | 0 | 0 | 0 | RA4 | RA3 | RA2 | RA1 | RA0 |
| 0x0442 | Data register (low) | W | RD7 | RD6 | RD5 | RD4 | RD3 | RD2 | RD1 | RD0 |
| 0x0443 | Data register (high) | W | RD15 | RD14 | RD13 | RD12 | RD11 | RD10 | RD9 | RD8 |
Table I-4-25 shows the formats of the registers related to sync signals.
| Register number | Register name | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 00 | Horizontal sync width register 1 | 0 | 0 | 0 | HSW1 | 0 | |||||||||||
| 01 | Horizontal sync width register 2 | 0 | 0 | 0 | HSW2 | 0 | |||||||||||
| 04 | Horizontal sync time period register | HST | 1 | ||||||||||||||
| 05 | Vertical sync timing register 1 | 0 | 0 | 0 | 0 | 0 | 0 | VST1 | |||||||||
| 06 | Vertical sync timing register 2 | 0 | 0 | 0 | 0 | 0 | 0 | VST2 | |||||||||
| 07 | Equalization pulse effective time period register | 0 | 0 | 0 | 0 | 0 | 0 | EET | |||||||||
| 08 | Vertical sync time period register | VST | |||||||||||||||
Diagram I-4-38 shows the relationship between the horizontal sync signal period and register values.
The entire period is set by the horizontal sync time period register (HST).
For the width of the horizontal sync signal, the emission line display period and the vertical sync period (the time in which the spot moves from the bottom to the top of the screen) are set separately.
In the display period, the horizontal sync signal width is set by the horizontal sync width 1 register (HSW1). In the vertical sync period, as shown in diagram I-4-39, since there is an ongoing vertical sync signal, the phase of the horizontal sync signal is reversed, so the horizontal sync width 2 register (HSW2) sets the width of the phase outside of the horizontal sync signal during this time.
The relation between these settings and horizontal timing is as follows:
- time = (HST + 1) * (main clock period)
- time = (HSW1) * (main clock period)
- time = (HSW2) * (main clock period)
The main clock is determined by the frequency setting in the CLKSEL field of control register 1 (table I-4-32), described below.
[diagram I-4-38]
[diagram I-4-39]
Diagram I-4-40 shows the relationship between the vertical sync signal period and register values.
The vertical sync period is set by the vertical sync time period register (VST).
The sync signal timing is set by the vertical sync timing registers 1 and 2 (VST1, VST2).
The equalization pulse effective time period register (EET) is responsible for stabilizing interlace operation.
The relationship between the vertical sync register values and vertical timing is as follows:
- time = (setting value) * (HST + 1) * (main clock period) / 2
[diagram I-4-40]
The display interval discussed here refers to settings that establish the display's timing and the physical extent of the display on screen.
Table I-4-26 lists the registers related to the display interval.
There are two groups of these registers, corresponding to the two screen layers.
Diagram I-4-41 shows the relationship between the horizontal display interval and the horizontal display start position (HDS0, HDS1) and horizontal display end position (HDE0, HDE1) registers.
The relationship between these registers' setting values and time is as follows:
- time = (setting value) * (main clock period)
Diagram I-4-42 shows the relationship between the vertical display interval and the vertical display start position (VDS0, VDS1) and vertical display end position (VDE0, VDE1) registers.
The relationship between these registers' setting values and time is as follows:
- time = (setting value) * (HST + 1) * (main clock period) / 2
| Register number | Register name | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 09 | Horizontal display start position register 0 | HDS0 | |||||||||||||||
| 0A | Horizontal display end position register 0 | HDE0 | |||||||||||||||
| 0B | Horizontal display start position register 1 | HDS1 | |||||||||||||||
| 0C | Horizontal display end position register 1 | HDE1 | |||||||||||||||
| 0D | Vertical display start position register 0 | VDS0 | |||||||||||||||
| 0E | Vertical display end position register 0 | VDE0 | |||||||||||||||
| 0F | Vertical display start position register 1 | VDS1 | |||||||||||||||
| 10 | Vertical display end position register 1 | VDE1 | |||||||||||||||
[diagram I-4-41]
[diagram I-4-42]
The display address related registers (table I-4-27) determine the virtual screen (VRAM) addresses whose data gets displayed to the screen.
There are also two groups of these registers, corresponding to the two screen layers.
The frame start address registers (FA0, FA1) are what determine what VRAM position is used for the upper left corner of the screen. These are set to an address relative to the start of VRAM.
Additionally, the horizontal adjust registers (HAJ0, HAJ1) establish the timing of the shift register (output time per pixel) by counting clocks. For concrete values, please see the standard settings table (table I-4-23).
The line interval address offset registers (LO0, LO1) determine the gap between successive lines' start addresses in interlace mode when skipping over the memory for skipped lines. The CRTC adds this value to the current line's start address to calculate the next line's start address.
Additionally, the field interval address offset registers (FO0, FO1) set the gap between field 0 and field 1's start address in interlace mode.
The screen is scrolled by adding or subtracting to the frame start address register. The number of pixels scrolled by adding or subtracting 1 to the register value is shown in table I-4-28.
| Register number | Register name | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 11 | Frame start address register 0 | FA0 | |||||||||||||||
| 12 | Horizontal adjust register 0 | HAJ0 | |||||||||||||||
| 13 | Field interval address offset register 0 | FO0 | |||||||||||||||
| 14 | Line interval address offset register 0 | LO0 | |||||||||||||||
| 15 | Frame start address register 1 | FA1 | |||||||||||||||
| 16 | Horizontal adjust register 1 | HAJ1 | |||||||||||||||
| 17 | Field interval address offset register 1 | FO1 | |||||||||||||||
| 18 | Line interval address offset register 1 | LO1 | |||||||||||||||
| Color depth | Single-layer mode | Double-layer mode |
|---|---|---|
| 32,768 | 4 pixels | 2 pixels |
| 256 | 8 pixels | --- |
| 16 | --- | 8 pixels |
The external horizontal adjust register (EHAJ) and external vertical adjust register (EVAJ) (table I-4-29) adjust the display timing between the external video signal and the computer screen while using the superimpose feature.
The external horizontal adjust register is set according to the selected clock frequency. The external vertical adjust register is typically set to 1 plus the value of the aforementioned vertical sync timing 1 register (VST1) (table I-4-25).
| Register number | Register name | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 19 | External sync horizontal adjust | EHAJ | |||||||||||||||
| 1A | External sync vertical adjust | EVAJ | |||||||||||||||
-
EHAJ is set according to the clock frequency as shown in the following table:
Clock (MHz) EHAJ 28.6363 0x0064 25.175 0x0058 24.5454 0x0056 21.0525 0x004A -
EVAJ is set to the VST1 value from register 05 plus one.
The horizontal and vertical zoom register (table I-4-30) is used to arbitrarily zoom the image. The register is set to the zoom ratio minus 1. For 1x, the register is set to 0.
| Register number | Register name | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1B | Horizontal and vertical zoom register | ZV1 | ZH1 | ZV0 | ZH0 | ||||||||||||
- ZV1 (bit 15-12): Screen layer 1 vertical zoom ratio.
- ZH1 (bit 11-8): Screen layer 1 horizontal zoom ratio.
- ZV0 (bit 7-4): Screen layer 0 vertical zoom ratio.
- ZH0 (bit 3-0): Screen layer 0 horizontal zoom ratio.
Control register 0 (table I-4-31) provides 2 groups of bits for each layer's possible settings.
START starts or stops display output.
ESYN selects whether to take the video sync signal from the external signal (during superimpose) or from the computer signal.
ESM0 and ESM1 determine whether superimpose mode or digitize mode is used. By default, superimpose mode is set, and video input is disabled.
CEN0 and CEN1 determine whether the VRAM address counter's low eight bits carry into the higher bits. When one of these bits is set to zero, cylindrical scrolling is performed for the corresponding layer. This bit should be zero outside of 640x400 pixel mode.
CL0 and CL1 set the color depth. The value to use corresponds to the number of screen layers. When one screen layer is used, CL1 should be set to the same value as CL0.
| Register number | Register name | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1C | Control register 0 | START | ESYN | ESM1 | ESM0 | CEN1 | CEN0 | CL1 | CL0 | ||||||||
-
START (bit 15): Start display. (Only this bit can be read.)
- 0: Stop display.
- 1: Start display.
-
ESYN (bit 14): Set external sync.
- 0: Computer screen.
- 1: External sync.
-
ESM1 (bit 7): Set screen layer 1 mode.
- 0: Superimpose mode.
- 1: Digitizer mode.
-
ESM0 (bit 6): Set screen layer 0 mode.
- 0: Superimpose mode.
- 1: Digitizer mode.
-
CEN1 (bit 5): Enable screen layer 1 counter carry.
- 0: Disable.
- 1: Enable.
-
CEN0 (bit 4): Enable screen layer 0 counter carry.
- 0: Disable.
- 1: Enable.
-
CL1 (bit 2-3): Sets color depth for screen layer 1.
-
CL0 (bit 0-1): Sets color depth for screen layer 0.
CL0, CL1 setting value One layer Two layers 0 0 -- -- 0 1 -- 32,768 colors 1 0 32,768 colors -- 1 1 256 colors 16 colors
The CLKSEL field of control register 1 (table I-4-32) selects the main clock frequency.
The subcarrier is used as a color carrier signal. During the vertical sync signal period, the main clock is divided to double the period after division. The value of SCSEL is this division factor minus one. For instance, setting 0 sets the ratio to 1:1. [Translator's note: the effective division factor is actually double the value of SCSEL + 1, since the divider determines the rate at which the subcarrier signal transitions, rather than the overall period.]
Control register 2 (table I-4-33) regulates the operation of the external vertical signal separation timing one-shot multi circuit.
The PM field sets the one-shot output pulse width in terms of main clock counts.
The 15th bit, RETRG (retrigger), means that when the trigger fires and the one-shot runs, the one-shot runs again using the next time the trigger fires again as a reference point.
Each bit in the dummy register (table I-4-34) has a meaning as follows:
DSPTV0, DSPTV1, DSPTH0, DSPTH1, FIELD, VSYNC, HSYNC, and VIN are read-only.
DSPTV0, DSPTV1, DSPTH0, and DSPTH1 are set to 1 with every display period.
FIELD indicates the field number during interlacing.
VSYNC and HSYNC become 1 with every emission line period.
VIN is 1 when a video input is present.
The remaining bits are write-only.
FR2 turns the sync signal generation circuit on or off.
FR3 determines whether halftoning is used during superimpose.
VCRDEN determines whether the video card is operating.
SCEN indicates whether the color carrier output is present.
| Register number | Register name | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1D | Control register 1 | SCSEL | CLKSEL | ||||||||||||||
-
SCSEL (bit 2-3): Selects the subcarrier division ratio.
- 0 0: 2x division ratio
- 0 1: 4x division ratio
- 1 0: 6x division ratio
- 1 1: 8x division ratio
The subcarrier toggles according to the time period formed by dividing the main clock by (SCSEL+1).
-
CLKSEL (bit 0-1): Selects the main clock speed.
- 0 0: 28.6363 MHz
- 0 1: 24.5454 MHz
- 1 0: 25.175 MHz
- 1 1: 21.0525 MHz
| Register number | Register name | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1F | Control register 2 | RETRG | PM | ||||||||||||||
-
RETRG (bit 15): Sets the trigger.
- 0: Retrigger enabled.
- 1: Retrigger disabled.
-
PM (bit 0-8): Sets the one-shot output pulse width according to the CRTC clock count. Set to one of the following values, according to the clock rate chosen in control register 1:
Clock (MHz) Setting value 28.6363 0x01CA 25.175 0x0192 24.5454 0x0188 21.0525 0x0150
| Register number | Register name | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Read | Write | ||||||||||||||||
| 1E | Dummy register | DSPTV1 | DSPTV0 | DSPTH1 | DSPTH0 | FIELD | VSYNC | HSYNC | VIN | FR3 | FR2 | FR1 | FR0 | ||||
- DSPTV1 (bit 15):
- 0: Not in vertical display period
- 1: In vertical display period
- DSPTV0 (bit 14):
- 0: Not in vertical display period
- 1: In vertical display period
- DSPTH1 (bit 13):
- 0: Not in horizontal display period
- 1: In horizontal display period
- DSPTH0 (bit 12):
- 0: Not in horizontal display period
- 1: In horizontal display period
- FIELD (bit 11):
- 0: Field 0
- 1: Field 1
- VSYNC (bit 10):
- 0: Not in vertical retrace period
- 1: In vertical retrace period
- HSYNC (bit 9):
- 0: Not in horizontal retrace period
- 1: In horizontal retrace period
- VIN (bit 8): Video in.
- 0: Not present
- 1: Present
- FR3 (bit 3) HTEN: Halftone.
- 0: Do not halftone
- 1: Halftone
- FR2 (bit 2) SGEN: Sync generator enable.
- 0: Disable
- 1: Enable
- FR1 (bit 1) VCRDEN: Video card enable.
- 0: Video card disabled.
- 1: Video card enabled.
- FR0 (bit 0) SCEN: Subcarrier enable.
- 0: No subcarrier output.
- 1: Subcarrier output.
The video output controller registers provide additional screen display controls alongside the CRTC internal registers. In this section, we describe these registers.
The video output controller composes the data read from VRAM (including both screen layers and sprites), manages palettes, and separates the VRAM data from rows of pixels into individual pixels, and then transmits pixels to the display.
The control-related registers are as follows:
- Control register
- Priority register
- Digital palette modify flag
- CRTC output control register
- Graphics VRAM display mode register
Of these, the graphics VRAM display mode register is related to FMR-50 compatibility, so is covered in "4.9: FMR-50 compatible screen display functionality". Here, we explain the remaining registers.
To write to the control register (table I-4-35) and priority register (I-4-36), the video output controller I/O register (table I-4-37) is used. The register number is set in I/O address 0x0448, and then the value is set using address 0x044A.
The register number can be set using 2 bits, but the upper bit is for later expansion, so in practice, the low bit alone selects whether the control register or priority register is accessed.
The control register selects one-screen or two-screen display, along with the color count.
The priority register selects the screen layer priority order, the video input brightness, and 16- or 256-color palette mode.
The YS field sets whether the screen exchange signal is in effect.
Please write to these registers using values from table I-4-23.
| Register number | Register name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 00 | Control register | 0 | 0 | 0 | PMODE | CL11 | CL10 | CL01 | CL00 |
| PMODE | CL11 | CL10 | CL01 | CL00 | Color mode | Layer |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | DISPLAY OFF | 1 layer mode |
| 0 | 0 | 1 | 0 | 1 | DISPLAY OFF | 1 layer mode |
| 0 | 1 | 0 | 1 | 0 | 256 color | 1 layer mode |
| 0 | 1 | 1 | 1 | 1 | 32,768 color | 1 layer mode |
| 1 | * | * | 0 | 0 | DISPLAY OFF | Screen layer 0 |
| 1 | * | * | 0 | 1 | 16 color | Screen layer 0 |
| 1 | * | * | 1 | 0 | DISPLAY OFF | Screen layer 0 |
| 1 | * | * | 1 | 1 | 32,768 color | Screen layer 0 |
| 1 | 0 | 0 | * | * | DISPLAY OFF | Screen layer 1 |
| 1 | 0 | 1 | * | * | 16 color | Screen layer 1 |
| 1 | 1 | 0 | * | * | DISPLAY OFF | Screen layer 1 |
| 1 | 1 | 1 | * | * | 32,768 color | Screen layer 1 |
- * indicates bits that are set to values for the other layer.
| Register number | Register name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 01 | Priority register | PLT0 | PLT1 | YS | YM | PR1 | |||
-
PLT0-1 (bit 4-5): Selects the palette.
- 0 0: Screen layer 0 has 16-color palette
- 1 0: Screen layer 1 has 16-color palette
- 0 1: 256-color palette
- 1 1: 256-color palette
-
YS (bit 3):
- 0: YS enable
- 1: YS disable
This bit has meaning when the CRTC is in the external sync state. YS must always be enabled when using 256-color mode with external sync.
-
YM (bit 2): Sets video input brightness.
- 0: High brightness
- 1: Low brightness
-
PR1 (bit 0): Sets screen layer priority order.
- 0: Screen layer 0 in front
- 1: Screen layer 1 in front
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0448 | Address register | W | 0 | 0 | 0 | 0 | 0 | 0 | RA1 | RA0 |
| 0x044A | Data register | W | RD7 | RD6 | RD5 | RD4 | RD3 | RD2 | RD1 | RD0 |
The DPMD flag in the digital palette modify flag register (table I-4-38) notifies when the digital palette registers have been written in FMR-50 compatibility mode.
The SPD0 and PAGE flags indicate the sprite status.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x044C | Digital palette modify flag register | R | DPMD | undefined | SPD0 | PAGE | ||||
-
DPMD (bit 7): Flag used for digital palette emulation.
- 0: Digital palette has not been written to
- 1: Digital palette has been written to
Reading this register resets it to 0.
-
SPD0 (bit 1): Sprite busy flag.
- 0: Not busy
- 1: Busy
-
PAGE (bit 0): The page that sprites are being rendered to.
- 0: Sprites are being rendered to page 0; page 1 is being displayed
- 1: Sprites are being rendered to page 1; page 0 is being displayed
The CRT output control register (table I-4-39) sets whether screen layer 0 and/or 1 are displayed.
If a layer has either one of its GREEN or COLOR bits set, then that layer is displayed.
When using only one screen layer (taking the entire 512KB of VRAM), the bits for screen layer 0 are used, but as an exception, when digitization is being used in 32,768-color mode, it is necessary to write the same bit values for layers 0 and 1.
Note that, as a holdover from the FM-11, GREEN indicates a green display and COLOR indicates a color display, but on the FM TOWNS, there is no such distinction.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0xFDA0 | CRT output control register | W | 0 | 0 | 0 | 0 | Layer 0 | Layer 1 | ||
| COLOR | GREEN | COLOR | GREEN | |||||||
-
For 2 layer mode:
COLOR GREEN Meaning 0 0 No display 0 1 Display 1 0 Display 1 1 Display -
For 1 layer mode:
Mode Layer 0 Layer 1 Display COLOR GREEN COLOR GREEN 256 color mode 0 0 0 0 No display 0 1 0 0 Display 1 0 0 0 Display 1 1 0 0 Display 32,768 color mode, external sync, superimpose 0 0 0 0 No display 0 1 0 0 Display 1 0 0 0 Display 1 1 0 0 Display 32,768 color mode, digitize writethrough 0 0 0 0 No display 0 1 0 1 Display 1 0 1 0 Display 1 1 1 1 Display
The FM TOWNS is designed to be able to use FMR-50 applications, behaving like an FMR-50 even from the perspective of screen display, so the TOWNS provides compatible display behavior. The FMR-50-compatible display is implemented in a combination of hardware and the BIOS, but in this section, we explain the hardware-level compatibility system.
The FMR-50 has a 640x400 pixel graphics display, capable of displaying 16 out of 4,096 colors, or 8 out of 16 colors. It also has a maximum 80 column x 25 row text screen which can display text in 16 colors.
The 16-color graphics display uses groupings of 4 bits of data. However, the color bits are not all in the same place. The data for all bits 3 (C3), bits 2 (C2), bits 1 (C1), and bits 0 (C0) are stored in separate regions of VRAM. The data region for an individual bit position is called a plane. VRAM is read over these planes in parallel, and this form of VRAM is called plane access VRAM. Diagram I-4-43 illustrates how plane access works. The FMR-50 also keeps a digital palette to select 8 out of 16 possible colors.
On the FMR-50, text display uses text VRAM, into which character codes are written in order to display characters.
The FM TOWNS supports the same form of plane access as the FMR-50 for graphics display. It also uses the graphics screen for text display.
[diagram I-4-43]
On the FM TOWNS, in order to implement FMR-50 compatible display, the FMR-50 compatible display mode (screen layer 0 in mode 1, and screen layer 1 in mode 4) is first selected. Screen layer 0 is used as the graphics screen, and screen layer 1 as the text screen.
FM TOWNS VRAM normally uses a bitmap layout, but page 0 and page 1 also support plane access.
One page in VRAM is 128KB, so each plane's size is 32KB, and for plane reading and writing, a 32KB memory window at 0xC0000 is used (diagram I-4-44). The graphics VRAM display mode register (table I-4-41) selects which pages to display, the graphics VRAM page select register (table I-4-44) selects the pages that are written to, and the graphics VRAM update mode register (table I-4-43) selects which planes to read from or write to. Diagram I-4-45 shows how the bit order in a CPU register corresponds to the bits transferred into each plane.
In the FMR-50-compatible 8-color display mode, the C3 plane is not used.
[diagram I-4-44]
[diagram I-4-45]
The digital palette registers (table I-4-40) configure the 8-out-of-16 color palette. However, these registers are dummies for FMR-50 compatibility, and do not directly influence color conversion even if they are written to. In order to actually set the palette, software must update the analog palette with colors equivalent to the FMR-50 palette settings based on the values in the digital palette registers.
However, the DPMD bit in the digital palette modify flag register can be consulted to determine whether a write has occurred to any of the digital palette registers.
For 16-out-of-4,096-colors display, the analog palette registers are used.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0xFD98 | Palette data 0 | R | R | C3 | C2 | C1 | C0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
| 0xFD99 | Palette data 1 | R | R | C3 | C2 | C1 | C0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
| 0xFD9A | Palette data 2 | R | R | C3 | C2 | C1 | C0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
| 0xFD9B | Palette data 3 | R | R | C3 | C2 | C1 | C0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
| 0xFD9C | Palette data 4 | R | R | C3 | C2 | C1 | C0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
| 0xFD9D | Palette data 5 | R | R | C3 | C2 | C1 | C0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
| 0xFD9E | Palette data 6 | R | R | C3 | C2 | C1 | C0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
| 0xFD9F | Palette data 7 | R | R | C3 | C2 | C1 | C0 | |||
| W | 0 | 0 | 0 | 0 | ||||||
- These are dummy registers used for FMR-50 compatibility, so they can be read from and written to, but their use requires software to emulate their original behavior.
The FMR-50 has text VRAM, but the FM TOWNS instead uses graphics VRAM layer 1 in screen mode 4. To display characters without using the BIOS, a character generator must be used to draw pixels to screen layer 1 using a text font.
The registers related to FMR-50 compatibility mode are described in table I-4-41, table I-4-42, table I-4-43, table I-4-45, and table I-4-46.
In FMR-50 compatibility mode, the PS2 bit sets which of VRAM page 0 or page 1 is displayed in the graphics screen. When sprite display is stopped, 0 must be set.
RAM1-4 set whether each plane is displayed.
| Memory address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x000C_FF82 | Graphics VRAM display mode register | R | undefined | |||||||
| W | 0 | 1 | RAM4 | PAGE SELECT | RAM SELECT BITS | |||||
| PS2 | 0 | RAM3 | RAM2 | RAM1 | ||||||
- FMR-50 compatibility register.
- RAM4 (bit 5): Plane C3 display.
- 0: Do not display
- 1: Display
- PS2 (bit 4): Selects the page to display.
- 0: Page 0
- 1: Page 1
- RAM3 (bit 2): Plane C2 display.
- 0: Do not display
- 1: Display
- RAM2 (bit 1): Plane C1 display.
- 0: Do not display
- 1: Display
- RAM1 (bit 0): Plane C0 display.
- 0: Do not display
- 1: Display
This register sets how many characters are displayed per line in the text screen, and has a bit indicating whether the lowest bit of the cursor position is set. Since this register is a dummy register, it is necessary to perform the actual character output via software emulation drawing into page 2 or 3.
| Memory address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x000C_FF80 | MIX register | R | undefined | CURSOR LSB | undefined | WIDTH | undefined | |||
| W | 0 | 0 | 0 | 0 | 0 | 0 | ||||
- FMR-50 compatibility register.
- CURSOR LSB (bit 5): Lowest bit of the cursor position value.
- WIDTH (bit 3): Number of characters displayed per line.
- 0: 40 characters
- 1: 80 characters
This register selects which planes the CPU reads from or writes to in VRAM. Several planes can be selected for writing, and they will all be simultaneously written to.
| Memory address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x000C_FF81 | Graphics VRAM update mode register | R | READOUT CONTROL | undefined | RAM SELECT BIT | |||||
| RC2 | RC1 | RAM4 | RAM3 | RAM2 | RAM1 | |||||
| W | READOUT CONTROL | 0 | 0 | RAM SELECT BIT | ||||||
| RC2 | RC1 | RAM4 | RAM3 | RAM2 | RAM1 | |||||
-
FMR-50 compatibility register.
-
RC1-2 (bit 6-7): Target plane for VRAM reads.
- 0 0: Read plane C0
- 0 1: Read plane C1
- 1 0: Read plane C2
- 1 1: Read plane C3
-
RAM4 (bit 3): Write to plane 3.
- 0: Do not write
- 1: Write
-
RAM3 (bit 2): Write to plane 2.
- 0: Do not write
- 1: Write
-
RAM2 (bit 1): Write to plane 1.
- 0: Do not write
- 1: Write
-
RAM1 (bit 0): Write to plane 0.
- 0: Do not write
- 1: Write
It is possible to write to several planes at once.
This register selects which page the CPU writes to in VRAM.
| Memory address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x000C_FF83 | Graphics VRAM page select register | R | undefined | PAGE SELECT | undefined | |||||
| PS2 | 0 | |||||||||
| W | 0 | 0 | 0 | PAGE SELECT | 0 | 0 | 0 | |||
| PS2 | 0 | |||||||||
- FMR-50 compatibility register.
- PS2 (bit 4): Selects the page to read from and write to.
- 0: Page 0
- 1: Page 1
By reading from the same I/O address as the CRT output control register, this register can be referenced to see whether the horizontal and/or vertical sync signals are ON or OFF.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0xFDA0 | SUB status register | R | undefined | HSYNC | VSYNC | |||||
- FMR-50 compatibility register.
- HSYNC (bit 1): Indicates whether the horizontal retrace period is in
progress.
- 0: No horizontal retrace.
- 1: Horizontal retrace.
- VSYNC (bit 0): Indicates whether the vertical retrace period is in
progress.
- 0: No vertical retrace.
- 1: Vertical retrace.
This register is mainly used to check whether display sync is in progress. Direct screen access during vertical sync will not cause flickering.
| Memory address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x000C_FF86 | Status register | R | HSYNC | undefined | 1 | undefined | VSYNC | undefined | ||
- Memory-mapped I/O FMR-50 compatibility register.
- HSYNC (bit 7): Indicates whether the horizontal retrace period is in
progress.
- 0: No horizontal retrace.
- 1: Horizontal retrace.
- VSYNC (bit 2): Indicates whether the vertical retrace period is in
progress.
- 0: No vertical retrace.
- 1: Vertical retrace.
In this section, we list the memory and I/O addresses related to the display system.
Diagram I-4-46 shows the memory address assignments used by the display system.
Parts of the 128KB of sprite memory (4KB for text VRAM, 4KB for kanji VRAM) are used for text VRAM emulation. Additionally, in FMR-50 compatibility mode, the graphics memory region can be indirectly accessed by reading from or writing to the plane access region.
[diagram I-4-46]
Diagram I-4-47 shows the I/O address mappings related to the display system.
[diagram I-4-47]
The video card has hardware for performing video conversion, digitization, and superimpose. It can be inserted into the video card connector. In this section, we describe the video card's structure and functionality.
Diagram I-4-48 provides a block diagram of the video card.
The video input can be used to perform superimpose or video digitization. The video output can convert the FM TOWNS analog RGB signal into a video signal. Video input and output has the form of a standard video composite signal (NTSC signal), making it possible to connect to various home video devices.
The card's analog RGB connector can output the superimposed image to a display, almost the same as the FM TOWNS' integrated RGB connector, but with some exceptions. Its output can still be used without using superimpose, but it can only guarantee the correct frequency characteristics with a horizontal frequency of 15.73KHz. For other modes, it is best to connect the display to the integrated connector.
Additional adjustments can be performed using the knobs on the back face of the video card (diagram I-4-49), as indicated in table I-4-47.
For information about the analog RGB connector, the video card connector, and their pin layouts, please see the appendices at the end of this book.
[diagram I-4-48]
[diagram I-4-49]
| Control | Adjustment |
|---|---|
| Hue VR | Video output and digitizer hue adjustment |
| Saturation VR | Video output and digitizer saturation adjustment |
| Luminance VR | Digitizer luminance adjustment |
| Contrast VR | Digitizer contrast adjustment |
Video conversion transforms an analog RGB signal into a video signal, and the FM TOWNS uses this ability to convert its screen output to a video signal. However, video signal conversion isn't guaranteed to work unless the horizontal frequency is 15.73KHz.
The output depends on the display mode as shown in table I-4-48. "BLUEBACK video output" in this table indicates that video conversion is incomplete.
After an external video signal is converted to an analog RGB signal, the computer's own generated image can be overlaid, and the combined output can be sent over the video card's analog RGB output and/or video output. During superimposition, the video image can be reduced to half brightness, the computer image can be halftoned, and/or the computer and video images can be displayed mixed (diagram I-4-50).
| 1 | Low resolution (15.75 KHz) | NTSC standard mode (28.6363MHz clock) | PC screen | No source | FM TOWNS internal sync (CSYNC) |
|---|---|---|---|---|---|
| 2 | Source present | ||||
| 3 | SI screen | No source | |||
| 4 | Source present | Video source sync | |||
| 5 | Non-NTSC-standard mode | PC screen | No source | FM TOWNS internal sync (CSYNC) | |
| 6 | Source present | ||||
| 7 | SI screen | No source | |||
| 8 | Source present | Video source sync | |||
| 9 | Medium or high resolution (24 KHz/31 KHz) | PC screen | No source | BLUEBACK video output | |
| 10 | Source present | ||||
-
PC screen: Computer screen only
-
SI screen: Superimposed screen (including digitized display)
-
Source: Video source signal
In situations 5 through 7, color bleeding or running will occur if the color sync signal is not synchronized to the video output.
The external video signal, after being converted to analog RGB, can be digitized by the A/D converter and written to the computer's VRAM. This capture is performed in 32,768 colors (5 bits per RGB channel). The ESM0 and ESM1 bits of the CRTC control register set each screen layer's digitization state.
In order to configure the superimpose and/or video digitization registers, the screen mode must be set to a superimpose- and/or digitization-capable mode, using the register settings shown in I-4-23. For superimpose, any of screen mode 9, 11, 14, or 18 can be used, and for digitization, any of screen mode 9, 11, or 18 can be used.
Afterward, the CRTC internal registers and video controller registers need to be changed according to the bit values listed in table I-4-49.
| Register | Computer | Video card | |||||||||||||
| CRTC internal register | * | Analog RGB output | Analog RGB output | Video output | |||||||||||
| ESYN | ESM0 | ESM1 | VCR DEN | FR2 | FR3 | Ys | Ym | Layer 0 | Layer 1 | Layer 0 | Layer 1 | Video layer | Layer 0 | Layer 1 | Video layer |
| 0 | 0 | 0 | 0 | 0 | 1 | PC INT | PC INT | PC INT | PC INT | none | none | none | BLUE | ||
| 0 | 0 | 0 | 1 | 0 | 1 | PC INT | PC INT | PC INT | PC INT | none | PC INT | PC INT | none | ||
| 1 | 0 | 0 | 1 | 0,1 | 1 | PC EXT | PC EXT | PC EXT | PC EXT | none | PC EXT | PC EXT | none | ||
| 1 | 0 | 1 | 1 | 0 | 1 | PC EXT | DIGI | PC EXT | DIGI | none | PC EXT | DIGI | none | ||
| 1 | 1 | 0 | 1 | 0 | 1 | DIGI | PC EXT | DIGI | PC EXT | none | DIGI | PC EXT | none | ||
| 1 | 1 | 1 | 1 | 0 | 1 | DIGI | DIGI | DIGI | DIGI | none | DIGI | DIGI | none | ||
| 1 | 0 | 0 | 1 | 0 | 0,1 | 0 | 0,1 | PC EXT | PC EXT | SUPER | SUPER | VIDEO | SUPER | SUPER | VIDEO |
| 1 | 0 | 0 | 1 | 1 | 0,1 | 0 | 0,1 | PC EXT | PC EXT | SUPER | SUPER | BLUE | SUPER | SUPER | BLUE |
| 1 | 0 | 1 | 1 | 0 | 0,1 | 0 | 0,1 | PC EXT | DIGI | SUPER | DIGI | VIDEO | SUPER | DIGI | VIDEO |
| 1 | 1 | 0 | 1 | 0 | 0,1 | 0 | 0,1 | DIGI | PC EXT | DIGI | SUPER | VIDEO | DIGI | SUPER | VIDEO |
| 1 | 1 | 1 | 1 | 0 | 0,1 | 0 | 0,1 | DIGI | DIGI | DIGI | DIGI | VIDEO | DIGI | DIGI | VIDEO |
- PC INT: Computer display with internal sync
- PC EXT: Computer display with external sync
- SUPER: Superimpose display
- DIGI: Digitize-through display
- BLUE: BLUEBACK sync generator output (solid blue color)
- VIDEO: Video signal input from video input connector
- Note: * marks the video output controller priority registers.
- Settings outside of those shown in the table are not possible.
- When FR2 = 0 and ESYN = 1 without video input, the computer display is used with internal sync.
- When Ym = 1, the video layer uses low brightness.
- When FR3 = 1, the video layer is displayed with screen layers 0 and 1 half transparent.
- Setting ESYN = 0 and FR2 = 1 is equivalent to setting Ys = 0 with regards to framebuffer handling.
Additionally, when using external sync, it is necessary to be aware of the following:
- 32,768 color single-layer mode:
- Superimpose: Screen layer 1 must be set to DISPLAY OFF (superimpose will be disabled if ON)
- Digitization: Screen layer 1 must be set to DISPLAY ON (digitization cannot happen if OFF)
- 256-color single-layer mode:
- Superimpose: Whether YS is enabled or disabled cannot be changed. YS is always enabled.
The FM TOWNS' music functionality is a major power-up compared to previous computers.
In addition to having a CD-ROM drive as standard equipment, which can also be used as a CD player, the FM TOWNS is equipped with FM and PCM sound generators capable of stereo output, allowing for various kinds of musical expression. Additionally, it is equipped with an internal microphone, microphone connector, audio input connector, and headphone connector, so various audio devices can be connected.
In this chapter, we describe the operation of the FM TOWNS' superior audio system hardware.
In this section, we give a general description of the audio system's structure and input/output signals. Detailed explanations of each part are provided in the following sections.
Diagram I-5-1 shows all of the FM TOWNS' audio system input and output signals.
[diagram I-5-1]
The FM TOWNS is designed to mix the various input signals into output using the electronic volume and mixer controls. One could say that it is equipped with a "computer controlled mixer". Diagram I-5-2 provides a block diagram of the audio system.
[diagram I-5-2]
Below, we provide an overview of each component.
On the bottom left of the front of the computer, there is an electronic condenser microphone. An external microphone connector can also be used to externally connect a microphone. When an external microphone is connected, the internal microphone is disconnected and cannot be used.
The microphone input signal is processed monaurally. The external microphone connector is a monaural minijack; in order to use other kinds of microphone, off-the-shelf adapter plugs can be used.
The signal level of microphone input can be low, so it is amplified by a special amplifier in order to balance it with other inputs, and then sent through the electronic volume control.
In order to record PCM samples with high quality, it is necessary to adjust the recording level to the optimal level. A suitable external microphone is as sensitive as possible, with a recommended catalog sensitivity of at least 55dB (0 dB = 1V/Pa).
Using the the audio line input, general audio outputs (stereo amps, tape decks, CD players, televisions, video, radio-cassette players, etc.) can be connected. The audio line input has independent left and right signals, and is processed as stereo.
The line input signal is sent as-is to the digital volume control.
The internally-equipped CD-ROM drive can be used as an audio CD player. The signal from the CD-ROM drive has independent left and right signals, and is processed as stereo. The signal from the CD-ROM drive is sent as-is to the digital volume control.
The PCM audio generator can play back eight channels of sound at the same time. Additionally, each channel can be distributed between the left and right channels, making stereo output possible. Its signal is sent directly to the mixer to let its level be adjusted, without going through the digital volume control.
The FM audio generator can generate 6 simultaneous channels of sound, and each channel can play in stereo (into the left, right, or both channels). This signal is also sent to the mixer to let its level be adjusted without going through electronic volume control. Note that the PSG sound generator from previous lower-end FM series models (the former FM sound generator IC) is not present in the TOWNS.
A circuit can mute the FM and/or PCM audio source outputs. The FM/PCM mute register sets whether either or both channels are muted.
The electronic volume control can control the volume of the output signal. The volume is controlled by accessing the electronic volume control registers from the CPU.
This circuit cuts off the mixer output, stopping the signal to the output connectors. This is set to the active state (detached) immediately after reset. The audio register sets whether mute is active or disabled.
The buffer is placed immediately in front of the output connectors, reducing interference from the connected equipment, preventing level or audio quality degradation. The output impedance is approximately 1Kohm.
The signal passing through the mute circuit is amplified by the speaker amp and then output through the internal speaker. At this point, the amp's left and right outputs are mixed equally into a monaural signal. Its volume can be manually adjusted. The output level is visualized by status indicators (LEDs).
When headphones are connected to the headphone connector, the signal from the mute circuit can be listened to in stereo. Note that when a headphone plug is inserted, the speaker sound is disabled. Volume adjustment and LED lighting behave in the same manner as for the internal speaker.
There are left and right channel (stereo) output connectors. These can be connected to a general audio system's inputs.
In the FM TOWNS, the electronic volume control is used to adjust the volume of each audio input signal. In this section, we explain the structure of the electronic volume control and attenuation settings.
Two Fujitsu MB87078 ICs are used for electronic volume control. One IC provides four electronic volume controls, so in total, eight signal volumes can be adjusted.
The electronic volume controls are assigned as shown in diagram I-5-3; in practice, only six channels are used.
Each channel's volume control is structured as shown in diagram I-5-4.
[diagram I-5-3]
[diagram I-5-4]
The CPU can control attenuation by writing to the electronic volume registers (table I-5-1).
Two groups of electronic volume registers are provided, corresponding to the number of volume controllers. In each group, there is a DATA register and a COM register.
In order to make a large change to volume, the COM register is used. Each channel's volume can be changed to -∞dB (mute) by EN = 0, -32.0dB by C32 = 1, or 0dB by C0 = 1 and C32 = 0. CH0 and CH1 set the channel.
To make fine changes to volume, the low 6 bits of the DATA register are used. Each channel's attenuation level can be set to one of 64 levels.
Each channel's audio level is set by the 6-bit value (0-63) as shown in table I-5-2, so if all six bits of data are zero, the attenuation is -31.5dB, or if the value is 63, it is 0dB.
The relationship between attenuation and the actual audio level ratio (transmission ratio) is as shown in table I-5-3.
In table I-5-3, if one remembers that 0dB is 1:1, -3dB is approximately 1/√2, -6dB is approximately 1/2, and -20dB is approximately 1/10, then it becomes convenient to calculate the signal transmission ratio for other attenuation factors. For example, -26dB converts as follows:
-26 dB = -20 dB + (-6 dB) ……… 1/10 * 1/2 = 1/20
In this way, adding attenuations (dB) corresponds to multiplying transmission ratios, so we can calculate that -26dB attenuation corresponds to 1/20 transmission ratio.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04E0 | Volume 1 DATA register | R | undefined | D5 | D4 | D3 | D2 | D1 | D0 | |
| W | 0 | 0 | ||||||||
| 0x04E1 | Volume 1 COM register | R | undefined | C32 | C0 | EN | CH1 | CH0 | ||
| W | 0 | 0 | 0 | |||||||
| 0x04E2 | Volume 2 DATA register | R | undefined | D5 | D4 | D3 | D2 | D1 | D0 | |
| W | 0 | 0 | ||||||||
| 0x04E3 | Volume 2 COM register | R | undefined | C32 | C0 | EN | CH1 | CH0 | ||
| W | 0 | 0 | 0 | |||||||
- EN: When zero, the electronic volume output level is set to -infinity dB.
- C32: When one, the electronic volume output level is set to -32 dB.
- C0: When one, the electronic volume output level is set to 0 dB.
- D0-5: Changes level between 111111 (0 dB) and 000000 (-31.5 dB).
- CH0-1: Selects the channel.
-
Volume 1:
CH1 CH0 Channel 0 0 Line input left 0 1 Line input right -
Volume 2:
CH1 CH0 Channel 0 0 CD audio left output 0 1 CD audio right output 1 0 Microphone input 1 1 Modem output* * when optional modem card is used
-
| D0-5 | Attenuation (dB) |
| 543210 | |
| 000000 | -31.5 |
| 000001 | -31.0 |
| 000010 | -30.5 |
| 000011 | -30.0 |
| 000100 | -29.5 |
| 000101 | -29.0 |
| 000110 | -28.5 |
| 000111 | -28.0 |
| 001000 | -27.5 |
| 001001 | -27.0 |
| 001010 | -26.5 |
| 001011 | -26.0 |
| 001100 | -25.5 |
| 001101 | -25.0 |
| 001110 | -24.5 |
| 001111 | -24.0 |
| 010000 | -23.5 |
| 010001 | -23.0 |
| 010010 | -22.5 |
| 010011 | -22.0 |
| 010100 | -21.5 |
| 010101 | -21.0 |
| 010110 | -20.5 |
| 010111 | -20.0 |
| 011000 | -19.5 |
| 011001 | -19.0 |
| 011010 | -18.5 |
| 011011 | -18.0 |
| 011100 | -17.5 |
| 011101 | -17.0 |
| 011110 | -16.5 |
| 011111 | -16.0 |
| 100000 | -15.5 |
| 100001 | -15.0 |
| 100010 | -14.5 |
| 100011 | -14.0 |
| 100100 | -13.5 |
| 100101 | -13.0 |
| 100110 | -12.5 |
| 100111 | -12.0 |
| 101000 | -11.5 |
| 101001 | -11.0 |
| 101010 | -10.5 |
| 101011 | -10.0 |
| 101100 | -9.5 |
| 101101 | -9.0 |
| 101110 | -8.5 |
| 101111 | -8.0 |
| 110000 | -7.5 |
| 110001 | -7.0 |
| 110010 | -6.5 |
| 110011 | -6.0 |
| 110100 | -5.5 |
| 110101 | -5.0 |
| 110110 | -4.5 |
| 110111 | -4.0 |
| 111000 | -3.5 |
| 111001 | -3.0 |
| 111010 | -2.5 |
| 111011 | -2.0 |
| 111100 | -1.5 |
| 111101 | -1.0 |
| 111110 | -0.5 |
| 111111 | 0.0 |
| dB | ratio |
|---|---|
| -0.0 | 1.000 |
| -0.5 | 0.944 |
| -1.0 | 0.891 |
| -1.5 | 0.841 |
| -2.0 | 0.794 |
| -2.5 | 0.750 |
| -3.0 | 0.708 |
| -3.5 | 0.668 |
| -4.0 | 0.631 |
| -4.5 | 0.596 |
| -5.0 | 0.562 |
| -5.5 | 0.531 |
| -6.0 | 0.501 |
| -6.5 | 0.473 |
| -7.0 | 0.447 |
| -7.5 | 0.422 |
| -8.0 | 0.398 |
| -8.5 | 0.376 |
| -9.0 | 0.355 |
| -9.5 | 0.335 |
| -10.0 | 0.316 |
| -10.5 | 0.299 |
| -11.0 | 0.282 |
| -11.5 | 0.266 |
| -12.0 | 0.251 |
| -12.5 | 0.237 |
| -13.0 | 0.224 |
| -13.5 | 0.211 |
| -14.0 | 0.200 |
| -14.5 | 0.188 |
| -15.0 | 0.178 |
| -15.5 | 0.168 |
| -16.0 | 0.158 |
| -16.5 | 0.150 |
| -17.0 | 0.141 |
| -17.5 | 0.133 |
| -18.0 | 0.126 |
| -18.5 | 0.119 |
| -19.0 | 0.112 |
| -19.5 | 0.106 |
| -20.0 | 0.100 |
| -20.5 | 0.094 |
| -21.0 | 0.089 |
| -21.5 | 0.084 |
| -22.0 | 0.079 |
| -22.5 | 0.075 |
| -23.0 | 0.071 |
| -23.5 | 0.067 |
| -24.0 | 0.063 |
| -24.5 | 0.060 |
| -25.0 | 0.056 |
| -25.5 | 0.053 |
| -26.0 | 0.050 |
| -26.5 | 0.047 |
| -27.0 | 0.045 |
| -27.5 | 0.042 |
| -28.0 | 0.040 |
| -28.5 | 0.038 |
| -29.0 | 0.035 |
| -29.5 | 0.033 |
| -30.0 | 0.032 |
| -30.5 | 0.030 |
| -31.0 | 0.028 |
| -31.5 | 0.027 |
| -32.0 | 0.025 |
The FM TOWNS has not only has an FM sound generator but also a PCM sound generator. An RF5C68 is used as the PCM sound generator IC.
Using this PCM sound generator, sampled audio playback is possible. There are a maximum of 8 playback channels, allowing for 8 simultaneous sounds to be played.
In this section, we describe the PCM sound generator hardware, as well as how sampling and playback works.
PCM is an abbreviation for pulse code modulation. It converts sound into digital data to enable it to be used in an audio generator. Since it uses samples of sound, it could also be called a sampling audio generator.
Audio sampling refers to the conversion of analog sound signals into digital data. Sound is essentially amplitude (air density) changing over time, so the data can be digitized by dividing the sound into very short time intervals and recording the amplitude at each interval as a binary value.
Sampled audio can be preserved as computer data, which can be converted back into audio frequencies by processing the data over time.
Diagram I-5-5 presents a block diagram of the PCM sound generator and related hardware.
The PCM sound generator related hardware is divided into the sampler section and sample playback section.
[diagram I-5-5]
Let's describe the hardware in each section.
Converts the stereo audio input from an external audio system to monaural.
Cuts out unnecessary signal when digitizing audio. The filter has the job of preventing unpleasant "hum" from being generated by interference between the sampling clock (dependent on the sample rate) and the input analog signal, and it also removes excessively high frequencies which can cause noise in the sampled audio. The filter cutoff frequency is approximately 4KHz, and is designed to reach a characteristic of -12dB/OCT.
Converts analog audio to digital. There is one AD converter channel (monaural).
Sampled data is written here.
Memory that stores playback data. At playback time, the CPU writes to waveform memory, and the PCM sound generator IC reads it, but the CPU can also read waveform memory.
Reads and composes sample data from waveform RAM, distributes it to the left and right channels, and outputs to the DA converter.
Converts digital waveform data into analog audio data (amplitude).
During playback, the PCM sound generator IC can simultaneously read the contents of eight channel regions of waveform memory. In this case, each channel's data is added together before being output from the DA converter.
Filters the stepped waveform from the PCM sound generator output in order to smoothly connect samples. The cutoff frequency is approximately 4KHz.
Sampling is performed in the stages from the L&R mixer to the user memory stage of diagram I-5-5.
Here, we describe how analog audio is digitized and data is recorded by the AD converter, the heart of the sampler.
Analog audio digitization is performed by the AD converter.
The number of samples taken per second is called the sampling rate. The maximum sampling rate is 19.2KHz, but an arbitrarily lower rate can be used.
The sampler reads 254 levels (-127 to +126) of amplitude. 0b1000_0000 (level 0) is the center, increasing in the positive direction to 0b1111_1110 (level +126) and decreasing in the negative direction to 0b0111_1111 (level -127) as shown in diagram I-5-6.
The most significant bit in sampling data is a sign bit. When the high bit is 1, the level is positive or zero, and when it is zero, the level is negative.
Additionally, the following two values in the middle of sampling data have special meaning:
- 0b1111_1111: loop stop data
- 0b0000_0000: null (invalid)
These values do not have meaning as sampling data.
[diagram I-5-6]
Diagram I-5-7 gives an overview of the structure of the AD converter.
Each eight bits of digital data generated by the AD conversion section are written to the AD sampling data register (table I-5-4) via a FIFO (first-in, first-out).
The FIFO's duty is to serve as a buffer between the AD conversion section and the AD sampling data register.
Sampling data can be stored in memory by reading the AD sampling data register contents and transferring them to memory.
In order to read the contents of the AD sampling data register, an arbitrary value is first written to the AD sampling flag register (table I-5-5) in order to clear the contents of the FIFO. This ensures that no data besides sampling data remains in the FIFO. The value written to the sampling flag register at this point has no particular meaning and is not preserved. Something like 0x00 is sufficient.
The contents of the AD sampling data register are shifted and updated every time it is read by the CPU. The AD conversion section writes to the FIFO if there is room, shifting in the new values.
The value of the AD sampling flag register is 0 when the CPU has read all of the data, and 1 when the FIFO writes new data. Therefore, by checking that the value of the AD sampling flag register is 1, then it is possible to correctly read waveform data from the AD sampling data register.
[diagram I-5-7]
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04E7 | AD sampling data register | R | SD7 | SD6 | SD5 | SD4 | SD3 | SD2 | SD1 | SD0 |
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04E8 | AD sampling flag register | R | SD7 | Sampling flag | ||||||
| W | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
- Sampling flag (bit 0): Indicates that the ADSD has stored sampling data. When the data is read, it is cleared. Writing causes all of the sampling data in the FIFO to be lost.
Playback is performed by the righthand part of diagram I-5-5, the area including the waveform memory, PCM sound generator registers, accumulation circuit, and output filter. The PCM sound generator registers (table I-5-6) are used in the playback process.
| I/O address | title |
|---|---|
| 0x04F0 | ENV data register |
| 0x04F1 | PAN data register |
| 0x04F2 | FDL data register |
| 0x04F3 | FDH data register |
| 0x04F4 | LSL data register |
| 0x04F5 | LSH data register |
| 0x04F6 | ST data register |
| 0x04F7 | Control register |
| 0x04F8 | Channel on/off register |
Here, we describe the sampled audio playback system. Playback is performed through the following flow:
- Waveform data to waveform memory transfer
- Waveform data read from waveform memory
- Waveform data processing and left-right panning
- Waveform 8-channel composition
- Digital to analog audio conversion
Out of these steps, the transfer to waveform memory is done using CPU instructions, and DA conversion is done by the DA converter, whereas the other steps are performed by the PCM sound source IC.
The PCM sound source IC can play back a maximum of 8 channels of audio simultaneously. When several channels are in use, then waveform data transfer to waveform memory, reading waveform data from waveform memory, waveform data processing, and left-right panning must be configured for each channel. The CB0-2 bits of the control register (table I-5-12) described below sets which channel these settings get applied to.
Waveform memory is memory where waveform data is stored for playback.
The PCM sound generator IC performs playback by reading the contents of waveform memory.
Therefore, prior to playback, it is necessary to have transferred the sampled waveform data to waveform memory beforehand.
This memory cannot be directly read from or written to by the CPU, so the 4KB main memory region from 0xC220_0000 to 0xC220_0FFF is used as a window for waveform memory access (diagram I-5-8). In other words, the 64KB of waveform memory is divided into sixteen 4KB banks (blocks), and by transferring data to this region in the main address space, each bank can be indirectly read from and written to. Which of these sixteen banks gets read from or written to is determined by the WB0-3 bits of the control register (table I-5-12) described below. Therefore, if one block of sampling data exceeds 4KB, it is necessary to change the value of WB0-3 during the transfer.
Furthermore, when using several channels, they divide and use parts of the 64KB of waveform memory, so it is necessary to set the waveform to play in each channel.
The PCM sound generator IC reads waveform memory in order to play the data, but the addresses in the ST data register (table I-5-7), FDL data register, and FDH data register (table I-5-8) must be set beforehand.
Concretely, the read start address is set in the ST data register, and the address increment rate is set in the FDL and FDH data registers.
The PCM sound generator IC reads the contents of waveform memory by updating the address from low to higher addresses according to the values set in these registers. At this time, the top eight bits of the address are gotten from the ST data register, and the low eight bits are all zero. Therefore, the starting position can be set in 256-byte increments.
An address is represented by 27 bits, with the address setting forming the 16 bits from 11 through 26 (the integer part), and the part below the decimal point consisting of bits 0 through 10 being discarded. When a value below the decimal point is set as an increment value, then the same address is read until the added incremental value fills an integer value.
Diagram I-5-9 gives an overview of how playback is managed while reading waveform memory.
When the address increment rate matches the sampling speed, the same waveform that was sampled can be reproduced, but also, by changing the increment value, the speed and frequency of playback can be changed. If the increment amount is decreased, then playback speed can be slowed (frequency is lowered), and if it is increased, playback speed can be sped up (frequency is raised).
Using this system, based on one waveform, it is possible to play sounds at various frequencies.
To repeat the same waveform, 0b1111_1111 (loop stop data) is written at the end of the repeating waveform, and the LSL and LSH data registers (table I-5-9) are set to the repeat start address.
[diagram I-5-9]
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04F6 | ST data register | W | AD15 | AD14 | AD13 | AD12 | AD11 | AD10 | AD9 | AD8 |
- When reading waveform memory, indicates the start address.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04F2 | FDL data register | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| 0x04F3 | FDH data register | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
- Sets the update rate for the waveform memory read address. Each bit's address
increment weighting is as follows:
-
FDH data register:
Bit Weighting D7 24 D6 23 D5 22 D4 21 D3 20 D2 2-1 D1 2-2 D0 2-3 -
FDL data register:
Bit Weighting D7 2-4 D6 2-5 D5 2-6 D4 2-7 D3 2-8 D2 2-9 D1 2-10 D0 2-11
-
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04F4 | LSL data register | W | AD7 | AD6 | AD5 | AD4 | AD3 | AD2 | AD1 | AD0 |
| 0x04F5 | LSH data register | W | AD15 | AD14 | AD13 | AD12 | AD11 | AD10 | AD9 | AD8 |
- When loop start data (0b1111_1111) is read from waveform memory, the data in LSL and LSH set the waveform memory address to go back to in order to continue reading.
The PCM sound generator IC supports amplitude amplification and attenuation, left-right panning, and suppression of values outside of an upper and lower limit (limiter). The ENV data register (table I-5-10) and PAN data register (table I-5-11) configure these operations.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04F0 | ENV data register | W | ENV | |||||||
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |||
- Strengthens or weakens the amplitude of the data read from waveform memory.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04F1 | PAN data register | W | RIGHT | LEFT | ||||||
| PAN3 | PAN2 | PAN1 | PAN0 | PAN3 | PAN2 | PAN1 | PAN0 | |||
- Separates the left and right output for sound being played from the current channel.
Here, we describe these operations.
Amplification is performed by multiplying seven bits of the eight-bit waveform data, excluding the sign bit, by the eight-bit value of the ENV data register.
Afterward, in order to determine the left-right position of the waveform data, the data is multiplied by the four-bit values for the left and right channel, giving a 19-bit value for the left and right waveform's amplitudes. The top four bits of the PAN data register indicate the right channel volume, and the bottom four bits the left channel volume. Therefore, in order to play at maximum volume from only the left or right channel, the following values can be used:
- 0b0000_1111: left side only
- 0b1111_0000: right side only
In order to place sound at the center, it is possible to set the left and right to the same value; however, if PAN were set to 0b1111_1111, the channel would play at double volume. For that reason, to keep each channel's volume at the same level, use the value 0b1000_1000 (diagram I-5-11).
By adjusting the left and right volumes this way, sound can be positioned at 16 directions. Also, by changing PAN gradually during playback, sound can be panned left and right.
[diagram I-5-10]
[diagram I-5-11]
The topmost 14 bits of the 19 bits from the previously accumulated channel values get added or subtracted. Whether to add or subtract is determined by the original wavetable data's sign bit.
After that, the top 10 bits of the 16-bit value are sent to the limiter. The waveform data is reduced by omitting the lowest bits this way.
Finally, the limiter cuts off values outside of the upper and lower limit. Using the limiter, when an overflow is detected in the previously-computed value, it is set to the limit value in the positive or negative direction. When this occurs, the limited part will not correctly reproduce the waveform, and the sound will be distorted (diagram I-5-12).
[diagram I-5-12]
The PCM sound source IC adds the left and right values for each channel, and sends the left and right results to the DA converter (diagram I-5-13).
[diagram I-5-13]
The DA converter converts the left-right waveform data composed from the eight channels into analog audio.
The control register (table I-5-12) selects which channel to configure waveform memory and data composition operations for. Furthermore, the channel ON/OFF register (table I-5-13) sets whether a channel is used at all.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04F7 | Control register | W | ON/OFF | MOD | 0 | 0 | WB3 | WB2 | WB1 | WB0 |
| 0 | CB2 | CB1 | CB0 |
- Sets mode, waveform memory bank address, and channel.
- ON/OFF (bit 7): Controls PCM sound output operation.
- 0: Do not start sound output
- 1: Start sound output (CPU cannot read while set to 1)
- MOD (bit 6): Sets the mode of bits 0-3.
- 0: Bits 0-3 are used as WB0-3.
- 1: Bits 0-2 are used as CB0-2.
- WB0-3 (bit 0-3): Selects the waveform memory bank address (1-16).
- CB0-2 (bit 0-2): Selects the channel (1-8).
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04F8 | Channel ON/OFF register | W | CH7 | CH6 | CH5 | CH4 | CH3 | CH2 | CH1 | CH0 |
- Controls the sound playback of each channel. Each channel whose bit is 0 is played. Only has an effect when bit 7 of the control register is 1.
The highest bit of the control register (ON/OFF bit) controls PCM sound generator playback, starting playback when 1 is written. Waveform memory is used by the PCM sound generator during playback, so the CPU cannot read from it at the same time. The low four bits of this register are used to select the bank of waveform memory. The lowest three bits are also used to select the channel number that is configured by the seven ENV, PAN, FDL, FDH, LSL, LSH, and SH data registers. Since the bottom three bits have two different meanings, the waveform memory bank is set if the MOD bit is 0, and the channel number is set if the MOD bit is 1.
To determine whether a channel is played or not, it is enabled if its bit in the channel ON/OFF register is zero. If the bit is 1, the channel's audio does not play.
The PCM sound generator IC reads waveform memory according to the start address and increment rate that were set beforehand, but the PCM sound generator by itself is not equipped to automatically stop, so if left alone, it would read until the end of waveform memory and then repeat reading from the beginning.
For this reason, waveform playback cannot be unattended. To that end, during playback, an interrupt can occur when the number of waveform memory bytes read reaches 4KB. As a result, when 4KB of waveform data is played (read), control can be diverted by the CPU, which can either let the next bank be read or stop the PCM sound source's operation.
The 64KB of waveform memory is divided into eight 8KB regions, and whether interrupts are enabled in each region can be individually configured.
To control these interrupts, the PCM interrupt mask register (table I-5-14) and PCM interrupt register (table I-5-15) are used.
The PCM interrupt mask register determines where interrupts are allowed or disallowed. If the bit corresponding to a region is 1, then interrupts can occur, and if the bit is 0, then interrupts cannot occur.
The PCM interrupt register can also be referenced to determine in which region an interrupt occurred. When an interrupt occurs, the corresponding bit for the region where it occurred becomes 1. Note that when the PCM interrupt register is read, all bits are cleared to zero.
Each bit in the PCM interrupt mask register and PCM interrupt register corresponds to an address range as shown in table I-5-16.
Interrupts can also happen for other reasons. The INT13 interrupt reason register (table I-5-17) can be referenced to inspect whether an interrupt occurred because of one of those other situations. If the PCM bit is 1, then a PCM interrupt occurred. Therefore, the procedure to follow is to read the INT13 interrupt reason register first, and if there is a PCM interrupt, then consult the PCM interrupt register.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04EA | PCM interrupt mask register | R/W | M7 | M6 | M5 | M4 | M3 | M2 | M1 | M0 |
- Masks interrupts for waveform memory bank positions.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04EB | PCM interrupt register | R | IF7 | IF6 | IF5 | IF4 | IF3 | IF2 | IF1 | IF0 |
- Read for the waveform memory bank(s) in which interrupts occurred.
* Table I-5-16: Relationship between bits in PCM interrupt related registers and waveform memory addresses
| Waveform memory address region | Mask | Interrupt |
|---|---|---|
| 0x0000 - 0x1FFF | M0 | IF0 |
| 0x2000 - 0x3FFF | M1 | IF1 |
| 0x4000 - 0x5FFF | M2 | IF2 |
| 0x6000 - 0x7FFF | M3 | IF3 |
| 0x8000 - 0x9FFF | M4 | IF4 |
| 0xA000 - 0xBFFF | M5 | IF5 |
| 0xC000 - 0xDFFF | M6 | IF6 |
| 0xE000 - 0xFFFF | M7 | IF7 |
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04E9 | INT13 interrupt reason register | R | undefined | PCM | undefined | FM | ||||
- PCM (bit 3): Whether a PCM interrupt occurred.
- 0: No PCM interrupt
- 1: PCM interrupt
- FM (bit 0): Whether an interrupt from the FM sound generator (timer) occurred.
- 0: No PCM interrupt
- 1: PCM interrupt
The FM TOWNS uses the YM2612 as an FM sound source IC. This sound source IC has six channels so can play six simultaneous sounds. Also, the sound from each channel can be output to both left and right or assigned to left or right.
In this section, we describe the structure of the FM sound source hardware and sound generation.
FM sound generation, short for frequency modulation, creates new sounds using harmonics generated by modulating the sound's components on the time axis.
The smallest unit it uses for sound composition is called a slot.
A slot, the smallest unit of waveform generation (music creation), has three input connections and one output connection. The waveform signals from the three input connections are electronically added, transformed, and/or multiplied and then output to the output connection.
A channel is composed four slots connected in a chosen pattern.
Note that the functional unit that carries out addition, multiplication, or other operations on the slot's input data is called an operator. The YM2612 has four operators, multiplexing calculation across six channels.
[diagram I-5-14]
A slot's logical structure is shown in diagram I-5-15.
The addition and multiplication units are not in reality internal to the slot, but are part of the operator, which is where the computation is performed.
The pitch data input is the signal that determines the waveform frequency, using a sawtooth waveform generated from inside of the sound generator IC.
The modulation data input is the signal that changes the shape of the waveform. It can use the slot's own output as feedback, or it can use another slot's output.
The envelope input is the signal that changes the waveform amplitude over time. It is formed by an envelope generator circuit.
The pitch data input and modulation data input signals are composed using the addition unit. Next, the signal undergoes sine wave transformation, and finally, it is multiplied by the envelope signal, and the result is output.
[diagram I-5-15]
Here we describe the operation of waveform composition in slots.
The sawtooth wave used as pitch data input is shaped as shown in diagram I-5-16, with a zoomed view in diagram I-5-17.
The sawtooth wave is output at a fixed time interval. Looking at the output values as an analog signal, it is a shape that could be called a discontinuous stair-step wave.
A counter is used to generate the output values. It counts according to the fixed-interval clock pulse, generating the sawtooth wave by increasing the output value. When the counter is full, the carry is ignored, and the count restarts again at zero, generating another period of the sawtooth wave with the same interval. In a case like diagram I-5-17 where the counter has four bits (16 steps), when the counter reaches 15 (0b1111), the carry into the fifth bit position at the next step is ignored and the counter returns to zero (0b0000).
The computation that transforms the composition of the modulation data input and pitch data input into a new waveform is easy to think about as a function in ROM, so below, we offer an explanation based on that idea. Specifically, if one considers a ROM where the value at each input address is the corresponding value of part of a sine wave, then simply by inputting the sawtooth wave into the ROM, a sine wave will be generated (diagrams I-5-18 and I-5-19).
In reality, a pure sawtooth wave is not the actual input; typically the modulation data input (another slot's modulation output) and pitch data input (sawtooth wave) are composed (diagram I-5-20) and the composed waveform is what gets sent to the ROM address lines, generating a new waveform (diagram I-5-21). Waveforms generated this way contain lots of harmonics (overtones), approximating natural sounds.
[diagram I-5-18]
[diagram I-5-19]
[diagram I-5-20]
[diagram I-5-21]
In music, when making a drum-like sound, the sound's buildup is sharp and it fades quickly, but to make a sound like playing a violin with a bow, the buildup is gentle, and it doesn't fade much at all. These sound differences are made by changing the sound amplitude. This is called the envelope, and there are the following elements to defining an envelope:
- Total level: maximum amplitude
- Attack: buildup length (in time)
- Decay: length of decline after attack (time)
- Sustain: pullback length (time)
- Sustain level: amplitude at start of pullback
- Release: trail-off time after key off (time)
In the FM sound source, the envelope input signal is what produces the envelope effect.
The envelope input signal is generated from the envelope generator circuit, and in the process, the level assignments of each element of the envelope shown in diagram I-5-22 can be set arbitrarily.
Slots have a switch for whether to connect their individual envelope signals, so each slot can select whether it has envelope modulation (multiplication by the envelope signal) performed.
Because the envelope gives the amplitude change over time, it is common to only give an envelope to the final slot, but it does not matter if other slots also use it. In that case, the subsequent slots' input signals' levels will be modified, and the timbre will change with time.
[diagram I-5-22]
As previously discussed, a channel is composed of four slots, and the timbre changes by the way that they are connected. Here, we describe how these connections are made.
The way slots are connected can be selected out of eight different groupings as shown in table I-5-18. These are called algorithms.
Connecting slots more in series generates a more complex waveform, which includes more harmonics and gives a brighter-feeling sound.
Alternatively, connecting slots in parallel allows triple or quadruple sounds to be composed in parallel, giving deeper and more interesting sounds. For example, organ-like sounds, or a sound like several instruments performing together are possible.
Grouping 4, as a midway point, is relatively easy to use for sound generation, since the result of two simple composition operators is easier to predict.
Slot 1 of each channel has its own output connected to its modulation data input (diagram I-5-23). This is called self-feedback.
The degree of feedback can be set arbitrarily.
Self-feedback combines sine waves and sawtooth waves, generating many harmonics and creating strong and provocative sounds.
[diagram I-5-23]
[table I-5-18]
Sound flutter is formed by intentionally shifting the pitch, strength, or other properties of the sound. In the FM TOWNS' FM sound generator, sound flutter uses an LFO (low frequency oscillator), so it can be performed at the hardware level.
To flutter the pitch, it is possible to change the frequency with detune and multiple, but on the FM TOWNS, detune and multiple aren't necessary; if they are used, they can be thought of as generating fixed gaps in the waveform (intentionally going out of tune).
By contrast, since the FM sound source used by previous FM series 8-bit models (YM2203) did not have an LFO, detune and multiple were controlled at software level.
For channel 3, each slot's frequency (pitch data input frequency) is independently settable. For details, please consult the sections about the internal registers that control the FM sound source.
The FM sound generator used by the FM TOWNS (YM2612) has two groups of internal registers.
One group is used to control channels 1 through 3, and the other group is used for channels 4 through 6.
The bit structure of the registers for channels 1 through 3 is shown in table I-5-19. The bit structure of the registers for channels 4 through 6 is also the same for internal addresses 0x30 through 0xB6.
0x21 through 0x2C control the entire FM sound generator, and 0x30 through 0x9E control individual slots.
0x30 through 0x9E control each of several channels and slots, and the relation between internal address and channel/slot is as shown in table I-5-20. Please note that there are numbers skipped on the way, and that the slot number order is 1, 3, 2, 4.
| Internal register | Bit structure | Description | Notes | |||||||
|---|---|---|---|---|---|---|---|---|---|---|
| b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | |||
| 0x21 | TEST | IC TEST DATA | Entire sound generator | |||||||
| 0x22 | TEST | LFO FREQ CONTROL | ||||||||
| 0x24 | TIMER-A | TIMER A HIGH 8 BITS | ||||||||
| 0x25 | TIMER-A | TIMER A LOW 8 BITS | ||||||||
| 0x26 | TIMER-A | TIMER B DATA | ||||||||
| 0x27 | MODE | RESET | ENABL | LOAD | TIMER-A/B CONTROL and CH 3 MODE | |||||
| B | A | B | A | B | A | |||||
| 0x28 | SLOT | CH | KEY ON/OFF | |||||||
| 0x2A | reserved | |||||||||
| 0x2B | ||||||||||
| 0x2C | TEST | IC TEST DATA | ||||||||
| 0x30-0x3E | DT | MULTI | Detune/Multiple (excludes addresses 0x33, 0x37, 0x3B) | Per slot | ||||||
| 0x40-0x4E | TL | Total Level (excludes addresses 0x43, 0x47, 0x4B) | ||||||||
| 0x50-0x5E | KS | AR | Key Scale/Attack Rate (excludes addresses 0x53, 0x57, 0x5B) | |||||||
| 0x60-0x6E | AM | DR | AMON/Decay Rate (excludes addresses 0x63, 0x67, 0x6B) | |||||||
| 0x70-0x7E | SR | Sustain rate (excludes addresses 0x73, 0x77, 0x7B) | ||||||||
| 0x80-0x8E | SL | RR | Sustain level/release (excludes addresses 0x83, 0x87, 0x8B) | |||||||
| 0x90-0x9E | SSG-EG | SSG-Type Envelope Control (excludes addresses 0x93, 0x97, 0x9B) | ||||||||
| 0xA0 | F-Num. 1 | F-Number/BLOCK | Per channel | |||||||
| 0xA1 | ||||||||||
| 0xA2 | ||||||||||
| 0xA4 | BLOCK | F-Num. 2 | ||||||||
| 0xA5 | ||||||||||
| 0xA6 | ||||||||||
| 0xA8 | CH 3 * F-Num. 1 | CH 3 Slots F-Number/BLOCK | Channel 3 special controls | |||||||
| 0xA9 | ||||||||||
| 0xAA | ||||||||||
| 0xAC | CH 3 * BLOCK | CH 3 * F-Num. 2 | ||||||||
| 0xAD | ||||||||||
| 0xAE | ||||||||||
| 0xB0 | FB | CONNECT | Self-Feedback/Connection | Per channel | ||||||
| 0xB1 | ||||||||||
| 0xB2 | ||||||||||
| 0xB4 | L | R | AMS | PMS | Output/flutter control | |||||
| 0xB5 | ||||||||||
| 0xB6 | ||||||||||
| Internal address | Channel | Slot |
| 0xX0 | 1 (4) | 1 |
| 0xX1 | 2 (5) | |
| 0xX2 | 3 (6) | |
| 0xX4 | 1 (4) | 3 |
| 0xX5 | 2 (5) | |
| 0xX6 | 3 (6) | |
| 0xX8 | 1 (4) | 2 |
| 0xX9 | 2 (5) | |
| 0xXA | 3 (6) | |
| 0xXC | 1 (4) | 4 |
| 0xXD | 2 (5) | |
| 0xXE | 3 (6) |
- Addresses except for 0xX3, 0xX7, 0xXB (where X is within 3 through 9) are assigned.
In order to write to the internal registers, four I/O registers are used, as shown in table I-5-21.
To read from or write to an FM sound generator register, the FM sound generator address register selects the internal address number, and after that, the data is written to (or read from) the FM sound generator data register.
Additionally, there are two groups of FM sound generator internal registers, for channels 1 through 3 and for channels 4 through 6, so two address registers and two data registers are provided.
The FM sound generator status register is composed of a BUSY bit, which indicates a condition where the registers cannot be written (writing prohibited when 1), and timer flags. The timer A and B flags can be consulted for their respective count-over conditions.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04D8 | FM sound generator status register | R | BUSY | undefined | FLAG B | FLAG A | ||||
| FM sound generator address register 0 | W | Timer, channel 1-3 address | ||||||||
| A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 | |||
| 0x04DA | FM sound generator data register 0 | W | Timer, channel 1-3 write data | |||||||
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |||
| 0x04DC | FM sound generator address register 1 | W | Channel 4-6 address | |||||||
| A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 | |||
| 0x04DE | FM sound generator data register 1 | W | Channel 4-6 write data | |||||||
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |||
Here, we describe the set of internal registers numbered (address) 0x21 through 0x2C.
0x21 and 0x2C are used for manufacturer testing, so when a user program is initializing, all of their bits are set to zero.
The LFO is used for pitch (or amplitude) flutter. The register's bit structure is shown in table I-5-22. When using the LFO, the LFO bit is set to 1, and the frequency is set by the FREQ-CTRL field.
The greater the frequency value, the greater the rate of flutter over time.
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x22 | LFO | FREQ-CTRL | ||||||
-
LFO (bit 3): LFO is on when set to 1.
-
FREQ-CTRL (bit 0-2): Sets the frequency according to the following:
FREQ-CTRL: 0 1 2 3 4 5 6 7 Freq (Hz): 3.98 5.56 6.02 6.37 6.88 9.63 48.1 72.2
The timer is used with the aim of counting the time from key-on to key-off. This way, the timer triggers an interrupt when its full count is reach so that the CPU does not need to track the length of the sound and can do other work.
Concretely, at key-on time, the timer is set so that an interrupt occurs at key-off time. The CPU can then perform the key-off operation to control the length of the sound.
Controlling many instrument sounds playing at the same time would be troublesome with only one timer when the sounds' lengths differ, so the FM sound source has two timers to address this problem. Timer A is used for short time intervals, and timer B for long time intervals. When timer B is not being used for audio, it is also used to read the mouse.
To configure the timer, register numbers 0x24 through 0x26 (table I-5-23) are used.
Timer A is an 10-bit presettable type (timer period set beforehand), and B is an 8-bit type. The 10 bits of A are composed of the initial value (NA) in register 0x24 (top 8 bits) and register 0x25 (low 2 bits). B's initial value (NB) is directly set by the value of register 0x26.
The timer adds one to the initial value at a fixed interval, and when it reaches the point where it carries out of the highest digit, the FM sound source status register's flag is set (becomes 1). This is when the interrupt occurs.
The time for each timer can be calculated by:
- TA = (12*(1024 - NA)/(internal clock frequency in KHz)) ms
- TB = (192*(256 - NA)/(internal clock frequency in KHz)) ms
The internal clock frequency is 600KHz.
Timer control is handled by register 0x27 (table I-5-24).
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x24 | NA | |||||||
| 0x25 | NA | |||||||
| 0x26 | NB | |||||||
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x27 | MODE | RESET | ENABL | LOAD | ||||
| B | A | B | A | B | A | |||
-
MODE (bit 6-7): Sets the channel 3 mode.
Setting Mode Meaning 0 0 Normal Sets channel 3 to normal sound generation mode. Play frequency is set by the 0xA2 and 0xA6 registers. 1 0 Sound effects Sets channel 3 to sound effects mode. Each slot's frequency can be individually configured. Slot 1 uses 0xA9 and 0xAD, slot 2 uses 0xAA and 0xAE, slot 3 uses 0xA8 and 0xAC, and slot 4 uses 0xA2 and 0xA6. 0 1 Voice synthesis Frequency generation behaves in the same manner as for sound effects mode, but channel 3's key on/off is also controlled by timer A, so that loading timer A performs key on, and key off is performed when the count finishes. -
RESET (bit 4-5): 1 = reset the timer flag
-
ENABL (bit 2-3): 1 = let the flag become 1 the timer count completes
-
LOAD (bit 0-1): 1 = load the configured value into the time and begin the count
When one of the load bits is set to 1, then the corresponding counter A and/or B will be given the initial value NA and/or NB, and the count will begin.
When an ENABL bit is 1, and the corresponding counter carries out of its highest digit, then the corresponding bit (A or B) in the FM sound source status register is set to 1. To clear a flag, the corresponding reset bit is set to 1. This operation has the meaning of replying to the flag, so the reset bit itself is also immediately cleared.
The MODE field is set to use channel 3's special abilities. To set the mode, bits 6 and 7 of register 0x27 are used.
Key on/off control can be set individually for each channel using internal register 0x28 (table I-5-25). Key on/off refers to the begin and end of a music note. Please note that the release interval still remains after key-off.
The bottom three bits select channel 1 through 6, and the top three bits select slot 1 through 4. For example, if one wants to set key-on for channel 4, slots 1 and 3, 0b0101_X100 is set. It does not matter if bit 3 is zero or one.
Note that registers 0x2A and 0x2B are reserved by the system and cannot be used by the user.
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x28 | SLOT | CH | ||||||
| 4 | 3 | 2 | 1 | |||||
-
Selects the slots and channels for key on/off.
-
SLOT (bit 4-7): The slot corresponding to each 1 bit is set ON.
-
CH (bit 0-2): Selects the channel.
CH Channel number 0 0 0 1 0 0 1 2 0 1 0 3 1 0 0 4 1 0 1 5 1 1 0 6
Here, we describe registers numbered 0x30 through 0x9E, which configure per-slot settings.
The pitch input to a slot (sawtooth wave) can have its frequency altered, intentionally causing a change in pitch.
The DETUNE setting slightly shifts each slot's frequency. The MULTIPLE shifts the audio by multiplying the detune amount by an integer ratio.
These settings are made using internal registers 0x30 through 0x3E (excluding 0x33, 0x37, and 0x3B).
The bit structure of DETUNE and MULTIPLE is shown in table I-5-26.
The highest bit of DETUNE (bit 6) indicates the sign, zero being positive (addition) and 1 being negative (subtraction). The correspondence between detune value and note shift is as shown in table I-5-27; it changes depending on the note block and note.
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x30-0x3E | DETUNE | MULTIPLE | ||||||
-
Excludes 0x33, 0x37, and 0x3B. For detune, bit 6 indicates the sign, and bits 4 and 5 indicate the absolute value (0-3).
-
DETUNE (bits 4-6): Sets the detune level. The relationship between the setting value and detune amount is indicated in table I-5-27.
-
MULTIPLE (bits 0-3): Sets the multiplier for the detune level.
Setting: 0 1 2 3 4 5 6 7 8 9 A B C D E F Multiplier: 1/2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
| BLOCK | NOTE | Cents | Frequency | ||||||
|---|---|---|---|---|---|---|---|---|---|
| Detune (lowest 2 bits) | Detune (lowest 2 bits) | ||||||||
| 0 | 1 | 2 | 3 | 0 | 1 | 2 | 3 | ||
| 0 | 0 | 0.000 | 0.000 | 4.491 | 8.970 | 0.000 | 0.000 | 0.048 | 0.095 |
| 0 | 1 | 0.000 | 0.000 | 3.784 | 7.580 | 0.000 | 0.000 | 0.048 | 0.095 |
| 0 | 2 | 0.000 | 0.000 | 3.479 | 6.353 | 0.000 | 0.000 | 0.048 | 0.095 |
| 0 | 3 | 0.000 | 0.000 | 2.674 | 5.343 | 0.000 | 0.000 | 0.048 | 0.095 |
| 1 | 0 | 0.000 | 2.247 | 4.491 | 4.491 | 0.000 | 0.048 | 0.095 | 0.095 |
| 1 | 1 | 0.000 | 1.891 | 3.780 | 5.667 | 0.000 | 0.048 | 0.095 | 0.143 |
| 1 | 2 | 0.000 | 1.590 | 3.179 | 4.767 | 0.000 | 0.048 | 0.095 | 0.143 |
| 1 | 3 | 0.000 | 1.337 | 2.874 | 4.009 | 0.000 | 0.048 | 0.095 | 0.143 |
| 2 | 0 | 0.000 | 1.124 | 2.247 | 4.491 | 0.000 | 0.048 | 0.095 | 0.191 |
| 2 | 1 | 0.000 | 0.346 | 2.836 | 3.780 | 0.000 | 0.048 | 0.143 | 0.191 |
| 2 | 2 | 0.000 | 0.795 | 2.395 | 3.179 | 0.000 | 0.048 | 0.143 | 0.191 |
| 2 | 3 | 0.000 | 0.663 | 2.006 | 3.342 | 0.000 | 0.048 | 0.143 | 0.238 |
| 3 | 0 | 0.000 | 1.124 | 2.247 | 2.808 | 0.000 | 0.095 | 0.191 | 0.238 |
| 3 | 1 | 0.000 | 0.346 | 1.891 | 2.836 | 0.000 | 0.095 | 0.191 | 0.286 |
| 3 | 2 | 0.000 | 0.795 | 1.590 | 2.385 | 0.000 | 0.095 | 0.191 | 0.288 |
| 3 | 3 | 0.000 | 0.668 | 1.672 | 2.340 | 0.000 | 0.095 | 0.238 | 0.334 |
| 4 | 0 | 0.000 | 0.562 | 1.405 | 2.247 | 0.000 | 0.085 | 0.238 | 0.381 |
| 4 | 1 | 0.000 | 0.709 | 1.418 | 1.891 | 0.000 | 0.143 | 0.286 | 0.381 |
| 4 | 2 | 0.000 | 0.597 | 1.193 | 1.769 | 0.000 | 0.143 | 0.298 | 0.429 |
| 4 | 3 | 0.000 | 0.502 | 1.170 | 1.672 | 0.000 | 0.143 | 0.334 | 0.477 |
| 5 | 0 | 0.000 | 0.562 | 1.124 | 1.545 | 0.000 | 0.191 | 0.381 | 0.525 |
| 5 | 1 | 0.000 | 0.473 | 0.946 | 1.418 | 0.000 | 0.191 | 0.381 | 0.572 |
| 5 | 2 | 0.000 | 0.398 | 0.895 | 1.232 | 0.000 | 0.191 | 0.429 | 0.620 |
| 5 | 3 | 0.000 | 0.418 | 0.836 | 1.170 | 0.000 | 0.238 | 0.477 | 0.668 |
| 6 | 0 | 0.000 | 0.351 | 0.773 | 1.124 | 0.000 | 0.238 | 0.525 | 0.763 |
| 6 | 1 | 0.000 | 0.555 | 0.709 | 1.005 | 0.000 | 0.286 | 0.672 | 0.811 |
| 6 | 2 | 0.000 | 0.298 | 0.646 | 0.945 | 0.000 | 0.286 | 0.520 | 0.906 |
| 6 | 3 | 0.000 | 0.283 | 0.585 | 0.835 | 0.000 | 0.334 | 0.668 | 0.354 |
| 7 | 0 | 0.000 | 0.281 | 0.562 | 0.773 | 0.000 | 0.391 | 0.763 | 1.049 |
| 7 | 1 | 0.000 | 0.236 | 0.473 | 0.650 | 0.000 | 0.391 | 0.763 | 1.049 |
| 7 | 2 | 0.000 | 0.199 | 0.399 | 0.547 | 0.000 | 0.391 | 0.763 | 1.049 |
| 7 | 3 | 0.000 | 0.167 | 0.334 | 0.480 | 0.000 | 0.381 | 0.763 | 1.049 |
- NOTE = N4 * 2 + N3
where N4 = F11, N3 = F11 * (F10 + F9 + F8) + /F11 * F10 * F9 * F8
F8-F11 indicate bit numbers from the F-number value.
Total level is the level at the peak of a sound's buildup. Table I-5-28 shows the total level bit structure. Each bit corresponds to an additional attenuation amount.
For example, when bits 3 and 4 are set to 1, then
12 + 6 = 18 (dB)
The larger this value is, the lower the volume becomes.
Changing the total level normally must happen after note key-off when the sound has stopped. Otherwise, as shown in diagram I-5-24, an unnatural envelope change will occur. However, in voice synthesis mode, the change will take effect with the next key-on, so this is not a concern.
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x40-0x4E | TOTAL LEVEL | |||||||
-
Excludes 0x43, 0x47, and 0x4B.
-
TOTAL LEVEL (bits 0-6): Selects the attenuation level.
Bit: 6 5 4 3 2 1 0 Attenuation (dB) 48 24 12 6 3 1.5 0.75
[diagram I-5-24]
The bit structure of the envelope parameters is shown in table I-5-29.
Keyscale (KS) is used to vary the envelope by pitch, so that each element of the envelope's rate changes with each note's pitch. Typically, this is used to make higher-pitched notes' envelopes change more quickly. The relationship between the modified and original rate is as follows:
- modified rate = original rate * 2 + (table I-5-30 referenced value)
The keycode in table I-5-30 is the NOTE value from table I-5-27 added to four times the BLOCK value, indicating the pitch value. Note that as an exception, when the original rate is 0, the modified rate is also 0.
Attack rate determines the buildup, decay rate the decline after the buildup, sustain rate the level to hold afterward, and release rate the linger time after key off.
The relation of these setting values to time is shown in table I-5-31.
In this table, the 0dB-96dB and 10%-90% columns both indicate the relationship between the rate value and the time needed for the indicated change.
The sustain level value indicates the level the note ultimately decays to relative to the total level. Each bit indicates an attenuation amount as shown in table I-5-32. The setting values are determined by referencing table I-5-31.
The release rate is determined by consulting table I-5-31 with the rate value formed by doubling the 4-bit setting value and adding 1.
The seventh bit of registers 0x6B through 0x6E enables or disables amplitude modulation per slot. 1 means on, and 0 means off. For more information about amplitude modulation, please reference the frequency and amplitude modulation settings.
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| 0x50-0x5E | KS | ATTACK RATE | |||||||
| 0x60-0x6E | AMON | DECAY RATE | |||||||
| 0x70-0x7E | SUSTAIN RATE | ||||||||
| 0x80-0x8E | SUSTAIN LEVEL | RELEASE RATE | |||||||
- Excludes 0xX3, 0xX7, and 0xXB.
| KS value | Key code | |||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 2 | 2 | 2 | 2 | 3 | 3 | 3 | 3 | 4 | 4 | 4 | 4 | 5 | 5 | 5 | 5 | 6 | 6 | 6 | 6 | 7 | 7 | 7 | 7 |
| 2 | 0 | 0 | 1 | 1 | 2 | 2 | 3 | 3 | 4 | 4 | 5 | 5 | 6 | 6 | 7 | 7 | 8 | 8 | 9 | 9 | 10 | 10 | 11 | 11 | 12 | 12 | 13 | 13 | 14 | 14 | 15 | 15 |
| 3 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
- Key code = BLOCK * 4 + NOTE
| Attack time | |||
| Rate | msec (0dB-96dB) | msec (10%-90%) | |
| 15 | 3 | 0.00 | 0.00 |
| 15 | 2 | 0.00 | 0.00 |
| 15 | 1 | 0.60 | 0.26 |
| 15 | 0 | 0.60 | 0.26 |
| 14 | 3 | 0.72 | 0.32 |
| 14 | 2 | 0.84 | 0.37 |
| 14 | 1 | 1.01 | 0.46 |
| 14 | 0 | 1.26 | 0.61 |
| 13 | 3 | 1.37 | 0.70 |
| 13 | 2 | 1.60 | 0.92 |
| 13 | 1 | 1.92 | 0.99 |
| 13 | 0 | 2.40 | 1.25 |
| 12 | 3 | 2.50 | 1.40 |
| 12 | 2 | 2.32 | 1.65 |
| 12 | 1 | 3.50 | 1.94 |
| 12 | 0 | 4.38 | 2.41 |
| 11 | 3 | 5.01 | 2.77 |
| 11 | 2 | 5.84 | 3.25 |
| 11 | 1 | 7.01 | 3.91 |
| 11 | 0 | 8.76 | 4.97 |
| 10 | 3 | 10.01 | 5.54 |
| 10 | 2 | 11.68 | 6.50 |
| 10 | 1 | 14.02 | 7.82 |
| 10 | 0 | 17.52 | 9.74 |
| 9 | 3 | 20.02 | 11.09 |
| 9 | 2 | 23.35 | 13.01 |
| 9 | 1 | 29.03 | 15.65 |
| 9 | 0 | 35.04 | 19.49 |
| 8 | 3 | 40.05 | 22.18 |
| 8 | 2 | 48.72 | 26.02 |
| 8 | 1 | 58.06 | 31.30 |
| 8 | 0 | 70.08 | 38.99 |
| 7 | 3 | 80.09 | 44.35 |
| 7 | 2 | 93.44 | 52.03 |
| 7 | 1 | 112.13 | 62.59 |
| 7 | 0 | 140.16 | 77.95 |
| 6 | 3 | 160.18 | 86.70 |
| 6 | 2 | 186.88 | 104.06 |
| 6 | 1 | 224.25 | 125.18 |
| 6 | 0 | 280.32 | 155.90 |
| 5 | 3 | 320.37 | 177.41 |
| 5 | 2 | 373.76 | 208.13 |
| 5 | 1 | 448.51 | 250.37 |
| 5 | 0 | 560.64 | 311.81 |
| 4 | 3 | 640.73 | 354.82 |
| 4 | 2 | 747.52 | 416.25 |
| 4 | 1 | 837.02 | 500.74 |
| 4 | 0 | 1121.28 | 623.62 |
| 3 | 3 | 1281.46 | 709.63 |
| 3 | 2 | 1495.04 | 832.51 |
| 3 | 1 | 1734.05 | 1001.47 |
| 3 | 0 | 2242.56 | 1247.23 |
| 2 | 3 | 2582.93 | 1419.26 |
| 2 | 2 | 2990.08 | 1665.02 |
| 2 | 1 | 3588.10 | 2002.94 |
| 2 | 0 | 4485.12 | 2494.46 |
| 1 | 3 | 5980.16 | 3330.05 |
| 1 | 2 | 5980.16 | 3330.05 |
| 1 | 1 | 8970.24 | 4688.91 |
| 1 | 0 | 8970.24 | |
| Sustain/decay/release time | |||
| Rate | msec (0dB-96dB) | msec (10%-90%) | |
| 15 | 3 | 7.57 | 1.52 |
| 15 | 2 | 7.57 | 1.52 |
| 15 | 1 | 7.57 | 1.52 |
| 15 | 0 | 7.57 | 1.52 |
| 14 | 3 | 8.65 | 1.73 |
| 14 | 2 | 10.09 | 2.03 |
| 14 | 1 | 12.11 | 2.43 |
| 14 | 0 | 15.14 | 3.05 |
| 13 | 3 | 17.30 | 3.50 |
| 13 | 2 | 20.18 | 4.07 |
| 13 | 1 | 24.22 | 4.80 |
| 13 | 0 | 30.27 | 5.09 |
| 12 | 3 | 34.59 | 6.96 |
| 12 | 2 | 40.56 | 8.10 |
| 12 | 1 | 48.43 | 9.75 |
| 12 | 0 | 60.54 | 12.18 |
| 11 | 3 | 69.19 | 13.92 |
| 11 | 2 | 80.72 | 16.20 |
| 11 | 1 | 96.86 | 19.50 |
| 11 | 0 | 121.08 | 24.36 |
| 10 | 3 | 139.38 | 27.84 |
| 10 | 2 | 161.44 | 32.40 |
| 10 | 1 | 193.73 | 39.00 |
| 10 | 0 | 242.16 | 48.72 |
| 9 | 3 | 276.75 | 55.68 |
| 9 | 2 | 322.98 | 64.80 |
| 9 | 1 | 387.45 | 78.00 |
| 9 | 0 | 484.32 | 97.44 |
| 8 | 3 | 553.51 | 111.36 |
| 8 | 2 | 645.76 | 129.60 |
| 8 | 1 | 774.91 | 158.00 |
| 8 | 0 | 968.64 | 194.88 |
| 7 | 3 | 1107.02 | 222.72 |
| 7 | 2 | 1291.52 | 259.20 |
| 7 | 1 | 1549.82 | 312.00 |
| 7 | 0 | 1937.28 | 388.76 |
| 6 | 3 | 2214.03 | 445.44 |
| 6 | 2 | 2583.04 | 518.40 |
| 6 | 1 | 3099.65 | 624.00 |
| 6 | 0 | 3874.55 | 779.52 |
| 5 | 3 | 4428.07 | 890.88 |
| 5 | 2 | 5166.08 | 1036.80 |
| 5 | 1 | 6199.30 | 1248.00 |
| 5 | 0 | 7749.12 | 1559.04 |
| 4 | 3 | 8856.14 | 1781.75 |
| 4 | 2 | 10332.15 | 2073.60 |
| 4 | 1 | 12398.59 | 2496.00 |
| 4 | 0 | 15498.24 | 3118.08 |
| 3 | 3 | 17712.27 | 3563.52 |
| 3 | 2 | 20664.32 | 4147.20 |
| 3 | 1 | 24797.19 | 4982.00 |
| 3 | 0 | 30996.48 | 6236.16 |
| 2 | 3 | 35424.55 | 7124.04 |
| 2 | 2 | 41328.64 | 8234.40 |
| 2 | 1 | 49534.37 | 9984.00 |
| 2 | 0 | 51992.96 | 12472.32 |
| 1 | 3 | 82657.28 | 16588.80 |
| 1 | 2 | 82657.26 | 16588.80 |
| 1 | 1 | 123985.92 | 24914.84 |
| 1 | 0 | 123985.92 | |
| Bit: | 7 | 6 | 5 | 4 |
|---|---|---|---|---|
| Attenuation (dB) | 24 | 12 | 6 | 3 |
- However, when all of bits 4-7 are set to 1, the attenuation is 93dB.
The FM sound source can perform SSG-type (simple waveform output like an older type of sound generator) envelope control. The waveform codes for this mode are as shown in table I-5-33, corresponding to the SSG-TYPE value from the internal registers.
Note that the attack rate must normally be 0x1F in this mode, except when using the waveforms marked with *, for which any value according to table I-5-31 can be given.
The SSG-type attenuation times are as shown in table I-5-34.
SSG-type attack rate and decay rate are each set using internal registers 0x50 through 0x5E and 0x60 through 0x6E.
An SSG-type waveform is either a sawtooth or triangle wave. The way to think about decay rate and sustain rate changes between rise and fall as shown in diagram I-5-25, so please be careful.
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
| 0x90-0x9E | KS | SSG-TYPE | ||||||||
-
Excludes 0x93, 0x97, and 0x9B.
SSG-TYPE Envelope waveform 1 0 0 0* ` 1 0 0 1* ` 1 0 1 0 ` 1 0 1 1* ` 1 1 0 0 `/ 1 1 0 1 /¯¯¯¯¯¯¯¯¯1 1 1 0 /\/\/\/\/\1 1 1 1 `/
| Decay time | |||
| Rate | msec (0dB-96dB) | msec (10%-90%) | |
| 15 | 3 | 0.96 | 0.38 |
| 15 | 2 | 0.96 | 0.38 |
| 15 | 1 | 0.96 | 0.38 |
| 15 | 0 | 0.96 | 0.38 |
| 14 | 3 | 1.10 | 0.42 |
| 14 | 2 | 1.28 | 0.50 |
| 14 | 1 | 1.54 | 0.58 |
| 14 | 0 | 1.92 | 0.76 |
| 13 | 3 | 2.19 | 0.85 |
| 13 | 2 | 2.56 | 1.02 |
| 13 | 1 | 3.07 | 1.21 |
| 13 | 0 | 3.84 | 1.52 |
| 12 | 3 | 4.39 | 1.73 |
| 12 | 2 | 5.12 | 2.03 |
| 12 | 1 | 6.14 | 2.42 |
| 12 | 0 | 7.68 | 3.05 |
| 11 | 3 | 8.78 | 3.46 |
| 11 | 2 | 10.24 | 3.07 |
| 11 | 1 | 12.29 | 4.85 |
| 11 | 0 | 15.36 | 6.11 |
| 10 | 3 | 17.55 | 6.93 |
| 10 | 2 | 20.48 | 8.13 |
| 10 | 1 | 24.58 | 9.69 |
| 10 | 0 | 30.72 | 12.21 |
| 9 | 3 | 35.11 | 13.86 |
| 9 | 2 | 40.96 | 16.26 |
| 9 | 1 | 49.15 | 19.38 |
| 9 | 0 | 61.44 | 24.42 |
| 8 | 3 | 70.22 | 27.72 |
| 8 | 2 | 81.92 | 32.52 |
| 8 | 1 | 98.30 | 38.76 |
| 8 | 0 | 122.88 | 48.84 |
| 7 | 3 | 140.43 | 55.44 |
| 7 | 2 | 163.84 | 65.04 |
| 7 | 1 | 196.61 | 77.52 |
| 7 | 0 | 245.76 | 97.68 |
| 6 | 3 | 280.97 | 110.88 |
| 6 | 2 | 327.68 | 130.08 |
| 6 | 1 | 393.22 | 155.04 |
| 6 | 0 | 491.52 | 195.38 |
| 5 | 3 | 561.74 | 221.76 |
| 5 | 2 | 655.36 | 260.16 |
| 5 | 1 | 786.43 | 310.08 |
| 5 | 0 | 983.94 | 390.72 |
| 4 | 3 | 1123.47 | 443.52 |
| 4 | 2 | 1310.72 | 520.32 |
| 4 | 1 | 1572.86 | 620.16 |
| 4 | 0 | 1966.08 | 781.44 |
| 3 | 3 | 2246.95 | 887.04 |
| 3 | 2 | 2621.44 | 1040.54 |
| 3 | 1 | 3145.73 | 1240.32 |
| 3 | 0 | 3932.16 | 1562.88 |
| 2 | 3 | 4493.90 | 1774.08 |
| 2 | 2 | 5242.98 | 2081.28 |
| 2 | 1 | 6291.46 | 2480.64 |
| 2 | 0 | 7864.32 | 3125.76 |
| 1 | 3 | 10485.76 | 4162.56 |
| 1 | 2 | 10485.76 | 4162.56 |
| 1 | 1 | 15728.64 | 6251.52 |
| 1 | 0 | 15728.64 | 6251.52 |
[diagram I-5-25]
Here, we describe the subset of registers used for per-channel settings.
The FM sound generator pitch (the generated frequency of the pitch data input) for each channel is set using internal registers 0xA0 through 0xA6 (excluding 0xA3) (table I-5-35).
BLOCK indicates the octave, selected from eight octaves. The BLOCK value (three bits, 1 through 7) is set to the same value as the octave value (1 through 8) except in the case of octave 8.
The F-number indicates the frequency offset within the octave using an 11-bit frequency code.
The relationship between each A note and each BLOCK is shown in table I-5-36, and the relationship between notes and their F-numbers is shown in table I-5-37.
Diagram I-5-26 shows examples of pitch settings.
When setting the pitch, first write the BLOCK and top three bits of the F-number (F-number2), and then write the bottom eight bits (F-number1). Getting this order wrong can lead to the incorrect setting.
Setting the pitch for channels 4, 5, and 6 also follows the same method.
If channel 3 is in sound effect mode or voice synthesis mode, then each slot's frequency can be set as shown in table I-5-38.
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Channel |
| 0xA0-0xA2 | F-Number 1 | 1-3 (4-6) | |||||||
| 0xA4-0xA6 | BLOCK | F-Number 2 | 1-3 (4-6) | ||||||
| A note | Frequency | BLOCK | Octave |
|---|---|---|---|
| A8 | 7040.0 | * | 8 |
| A7 | 3520.0 | 7 | 7 |
| A6 | 1760.0 | 6 | 6 |
| A5 | 880.0 | 5 | 5 |
| A4 | 440.0 | 4 | 4 |
| A3 | 220.0 | 3 | 3 |
| A2 | 110.0 | 2 | 2 |
| A1 | 55.0 | 1 | 1 |
- The * setting is configured with BLOCK = 7 and MULTIPLE = 2.
| Note | Frequency | F-number value |
|---|---|---|
| C5 | 523.3 | 1371 |
| B4 | 493.9 | 1294 |
| A♯4 | 466.2 | 1222 |
| A4 | 440.0 | 1153 |
| G♯4 | 415.3 | 1088 |
| G4 | 392.0 | 1027 |
| F♯4 | 370.0 | 969 |
| F4 | 349.2 | 915 |
| E4 | 329.6 | 864 |
| D♯4 | 311.1 | 815 |
| D4 | 293.7 | 769 |
| C♯4 | 277.2 | 726 |
- The F-number value stays the same if the BLOCK changes.
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Channel | Slot |
| 0xA2 | F-Number 1 | 3 | 4 | |||||||
| 0xA6 | BLOCK | F-Number 2 | 3 | 4 | ||||||
| 0xA8 | F-Number 1 | 3 | 3 | |||||||
| 0xA9 | F-Number 1 | 3 | 1 | |||||||
| 0xAA | F-Number 1 | 3 | 2 | |||||||
| 0xAC | BLOCK | F-Number 2 | 3 | 3 | ||||||
| 0xAD | BLOCK | F-Number 2 | 3 | 1 | ||||||
| 0xAE | BLOCK | F-Number 2 | 3 | 2 | ||||||
[diagram I-5-26]
The structure of the slot 1 self-feedback and connection bits is shown in table I-5-39.
Self-feedback refers to slot 1's ability to send its output back into its own input.
The slot connection, also referred to as the algorithm, is set to one of the algorithm pattern numbers indicated in diagram I-5-17.
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Channel |
| 0xB0-0xB2 | Self-feedback | Connection | 1-3 (4-6) | ||||||
-
Self-feedback (bit 3-5): Sets the feedback amount.
Setting: 0 1 2 3 4 5 6 7 Feedback: OFF π/16 π/8 π/4 π/2 π 2π 4π
Amplitude modulation produces vibrato, and frequency modulation produces tremolo.
For these settings, the amplitude modulation strength (AMS) and phase modulation strength (PMS) fields shown in table I-5-40 are used.
Phase modulation is also called frequency modulation.
| Internal address | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Channel |
| 0xB4-0xB6 | L | R | AMS | PMS | 1-3 (4-6) | ||||
-
L, R (bits 7, 6): Sets whether output occurs on each line.
- 0: No output
- 1: Output
-
AMS (bits 4-5): Sets the degree of amplitude modulation.
AMS: 0 1 2 3 Modulation (dB): 0 1.4 5.9 11.8 -
PMS (bits 0-2): Sets the degree of phase modulation.
PMS: 0 1 2 3 4 5 6 7 Modulation (cents): 0 ±3.4 ±6.7 ±10 ±14 ±20 ±40 ±80
Each channel can output to either the left, right, or both lines. The modulation settings registers' bits 6 and 7 are used for this setting. Bit 7 is left (L), and bit 6 is right (R) line output, with a value of 1 meaning output, and a value of 0 meaning no output. Setting both bits to 1 is allowed in order to output to both lines.
This method allows for positioning to the left, right, or center, but not for subtle "left-facing" or "right-facing" settings. Additionally, in center position, the total level will be doubled compared to playing only one side, so the channel volume may be too high. One can increase the total level attenuation (for example by 6dB = half volume) to compensate.
The LEDs on the front panel of the FM TOWNS chassis have the function of displaying the speaker (or headphone) output signal level and volume setting level.
In this section, we explain the LEDs and their functionality.
The LEDs display the momentary speaker (or headphone) output signal level.
Additionally, the speaker (or headphone) volume setting level is shown. Volume setting is performed by the UP/DOWN buttons, and pressing these buttons shows the volume setting level for a few seconds.
The block structure of the LED lighting structure is shown in diagram I-5-27.
The relationship between output signal level and the lighting of the five LEDs is as shown in table I-5-41, lighting like a bar graph corresponding to the signal strength.
The volume setting level is shown in the same manner. Furthermore, if the UP/DOWN volume buttons are pressed during output signal display, the volume setting level is shown for several seconds, after which the output signal level display returns.
| Audio signal size | LED0 | LED1 | LED2 | LED3 | LED4 |
|---|---|---|---|---|---|
| low ↑ middle ↓ high |
1 | 1 | 1 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 | |
| 0 | 0 | 1 | 1 | 1 | |
| 0 | 0 | 0 | 1 | 1 | |
| 0 | 0 | 0 | 0 | 1 | |
| 0 | 0 | 0 | 0 | 0 |
To control the LEDs, the audio register (table I-5-42) is used.
The display control bit sets whether LED lighting occurs or not. When set to 1, lighting control stops.
The mute bit is not in and of itself an LED control, but sets whether audio output is forbidden or not. When set to zero, audio output completely stops, so LED lighting also stops. At reset time, this bit is zero, so in order for audio output to occur, it must be set to 1. This bit is also useful for temporarily stopping audio output. For example, to eliminate the "snap" noise at power off, this bit can be used.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04EC | Audio register | R | LOFF | MUTE | undefined | |||||
| W | 1 | 1 | 1 | 1 | 1 | 1 | ||||
- LOFF (bit 7): Sets whether to use the audio level indicator.
- 0: Use
- 1: Do not use
- MUTE (bit 6): Sets whether audio output occurs.
- 0: No output
- 1: Output
The FM TOWNS has circuits to individually mute the FM and PCM sound generators. The FM/PCM mute register (table I-5-43) is used to mute and unmute these generators.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04D5 | FM/PCM mute register | R | undefined | FM MUTE | PCM MUTE | |||||
| W | 0 | 0 | 0 | 0 | 0 | 0 | ||||
- PCM MUTE: When zero, the PCM sound generator is muted.
- FM MUTE: When zero, the FM sound generator is muted.
A CD-ROM is external storage equipment, using the same media as audio CDs to record computer data.
The formatted storage size of a CD-ROM is 540MB. [Translator's note: a standard CD-ROM is typically considered to have a capacity of at least 650MB.] This storage size is a dramatic increase by comparison with floppy disks and hard disks used as computer external storage equipment. For example, encyclopedias with vast amounts of text and image data are stored on CD-ROM, with the ability to freely search them. Furthermore, a single CD-ROM can contain not only computer data (text, image, or program data) but also music data (data recorded in the same way as a CD), being able to also play the music off the disc.
In this chapter, we describe the CD-ROM format, the hardware mechanism the CD-ROM drive reads with, and the internal registers that control the CD-ROM drive.
Note that a CD-ROM drive works the same way regardless of whether it is used with a music CD or CD-ROM, so in this book's description, we refer to it as a CD drive.
In this chapter, we describe how data is stored on a CD-ROM. However, the CD-ROM format is extremely complex, so for the sake of space in this book, we limit ourselves to describing the fundamentals.
A CD-ROM is only written on one side.
The smallest unit of data storage in a CD-ROM is called a sector. One CD-ROM holds approximately 270,000 sectors [translator's note: 333,000 sectors or more is usually considered standard].
On floppy disks and hard disks, sectors are structured as shown in diagram I-6-1, in concentric circles, with sectors on the outside physically longer than sectors on the inside. As a result, by reading and writing at a fixed rate of rotation, the time needed to read a sector is the same for inner and outer sectors, and data is always accessed at a fixed speed.
By contrast, CD-ROM sectors, exactly like a music CD, are arranged in a spiral from the inside to the outside as shown in diagram I-6-2. Every sector is also the same physical length. In this way, data is recorded at a fixed density across the entire disk.
Since all sectors have the same physical length, the number of sectors per track increases the further outward the tracks go. Because of this, in order for the CD-ROM to read data at the same speed (move the head at fixed linear speed), the rotation speed lowers for outer tracks and increases for inner tracks.
This style of data storage allows for free reading of sequential data, such as when playing from a music CD, but for random access into a CD-ROM, it causes some problems. Specifically, during random access, the read head has to frequently go back and forth between inner and outer tracks, and the disk rotation speed has to change each time; moreover, it is necessary to wait until the speed settles with each change, making seeks take additional time.
[diagram I-6-1]
[diagram I-6-2]
The FM TOWNS CD-ROM's logical data format currently mostly follows the typical ISO 9660 standard.
ISO 9660 (CD-ROM volume and file structure for information exchange) specifies the recording format and file structure for the CD-ROM standard.
An address, in addition to a time value as a physical address, is specified by a 2,048-byte (or any greater power of two bytes) logical sector. The space on the CD-ROM is further divided into blocks as shown in diagram I-6-3. The blocks from 0 through 15 are used as the system region, with how they are used entrusted to the system. The area from logical sector 16 onwards is called the data region, and the files and directories are arranged after the volume descriptor, path table, root directory, and other file management information.
[diagram I-6-3]
Diagram I-6-4 shows the formats a sector (also referred to as data block) can take.
CD-ROM data blocks have two formats, Mode 1 or Mode 2.
Mode 2 is used for music CD storage, but CD-ROMs can also use it. Mode 1 is unique to the CD-ROM format.
In mode 2, starting from the beginning of the block, a sync signal, ID, and the data contents are stored in order. The sync signal is used to maintain synchronization for correctly playing sequential data.
The ID indicates the sector position. It is a logical position within the CD-ROM. On a CD, 1/75 of a second (one frame) of music data is stored per sector, and a sector is identified by the number of minutes, seconds, and frames from the beginning of the CD to the indicated sector. On a CD-ROM, even when data other than music is recorded, sectors are still identified using this same method.
The first byte of the ID indicates the minute, the second byte the second, and the third byte the frame. The fourth byte indicates the mode of the data block format.
The data region has 2,336 bytes. This is where computer or music data is recorded.
Mode 1 adds error correction functionality to Mode 2. For this reason, its data region is reduced to 2,048 bytes, with 288 bytes used for error detection and correction. Within those 288 bytes is a four-byte EDC (error detection code) used for error detection. The ECC (error correction code) is 276 bytes. The EDC contents are checked by the CD controller, and if necessary, error status notifications are handled by automatic correction using the ECC.
Mode 1 is used for recording data that cannot permit errors (programs, etc.), and mode 2 is used for recording music or image data which can tolerate some amount of errors. A CD-ROM can be efficiently used by using each of these modes for their different purposes.
At the point of reading a sector from within a CD, error correction is performed, realizing an error occurrence rate of 1 per 109 bytes. This error management is performed for both CD-ROM mode 1 and 2. Mode 1 uses further error correction functionality with both the EDC and ECC, reducing the error occurrence rate to 1 per 1013 bytes and making it suitable to entrust with computer storage.
[diagram I-6-4]
In this section, we explain the CD drive control structure.
Diagram I-6-5 shows the block structure of the CD drive controller. Diagram I-6-6 illustrates the command flow for the CD drive controller.
The CPU cannot directly send commands to the CD drive. The CPU sends commands via the CD controller, and the CD controller sends commands to the CD drive.
The CD controller can also read the CD drive's status. The CPU can indirectly receive that status from the CD controller.
[diagram I-6-5]
[diagram I-6-6]
The RAM buffer is memory that temporarily stores data read from the CD-ROM.
The CD drive is connected to the bus via the CD controller.
The CD controller is equipped with a Fujitsu MB88505 one-chip microcontroller (called the sub-MPU below) and CDC.
The sub-MPU primarily handles direct control of the CD drive. The CDC transfers data between the CPU and sub-MPU, and is used to transfer data read from the CD to memory (whether by the CPU or by DMA). The CDC internal registers are used to control these data transfers. For a description of these registers, please see "6.3: CD drive related registers".
Diagram I-6-7 shows the procedure for controlling the CD drive.
- A reset signal is sent from the CPU to the CDC via the main control register (table I-6-1).
- The CDC sends a reset instruction to the CD drive.
- The CD drive performs initialization operations (for example, clearing things like internal drive status), and when those complete, it sends the initialization completed status to the CD controller's MPU.
- The MPU notifies the CDC that the CD drive has completed initialization.
- The CDC triggers an interrupt on the CPU. The CPU can then send the next command.
Since the CPU is notified by an interrupt, it can do other work until initialization is completed.
Note that the CPU interrupt is masked if the SMIM bit of the mask control register is 0, so it is necessary to set the bit to 1 to allow the interrupt to occur.
[diagram I-6-7]
Commands from the CPU to control the CD drive are performed according to the following process.
- The CPU sends a command and parameters to the CD controller via the command register (table I-6-3) and parameter register (table I-6-4).
- The CDC triggers an interrupt on the CD controller's sub-MPU. The sub-MPU reads the command and parameters, and sends the necessary instructions to the CD drive.
- The CD drive executes those instructions, and when execution completes, sends the completed status to the sub-MPU.
- The sub-MPU notifies the CDC that the CD operation has completed.
- The CDC triggers an interrupt on the CPU. The CPU can then send a new command or perform other operations. The CPU interrupt is masked if the mask control register's SMIM bit is 0, so it is necessary to set the bit to 1 before the interrupt occurs.
At this time, the CPU can continue controlling the CD drive by sending further commands.
In the time between when the CPU sends a command and the command completion notification interrupt is triggered, the CPU can perform other tasks.
If the command register's IRQ and status bits are set to 1 when the command is sent from the CPU to the CDC, then the CPU will receive an additional interrupt once the sub-MPU sends the command to the CD drive. This is useful when one wants to immediately check whether the command was successfully accepted or not.
Here, we describe the CDC internal registers related to controlling the CD drive. However, the formats of the commands to the CDC, status replies from the CDC, and parameters have not been publicly released. When developing programs using the CD-ROM, please use the CD-ROM BIOS.
Inside of the CDC are write-only and read-only registers.
- Write-only registers:
- Mask control register: interrupt settings
- Command register: command settings
- Parameter register: parameter settings
- Transfer control register: data transfer mode settings
- Read-only registers:
- Mask status register: read interrupt related status
- Status register: read command status
- Data register: read data, when using software transfer
- CD subcode status register: gives status when reading subcodes
- CD subcode data register: reads subcode data value
The mask control register (table I-6-1) has bits which mask or allow interrupt requests and which an interrupt handler can use to clear completed interrupt requests. The SRST bit is also provided for resetting the sub-MPU at initialization time.
The mask status register (table I-6-2) is read by an interrupt handler to determine the reason for an interrupt.
The command register (table I-6-3) is used for writing command bytes to the CD drive.
TYPE indicates the nature of the command. PLAY commands have to do with music playback, data reading, and other commands requiring actual movement within the CD drive, whereas STATE control commands are commands that only alter setting values such as the operating mode.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04C0 | Mask control register | W | SMIC | DEIC | 0 | 0 | 0 | SRST | SMIM | DEIM |
-
SMIC (bit 7): SUB MPU IRQ CLEAR.
- 1: Clears an interrupt request from the sub-MPU.
-
DEIC (bit 6): DMA END IRQ CLEAR.
- 1: Clears an interrupt request arising from the completion of a DMA transfer.
-
SRST (bit 2): SUB MPU RESET.
- 1: Reset the sub-MPU.
-
SMIM (bit 1): SUB MPU IRQ MASK.
- 0: Interrupt requests disallowed from the sub-MPU.
- 1: Interrupt requests allowed from the sub-MPU.
-
DEIM (bit 0): DMA END IRQ ENABLE MASK.
- 0: Interrupt requests disallowed for end of DMA transfer.
- 1: Interrupt requests allowed for end of DMA transfer.
-
Each of bits 2 and 3 is reset by hardware at the end of a transfer. Bit 6 is set at the end of a DMA transfer.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04C0 | Mask status register | R | SIRQ | DEI | STSF | DTSF | undefined | SRQ | DRY | |
- SIRQ (bit 7): SUB MPU IRQ.
- 0: No interrupt request from sub-MPU.
- 1: Interrupt request from sub-MPU.
- DEI (bit 6): DMA END IRQ.
- 0: No interrupt request from DMA transfer.
- 1: Interrupt request from DMA transfer.
- STSF (bit 5): SOFT TRANS.
- 0: Software transfer complete.
- 1: Software transfer in progress.
- DTSF (bit 4): DATA TRANS.
- 0: DMA not transferring.
- 1: DMA transfer in progress.
- SRQ (bit 1): STATUS READ REQUEST.
- 0: No status read request.
- 1: Sub-MPU has a status read request from after a command's execution.
- DRY (bit 0): SUB MPU READY.
- 0: Sub-MPU state cannot accept commands.
- 1: Sub-MPU state can accept commands.
- Each of bits 0, 1, 7 is set by the sub-MPU. Bit 6 is set when DMA transfer completes.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04C2 | Command register | W | TYPE | IRQ | STATUS | COMMAND CODE | ||||
- This register sends commands from the CPU to the sub-MPU.
- TYPE (bit 7): Indicates the command type.
- 0: PLAY command
- 1: STATE control command
- IRQ (bit 6): Controls IRQs for command status requests.
- 0: IRQ off
- 1: IRQ on
- STATUS (bit 5): Command status request control.
- 0: No request
- 1: Request active
- COMMAND CODE (bit 0-4): Command code.
The parameter register (table I-6-4) is used by the CPU to write command parameters to the sub-MPU. This register has an 8-byte FIFO (first-in first-out) structure, so eight bytes must be written in a row.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04C4 | Parameter register | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
- This register sets the operation mode alongside the command from the CPU. The same address provides access to an eight-byte FIFO, so the same address must be written eight times.
The status register (table I-6-5) stores the command status from the sub-MPU to be referenced by the CPU. This register likewise has a 4-byte FIFO structure, so at read time, it must be read four times.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04C2 | Status register | R | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
- Stores the status information from the sub-MPU after its execution has completed. The same address provides access to a four-byte FIFO, so the same address must be read four times.
The transfer control register (table I-6-6) is used to set whether data from the CD-ROM is transferred by DMA or by programmatic CPU reads. To have the CPU read, DTS can be set to 0 and STS to 1. To reading via DMA, DTS can bet set to 1.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04C6 | Transfer control register | W | 0 | 0 | 0 | DTS | STS | 0 | 0 | 0 |
- DTS (bit 4): DMA TRANSFER MODE.
- 0: Not in DMA data transfer mode
- 1: DMA data transfer mode active
- STS (bit 3): SOFTWARE TRANSFER START.
- 1: Data transfer can begin via the CPU reading from the data register.
The data register (table I-6-7) works as a "window" for the CPU to read data from.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04C4 | Data register | R | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
- Data register used for reading when in software transfer mode.
The CD subcode status register (table I-6-8) is checked when reading subcodes to see whether they are valid or not.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04CC | CD subcode status register | R | undefined | OVERRUN | SUBC-DAT-R | |||||
A subcode is one byte of supplemental data attached to each CD data frame (diagram I-6-8), whose bits are named P, Q, R, ..., W starting from the highest bit. One sector is composed of 98 data frames, so there is a total of 98 subcode bytes per sector. Therefore there is also a total of 98 P, Q, R, ..., W bits. These are each collectively referred to as SUBP data, SUBQ data, and so on. Diagram I-6-9 shows the format of the Q bits collected from the subcode data of one sector (SUBQ data).
Normally, SUBQ data is made up of timing information.
SUBR through SUBW are generally used to store graphics data for a still image to show during CD playback.
[diagram I-6-8]
[diagram I-6-9]
The CD subcode data register (table I-6-9) is used for reading subcodes.
The subcode data is valid if the OVERRUN bit is 0 and SUBC-DAT-R bit is 1. When an overrun occurs (OVERRUN bit is 1), it indicates that data was dropped. An overrun indicates that more data entered the the CD subcode data register before its existing data could be read by the CPU.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04CD | CD subcode data register | R | SUBC P-DATA | SUBC Q-DATA | SUBC R-DATA | SUBC S-DATA | SUBC T-DATA | SUBC U-DATA | SUBC V-DATA | SUBC W-DATA |
- Data register used for reading CD subcodes.
The FM TOWNS supports various input and output devices.
In this chapter, we explain various such devices including the keyboard, TOWNS pad, TOWNS mouse, printer, floppy disk, hard disk, and RS-232C interface.
A keyboard is optional for the FM TOWNS, but it is an essential device when inputting large amounts of text. In this section, we explain the structure and operation of the keyboard and keyboard interface.
Table I-7-1 presents the specifications for the keyboard.
| Item | Specification |
| Interface | Serial
|
| Controller | 8042 |
| Key scanner | Equipped on keyboard side (JIS/thumb shift) Processor: 8049 |
Keyboards come in JIS layout type (diagram I-7-1) and thumb-shift type (diagram I-7-2), and each type comes in variants with and without a ten-key pad. The user can choose according to their preference.
The keyboard is fundamentally the same as the FMR series, with the exception that a mouse cannot be connected.
The keyboard interface is a serial interface used to connect the computer to the keyboard. Communication typically goes in one direction, only sending data from the keyboard to the computer, but bidirectional communication is also possible when using special devices.
The keyboard is internally equipped with an Intel 8049 as the keyboard controller microcontroller, which performs the duty of detecting the key numbers of pressed keys and sending them to the computer.
On the computer side, a separate Intel 8042 microcontroller is equipped for use by the keyboard, which performs the duty of converting the serial signal from the keyboard into a parallel signal and communicating with the CPU (diagram I-7-3).
[diagram I-7-1]
[diagram I-7-2]
[diagram I-7-3]
Commands to do things like detect pressed keys from user-written programs are sent to the keyboard interface (8042), and afterward, data is returned from the keyboard to the 8042 to be read back.
Six registers are involved in this control process.
Sending commands to the 8042 is performed by writing a value to the command register (table I-7-2).
There are two types of command format. Common commands are used by keyboards. Device commands are used when sending commands to other non-keyboard types of devices.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0602 | Command register | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
-
Common command format:
Bit: 7 6 5 4 3 2 1 0 1 0 1 Command -
Device command format:
Bit: 7 6 5 4 3 2 1 0 Byte 1 1 1 0 X Expansion device ID 2 0 CNT (data length) 3 0 Data #1 3 0 Data #2
Table I-7-3 gives the meaning of values for common commands.
| Command register value | Command name | Function | Target |
|---|---|---|---|
| 10100001 | RESET | When this command is received, the device returns to its default state. This command takes priority when received in the middle of data transfer, other commands are being received, or any other situation. | |
| 10100100 | Simultaneous keystroke observation on | Enables simultaneous keystrokes on a thumb-shift keyboard. | Used by the computer-side microcontroller. |
| 10100101 | Simultaneous keystroke observation off | Disables simultaneous keystrokes on a thumb-shift keyboard. Defaults to disabled. | " |
| 10101001 | Typematic interval | Sets typematic start time to 400ms. | The defaults are 400ms-30ms. Used by the computer-side microcontroller. |
| 10101010 | Sets typematic start time to 500ms. | ||
| 10101011 | Sets typematic start time to 300ms. | ||
| 10101100 | Sets typematic repeat interval to 50ms. | ||
| 10101101 | Sets typematic repeat interval to 30ms. | ||
| 10101110 | Sets typematic repeat interval to 20ms.* | ||
| 10110000 | Enable diagonal cursor movement | Enables diagonal cursor movement keys (sending two key codes alternatingly). Defaults to enabled. | Used by the keyboard-side microcontroller. |
| 10110001 | Disable diagonal cursor movement | Disables diagonal cursor movement keys (two codes sent alternatingly). Defaults to enabled. | " |
| 10110010 | NMI ACK | The main CPU's NMI handler must quickly send this command when it detects an NMI from the keyboard. The computer-side microcontroller will not resume processing until this occurs. Also, this command must not be sent outside of an NMI acknowledgment. | Used by the computer-side microcontroller. |
| 10110011 - 10111111 |
Reserved |
- * At a typematic interval of 20ms, data transfer may lag if alternatingly transmitting keyboard and mouse data.
In table I-7-3, "typematic" refers to the continuous sending of key data by autorepeating a key that is being continuously held down. Diagram I-7-4 shows the timing of key sends, and diagram I-7-5 demonstrates the meaning of the typematic start time and typematic period when using autorepeat. "Make" is when a key is pressed, and "break" refers to a key being released.
[diagram I-7-4]
[diagram I-7-5]
Data sent from the keyboard to the computer is read from the keyboard data register (table I-7-4). The formats of data returned from the keyboard are as follows:
There are four different data formats. Key data is for reading normal key input. Typematic is used for repeated keys.
Also, device attribute information data is used to get the status of devices other than a keyboard or mouse that are connected to the keyboard interface. Additionally, expansion data is used to transfer arbitrary data bytes to the 386 CPU.
The address value of each key is as shown in diagrams I-7-6 and I-7-7.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0600 | Keyboard data register | R | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
- Key data format:
- First byte:
- bit 7: 1 = first byte
- bits 5-6:
- 0 0: Thumb-shift keyboard (2 byte sequence)
- 0 1: JIS keyboard (2 byte sequence)
- 1 0: New JIS keyboard (2 byte sequence)
- 1 1: Expansion use
- bit 4: 0 = make code, 1 = break code
- bit 3: 0 = CTRL key not pressed, 1 = CTRL key pressed
- bit 2: 0 = SHIFT key not pressed, 1 = SHIFT key pressed (or handakuon key pressed)
- bit 1: 1 = left thumb shift key pressed, 0 = not pressed
- bit 0: 1 = right thumb shift key pressed, 0 = not pressed
- Second byte:
- bit 7: 0 = second byte
- bit 0-6: key code
- First byte:
- Typematic data format:
- First byte:
- bit 7: 1 = first byte
- bit 6: 1
- bit 5: 1
- bit 4: 1 = typematic
- bit 3: CTRL pressed
- bit 2: SHIFT pressed
- bit 1: left thumb shift
- bit 0: right thumb shift
- Second byte:
- bit 7: 0 = second byte
- bit 0-6: key code
- For typematic data, the keyboard type can be assumed to be the same as the immediately previous data's type. Data sent from the keyboard to the computer also follows the same fundamental format described above.
- First byte:
- Device attribute information data format:
- First byte, bits 2-7: 111010
- Second byte, bit 7: 0
- First byte, bits 0-1; second byte, bits 5-6: expansion device ID
- Second byte: bits 0-4: status
- This data format is for notifying the CPU of the status of non-keyboard devices.
- Expansion data format:
- First byte, bits 2-7: 111011
- Second byte, bit 7: 0
- First byte, bits 0-1; second byte, bits 5-6: expansion device ID
- Second byte: bits 0-4: CNT (byte count)
- Expansion data is for non-keyboard devices connected via the keyboard interface. The computer-side microcontroller (8042) sends this data to the main CPU without any processing. CNT indicates the byte count of the data following the second byte (including the second byte). If zero, it indicates the maximum of 32 bytes.
[diagram I-7-6]
[diagram I-7-7]
The status register (table I-7-5) is used to inspect the status of the 8042. Before sending a command, it is necessary to read this register and confirm that IBF is 0. When this bit is 1, written commands will be ignored.
Also, OBF is 1 when there is data sent from the 8042 to the 80386 CPU, so when reading from the key data register, first confirm that this bit is 1.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0602 | Status register | R | ST7 | ST6 | ST5 | ST4 | F1 | F0 | IBF | OBF |
- ST4-7 (bit 4-7): Bit available for user-defined status (contents not yet determined).
- F1 (bit 3): Undefined.
- F0 (bit 2): Generic flag (set by the 8042's internal program)
- IBF (bit 1): Indicates the 8042 input buffer state.
- 0 = no data (data can be written)
- 1 = data available (data cannot be written)
- When the main CPU (80386) writes data to the input buffer, this bit becomes 1, and when the 8042 shifts that data into its accumulator, this bit becomes 0 again.
- OBF (bit 0): Indicates the 8042 output buffer state.
- 0 = no data
- 1 = data available
- When the 8042 loads data into the output buffer, this bit becomes 1, and when the main CPU (80386) reads the data from the output buffer, this bit becomes 0 again.
The 8042 data register (table I-7-6) is used for commands that need two bytes of information (parameters). In this case, the parameter is written to the 8042 data register first, and afterward, the initial byte is written to the command register.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0600 | 8042 data register | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
The interrupt cause flag register (table I-7-7) can be used to inspect the cause of an interrupt.
There are two bits, a flag indicating whether there is an interrupt from the keyboard (KBINT) and a flag indicate whether a non-maskable interrupt came from the keyboard interface (NMI).
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0604 | Interrupt cause flag register | R | undefined | NMI | KBINT | |||||
- NMI (bit 1): Indicates whether an NMI came from the keyboard interface.
- 0 = No NMI
- 1 = NMI active
- KBINT (bit 0): Indicates whether an interrupt came from the keyboard.
- 0 = No interrupt
- 1 = Interrupt active
The interrupt control register (table I-7-8) only has a flag to control whether keyboard interrupts are allowed (KBMSK).
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x0604 | Interrupt control register | W | 0 | 0 | 0 | 0 | 0 | 0 | 0 | KBMSK |
- KBMSK (bit 0): Keyboard interrupt control.
- 0 = Interrupts disabled
- 1 = Interrupts enabled
In this section, we describe the structure and operation of the TOWNS pad and its interface hardware.
The interface between the main unit and TOWNS pad sends the TOWNS pad's up-down-left-right movement buttons, A button, B button, SELECT button, and RUN button state to the computer (diagram I-7-8).
The signal lines from the TOWNS pad's internal switches are all connected to the main unit's GND. Every switch thus works in the same way. The COM output can be set to zero for compatibility with an MSX-specification pad. This also sets the COM input to zero, making it possible to read input from each switch.
Note that it is necessary to set the TRIG output to 1 when reading the signal from pressing the A or B button.
[diagram I-7-8]
Since two TOWNS pads can be connected at once, registers are provided corresponding to each connector.
The A, B, RUN, SELECT, and up-down-left-right movement buttons' state can be read from the pad 1 and pad 2 input registers (table I-7-9).
To control COM and TRIG output, the pad output register (table I-7-10) is used. Before reading a value from the pad 1 or 2 input register, if the COM input will be read, then the corresponding COM flag must be set to 0, and if the TRIG inputs will be read, then the corresponding TRIG flag must be set to 1.
| I/O address | Register name | R/W | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0x04D0 | Pad 1 input register | R | COM | TRIG2 | TRIG1 | RIGHT | LEFT | BACK | FWD | |
| 0x04D2 | Pad 2 input register | R | COM | TRIG2 | TRIG1 | RIGHT | LEFT | BACK | FWD |
-
Indicates the state of each button on the TOWNS pad.
-
COM (bit 6): Indicates the COM input.
- 0 = COM input off
- 1 = COM input on
-
TRIG1, 2 (bit 4, 5): Indicates the A button (TRIG1) and B button (TRIG2) state.
- 0 = Button pressed
- 1 = Button not pressed
RIGHT LEFT BACK FWD Meaning 0 1 1 1 D-pad right pressed 1 0 1 1 D-pad left pressed 1 1 0 1 D-pad down pressed 1 1 1 0 D-pad up pressed 0 0 1 1 RUN button pressed 1 1 0 0 SELECT button pressed
| I/O address | Register name | R |