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jonmon6691/optiboot_atmega328.lst Secret

Created October 7, 2020 23:43
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Arduino bootloader as compiled by myself, which differs from the original
Raw
optiboot_atmega328.lst
optiboot_atmega328.elf: file format elf32-avr
Sections:
Idx Name Size VMA LMA File off Algn
0 .data 00000000 00800100 00800100 00000268 2**0
CONTENTS, ALLOC, LOAD, DATA
1 .text 00000214 00007e00 00007e00 00000054 2**1
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .version 00000002 00007ffe 00007ffe 00000268 2**0
CONTENTS, READONLY
3 .stab 00000c78 00000000 00000000 0000026c 2**2
CONTENTS, READONLY, DEBUGGING
4 .stabstr 00000e4a 00000000 00000000 00000ee4 2**0
CONTENTS, READONLY, DEBUGGING
5 .comment 00000011 00000000 00000000 00001d2e 2**0
CONTENTS, READONLY
Disassembly of section .text:
00007e00 <main>:
7e00: 11 24 eor r1, r1
7e02: 84 b7 in r24, 0x34 ; 52
7e04: 14 be out 0x34, r1 ; 52
7e06: 81 ff sbrs r24, 1
7e08: fd d0 rcall .+506 ; 0x8004 <appStart>
7e0a: 85 e0 ldi r24, 0x05 ; 5
7e0c: 80 93 81 00 sts 0x0081, r24 ; 0x800081 <__DATA_REGION_ORIGIN__+0x21>
7e10: 82 e0 ldi r24, 0x02 ; 2
7e12: 80 93 c0 00 sts 0x00C0, r24 ; 0x8000c0 <__DATA_REGION_ORIGIN__+0x60>
7e16: 88 e1 ldi r24, 0x18 ; 24
7e18: 80 93 c1 00 sts 0x00C1, r24 ; 0x8000c1 <__DATA_REGION_ORIGIN__+0x61>
7e1c: 96 e0 ldi r25, 0x06 ; 6
7e1e: 90 93 c2 00 sts 0x00C2, r25 ; 0x8000c2 <__DATA_REGION_ORIGIN__+0x62>
7e22: 90 e1 ldi r25, 0x10 ; 16
7e24: 90 93 c4 00 sts 0x00C4, r25 ; 0x8000c4 <__DATA_REGION_ORIGIN__+0x64>
7e28: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <__DATA_REGION_ORIGIN__>
7e2c: 8e e0 ldi r24, 0x0E ; 14
7e2e: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <__DATA_REGION_ORIGIN__>
7e32: 25 9a sbi 0x04, 5 ; 4
7e34: 86 e0 ldi r24, 0x06 ; 6
7e36: 20 e3 ldi r18, 0x30 ; 48
7e38: 3c ef ldi r19, 0xFC ; 252
7e3a: 91 e0 ldi r25, 0x01 ; 1
7e3c: 30 93 85 00 sts 0x0085, r19 ; 0x800085 <__DATA_REGION_ORIGIN__+0x25>
7e40: 20 93 84 00 sts 0x0084, r18 ; 0x800084 <__DATA_REGION_ORIGIN__+0x24>
7e44: 96 bb out 0x16, r25 ; 22
7e46: b0 9b sbis 0x16, 0 ; 22
7e48: fe cf rjmp .-4 ; 0x7e46 <main+0x46>
7e4a: 1d 9a sbi 0x03, 5 ; 3
7e4c: a8 95 wdr
7e4e: 81 50 subi r24, 0x01 ; 1
7e50: a9 f7 brne .-22 ; 0x7e3c <main+0x3c>
7e52: c0 e0 ldi r28, 0x00 ; 0
7e54: d0 e0 ldi r29, 0x00 ; 0
7e56: 08 e1 ldi r16, 0x18 ; 24
7e58: 38 e0 ldi r19, 0x08 ; 8
7e5a: f3 2e mov r15, r19
7e5c: ee 24 eor r14, r14
7e5e: e3 94 inc r14
7e60: 45 e0 ldi r20, 0x05 ; 5
7e62: b4 2e mov r11, r20
7e64: 51 e1 ldi r21, 0x11 ; 17
7e66: a5 2e mov r10, r21
7e68: 13 e0 ldi r17, 0x03 ; 3
7e6a: a7 d0 rcall .+334 ; 0x7fba <getch>
7e6c: 81 34 cpi r24, 0x41 ; 65
7e6e: 91 f4 brne .+36 ; 0x7e94 <main+0x94>
7e70: a4 d0 rcall .+328 ; 0x7fba <getch>
7e72: d8 2e mov r13, r24
7e74: ae d0 rcall .+348 ; 0x7fd2 <verifySpace>
7e76: 82 e8 ldi r24, 0x82 ; 130
7e78: d8 12 cpse r13, r24
7e7a: 03 c0 rjmp .+6 ; 0x7e82 <main+0x82>
7e7c: 84 e0 ldi r24, 0x04 ; 4
7e7e: 96 d0 rcall .+300 ; 0x7fac <putch>
7e80: 92 c0 rjmp .+292 ; 0x7fa6 <main+0x1a6>
7e82: e1 e8 ldi r30, 0x81 ; 129
7e84: de 12 cpse r13, r30
7e86: 03 c0 rjmp .+6 ; 0x7e8e <main+0x8e>
7e88: 84 e0 ldi r24, 0x04 ; 4
7e8a: 90 d0 rcall .+288 ; 0x7fac <putch>
7e8c: 8c c0 rjmp .+280 ; 0x7fa6 <main+0x1a6>
7e8e: 83 e0 ldi r24, 0x03 ; 3
7e90: 8d d0 rcall .+282 ; 0x7fac <putch>
7e92: 89 c0 rjmp .+274 ; 0x7fa6 <main+0x1a6>
7e94: 82 34 cpi r24, 0x42 ; 66
7e96: 19 f4 brne .+6 ; 0x7e9e <main+0x9e>
7e98: 84 e1 ldi r24, 0x14 ; 20
7e9a: a7 d0 rcall .+334 ; 0x7fea <getNch>
7e9c: 84 c0 rjmp .+264 ; 0x7fa6 <main+0x1a6>
7e9e: 85 34 cpi r24, 0x45 ; 69
7ea0: 19 f4 brne .+6 ; 0x7ea8 <main+0xa8>
7ea2: 85 e0 ldi r24, 0x05 ; 5
7ea4: a2 d0 rcall .+324 ; 0x7fea <getNch>
7ea6: 7f c0 rjmp .+254 ; 0x7fa6 <main+0x1a6>
7ea8: 85 35 cpi r24, 0x55 ; 85
7eaa: 49 f4 brne .+18 ; 0x7ebe <main+0xbe>
7eac: 86 d0 rcall .+268 ; 0x7fba <getch>
7eae: c8 2f mov r28, r24
7eb0: 84 d0 rcall .+264 ; 0x7fba <getch>
7eb2: d0 e0 ldi r29, 0x00 ; 0
7eb4: d8 2b or r29, r24
7eb6: cc 0f add r28, r28
7eb8: dd 1f adc r29, r29
7eba: 8b d0 rcall .+278 ; 0x7fd2 <verifySpace>
7ebc: 74 c0 rjmp .+232 ; 0x7fa6 <main+0x1a6>
7ebe: 86 35 cpi r24, 0x56 ; 86
7ec0: 29 f4 brne .+10 ; 0x7ecc <main+0xcc>
7ec2: 84 e0 ldi r24, 0x04 ; 4
7ec4: 92 d0 rcall .+292 ; 0x7fea <getNch>
7ec6: 80 e0 ldi r24, 0x00 ; 0
7ec8: 71 d0 rcall .+226 ; 0x7fac <putch>
7eca: 6d c0 rjmp .+218 ; 0x7fa6 <main+0x1a6>
7ecc: 84 36 cpi r24, 0x64 ; 100
7ece: 09 f0 breq .+2 ; 0x7ed2 <main+0xd2>
7ed0: 3f c0 rjmp .+126 ; 0x7f50 <main+0x150>
7ed2: 73 d0 rcall .+230 ; 0x7fba <getch>
7ed4: 72 d0 rcall .+228 ; 0x7fba <getch>
7ed6: 98 2e mov r9, r24
7ed8: 70 d0 rcall .+224 ; 0x7fba <getch>
7eda: c1 15 cp r28, r1
7edc: f0 e7 ldi r31, 0x70 ; 112
7ede: df 07 cpc r29, r31
7ee0: 38 f4 brcc .+14 ; 0x7ef0 <main+0xf0>
7ee2: fe 01 movw r30, r28
7ee4: 17 bf out 0x37, r17 ; 55
7ee6: e8 95 spm
7ee8: c1 2c mov r12, r1
7eea: dd 24 eor r13, r13
7eec: d3 94 inc r13
7eee: 03 c0 rjmp .+6 ; 0x7ef6 <main+0xf6>
7ef0: c1 2c mov r12, r1
7ef2: dd 24 eor r13, r13
7ef4: d3 94 inc r13
7ef6: 61 d0 rcall .+194 ; 0x7fba <getch>
7ef8: f6 01 movw r30, r12
7efa: 81 93 st Z+, r24
7efc: 6f 01 movw r12, r30
7efe: 9e 12 cpse r9, r30
7f00: fa cf rjmp .-12 ; 0x7ef6 <main+0xf6>
7f02: c1 15 cp r28, r1
7f04: f0 e7 ldi r31, 0x70 ; 112
7f06: df 07 cpc r29, r31
7f08: 18 f0 brcs .+6 ; 0x7f10 <main+0x110>
7f0a: fe 01 movw r30, r28
7f0c: 17 bf out 0x37, r17 ; 55
7f0e: e8 95 spm
7f10: 60 d0 rcall .+192 ; 0x7fd2 <verifySpace>
7f12: 07 b6 in r0, 0x37 ; 55
7f14: 00 fc sbrc r0, 0
7f16: fd cf rjmp .-6 ; 0x7f12 <main+0x112>
7f18: fe 01 movw r30, r28
7f1a: a0 e0 ldi r26, 0x00 ; 0
7f1c: b1 e0 ldi r27, 0x01 ; 1
7f1e: 8c 91 ld r24, X
7f20: 11 96 adiw r26, 0x01 ; 1
7f22: 2c 91 ld r18, X
7f24: 11 97 sbiw r26, 0x01 ; 1
7f26: 90 e0 ldi r25, 0x00 ; 0
7f28: 92 2b or r25, r18
7f2a: 0c 01 movw r0, r24
7f2c: e7 be out 0x37, r14 ; 55
7f2e: e8 95 spm
7f30: 11 24 eor r1, r1
7f32: 32 96 adiw r30, 0x02 ; 2
7f34: 12 96 adiw r26, 0x02 ; 2
7f36: a0 38 cpi r26, 0x80 ; 128
7f38: 81 e0 ldi r24, 0x01 ; 1
7f3a: b8 07 cpc r27, r24
7f3c: 81 f7 brne .-32 ; 0x7f1e <main+0x11e>
7f3e: fe 01 movw r30, r28
7f40: b7 be out 0x37, r11 ; 55
7f42: e8 95 spm
7f44: 07 b6 in r0, 0x37 ; 55
7f46: 00 fc sbrc r0, 0
7f48: fd cf rjmp .-6 ; 0x7f44 <main+0x144>
7f4a: a7 be out 0x37, r10 ; 55
7f4c: e8 95 spm
7f4e: 2b c0 rjmp .+86 ; 0x7fa6 <main+0x1a6>
7f50: 84 37 cpi r24, 0x74 ; 116
7f52: b1 f4 brne .+44 ; 0x7f80 <main+0x180>
7f54: 32 d0 rcall .+100 ; 0x7fba <getch>
7f56: 31 d0 rcall .+98 ; 0x7fba <getch>
7f58: 98 2e mov r9, r24
7f5a: 2f d0 rcall .+94 ; 0x7fba <getch>
7f5c: 3a d0 rcall .+116 ; 0x7fd2 <verifySpace>
7f5e: 89 2c mov r8, r9
7f60: fe 01 movw r30, r28
7f62: 6f 01 movw r12, r30
7f64: 8f ef ldi r24, 0xFF ; 255
7f66: c8 1a sub r12, r24
7f68: d8 0a sbc r13, r24
7f6a: 84 91 lpm r24, Z
7f6c: 1f d0 rcall .+62 ; 0x7fac <putch>
7f6e: 8a 94 dec r8
7f70: f6 01 movw r30, r12
7f72: 81 10 cpse r8, r1
7f74: f6 cf rjmp .-20 ; 0x7f62 <main+0x162>
7f76: 21 96 adiw r28, 0x01 ; 1
7f78: 9a 94 dec r9
7f7a: c9 0d add r28, r9
7f7c: d1 1d adc r29, r1
7f7e: 13 c0 rjmp .+38 ; 0x7fa6 <main+0x1a6>
7f80: 85 37 cpi r24, 0x75 ; 117
7f82: 41 f4 brne .+16 ; 0x7f94 <main+0x194>
7f84: 26 d0 rcall .+76 ; 0x7fd2 <verifySpace>
7f86: 8e e1 ldi r24, 0x1E ; 30
7f88: 11 d0 rcall .+34 ; 0x7fac <putch>
7f8a: 85 e9 ldi r24, 0x95 ; 149
7f8c: 0f d0 rcall .+30 ; 0x7fac <putch>
7f8e: 8f e0 ldi r24, 0x0F ; 15
7f90: 0d d0 rcall .+26 ; 0x7fac <putch>
7f92: 09 c0 rjmp .+18 ; 0x7fa6 <main+0x1a6>
7f94: 81 35 cpi r24, 0x51 ; 81
7f96: 31 f4 brne .+12 ; 0x7fa4 <main+0x1a4>
7f98: 00 93 60 00 sts 0x0060, r16 ; 0x800060 <__DATA_REGION_ORIGIN__>
7f9c: f0 92 60 00 sts 0x0060, r15 ; 0x800060 <__DATA_REGION_ORIGIN__>
7fa0: 18 d0 rcall .+48 ; 0x7fd2 <verifySpace>
7fa2: 01 c0 rjmp .+2 ; 0x7fa6 <main+0x1a6>
7fa4: 16 d0 rcall .+44 ; 0x7fd2 <verifySpace>
7fa6: 80 e1 ldi r24, 0x10 ; 16
7fa8: 01 d0 rcall .+2 ; 0x7fac <putch>
7faa: 5f cf rjmp .-322 ; 0x7e6a <main+0x6a>
00007fac <putch>:
}
}
void putch(char ch) {
#ifndef SOFT_UART
while (!(UCSR0A & _BV(UDRE0)));
7fac: 90 91 c0 00 lds r25, 0x00C0 ; 0x8000c0 <__DATA_REGION_ORIGIN__+0x60>
7fb0: 95 ff sbrs r25, 5
7fb2: fc cf rjmp .-8 ; 0x7fac <putch>
UDR0 = ch;
7fb4: 80 93 c6 00 sts 0x00C6, r24 ; 0x8000c6 <__DATA_REGION_ORIGIN__+0x66>
7fb8: 08 95 ret
00007fba <getch>:
[uartBit] "I" (UART_RX_BIT)
:
"r25"
);
#else
while(!(UCSR0A & _BV(RXC0)))
7fba: 80 91 c0 00 lds r24, 0x00C0 ; 0x8000c0 <__DATA_REGION_ORIGIN__+0x60>
7fbe: 87 ff sbrs r24, 7
7fc0: fc cf rjmp .-8 ; 0x7fba <getch>
;
if (!(UCSR0A & _BV(FE0))) {
7fc2: 80 91 c0 00 lds r24, 0x00C0 ; 0x8000c0 <__DATA_REGION_ORIGIN__+0x60>
7fc6: 84 fd sbrc r24, 4
7fc8: 01 c0 rjmp .+2 ; 0x7fcc <getch+0x12>
}
#endif
// Watchdog functions. These are only safe with interrupts turned off.
void watchdogReset() {
__asm__ __volatile__ (
7fca: a8 95 wdr
* don't care that an invalid char is returned...)
*/
watchdogReset();
}
ch = UDR0;
7fcc: 80 91 c6 00 lds r24, 0x00C6 ; 0x8000c6 <__DATA_REGION_ORIGIN__+0x66>
LED_PIN |= _BV(LED);
#endif
#endif
return ch;
}
7fd0: 08 95 ret
00007fd2 <verifySpace>:
do getch(); while (--count);
verifySpace();
}
void verifySpace() {
if (getch() != CRC_EOP) {
7fd2: f3 df rcall .-26 ; 0x7fba <getch>
7fd4: 80 32 cpi r24, 0x20 ; 32
7fd6: 39 f0 breq .+14 ; 0x7fe6 <verifySpace+0x14>
"wdr\n"
);
}
void watchdogConfig(uint8_t x) {
WDTCSR = _BV(WDCE) | _BV(WDE);
7fd8: 88 e1 ldi r24, 0x18 ; 24
7fda: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <__DATA_REGION_ORIGIN__>
WDTCSR = x;
7fde: 88 e0 ldi r24, 0x08 ; 8
7fe0: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <__DATA_REGION_ORIGIN__>
7fe4: ff cf rjmp .-2 ; 0x7fe4 <verifySpace+0x12>
if (getch() != CRC_EOP) {
watchdogConfig(WATCHDOG_16MS); // shorten WD timeout
while (1) // and busy-loop so that WD causes
; // a reset and app start.
}
putch(STK_INSYNC);
7fe6: 84 e1 ldi r24, 0x14 ; 20
7fe8: e1 cf rjmp .-62 ; 0x7fac <putch>
00007fea <getNch>:
::[count] "M" (UART_B_VALUE)
);
}
#endif
void getNch(uint8_t count) {
7fea: cf 93 push r28
do getch(); while (--count);
7fec: c8 2f mov r28, r24
7fee: e5 df rcall .-54 ; 0x7fba <getch>
7ff0: c1 50 subi r28, 0x01 ; 1
verifySpace();
}
7ff2: e9 f7 brne .-6 ; 0x7fee <getNch+0x4>
}
#endif
void getNch(uint8_t count) {
do getch(); while (--count);
verifySpace();
7ff4: cf 91 pop r28
7ff6: ed cf rjmp .-38 ; 0x7fd2 <verifySpace>
00007ff8 <watchdogConfig>:
"wdr\n"
);
}
void watchdogConfig(uint8_t x) {
WDTCSR = _BV(WDCE) | _BV(WDE);
7ff8: e0 e6 ldi r30, 0x60 ; 96
7ffa: f0 e0 ldi r31, 0x00 ; 0
7ffc: 98 e1 ldi r25, 0x18 ; 24
7ffe: 90 83 st Z, r25
WDTCSR = x;
8000: 80 83 st Z, r24
8002: 08 95 ret
00008004 <appStart>:
"wdr\n"
);
}
void watchdogConfig(uint8_t x) {
WDTCSR = _BV(WDCE) | _BV(WDE);
8004: e0 e6 ldi r30, 0x60 ; 96
8006: f0 e0 ldi r31, 0x00 ; 0
8008: 88 e1 ldi r24, 0x18 ; 24
800a: 80 83 st Z, r24
WDTCSR = x;
800c: 10 82 st Z, r1
}
void appStart() {
watchdogConfig(WATCHDOG_OFF);
__asm__ __volatile__ (
800e: ee 27 eor r30, r30
8010: ff 27 eor r31, r31
8012: 09 94 ijmp
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