Bugblock.scala

// See LICENSE for license details.
package sifive.blocks.devices.bugblock

import Chisel._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tile._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.interrupts._
import chisel3.core.{Input, Output}

case class BugblockParams(address: BigInt)

class BugblockPortIO extends Bundle {
  val bugport = Output(UInt(4.W))   // <- comment this line to make firrtl not crash!
}

abstract class Bugblock(cbus: TLBusWrapper, val c: BugblockParams)(implicit p: Parameters)
  extends IORegisterRouter(
    RegisterRouterParams(
      name = "bugblock",
      compat = Seq("sifive,bugblock"),
      base = c.address,
      size = 4096,
      beatBytes = cbus.beatBytes),
    new BugblockPortIO)
    with HasInterruptSources {

  def nInterrupts = 4

  lazy val module = new LazyModuleImp(this) {

    val dummyReg = Reg(Bool())

    regmap (
      0x0 -> Seq(RegField(1,dummyReg,RegFieldDesc("dummy","dummy register")))
    )
  }
}


class TLBugblock(cbus: TLBusWrapper, params: BugblockParams)(implicit p: Parameters)
  extends Bugblock(cbus, params) with HasTLControlRegMap

case class BugblockAttachParams(
  bugblock: BugblockParams,
  controlBus: TLBusWrapper,
  intNode: IntInwardNode,
  mclock: Option[ModuleValue[Clock]] = None,
  mreset: Option[ModuleValue[Bool]] = None,
  controlXType: ClockCrossingType = NoCrossing,
  intXType: ClockCrossingType = NoCrossing)
  (implicit val p: Parameters)

object Bugblock {
  val nextId = { var i = -1; () => { i += 1; i} }

  def attach(params: BugblockAttachParams): TLBugblock = {
    implicit val p = params.p
    val name = s"bugblock"
    val cbus = params.controlBus
    val bugblock = LazyModule(new TLBugblock(cbus, params.bugblock))
    bugblock.suggestName(name)
    cbus.coupleTo(s"device_named_$name") {
      bugblock.controlXing(params.controlXType) := TLFragmenter(cbus.beatBytes, cbus.blockBytes) := _
    }
    params.intNode := bugblock.intXing(params.intXType)
    InModuleBody { bugblock.module.clock := params.mclock.map(_.getWrappedValue).getOrElse(cbus.module.clock) }
    InModuleBody { bugblock.module.reset := params.mreset.map(_.getWrappedValue).getOrElse(cbus.module.reset) }

    bugblock
  }

  def attachAndMakePort(params: BugblockAttachParams): ModuleValue[BugblockPortIO] = {
    val bugblock = attach(params)
    val bugblockNode = bugblock.ioNode.makeSink()(params.p)
    InModuleBody { bugblockNode.makeIO()(ValName(bugblock.name)) }
  }
}


class BugblockPins extends Bundle {
  val wdog_resets = Output(UInt(4.W))
}


case object PeripheryBugblockKey extends Field[Seq[BugblockParams]]

trait HasPeripheryBugblock { this: BaseSubsystem =>
  val bugblockNodes = p(PeripheryBugblockKey).map { ps => Bugblock.attach(BugblockAttachParams(ps, pbus, ibus.fromAsync)).ioNode.makeSink }
}

trait HasPeripheryBugblockBundle {
  val bugblock: Seq[BugblockPortIO]
}

trait HasPeripheryBugblockModuleImp extends LazyModuleImp with HasPeripheryBugblockBundle {
  val outer: HasPeripheryBugblock
  val bugblock = outer.bugblockNodes.zipWithIndex.map { case(n,i) => n.makeIO()(ValName(s"bugblock")) }
}