Testbench para a atividade 3 de PCS 3612 – Organização e Arquitetura de Computadores I

README.md

O que testa?

O sinal pronto tem que estar ativo no final e a saída x tem que ter o valor que foi definido nos testes.

Sugiro criar uma planilha no google sheets e depois por os dados no teste.

Testado com este ghdl:

GHDL 0.36 (v0.36) [Dunoon edition]
 Compiled with GNAT Version: 9.2.0
 GCC back-end code generator
Written by Tristan Gingold.

Como utilizar

Por todos os arquivos no mesmo diretório com o arquivo formula.vhd

Parâmetros

Pode-se editar os parâmetros no .vht

Tamanho

(linha 39):

        -- constants
	constant SIZE: natural := 32; 

Lista de testes

(linha 96):

constant valores_esperados : valores_esperados_array :=
(
   (12,  8, 24),
   (2,  -2,  4),
   (1,   4,  4),
   (-3,  7,  6),
   (8,   8, 16),
   (-3, -3,  6)
);

Compilação e Elaboração do vhdl

Para compilar, basta rodar o make:

$ make
ghdl -a  formula.vhd
ghdl -a  formula_testbench.vht
ghdl -e  formula_testbench

Para testar

Basta rodar make test e ver o resultado. Obs: para sair é só dar Interrupt, i.e. Ctrl + C.

$ make test
formula_testbench.vht:110:8:@0ms:(report note): INICIO DO TESTE...

formula_testbench.vht:112:16:@0ms:(report note): TESTANDO PARA: 
a = 12
b = 8
formula_testbench.vht:141:24:@240ns:(report note): TEST OK

formula_testbench.vht:112:16:@240ns:(report note): TESTANDO PARA: 
a = 2
b = -2
formula_testbench.vht:141:24:@480ns:(report note): TEST OK

formula_testbench.vht:112:16:@480ns:(report note): TESTANDO PARA: 
a = 1
b = 4
formula_testbench.vht:141:24:@720ns:(report note): TEST OK

formula_testbench.vht:112:16:@720ns:(report note): TESTANDO PARA: 
a = -3
b = 7
formula_testbench.vht:141:24:@960ns:(report note): TEST OK

formula_testbench.vht:112:16:@960ns:(report note): TESTANDO PARA: 
a = 8
b = 8
formula_testbench.vht:141:24:@1200ns:(report note): TEST OK

formula_testbench.vht:112:16:@1200ns:(report note): TESTANDO PARA: 
a = -3
b = -3
formula_testbench.vht:141:24:@1440ns:(report note): TEST OK

formula_testbench.vht:144:8:@1440ns:(report note): FIM DO TESTE!


^Cmake: *** [Makefile:12: test] Interrupt

formula_testbench.vht

-- Copyright 2019 João Victor Marques de Oliveirajoao.marques.oliveira@usp.br
-- 
-- 
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject to
-- the following conditions:
-- 
-- The above copyright notice and this permission notice shall be included
-- in all copies or substantial portions of the Software.
-- 
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-- OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-- 
-- 
-- TestBench para atividade 07
-- PCS 3612 - Organização e Arquitetura de Computadores I
-- 
-- Autor: João Victor Marques de Oliveira
-- Data: 1 Nov 2019

-- TestBench para atividade 07
-- PCS 3612 - Organiza��o e Arquitetura de Computadores I
-- 
-- Autor: Jo�o Victor Marques de Oliveira
-- Data: 1 Nov 2019

library ieee;                                               
use ieee.numeric_bit.all;            

-- testbench n�o tem inputs nem outputs
entity formula_testbench is
end formula_testbench;

architecture formula_testbench_arch of formula_testbench is
	-- constants
	constant SIZE: natural := 32;                                                 
	-- sinais                                                 
	signal a: bit_vector(SIZE-1 downto 0);
	signal b: bit_vector(SIZE-1 downto 0);
	signal x: bit_vector(SIZE-1 downto 0);	

	signal clock: 	bit;
	signal reset: 	bit;
	signal inicia: 	bit;
	signal pronto: 	bit;

	

	component formula
		generic (
			size: natural := 4
		);
		port (
			clock, reset: in bit;
			inicia: in bit;
			a, b: in bit_vector(size-1 downto 0);
			pronto: out bit;
			x: out bit_vector(size-1 downto 0)
		);
	end component;

begin
	i1 : formula
	generic map (
		size => SIZE
	)
	port map (
		clock, reset,
		inicia,
		a,b,
		pronto,
		x
	);

	t_clock: process
	begin
		loop
			clock <= '0';
			wait for 10 ns;
			clock <= '1';
			wait for 10 ns;
		end loop;
	end process t_clock;

	process
		type entrada_saida is record
			a: integer;
			b: integer;
			x: integer;
		end record;

		type valores_esperados_array is array (natural range <>) of entrada_saida;
		constant valores_esperados : valores_esperados_array :=
		(
			(12, 8,     24),
			(2,	 -2,    4),
			(1,	 4,     4),
			(-3, 7,     6),
			(8,	 8,     16),
			(-3, -3,    6)
		);

		variable pronto_ok: boolean;
		variable x_ok: boolean;
		
 begin
	report "INICIO DO TESTE..." & LF severity note;
	for i in valores_esperados'range loop
		report 	"TESTANDO PARA: " & LF &
				"a = " & integer'image(valores_esperados(i).a) & LF &
				"b = " & integer'image(valores_esperados(i).b)
		severity note;
		-- reset
		reset <= '1';
		wait for 20 ns;
		reset <= '0';
		--  configura os valores
		a <= bit_vector(to_signed(valores_esperados(i).a, a'length));
		b <= bit_vector(to_signed(valores_esperados(i).b, b'length));
		-- inicia
		inicia <= '1';
		wait for 20 ns;
		inicia <= '0';
		-- espera o resultado final
		wait for 200 ns;
		--  verifica o resultado
		pronto_ok := (pronto = '1');
		x_ok := (to_integer(signed(x)) = valores_esperados(i).x);
		assert pronto_ok
			report 	"N�o deu sinal de pronto!" & LF
			severity error;
		assert x_ok
			report  "Valor de x diferente do esperado!" & LF &
				   	"esperado: " & integer'image(valores_esperados(i).x) & LF &
					"obtido: " & integer'image(to_integer(signed(x))) & LF
			severity error;
		if x_ok and pronto_ok then
			report "TEST OK" & LF severity note;
		end if;
	end loop;
	report "FIM DO TESTE!" severity note;
        std.env.stop;
 end process;

end formula_testbench_arch;

Makefile

GHDL=ghdl
GHDLFLAGS=
MODULES=\
    formula.o \
    formula_testbench.o \
	formula_testbench

all: $(MODULES)
.PHONY: all 

test: $(MODULES)
	@ $(GHDL) -r $(GHDLFLAGS) formula_testbench

# Binary depends on the object file
%: %.o
	$(GHDL) -e $(GHDLFLAGS) $@

# Object file depends on source
%.o: %.vhd
	$(GHDL) -a $(GHDLFLAGS) $<

%.o: %.vht
	$(GHDL) -a $(GHDLFLAGS) $<

clean:
	@ echo "Cleaning up..."
	@ rm -f *.o *_testbench work*.cf