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Notes about clocks in Caravel

2021-05-09 by kbeckmann

These are my notes of how I interpret how the clock tree works in Caravel. It might be inaccurate.

High level module hierarchy

caravel:
@kbeckmann
kbeckmann / callstack.txt
Last active April 8, 2021 19:04
cxxrtl: Segfault when assigning an array element indexed with a wire
Program terminated with signal SIGSEGV, Segmentation fault.
#0 0x0000561db819718a in std::vector<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t, std::allocator<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t> >::size (this=<optimized out>)
at /usr/include/c++/10.2.0/bits/stl_vector.h:919
919 { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }
(gdb) bt
#0 0x0000561db819718a in std::vector<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t, std::allocator<Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_ops<Yosys::RTLIL::IdString> >::entry_t> >::size (this=<optimized out>)
at /usr/include/c++/10.2.0/bits/stl_vector.h:919
#1 Yosys::hashlib::dict<Yosys::RTLIL::IdString, Yosys::RTLIL::Const, Yosys::hashlib::hash_
@kbeckmann
kbeckmann / secworks_chacha_cxxrtl.py
Last active April 7, 2021 10:09
Trying to run cxxrtl with a complex design
from nmigen import *
from nmigen._toolchain.yosys import *
from nmigen.back.cxxrtl import rtlil
import os, subprocess
def _convert_rtlil_text(rtlil_text, black_boxes, verilog_boxes, *, src_loc_at=0):
if black_boxes is not None:
if not isinstance(black_boxes, dict):
raise TypeError("CXXRTL black boxes must be a dictionary, not {!r}"
from nmigen import *
from enum import IntEnum
from nmigen.utils import bits_for
class AccessFlags(IntEnum):
R = 1 << 0
W = 1 << 1
RW = R | W
from nmigen import *
from nmigen.build import *
from nmigen_boards.tang_nano import TangNanoPlatform
class Blinky(Elaboratable):
def elaborate(self, platform):
m = Module()
platform.add_resources([
from nmigen import *
from nmigen.build import *
import itertools
from nmigen_boards.tang_nano import TangNanoPlatform
class Blinky(Elaboratable):
def elaborate(self, platform):
m = Module()
import time
import psutil
import multiprocessing as mp
from multiprocessing import Process
def f(thread, duty, freq, q):
p = psutil.Process()
p.cpu_affinity([thread])
while True:
@kbeckmann
kbeckmann / bond1.netdev
Created September 13, 2019 17:06
LACP port trunking with systemd-networkd
[NetDev]
Name=bond1
Kind=bond
[Bond]
Mode=802.3ad
MIIMonitorSec=1s
LACPTransmitRate=fast
UpDelaySec=2s
DownDelaySec=8s
@kbeckmann
kbeckmann / ConvertRawToSDRAngel.py
Created May 19, 2019 19:28
Convert RAW iq samples to SDRAngel "sdriq" format
import sys
import struct
import binascii
# See https://github.com/f4exb/sdrangel/tree/master/plugins/samplesource/filesource
data = open(sys.argv[1], "rb").read()
out = open(sys.argv[2], "wb")
w = bytearray()
@kbeckmann
kbeckmann / fuzzer.c
Created September 17, 2018 21:09
afl-fuzz harness suitable for afl-launch
/*
$ AFL_USE_ASAN=1 afl-clang-fast fuzzer.c -o fuzzer
$ afl-launch -i in_dir -o out_dir -m none -n $(nproc --all) -- ./fuzzer @@
$ afl-whatsup -s out_dir
*/
#include <stdio.h>
#include <stdlib.h>
#define BUF_SIZE 1024*1024