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September 4, 2025 14:51
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| fbuf frame buffer base: 0xfa09d000000 [sz 33554432] | |
| pci_xhci adding device passthru | |
| Init port 1 0xe03 | |
| Init empty port 2 0x2a0 | |
| Init empty port 3 0x2a0 | |
| Init empty port 4 0x2a0 | |
| Init empty port 5 0x2a0 | |
| Init empty port 6 0x2a0 | |
| Init empty port 7 0x2a0 | |
| Init empty port 8 0x2a0 | |
| pci_xhci dboff: 0x4a0, rtsoff: 0xcc0 | |
| xhci reset unassigned slot (2)? | |
| xhci reset unassigned slot (3)? | |
| xhci reset unassigned slot (4)? | |
| xhci reset unassigned slot (5)? | |
| xhci reset unassigned slot (6)? | |
| xhci reset unassigned slot (7)? | |
| xhci reset unassigned slot (8)? | |
| xhci reset unassigned slot (9)? | |
| xhci reset unassigned slot (10)? | |
| xhci reset unassigned slot (11)? | |
| xhci reset unassigned slot (12)? | |
| xhci reset unassigned slot (13)? | |
| xhci reset unassigned slot (14)? | |
| xhci reset unassigned slot (15)? | |
| xhci reset unassigned slot (16)? | |
| xhci reset unassigned slot (17)? | |
| xhci reset unassigned slot (18)? | |
| xhci reset unassigned slot (19)? | |
| xhci reset unassigned slot (20)? | |
| xhci reset unassigned slot (21)? | |
| xhci reset unassigned slot (22)? | |
| xhci reset unassigned slot (23)? | |
| xhci reset unassigned slot (24)? | |
| xhci reset unassigned slot (25)? | |
| xhci reset unassigned slot (26)? | |
| xhci reset unassigned slot (27)? | |
| xhci reset unassigned slot (28)? | |
| xhci reset unassigned slot (29)? | |
| xhci reset unassigned slot (30)? | |
| xhci reset unassigned slot (31)? | |
| xhci reset unassigned slot (32)? | |
| xhci reset unassigned slot (33)? | |
| xhci reset unassigned slot (34)? | |
| xhci reset unassigned slot (35)? | |
| xhci reset unassigned slot (36)? | |
| xhci reset unassigned slot (37)? | |
| xhci reset unassigned slot (38)? | |
| xhci reset unassigned slot (39)? | |
| xhci reset unassigned slot (40)? | |
| xhci reset unassigned slot (41)? | |
| xhci reset unassigned slot (42)? | |
| xhci reset unassigned slot (43)? | |
| xhci reset unassigned slot (44)? | |
| xhci reset unassigned slot (45)? | |
| xhci reset unassigned slot (46)? | |
| xhci reset unassigned slot (47)? | |
| xhci reset unassigned slot (48)? | |
| xhci reset unassigned slot (49)? | |
| xhci reset unassigned slot (50)? | |
| xhci reset unassigned slot (51)? | |
| xhci reset unassigned slot (52)? | |
| xhci reset unassigned slot (53)? | |
| xhci reset unassigned slot (54)? | |
| xhci reset unassigned slot (55)? | |
| xhci reset unassigned slot (56)? | |
| xhci reset unassigned slot (57)? | |
| xhci reset unassigned slot (58)? | |
| xhci reset unassigned slot (59)? | |
| xhci reset unassigned slot (60)? | |
| xhci reset unassigned slot (61)? | |
| xhci reset unassigned slot (62)? | |
| xhci reset unassigned slot (63)? | |
| xhci reset unassigned slot (64)? | |
| start libusb pullthread | |
| pci_xhci pci_emu_alloc: 3456 | |
| pci_xhci: hostcap read offset 0x0 -> 0x1000020 | |
| pci_xhci: hostcap read offset 0x4 -> 0x8000140 | |
| pci_xhci: hostcap read offset 0x8 -> 0x4 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: hostcap read offset 0x14 -> 0x4a0 | |
| pci_xhci: hostcap read offset 0x18 -> 0xcc0 | |
| pci_xhci: hostop read offset 0x8 -> 0x1 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x4 -> 0x20425355 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x14 -> 0x20425355 | |
| pci_xhci: hostop read offset 0x4 -> 0x1 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x2 | |
| xhci reset unassigned slot (2)? | |
| xhci reset unassigned slot (3)? | |
| xhci reset unassigned slot (4)? | |
| xhci reset unassigned slot (5)? | |
| xhci reset unassigned slot (6)? | |
| xhci reset unassigned slot (7)? | |
| xhci reset unassigned slot (8)? | |
| xhci reset unassigned slot (9)? | |
| xhci reset unassigned slot (10)? | |
| xhci reset unassigned slot (11)? | |
| xhci reset unassigned slot (12)? | |
| xhci reset unassigned slot (13)? | |
| xhci reset unassigned slot (14)? | |
| xhci reset unassigned slot (15)? | |
| xhci reset unassigned slot (16)? | |
| xhci reset unassigned slot (17)? | |
| xhci reset unassigned slot (18)? | |
| xhci reset unassigned slot (19)? | |
| xhci reset unassigned slot (20)? | |
| xhci reset unassigned slot (21)? | |
| xhci reset unassigned slot (22)? | |
| xhci reset unassigned slot (23)? | |
| xhci reset unassigned slot (24)? | |
| xhci reset unassigned slot (25)? | |
| xhci reset unassigned slot (26)? | |
| xhci reset unassigned slot (27)? | |
| xhci reset unassigned slot (28)? | |
| xhci reset unassigned slot (29)? | |
| xhci reset unassigned slot (30)? | |
| xhci reset unassigned slot (31)? | |
| xhci reset unassigned slot (32)? | |
| xhci reset unassigned slot (33)? | |
| xhci reset unassigned slot (34)? | |
| xhci reset unassigned slot (35)? | |
| xhci reset unassigned slot (36)? | |
| xhci reset unassigned slot (37)? | |
| xhci reset unassigned slot (38)? | |
| xhci reset unassigned slot (39)? | |
| xhci reset unassigned slot (40)? | |
| xhci reset unassigned slot (41)? | |
| xhci reset unassigned slot (42)? | |
| xhci reset unassigned slot (43)? | |
| xhci reset unassigned slot (44)? | |
| xhci reset unassigned slot (45)? | |
| xhci reset unassigned slot (46)? | |
| xhci reset unassigned slot (47)? | |
| xhci reset unassigned slot (48)? | |
| xhci reset unassigned slot (49)? | |
| xhci reset unassigned slot (50)? | |
| xhci reset unassigned slot (51)? | |
| xhci reset unassigned slot (52)? | |
| xhci reset unassigned slot (53)? | |
| xhci reset unassigned slot (54)? | |
| xhci reset unassigned slot (55)? | |
| xhci reset unassigned slot (56)? | |
| xhci reset unassigned slot (57)? | |
| xhci reset unassigned slot (58)? | |
| xhci reset unassigned slot (59)? | |
| xhci reset unassigned slot (60)? | |
| xhci reset unassigned slot (61)? | |
| xhci reset unassigned slot (62)? | |
| xhci reset unassigned slot (63)? | |
| xhci reset unassigned slot (64)? | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x38: 0x40 | |
| pci_xhci: hostop write offset 0x30: 0xbf13f000 | |
| pci_xhci: hostop write offset 0x34: 0x0 | |
| pci_xhci: opregs dcbaap = 0xbf13f000 (vaddr 0xf9912f3f000) | |
| pci_xhci: hostop write offset 0x18: 0xbf140001 | |
| pci_xhci: hostop write offset 0x1c: 0x0 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x0 | |
| pci_xhci: rtsregs read offset 0x0 -> 0x0 | |
| pci_xhci: runtime regs write offset 0x20: 0x0 | |
| pci_xhci: rtsregs read offset 0x0 -> 0x0 | |
| pci_xhci: runtime regs write offset 0x20: 0x1 | |
| pci_xhci: runtime regs write offset 0x28: 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141000 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: runtime regs write offset 0x30: 0xbf13f240 | |
| pci_xhci: runtime regs write offset 0x34: 0x0 | |
| pci_xhci: wr erstba erst (0xf9912f3f240) ptr 0xbf141000, sz 512 | |
| pci_xhci: rtsregs read offset 0x0 -> 0x0 | |
| pci_xhci: runtime regs write offset 0x20: 0x2 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x1 | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 0/seg 0, enq idx 0/seg 0, pcs 1 | |
| (erdp=0xbf141000, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x20e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0xe11 | |
| xhci reset port 1 | |
| usb_passthru_reset | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 0/seg 0, enq idx 1/seg 0, pcs 1 | |
| (erdp=0xbf141000, erst=0xbf141000, tblsz=512, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x200e01 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x9, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x00002401, TRB_CYCLE 1/ccs 1 | |
| pci_xhci enable slot (error=0) slot 1 | |
| pci_xhci: command 0x9 result: 0x1 | |
| pci_xhci: insert event 0[bf140000] 2[1000000] 3[1008401] | |
| erdp idx 0/seg 0, enq idx 2/seg 0, pcs 1 | |
| (erdp=0xbf141000, erst=0xbf141000, tblsz=512, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141008 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141038 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141030, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xb, Trb0 x00000000bf13f280 dwTrb2 x00000000 dwTrb3 x01002c01, TRB_CYCLE 1/ccs 1 | |
| pci_xhci: address device, input ctl: D 0x00000000 A 0x00000003, | |
| slot 08300000 00010000 00000000 00000000 | |
| ep0 00000000 00400026 00000000bf143001 00000008 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: address device, dev ctx | |
| slot 00000000 00000000 00000000 00000000 | |
| usb_passthru_reset | |
| init_ep 1 with no pstreams | |
| init_ep tr DCS 1 | |
| pci_xhci: address device, output ctx | |
| slot 08300000 00010000 00000000 10000001 | |
| ep0 00000001 00400026 00000000bf143001 00000008 | |
| pci_xhci: command 0xb result: 0x1 | |
| pci_xhci: insert event 0[bf140010] 2[1000000] 3[1008401] | |
| erdp idx 3/seg 0, enq idx 3/seg 0, pcs 1 | |
| (erdp=0xbf141030, erst=0xbf141000, tblsz=512, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141038 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141048 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141040, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 00400026 00000000bf143001 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f43000] type x02 SETUP_STAGE 0:x0008000001000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f43010 | |
| xhci update ep-ring, addr bf143011 | |
| pci_xhci: trb[@0xf9912f43010] type x03 DATA_STAGE 0:x00000000bff424a8 2:x00000008 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f43020 | |
| xhci update ep-ring, addr bf143021 | |
| pci_xhci: trb[@0xf9912f43020] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f43030 | |
| xhci update ep-ring, addr bf143031 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 8 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143000 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143000] 2[1000000] 3[1018000] | |
| erdp idx 4/seg 0, enq idx 4/seg 0, pcs 1 | |
| (erdp=0xbf141040, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143010 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143010] 2[1000000] 3[1018000] | |
| erdp idx 4/seg 0, enq idx 5/seg 0, pcs 1 | |
| (erdp=0xbf141040, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143020 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143020] 2[1000000] 3[1018000] | |
| erdp idx 4/seg 0, enq idx 6/seg 0, pcs 1 | |
| (erdp=0xbf141040, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141048 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141078 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141070, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 00400026 00000000bf143031 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f43030] type x02 SETUP_STAGE 0:x0012000001000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f43040 | |
| xhci update ep-ring, addr bf143041 | |
| pci_xhci: trb[@0xf9912f43040] type x03 DATA_STAGE 0:x00000000bf13de98 2:x00000012 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f43050 | |
| xhci update ep-ring, addr bf143051 | |
| pci_xhci: trb[@0xf9912f43050] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f43060 | |
| xhci update ep-ring, addr bf143061 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 12 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 18 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143030 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143030] 2[1000000] 3[1018000] | |
| erdp idx 7/seg 0, enq idx 7/seg 0, pcs 1 | |
| (erdp=0xbf141070, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143040 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143040] 2[1000000] 3[1018000] | |
| erdp idx 7/seg 0, enq idx 8/seg 0, pcs 1 | |
| (erdp=0xbf141070, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143050 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143050] 2[1000000] 3[1018000] | |
| erdp idx 7/seg 0, enq idx 9/seg 0, pcs 1 | |
| (erdp=0xbf141070, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141078 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1410a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1410a0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xd, Trb0 x00000000bf13f280 dwTrb2 x00000000 dwTrb3 x01003401, TRB_CYCLE 1/ccs 1 | |
| pci_xhci: eval ctx, input ctl: D 0x00000000 A 0x00000002, | |
| slot 00000000 00000000 00000000 00000000 | |
| ep0 00000000 02000026 00000000bf143061 00000008 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: eval ctx, dev ctx | |
| slot 08300000 00010000 00000000 10000001 | |
| pci_xhci: eval ctx, output ctx | |
| slot 08300000 00010000 00000000 10000001 | |
| ep0 00000001 02000026 00000000bf143061 00000008 | |
| pci_xhci: command 0xd result: 0x1 | |
| pci_xhci: insert event 0[bf140020] 2[1000000] 3[1008401] | |
| erdp idx 10/seg 0, enq idx 10/seg 0, pcs 1 | |
| (erdp=0xbf1410a0, erst=0xbf141000, tblsz=512, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf1410a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1410b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1410b0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143061 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f43060] type x02 SETUP_STAGE 0:x0008000002000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f43070 | |
| xhci update ep-ring, addr bf143071 | |
| pci_xhci: trb[@0xf9912f43070] type x03 DATA_STAGE 0:x00000000bff424a8 2:x00000008 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f43080 | |
| xhci update ep-ring, addr bf143081 | |
| pci_xhci: trb[@0xf9912f43080] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f43090 | |
| xhci update ep-ring, addr bf143091 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 8 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143060 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143060] 2[1000000] 3[1018000] | |
| erdp idx 11/seg 0, enq idx 11/seg 0, pcs 1 | |
| (erdp=0xbf1410b0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143070 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143070] 2[1000000] 3[1018000] | |
| erdp idx 11/seg 0, enq idx 12/seg 0, pcs 1 | |
| (erdp=0xbf1410b0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143080 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143080] 2[1000000] 3[1018000] | |
| erdp idx 11/seg 0, enq idx 13/seg 0, pcs 1 | |
| (erdp=0xbf1410b0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf1410b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1410e8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1410e0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143091 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f43090] type x02 SETUP_STAGE 0:x0079000002000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f430a0 | |
| xhci update ep-ring, addr bf1430a1 | |
| pci_xhci: trb[@0xf9912f430a0] type x03 DATA_STAGE 0:x00000000bf13d098 2:x00000079 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f430b0 | |
| xhci update ep-ring, addr bf1430b1 | |
| pci_xhci: trb[@0xf9912f430b0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f430c0 | |
| xhci update ep-ring, addr bf1430c1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 79 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 121 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143090 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143090] 2[1000000] 3[1018000] | |
| erdp idx 14/seg 0, enq idx 14/seg 0, pcs 1 | |
| (erdp=0xbf1410e0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf1430a0 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430a0] 2[1000000] 3[1018000] | |
| erdp idx 14/seg 0, enq idx 15/seg 0, pcs 1 | |
| (erdp=0xbf1410e0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf1430b0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430b0] 2[1000000] 3[1018000] | |
| erdp idx 14/seg 0, enq idx 16/seg 0, pcs 1 | |
| (erdp=0xbf1410e0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf1410e8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141118 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141110, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf1430c1 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f430c0] type x02 SETUP_STAGE 0:x0002000003000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f430d0 | |
| xhci update ep-ring, addr bf1430d1 | |
| pci_xhci: trb[@0xf9912f430d0] type x03 DATA_STAGE 0:x00000000bff4240c 2:x00000002 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f430e0 | |
| xhci update ep-ring, addr bf1430e1 | |
| pci_xhci: trb[@0xf9912f430e0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f430f0 | |
| xhci update ep-ring, addr bf1430f1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 300 wIndex: 0 wLength: 2 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 2 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf1430c0 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430c0] 2[1000000] 3[1018000] | |
| erdp idx 17/seg 0, enq idx 17/seg 0, pcs 1 | |
| (erdp=0xbf141110, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf1430d0 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430d0] 2[1000000] 3[1018000] | |
| erdp idx 17/seg 0, enq idx 18/seg 0, pcs 1 | |
| (erdp=0xbf141110, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf1430e0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430e0] 2[1000000] 3[1018000] | |
| erdp idx 17/seg 0, enq idx 19/seg 0, pcs 1 | |
| (erdp=0xbf141110, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141118 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141148 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141140, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf1430f1 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f430f0] type x02 SETUP_STAGE 0:x0004000003000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f43100 | |
| xhci update ep-ring, addr bf143101 | |
| pci_xhci: trb[@0xf9912f43100] type x03 DATA_STAGE 0:x00000000bf13cc98 2:x00000004 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f43110 | |
| xhci update ep-ring, addr bf143111 | |
| pci_xhci: trb[@0xf9912f43110] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f43120 | |
| xhci update ep-ring, addr bf143121 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 300 wIndex: 0 wLength: 4 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 4 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf1430f0 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430f0] 2[1000000] 3[1018000] | |
| erdp idx 20/seg 0, enq idx 20/seg 0, pcs 1 | |
| (erdp=0xbf141140, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143100 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143100] 2[1000000] 3[1018000] | |
| erdp idx 20/seg 0, enq idx 21/seg 0, pcs 1 | |
| (erdp=0xbf141140, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143110 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143110] 2[1000000] 3[1018000] | |
| erdp idx 20/seg 0, enq idx 22/seg 0, pcs 1 | |
| (erdp=0xbf141140, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141148 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141178 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141170, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143121 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f43120] type x02 SETUP_STAGE 0:x0000000000010900 2:x00000008 3:x00000861 | |
| pci_xhci: next trb: 0xf9912f43130 | |
| xhci update ep-ring, addr bf143131 | |
| pci_xhci: trb[@0xf9912f43130] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0xf9912f43140 | |
| xhci update ep-ring, addr bf143141 | |
| pci_xhci[1948]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143120 861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143120] 2[1000000] 3[1018000] | |
| erdp idx 23/seg 0, enq idx 23/seg 0, pcs 1 | |
| (erdp=0xbf141170, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000000bf143130 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143130] 2[1000000] 3[1018000] | |
| erdp idx 23/seg 0, enq idx 24/seg 0, pcs 1 | |
| (erdp=0xbf141170, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141178 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141198 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141190, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000000bf13f280 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000000 A:x00000019 7:x00000000 | |
| enable ep[3] 00000000 04000036 00000000bf144001 00001000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[4] 00000000 04000016 00000000bf145001 00001000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20300000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[bf140030] 2[1000000] 3[1008401] | |
| erdp idx 25/seg 0, enq idx 25/seg 0, pcs 1 | |
| (erdp=0xbf141190, erst=0xbf141000, tblsz=512, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141198 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1411a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1411a0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143141 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f43140] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f43150 | |
| xhci update ep-ring, addr bf143151 | |
| pci_xhci: trb[@0xf9912f43150] type x03 DATA_STAGE 0:x00000000bff42562 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f43160 | |
| xhci update ep-ring, addr bf143161 | |
| pci_xhci: trb[@0xf9912f43160] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f43170 | |
| xhci update ep-ring, addr bf143171 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143140 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143140] 2[1000000] 3[1018000] | |
| erdp idx 26/seg 0, enq idx 26/seg 0, pcs 1 | |
| (erdp=0xbf1411a0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143150 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143150] 2[1000000] 3[1018000] | |
| erdp idx 26/seg 0, enq idx 27/seg 0, pcs 1 | |
| (erdp=0xbf1411a0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143160 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143160] 2[1000000] 3[1018000] | |
| erdp idx 26/seg 0, enq idx 28/seg 0, pcs 1 | |
| (erdp=0xbf1411a0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf1411a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1411d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1411d0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143171 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f43170] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f43180 | |
| xhci update ep-ring, addr bf143181 | |
| pci_xhci: trb[@0xf9912f43180] type x03 DATA_STAGE 0:x00000000bff42622 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f43190 | |
| xhci update ep-ring, addr bf143191 | |
| pci_xhci: trb[@0xf9912f43190] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f431a0 | |
| xhci update ep-ring, addr bf1431a1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143170 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143170] 2[1000000] 3[1018000] | |
| erdp idx 29/seg 0, enq idx 29/seg 0, pcs 1 | |
| (erdp=0xbf1411d0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143180 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143180] 2[1000000] 3[1018000] | |
| erdp idx 29/seg 0, enq idx 30/seg 0, pcs 1 | |
| (erdp=0xbf1411d0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143190 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143190] 2[1000000] 3[1018000] | |
| erdp idx 29/seg 0, enq idx 31/seg 0, pcs 1 | |
| (erdp=0xbf1411d0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf1411d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141208 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141200, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf1431a1 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f431a0] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f431b0 | |
| xhci update ep-ring, addr bf1431b1 | |
| pci_xhci: trb[@0xf9912f431b0] type x03 DATA_STAGE 0:x00000000bff42652 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f431c0 | |
| xhci update ep-ring, addr bf1431c1 | |
| pci_xhci: trb[@0xf9912f431c0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f431d0 | |
| xhci update ep-ring, addr bf1431d1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf1431a0 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431a0] 2[1000000] 3[1018000] | |
| erdp idx 32/seg 0, enq idx 32/seg 0, pcs 1 | |
| (erdp=0xbf141200, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf1431b0 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431b0] 2[1000000] 3[1018000] | |
| erdp idx 32/seg 0, enq idx 33/seg 0, pcs 1 | |
| (erdp=0xbf141200, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf1431c0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431c0] 2[1000000] 3[1018000] | |
| erdp idx 32/seg 0, enq idx 34/seg 0, pcs 1 | |
| (erdp=0xbf141200, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141208 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141238 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141230, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf1431d1 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f431d0] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f431e0 | |
| xhci update ep-ring, addr bf1431e1 | |
| pci_xhci: trb[@0xf9912f431e0] type x03 DATA_STAGE 0:x00000000bff42712 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f431f0 | |
| xhci update ep-ring, addr bf1431f1 | |
| pci_xhci: trb[@0xf9912f431f0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f43200 | |
| xhci update ep-ring, addr bf143201 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf1431d0 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431d0] 2[1000000] 3[1018000] | |
| erdp idx 35/seg 0, enq idx 35/seg 0, pcs 1 | |
| (erdp=0xbf141230, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf1431e0 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431e0] 2[1000000] 3[1018000] | |
| erdp idx 35/seg 0, enq idx 36/seg 0, pcs 1 | |
| (erdp=0xbf141230, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf1431f0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431f0] 2[1000000] 3[1018000] | |
| erdp idx 35/seg 0, enq idx 37/seg 0, pcs 1 | |
| (erdp=0xbf141230, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141238 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141268 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141260, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143201 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f43200] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f43210 | |
| xhci update ep-ring, addr bf143211 | |
| pci_xhci: trb[@0xf9912f43210] type x03 DATA_STAGE 0:x00000000bff42802 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f43220 | |
| xhci update ep-ring, addr bf143221 | |
| pci_xhci: trb[@0xf9912f43220] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f43230 | |
| xhci update ep-ring, addr bf143231 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143200 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143200] 2[1000000] 3[1018000] | |
| erdp idx 38/seg 0, enq idx 38/seg 0, pcs 1 | |
| (erdp=0xbf141260, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143210 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143210] 2[1000000] 3[1018000] | |
| erdp idx 38/seg 0, enq idx 39/seg 0, pcs 1 | |
| (erdp=0xbf141260, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143220 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143220] 2[1000000] 3[1018000] | |
| erdp idx 38/seg 0, enq idx 40/seg 0, pcs 1 | |
| (erdp=0xbf141260, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141268 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141298 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141290, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143231 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9912f43230] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0xf9912f43240 | |
| xhci update ep-ring, addr bf143241 | |
| pci_xhci: trb[@0xf9912f43240] type x03 DATA_STAGE 0:x00000000bff42542 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0xf9912f43250 | |
| xhci update ep-ring, addr bf143251 | |
| pci_xhci: trb[@0xf9912f43250] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf9912f43260 | |
| xhci update ep-ring, addr bf143261 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143230 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143230] 2[1000000] 3[1018000] | |
| erdp idx 41/seg 0, enq idx 41/seg 0, pcs 1 | |
| (erdp=0xbf141290, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143240 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143240] 2[1000000] 3[1018000] | |
| erdp idx 41/seg 0, enq idx 42/seg 0, pcs 1 | |
| (erdp=0xbf141290, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143250 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143250] 2[1000000] 3[1018000] | |
| erdp idx 41/seg 0, enq idx 43/seg 0, pcs 1 | |
| (erdp=0xbf141290, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141298 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1412c8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1412c0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: hostop read offset 0x0 -> 0x1 | |
| pci_xhci: hostop write offset 0x0: 0x0 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostcap read offset 0x0 -> 0x1000020 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x0 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostcap read offset 0x0 -> 0x1000020 | |
| pci_xhci: hostcap read offset 0x18 -> 0xcc0 | |
| pci_xhci: hostcap read offset 0x4 -> 0x8000140 | |
| pci_xhci: hostcap read offset 0x8 -> 0x4 | |
| pci_xhci: hostcap read offset 0xc -> 0x0 | |
| pci_xhci: hostcap read offset 0x0 -> 0x1000020 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x0 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x2 | |
| xhci reset unassigned slot (2)? | |
| xhci reset unassigned slot (3)? | |
| xhci reset unassigned slot (4)? | |
| xhci reset unassigned slot (5)? | |
| xhci reset unassigned slot (6)? | |
| xhci reset unassigned slot (7)? | |
| xhci reset unassigned slot (8)? | |
| xhci reset unassigned slot (9)? | |
| xhci reset unassigned slot (10)? | |
| xhci reset unassigned slot (11)? | |
| xhci reset unassigned slot (12)? | |
| xhci reset unassigned slot (13)? | |
| xhci reset unassigned slot (14)? | |
| xhci reset unassigned slot (15)? | |
| xhci reset unassigned slot (16)? | |
| xhci reset unassigned slot (17)? | |
| xhci reset unassigned slot (18)? | |
| xhci reset unassigned slot (19)? | |
| xhci reset unassigned slot (20)? | |
| xhci reset unassigned slot (21)? | |
| xhci reset unassigned slot (22)? | |
| xhci reset unassigned slot (23)? | |
| xhci reset unassigned slot (24)? | |
| xhci reset unassigned slot (25)? | |
| xhci reset unassigned slot (26)? | |
| xhci reset unassigned slot (27)? | |
| xhci reset unassigned slot (28)? | |
| xhci reset unassigned slot (29)? | |
| xhci reset unassigned slot (30)? | |
| xhci reset unassigned slot (31)? | |
| xhci reset unassigned slot (32)? | |
| xhci reset unassigned slot (33)? | |
| xhci reset unassigned slot (34)? | |
| xhci reset unassigned slot (35)? | |
| xhci reset unassigned slot (36)? | |
| xhci reset unassigned slot (37)? | |
| xhci reset unassigned slot (38)? | |
| xhci reset unassigned slot (39)? | |
| xhci reset unassigned slot (40)? | |
| xhci reset unassigned slot (41)? | |
| xhci reset unassigned slot (42)? | |
| xhci reset unassigned slot (43)? | |
| xhci reset unassigned slot (44)? | |
| xhci reset unassigned slot (45)? | |
| xhci reset unassigned slot (46)? | |
| xhci reset unassigned slot (47)? | |
| xhci reset unassigned slot (48)? | |
| xhci reset unassigned slot (49)? | |
| xhci reset unassigned slot (50)? | |
| xhci reset unassigned slot (51)? | |
| xhci reset unassigned slot (52)? | |
| xhci reset unassigned slot (53)? | |
| xhci reset unassigned slot (54)? | |
| xhci reset unassigned slot (55)? | |
| xhci reset unassigned slot (56)? | |
| xhci reset unassigned slot (57)? | |
| xhci reset unassigned slot (58)? | |
| xhci reset unassigned slot (59)? | |
| xhci reset unassigned slot (60)? | |
| xhci reset unassigned slot (61)? | |
| xhci reset unassigned slot (62)? | |
| xhci reset unassigned slot (63)? | |
| xhci reset unassigned slot (64)? | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostop read offset 0x8 -> 0x1 | |
| pci_xhci: hostcap read offset 0x4 -> 0x8000140 | |
| pci_xhci: hostop read offset 0x38 -> 0x40 | |
| pci_xhci: hostop write offset 0x38: 0x40 | |
| pci_xhci: hostop write offset 0x30: 0x42a0000 | |
| pci_xhci: hostop write offset 0x34: 0x1 | |
| pci_xhci: opregs dcbaap = 0x1042a0000 (vaddr 0xf99580a0000) | |
| pci_xhci: hostop read offset 0x18 -> 0x0 | |
| pci_xhci: hostop read offset 0x1c -> 0x0 | |
| pci_xhci: hostop write offset 0x18: 0x42a1001 | |
| pci_xhci: hostop write offset 0x1c: 0x1 | |
| pci_xhci: hostcap read offset 0x14 -> 0x4a0 | |
| pci_xhci: rtsregs read offset 0x8 -> 0x1 | |
| pci_xhci: runtime regs write offset 0x28: 0x1 | |
| pci_xhci: rtsregs read offset 0x10 -> 0xbf13f240 | |
| pci_xhci: rtsregs read offset 0x14 -> 0x0 | |
| pci_xhci: runtime regs write offset 0x30: 0x42a3000 | |
| pci_xhci: runtime regs write offset 0x34: 0x1 | |
| pci_xhci: wr erstba erst (0xf99580a3000) ptr 0x1042a2000, sz 256 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2000 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: hostop read offset 0x14 -> 0x0 | |
| pci_xhci: hostop write offset 0x14: 0x2 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2000 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: rtsregs read offset 0x4 -> 0x0 | |
| pci_xhci: runtime regs write offset 0x24: 0xa0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostcap read offset 0x0 -> 0x1000020 | |
| pci_xhci: hostcap read offset 0x18 -> 0xcc0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x4 | |
| pci_xhci: rtsregs read offset 0x0 -> 0x2 | |
| pci_xhci: runtime regs write offset 0x20: 0x2 | |
| pci_xhci: hostop read offset 0x0 -> 0x4 | |
| pci_xhci: hostop write offset 0x0: 0x5 | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 0/seg 0, enq idx 0/seg 0, pcs 1 | |
| (erdp=0x1042a2000, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop write offset 0x4: 0x18 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2008 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2018 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2010, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: hostcap read offset 0xc -> 0x0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0xe01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 2: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 2 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 3: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 3 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 4: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 4 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x9, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x00002401, TRB_CYCLE 1/ccs 1 | |
| pci_xhci enable slot (error=0) slot 1 | |
| pci_xhci: command 0x9 result: 0x1 | |
| pci_xhci: insert event 0[1042a1000] 2[1000000] 3[1008401] | |
| erdp idx 1/seg 0, enq idx 1/seg 0, pcs 1 | |
| (erdp=0x1042a2010, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2018 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2028 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2020, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0xe11 | |
| xhci reset port 1 | |
| usb_passthru_reset | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 2/seg 0, enq idx 2/seg 0, pcs 1 | |
| (erdp=0x1042a2020, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2028 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2038 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2030, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x200e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x80e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x400e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x20e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xb, Trb0 x00000001042ba000 dwTrb2 x00000000 dwTrb3 x01002c01, TRB_CYCLE 1/ccs 1 | |
| pci_xhci: address device, input ctl: D 0x00000000 A 0x00000003, | |
| slot 08400000 00010000 00000000 00000000 | |
| ep0 00000000 02000026 00000001042bb001 00000000 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: address device, dev ctx | |
| slot 00000000 00000000 00000000 00000000 | |
| usb_passthru_reset | |
| init_ep 1 with no pstreams | |
| init_ep tr DCS 1 | |
| pci_xhci: address device, output ctx | |
| slot 08400000 00010000 00000000 10000001 | |
| ep0 00000001 02000026 00000001042bb001 00000000 | |
| pci_xhci: command 0xb result: 0x1 | |
| pci_xhci: insert event 0[1042a1010] 2[1000000] 3[1008401] | |
| erdp idx 3/seg 0, enq idx 3/seg 0, pcs 1 | |
| (erdp=0x1042a2030, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2038 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2048 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2040, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: hostop read offset 0x30 -> 0x42a0000 | |
| pci_xhci: hostop read offset 0x34 -> 0x1 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb001 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb000] type x02 SETUP_STAGE 0:x0008000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb010 | |
| xhci update ep-ring, addr 1042bb011 | |
| pci_xhci: trb[@0xf99580bb010] type x03 DATA_STAGE 0:x0000000104290480 2:x00000008 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb020 | |
| xhci update ep-ring, addr 1042bb021 | |
| pci_xhci: trb[@0xf99580bb020] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb030 | |
| xhci update ep-ring, addr 1042bb031 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 8 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb000 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb010 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb020 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb020] 2[1000000] 3[1018000] | |
| erdp idx 4/seg 0, enq idx 4/seg 0, pcs 1 | |
| (erdp=0x1042a2040, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2048 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2058 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2050, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb031 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb030] type x02 SETUP_STAGE 0:x0000000000283100 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0xf99580bb040 | |
| xhci update ep-ring, addr 1042bb041 | |
| pci_xhci: trb[@0xf99580bb040] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0xf99580bb050 | |
| xhci update ep-ring, addr 1042bb051 | |
| pci_xhci[1948]: xfer->ndata 2 1 | |
| usb_passthru_request: bRequest: 31 bmRequestType: 0 wValue: 28 wIndex: 0 wLength: 0 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb030 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000001042bb040 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb040] 2[1000000] 3[1018000] | |
| erdp idx 5/seg 0, enq idx 5/seg 0, pcs 1 | |
| (erdp=0x1042a2050, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2058 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2068 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2060, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb051 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb050] type x02 SETUP_STAGE 0:x0012000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb060 | |
| xhci update ep-ring, addr 1042bb061 | |
| pci_xhci: trb[@0xf99580bb060] type x03 DATA_STAGE 0:x0000000104199ea0 2:x00000012 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb070 | |
| xhci update ep-ring, addr 1042bb071 | |
| pci_xhci: trb[@0xf99580bb070] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb080 | |
| xhci update ep-ring, addr 1042bb081 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 12 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 18 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb050 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb060 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb070 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb070] 2[1000000] 3[1018000] | |
| erdp idx 6/seg 0, enq idx 6/seg 0, pcs 1 | |
| (erdp=0x1042a2060, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2068 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2078 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2070, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb081 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb080] type x02 SETUP_STAGE 0:x000500000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb090 | |
| xhci update ep-ring, addr 1042bb091 | |
| pci_xhci: trb[@0xf99580bb090] type x03 DATA_STAGE 0:x00000001041cc4e0 2:x00000005 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb0a0 | |
| xhci update ep-ring, addr 1042bb0a1 | |
| pci_xhci: trb[@0xf99580bb0a0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb0b0 | |
| xhci update ep-ring, addr 1042bb0b1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 5 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 5 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb080 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb090 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb0a0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb0a0] 2[1000000] 3[1018000] | |
| erdp idx 7/seg 0, enq idx 7/seg 0, pcs 1 | |
| (erdp=0x1042a2070, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2078 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2088 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2080, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb0b1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb0b0] type x02 SETUP_STAGE 0:x001600000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb0c0 | |
| xhci update ep-ring, addr 1042bb0c1 | |
| pci_xhci: trb[@0xf99580bb0c0] type x03 DATA_STAGE 0:x0000000104199ea0 2:x00000016 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb0d0 | |
| xhci update ep-ring, addr 1042bb0d1 | |
| pci_xhci: trb[@0xf99580bb0d0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb0e0 | |
| xhci update ep-ring, addr 1042bb0e1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 16 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 22 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb0b0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb0c0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb0d0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb0d0] 2[1000000] 3[1018000] | |
| erdp idx 8/seg 0, enq idx 8/seg 0, pcs 1 | |
| (erdp=0x1042a2080, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2088 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2098 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2090, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb0e1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb0e0] type x02 SETUP_STAGE 0:x0009000002000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb0f0 | |
| xhci update ep-ring, addr 1042bb0f1 | |
| pci_xhci: trb[@0xf99580bb0f0] type x03 DATA_STAGE 0:x0000000100c25950 2:x00000009 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb100 | |
| xhci update ep-ring, addr 1042bb101 | |
| pci_xhci: trb[@0xf99580bb100] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb110 | |
| xhci update ep-ring, addr 1042bb111 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 9 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 9 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb0e0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb0f0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb100 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb100] 2[1000000] 3[1018000] | |
| erdp idx 9/seg 0, enq idx 9/seg 0, pcs 1 | |
| (erdp=0x1042a2090, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2098 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a20a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a20a0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb111 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb110] type x02 SETUP_STAGE 0:x0079000002000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb120 | |
| xhci update ep-ring, addr 1042bb121 | |
| pci_xhci: trb[@0xf99580bb120] type x03 DATA_STAGE 0:x00000001042a6c80 2:x00000079 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb130 | |
| xhci update ep-ring, addr 1042bb131 | |
| pci_xhci: trb[@0xf99580bb130] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb140 | |
| xhci update ep-ring, addr 1042bb141 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 79 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 121 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb110 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb120 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb130 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb130] 2[1000000] 3[1018000] | |
| erdp idx 10/seg 0, enq idx 10/seg 0, pcs 1 | |
| (erdp=0x1042a20a0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a20a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a20b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a20b0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb141 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb140] type x02 SETUP_STAGE 0:x00ff000003000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb150 | |
| xhci update ep-ring, addr 1042bb151 | |
| pci_xhci: trb[@0xf99580bb150] type x03 DATA_STAGE 0:x0000000101c43500 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb160 | |
| xhci update ep-ring, addr 1042bb161 | |
| pci_xhci: trb[@0xf99580bb160] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb170 | |
| xhci update ep-ring, addr 1042bb171 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 300 wIndex: 0 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 251 txlen 4 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb140 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:251 trb 3 00000001042bb150 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[1042bb150] 2[d0000fb] 3[1018000] | |
| erdp idx 11/seg 0, enq idx 11/seg 0, pcs 1 | |
| (erdp=0x1042a20b0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb160 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb160] 2[10000fb] 3[1018000] | |
| erdp idx 11/seg 0, enq idx 12/seg 0, pcs 1 | |
| (erdp=0x1042a20b0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a20b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a20d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a20d0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb171 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb170] type x02 SETUP_STAGE 0:x00ff040903030680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb180 | |
| xhci update ep-ring, addr 1042bb181 | |
| pci_xhci: trb[@0xf99580bb180] type x03 DATA_STAGE 0:x0000000101c43500 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb190 | |
| xhci update ep-ring, addr 1042bb191 | |
| pci_xhci: trb[@0xf99580bb190] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb1a0 | |
| xhci update ep-ring, addr 1042bb1a1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 303 wIndex: 1033 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 223 txlen 32 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb170 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:223 trb 3 00000001042bb180 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[1042bb180] 2[d0000df] 3[1018000] | |
| erdp idx 13/seg 0, enq idx 13/seg 0, pcs 1 | |
| (erdp=0x1042a20d0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb190 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb190] 2[10000df] 3[1018000] | |
| erdp idx 13/seg 0, enq idx 14/seg 0, pcs 1 | |
| (erdp=0x1042a20d0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a20d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a20f8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a20f0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb1a1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb1a0] type x02 SETUP_STAGE 0:x00ff040903020680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb1b0 | |
| xhci update ep-ring, addr 1042bb1b1 | |
| pci_xhci: trb[@0xf99580bb1b0] type x03 DATA_STAGE 0:x0000000101c43500 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb1c0 | |
| xhci update ep-ring, addr 1042bb1c1 | |
| pci_xhci: trb[@0xf99580bb1c0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb1d0 | |
| xhci update ep-ring, addr 1042bb1d1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 302 wIndex: 1033 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 237 txlen 18 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb1a0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:237 trb 3 00000001042bb1b0 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[1042bb1b0] 2[d0000ed] 3[1018000] | |
| erdp idx 15/seg 0, enq idx 15/seg 0, pcs 1 | |
| (erdp=0x1042a20f0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb1c0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb1c0] 2[10000ed] 3[1018000] | |
| erdp idx 15/seg 0, enq idx 16/seg 0, pcs 1 | |
| (erdp=0x1042a20f0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a20f8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2118 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2110, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb1d1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb1d0] type x02 SETUP_STAGE 0:x00ff040903010680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb1e0 | |
| xhci update ep-ring, addr 1042bb1e1 | |
| pci_xhci: trb[@0xf99580bb1e0] type x03 DATA_STAGE 0:x0000000101c43500 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb1f0 | |
| xhci update ep-ring, addr 1042bb1f1 | |
| pci_xhci: trb[@0xf99580bb1f0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb200 | |
| xhci update ep-ring, addr 1042bb201 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 301 wIndex: 1033 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 229 txlen 26 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb1d0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:229 trb 3 00000001042bb1e0 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[1042bb1e0] 2[d0000e5] 3[1018000] | |
| erdp idx 17/seg 0, enq idx 17/seg 0, pcs 1 | |
| (erdp=0x1042a2110, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb1f0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb1f0] 2[10000e5] 3[1018000] | |
| erdp idx 17/seg 0, enq idx 18/seg 0, pcs 1 | |
| (erdp=0x1042a2110, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2118 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2138 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2130, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042ba000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000000 A:x00000019 7:x00000000 | |
| enable ep[3] 00000000 04000f36 00000001042c0001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[4] 00000000 04000f16 00000001042c2001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1020] 2[1000000] 3[1008401] | |
| erdp idx 19/seg 0, enq idx 19/seg 0, pcs 1 | |
| (erdp=0x1042a2130, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2138 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2148 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2140, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01033c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 3: slot 1: type 15 | |
| pci_xhci: reset ep[3] 00000003 04000f36 00000001042c0001 00000000 | |
| pci_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[1042a1030] 2[1000000] 3[1008401] | |
| erdp idx 20/seg 0, enq idx 20/seg 0, pcs 1 | |
| (erdp=0x1042a2140, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2148 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2158 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2150, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042c4000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000008 A:x00000009 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000003 04000f36 00000001042c0001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1040] 2[1000000] 3[1008401] | |
| erdp idx 21/seg 0, enq idx 21/seg 0, pcs 1 | |
| (erdp=0x1042a2150, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2158 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2168 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2160, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01043c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 4: slot 1: type 15 | |
| pci_xhci: reset ep[4] 00000003 04000f16 00000001042c2001 00000000 | |
| pci_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[1042a1050] 2[1000000] 3[1008401] | |
| erdp idx 22/seg 0, enq idx 22/seg 0, pcs 1 | |
| (erdp=0x1042a2160, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2168 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2178 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2170, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042c4000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000010 A:x00000011 7:x00000000 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000003 04000f16 00000001042c2001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1060] 2[1000000] 3[1008401] | |
| erdp idx 23/seg 0, enq idx 23/seg 0, pcs 1 | |
| (erdp=0x1042a2170, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2178 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2188 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2180, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb201 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb200] type x02 SETUP_STAGE 0:x0000000000010900 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0xf99580bb210 | |
| xhci update ep-ring, addr 1042bb211 | |
| pci_xhci: trb[@0xf99580bb210] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0xf99580bb220 | |
| xhci update ep-ring, addr 1042bb221 | |
| pci_xhci[1948]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb200 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000001042bb210 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb210] 2[1000000] 3[1018000] | |
| erdp idx 24/seg 0, enq idx 24/seg 0, pcs 1 | |
| (erdp=0x1042a2180, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2188 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2198 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2190, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042ba000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000018 A:x00000199 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000000 04000f36 00000001069f3001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000000 04000f16 0000000100c10001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[7] 00000000 04000f36 0000000100c8b001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[8] 00000000 04000016 0000000100c69001 00000000 | |
| init_ep 8 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1070] 2[1000000] 3[1008401] | |
| erdp idx 25/seg 0, enq idx 25/seg 0, pcs 1 | |
| (erdp=0x1042a2190, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2198 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a21a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a21a0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb221 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb220] type x02 SETUP_STAGE 0:x0000000000010b01 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0xf99580bb230 | |
| xhci update ep-ring, addr 1042bb231 | |
| pci_xhci: trb[@0xf99580bb230] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0xf99580bb240 | |
| xhci update ep-ring, addr 1042bb241 | |
| pci_xhci[1948]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb220 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000001042bb230 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb230] 2[1000000] 3[1018000] | |
| erdp idx 26/seg 0, enq idx 26/seg 0, pcs 1 | |
| (erdp=0x1042a21a0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a21a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a21b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a21b0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01033c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 3: slot 1: type 15 | |
| pci_xhci: reset ep[3] 00000003 04000f36 00000001069f3001 00000000 | |
| pci_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[1042a1080] 2[1000000] 3[1008401] | |
| erdp idx 27/seg 0, enq idx 27/seg 0, pcs 1 | |
| (erdp=0x1042a21b0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a21b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a21c8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a21c0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042c4000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000008 A:x00000009 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000003 04000f36 00000001069f3001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1090] 2[1000000] 3[1008401] | |
| erdp idx 28/seg 0, enq idx 28/seg 0, pcs 1 | |
| (erdp=0x1042a21c0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a21c8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a21d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a21d0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01043c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 4: slot 1: type 15 | |
| pci_xhci: reset ep[4] 00000003 04000f16 0000000100c10001 00000000 | |
| pci_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[1042a10a0] 2[1000000] 3[1008401] | |
| erdp idx 29/seg 0, enq idx 29/seg 0, pcs 1 | |
| (erdp=0x1042a21d0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a21d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a21e8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a21e0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042c4000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000010 A:x00000011 7:x00000000 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000003 04000f16 0000000100c10001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a10b0] 2[1000000] 3[1008401] | |
| erdp idx 30/seg 0, enq idx 30/seg 0, pcs 1 | |
| (erdp=0x1042a21e0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a21e8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a21f8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a21f0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01073c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 7: slot 1: type 15 | |
| pci_xhci: reset ep[7] 00000003 04000f36 0000000100c8b001 00000000 | |
| pci_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[1042a10c0] 2[1000000] 3[1008401] | |
| erdp idx 31/seg 0, enq idx 31/seg 0, pcs 1 | |
| (erdp=0x1042a21f0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a21f8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2208 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2200, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042c4000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000080 A:x00000081 7:x00000000 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00000003 04000f36 0000000100c8b001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a10d0] 2[1000000] 3[1008401] | |
| erdp idx 32/seg 0, enq idx 32/seg 0, pcs 1 | |
| (erdp=0x1042a2200, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2208 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2218 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2210, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01083c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 8: slot 1: type 15 | |
| pci_xhci: reset ep[8] 00000003 04000016 0000000100c69001 00000000 | |
| pci_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[1042a10e0] 2[1000000] 3[1008401] | |
| erdp idx 33/seg 0, enq idx 33/seg 0, pcs 1 | |
| (erdp=0x1042a2210, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2218 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2228 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2220, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042c4000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000100 A:x00000101 7:x00000000 | |
| config ep - dropping ep 8 | |
| pci_xhci disable_ep 8 | |
| enable ep[8] 00000003 04000016 0000000100c69001 00000000 | |
| init_ep 8 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a10f0] 2[1000000] 3[1008401] | |
| erdp idx 34/seg 0, enq idx 34/seg 0, pcs 1 | |
| (erdp=0x1042a2220, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2228 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2238 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2230, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042c4000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000098 A:x00000099 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00008401 04000f36 0000000100c07100 00000000 | |
| init_ep 3 with pstreams 4 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00008401 04000f16 0000000100c07200 00000000 | |
| init_ep 4 with pstreams 4 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00008401 04000f36 0000000100c07000 00000000 | |
| init_ep 7 with pstreams 4 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1100] 2[1000000] 3[1008401] | |
| erdp idx 35/seg 0, enq idx 35/seg 0, pcs 1 | |
| (erdp=0x1042a2230, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2238 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2248 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2240, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x10007 | |
| pci_xhci doorbell slot 1 epid 7 stream 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[7] 00008401 04000f36 0000000100c07000 00000000 | |
| pci_xhci: invalid stream 1: 34 | |
| pci_xhci: doorbell write offset 0x1: 0x10003 | |
| pci_xhci doorbell slot 1 epid 3 stream 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[3] 00008401 04000f36 0000000100c07100 00000000 | |
| pci_xhci: invalid stream 1: 34 | |
| pci_xhci: doorbell write offset 0x1: 0x8 | |
| pci_xhci doorbell slot 1 epid 8 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[8] 00000001 04000016 0000000100c69001 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf9954a69000] type x01 NORMAL 0:x0000000100a71680 2:x00000020 3:x00000421 | |
| pci_xhci: next trb: 0xf9954a69010 | |
| xhci update ep-ring, addr 100c69011 | |
| pci_xhci[1948]: xfer->ndata 1 8 | |
| usb_passthru_calculate_xfer_ptr processed: 0 len: 32, status: 2 | |
| usb_passthru handle data - DIR=OUT|EP=4, blen 32, transfer_type: 2, ndata: 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?0:32 trb 1 0000000100c69000 421 (err 1) IOC?1 | |
| usb_passthru_calculate_xfer_ptr processed: 0 len: 32, status: 2 | |
| usb_passthru_data_callback: act_len: 32 blen:32 in:0 epid:4 status: 0 | |
| xhci device interrupt on endpoint 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 1 0000000100c69000 421 (err 1) IOC?1 | |
| pci_xhci: insert event 0[100c69000] 2[1000000] 3[1088000] | |
| erdp idx 36/seg 0, enq idx 36/seg 0, pcs 1 | |
| (erdp=0x1042a2240, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci doorbell slot 1 epid 8 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[8] 00000001 04000016 0000000100c69011 00000000 | |
| doorbell, ccs 1, trb ccs 0 | |
| pci_xhci: ring 100c69011 trb[100c69010] EP 8 is RESERVED? | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2248 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2258 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2250, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: hostop read offset 0x4 -> 0x0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01033c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 3: slot 1: type 15 | |
| pci_xhci: reset ep[3] 00008403 04000f36 0000000100c07100 00000000 | |
| pci_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[1042a1110] 2[1000000] 3[1008401] | |
| erdp idx 37/seg 0, enq idx 37/seg 0, pcs 1 | |
| (erdp=0x1042a2250, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x10, Trb0 x0000000100c16013 dwTrb2 x00010000 dwTrb3 x01034001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci set_tr: new-tr x0000000100c16010, SCT 1 DCS 1 | |
| stream-id 1, slot 1, epid 3, C 1 | |
| pci_xhci: command 0x10 result: 0x22 | |
| pci_xhci: insert event 0[1042a1120] 2[22000000] 3[1008401] | |
| erdp idx 37/seg 0, enq idx 38/seg 0, pcs 1 | |
| (erdp=0x1042a2250, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2258 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2278 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2270, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2270 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2278 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: hostop read offset 0x4 -> 0x0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01073c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 7: slot 1: type 15 | |
| pci_xhci: reset ep[7] 00008403 04000f36 0000000100c07000 00000000 | |
| pci_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[1042a1130] 2[1000000] 3[1008401] | |
| erdp idx 39/seg 0, enq idx 39/seg 0, pcs 1 | |
| (erdp=0x1042a2270, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x10, Trb0 x00000001042c3013 dwTrb2 x00010000 dwTrb3 x01074001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci set_tr: new-tr x00000001042c3010, SCT 1 DCS 1 | |
| stream-id 1, slot 1, epid 7, C 1 | |
| pci_xhci: command 0x10 result: 0x22 | |
| pci_xhci: insert event 0[1042a1140] 2[22000000] 3[1008401] | |
| erdp idx 39/seg 0, enq idx 40/seg 0, pcs 1 | |
| (erdp=0x1042a2270, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2278 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2298 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2290, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2290 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2298 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000100c06000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000098 A:x00000099 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000003 04000f36 00000001069f3001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000001 04000f16 0000000100c10001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00000003 04000f36 0000000100c8b001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1150] 2[1000000] 3[1008401] | |
| erdp idx 41/seg 0, enq idx 41/seg 0, pcs 1 | |
| (erdp=0x1042a2290, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2298 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a22a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a22a0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0xe11 | |
| xhci reset port 1 | |
| usb_passthru_reset | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 42/seg 0, enq idx 42/seg 0, pcs 1 | |
| (erdp=0x1042a22a0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a22a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a22b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a22b0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x200e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x80e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x400e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x20e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x11, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01004401, TRB_CYCLE 1/ccs 1 | |
| pci_xhci reset device slot 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: command 0x11 result: 0x1 | |
| pci_xhci: insert event 0[1042a1160] 2[1000000] 3[1008401] | |
| erdp idx 43/seg 0, enq idx 43/seg 0, pcs 1 | |
| (erdp=0x1042a22b0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a22b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a22c8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a22c0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xb, Trb0 x00000001042ba000 dwTrb2 x00000000 dwTrb3 x01002c01, TRB_CYCLE 1/ccs 1 | |
| pci_xhci: address device, input ctl: D 0x00000000 A 0x00000003, | |
| slot 08400000 00010000 00000000 00000000 | |
| ep0 00000000 02000026 00000001042bb241 00000000 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: address device, dev ctx | |
| slot 08400000 00010000 00000000 08000001 | |
| usb_passthru_reset | |
| init_ep 1 with no pstreams | |
| init_ep tr DCS 1 | |
| pci_xhci: address device, output ctx | |
| slot 08400000 00010000 00000000 10000001 | |
| ep0 00000001 02000026 00000001042bb241 00000000 | |
| pci_xhci: command 0xb result: 0x1 | |
| pci_xhci: insert event 0[1042a1170] 2[1000000] 3[1008401] | |
| erdp idx 44/seg 0, enq idx 44/seg 0, pcs 1 | |
| (erdp=0x1042a22c0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a22c8 | |
| pci_xhci: hostop read offset 0x30 -> 0x42a0000 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: hostop read offset 0x34 -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a22d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a22d0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb241 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb240] type x02 SETUP_STAGE 0:x0008000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb250 | |
| xhci update ep-ring, addr 1042bb251 | |
| pci_xhci: trb[@0xf99580bb250] type x03 DATA_STAGE 0:x000000081ca42fc0 2:x00000008 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb260 | |
| xhci update ep-ring, addr 1042bb261 | |
| pci_xhci: trb[@0xf99580bb260] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb270 | |
| xhci update ep-ring, addr 1042bb271 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 8 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb240 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb250 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb260 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb260] 2[1000000] 3[1018000] | |
| erdp idx 45/seg 0, enq idx 45/seg 0, pcs 1 | |
| (erdp=0x1042a22d0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a22d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a22e8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a22e0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb271 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb270] type x02 SETUP_STAGE 0:x0000000000283100 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0xf99580bb280 | |
| xhci update ep-ring, addr 1042bb281 | |
| pci_xhci: trb[@0xf99580bb280] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0xf99580bb290 | |
| xhci update ep-ring, addr 1042bb291 | |
| pci_xhci[1948]: xfer->ndata 2 1 | |
| usb_passthru_request: bRequest: 31 bmRequestType: 0 wValue: 28 wIndex: 0 wLength: 0 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb270 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000001042bb280 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb280] 2[1000000] 3[1018000] | |
| erdp idx 46/seg 0, enq idx 46/seg 0, pcs 1 | |
| (erdp=0x1042a22e0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a22e8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a22f8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a22f0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb291 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb290] type x02 SETUP_STAGE 0:x0012000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb2a0 | |
| xhci update ep-ring, addr 1042bb2a1 | |
| pci_xhci: trb[@0xf99580bb2a0] type x03 DATA_STAGE 0:x00000001063e4d00 2:x00000012 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb2b0 | |
| xhci update ep-ring, addr 1042bb2b1 | |
| pci_xhci: trb[@0xf99580bb2b0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb2c0 | |
| xhci update ep-ring, addr 1042bb2c1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 12 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 18 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb290 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb2a0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb2b0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb2b0] 2[1000000] 3[1018000] | |
| erdp idx 47/seg 0, enq idx 47/seg 0, pcs 1 | |
| (erdp=0x1042a22f0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a22f8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2308 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2300, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb2c1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb2c0] type x02 SETUP_STAGE 0:x000500000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb2d0 | |
| xhci update ep-ring, addr 1042bb2d1 | |
| pci_xhci: trb[@0xf99580bb2d0] type x03 DATA_STAGE 0:x0000000101326570 2:x00000005 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb2e0 | |
| xhci update ep-ring, addr 1042bb2e1 | |
| pci_xhci: trb[@0xf99580bb2e0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb2f0 | |
| xhci update ep-ring, addr 1042bb2f1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 5 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 5 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb2c0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb2d0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb2e0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb2e0] 2[1000000] 3[1018000] | |
| erdp idx 48/seg 0, enq idx 48/seg 0, pcs 1 | |
| (erdp=0x1042a2300, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2308 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2318 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2310, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb2f1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb2f0] type x02 SETUP_STAGE 0:x001600000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb300 | |
| xhci update ep-ring, addr 1042bb301 | |
| pci_xhci: trb[@0xf99580bb300] type x03 DATA_STAGE 0:x00000001063e4d00 2:x00000016 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb310 | |
| xhci update ep-ring, addr 1042bb311 | |
| pci_xhci: trb[@0xf99580bb310] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb320 | |
| xhci update ep-ring, addr 1042bb321 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 16 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 22 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb2f0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb300 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb310 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb310] 2[1000000] 3[1018000] | |
| erdp idx 49/seg 0, enq idx 49/seg 0, pcs 1 | |
| (erdp=0x1042a2310, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2318 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2328 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2320, events cnt 0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb321 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb320] type x02 SETUP_STAGE 0:x0079000002000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb330 | |
| xhci update ep-ring, addr 1042bb331 | |
| pci_xhci: trb[@0xf99580bb330] type x03 DATA_STAGE 0:x0000000106342b00 2:x00000079 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb340 | |
| xhci update ep-ring, addr 1042bb341 | |
| pci_xhci: trb[@0xf99580bb340] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb350 | |
| xhci update ep-ring, addr 1042bb351 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 79 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 121 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb320 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb330 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb340 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb340] 2[1000000] 3[1018000] | |
| erdp idx 50/seg 0, enq idx 50/seg 0, pcs 1 | |
| (erdp=0x1042a2320, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2328 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2338 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2330, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb351 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb350] type x02 SETUP_STAGE 0:x00ff040903010680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb360 | |
| xhci update ep-ring, addr 1042bb361 | |
| pci_xhci: trb[@0xf99580bb360] type x03 DATA_STAGE 0:x0000000100f65f00 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb370 | |
| xhci update ep-ring, addr 1042bb371 | |
| pci_xhci: trb[@0xf99580bb370] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb380 | |
| xhci update ep-ring, addr 1042bb381 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 301 wIndex: 1033 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 229 txlen 26 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb350 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:229 trb 3 00000001042bb360 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[1042bb360] 2[d0000e5] 3[1018000] | |
| erdp idx 51/seg 0, enq idx 51/seg 0, pcs 1 | |
| (erdp=0x1042a2330, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb370 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb370] 2[10000e5] 3[1018000] | |
| erdp idx 51/seg 0, enq idx 52/seg 0, pcs 1 | |
| (erdp=0x1042a2330, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2338 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2358 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2350, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042ba000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000000 A:x00000019 7:x00000000 | |
| enable ep[3] 00000000 04000f36 0000000100c70001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[4] 00000000 04000f16 0000000100e19001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1180] 2[1000000] 3[1008401] | |
| erdp idx 53/seg 0, enq idx 53/seg 0, pcs 1 | |
| (erdp=0x1042a2350, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2358 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2368 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2360, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb381 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb380] type x02 SETUP_STAGE 0:x0000000000010900 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0xf99580bb390 | |
| xhci update ep-ring, addr 1042bb391 | |
| pci_xhci: trb[@0xf99580bb390] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0xf99580bb3a0 | |
| xhci update ep-ring, addr 1042bb3a1 | |
| pci_xhci[1948]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb380 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000001042bb390 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb390] 2[1000000] 3[1018000] | |
| erdp idx 54/seg 0, enq idx 54/seg 0, pcs 1 | |
| (erdp=0x1042a2360, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2368 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2378 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2370, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042ba000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000018 A:x00000199 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000000 04000f36 0000000100c6a001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000000 04000f16 0000000105973001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[7] 00000000 04000f36 0000000106b80001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[8] 00000000 04000016 0000000106b6f001 00000000 | |
| init_ep 8 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1190] 2[1000000] 3[1008401] | |
| erdp idx 55/seg 0, enq idx 55/seg 0, pcs 1 | |
| (erdp=0x1042a2370, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2378 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2388 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2380, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb3a1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb3a0] type x02 SETUP_STAGE 0:x0000000000010b01 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0xf99580bb3b0 | |
| xhci update ep-ring, addr 1042bb3b1 | |
| pci_xhci: trb[@0xf99580bb3b0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0xf99580bb3c0 | |
| xhci update ep-ring, addr 1042bb3c1 | |
| pci_xhci[1948]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb3a0 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000001042bb3b0 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb3b0] 2[1000000] 3[1018000] | |
| erdp idx 56/seg 0, enq idx 56/seg 0, pcs 1 | |
| (erdp=0x1042a2380, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2388 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2398 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2390, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000106b5e000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000098 A:x00000099 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00008401 04000f36 0000000100c07100 00000000 | |
| init_ep 3 with pstreams 4 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00008401 04000f16 0000000100c07000 00000000 | |
| init_ep 4 with pstreams 4 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00008401 04000f36 0000000100c07200 00000000 | |
| init_ep 7 with pstreams 4 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a11a0] 2[1000000] 3[1008401] | |
| erdp idx 57/seg 0, enq idx 57/seg 0, pcs 1 | |
| (erdp=0x1042a2390, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2398 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a23a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a23a0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x10007 | |
| pci_xhci doorbell slot 1 epid 7 stream 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[7] 00008401 04000f36 0000000100c07200 00000000 | |
| pci_xhci: invalid stream 1: 34 | |
| pci_xhci: doorbell write offset 0x1: 0x8 | |
| pci_xhci doorbell slot 1 epid 8 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[8] 00000001 04000016 0000000106b6f001 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf995a96f000] type x01 NORMAL 0:x00000001063e4d00 2:x00000020 3:x00000421 | |
| pci_xhci: next trb: 0xf995a96f010 | |
| xhci update ep-ring, addr 106b6f011 | |
| pci_xhci[1948]: xfer->ndata 1 8 | |
| usb_passthru_calculate_xfer_ptr processed: 0 len: 32, status: 2 | |
| usb_passthru handle data - DIR=OUT|EP=4, blen 32, transfer_type: 2, ndata: 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?0:32 trb 1 0000000106b6f000 421 (err 1) IOC?1 | |
| pci_xhci: hostop read offset 0x4 -> 0x0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01083c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 8: slot 1: type 15 | |
| pci_xhci: reset ep[8] 00000003 04000016 0000000106b6f011 00000000 | |
| usb_passthru_cancel | |
| pci_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[1042a11b0] 2[1000000] 3[1008401] | |
| erdp idx 58/seg 0, enq idx 58/seg 0, pcs 1 | |
| (erdp=0x1042a23a0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a23a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a23b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a23b0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01073c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 7: slot 1: type 15 | |
| pci_xhci: reset ep[7] 00008403 04000f36 0000000100c07200 00000000 | |
| pci_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[1042a11c0] 2[1000000] 3[1008401] | |
| erdp idx 59/seg 0, enq idx 59/seg 0, pcs 1 | |
| (erdp=0x1042a23b0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x10, Trb0 x0000000100c8b013 dwTrb2 x00010000 dwTrb3 x01074001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci set_tr: new-tr x0000000100c8b010, SCT 1 DCS 1 | |
| stream-id 1, slot 1, epid 7, C 1 | |
| pci_xhci: command 0x10 result: 0x22 | |
| pci_xhci: insert event 0[1042a11d0] 2[22000000] 3[1008401] | |
| erdp idx 59/seg 0, enq idx 60/seg 0, pcs 1 | |
| (erdp=0x1042a23b0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a23b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a23d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a23d0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a23d0 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a23d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000100c17000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000098 A:x00000099 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000001 04000f36 0000000100c6a001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000001 04000f16 0000000105973001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00000003 04000f36 0000000106b80001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a11e0] 2[1000000] 3[1008401] | |
| erdp idx 61/seg 0, enq idx 61/seg 0, pcs 1 | |
| (erdp=0x1042a23d0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a23d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a23e8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a23e0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0xe11 | |
| xhci reset port 1 | |
| usb_passthru_reset | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 62/seg 0, enq idx 62/seg 0, pcs 1 | |
| (erdp=0x1042a23e0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a23e8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a23f8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a23f0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x200e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x80e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x400e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x20e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x11, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01004401, TRB_CYCLE 1/ccs 1 | |
| pci_xhci reset device slot 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: command 0x11 result: 0x1 | |
| pci_xhci: insert event 0[1042a11f0] 2[1000000] 3[1008401] | |
| erdp idx 63/seg 0, enq idx 63/seg 0, pcs 1 | |
| (erdp=0x1042a23f0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a23f8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2408 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2400, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xb, Trb0 x00000001042ba000 dwTrb2 x00000000 dwTrb3 x01002c01, TRB_CYCLE 1/ccs 1 | |
| pci_xhci: address device, input ctl: D 0x00000000 A 0x00000003, | |
| slot 08400000 00010000 00000000 00000000 | |
| ep0 00000000 02000026 00000001042bb3c1 00000000 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: address device, dev ctx | |
| slot 08400000 00010000 00000000 08000001 | |
| usb_passthru_reset | |
| init_ep 1 with no pstreams | |
| init_ep tr DCS 1 | |
| pci_xhci: address device, output ctx | |
| slot 08400000 00010000 00000000 10000001 | |
| ep0 00000001 02000026 00000001042bb3c1 00000000 | |
| pci_xhci: command 0xb result: 0x1 | |
| pci_xhci: insert event 0[1042a1200] 2[1000000] 3[1008401] | |
| erdp idx 64/seg 0, enq idx 64/seg 0, pcs 1 | |
| (erdp=0x1042a2400, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2408 | |
| pci_xhci: hostop read offset 0x30 -> 0x42a0000 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: hostop read offset 0x34 -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2418 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2410, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb3c1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb3c0] type x02 SETUP_STAGE 0:x0008000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb3d0 | |
| xhci update ep-ring, addr 1042bb3d1 | |
| pci_xhci: trb[@0xf99580bb3d0] type x03 DATA_STAGE 0:x00000001063c8d40 2:x00000008 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb3e0 | |
| xhci update ep-ring, addr 1042bb3e1 | |
| pci_xhci: trb[@0xf99580bb3e0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb3f0 | |
| xhci update ep-ring, addr 1042bb3f1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 8 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb3c0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb3d0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb3e0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb3e0] 2[1000000] 3[1018000] | |
| erdp idx 65/seg 0, enq idx 65/seg 0, pcs 1 | |
| (erdp=0x1042a2410, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2418 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2428 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2420, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb3f1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb3f0] type x02 SETUP_STAGE 0:x0000000000283100 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0xf99580bb400 | |
| xhci update ep-ring, addr 1042bb401 | |
| pci_xhci: trb[@0xf99580bb400] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0xf99580bb410 | |
| xhci update ep-ring, addr 1042bb411 | |
| pci_xhci[1948]: xfer->ndata 2 1 | |
| usb_passthru_request: bRequest: 31 bmRequestType: 0 wValue: 28 wIndex: 0 wLength: 0 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb3f0 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000001042bb400 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb400] 2[1000000] 3[1018000] | |
| erdp idx 66/seg 0, enq idx 66/seg 0, pcs 1 | |
| (erdp=0x1042a2420, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2428 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2438 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2430, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb411 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb410] type x02 SETUP_STAGE 0:x0012000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb420 | |
| xhci update ep-ring, addr 1042bb421 | |
| pci_xhci: trb[@0xf99580bb420] type x03 DATA_STAGE 0:x00000001063e4740 2:x00000012 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb430 | |
| xhci update ep-ring, addr 1042bb431 | |
| pci_xhci: trb[@0xf99580bb430] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb440 | |
| xhci update ep-ring, addr 1042bb441 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 12 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 18 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb410 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb420 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb430 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb430] 2[1000000] 3[1018000] | |
| erdp idx 67/seg 0, enq idx 67/seg 0, pcs 1 | |
| (erdp=0x1042a2430, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2438 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2448 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2440, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb441 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb440] type x02 SETUP_STAGE 0:x000500000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb450 | |
| xhci update ep-ring, addr 1042bb451 | |
| pci_xhci: trb[@0xf99580bb450] type x03 DATA_STAGE 0:x0000000101326570 2:x00000005 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb460 | |
| xhci update ep-ring, addr 1042bb461 | |
| pci_xhci: trb[@0xf99580bb460] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb470 | |
| xhci update ep-ring, addr 1042bb471 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 5 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 5 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb440 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb450 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb460 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb460] 2[1000000] 3[1018000] | |
| erdp idx 68/seg 0, enq idx 68/seg 0, pcs 1 | |
| (erdp=0x1042a2440, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2448 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2458 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2450, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb471 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb470] type x02 SETUP_STAGE 0:x001600000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb480 | |
| xhci update ep-ring, addr 1042bb481 | |
| pci_xhci: trb[@0xf99580bb480] type x03 DATA_STAGE 0:x00000001063e4740 2:x00000016 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb490 | |
| xhci update ep-ring, addr 1042bb491 | |
| pci_xhci: trb[@0xf99580bb490] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb4a0 | |
| xhci update ep-ring, addr 1042bb4a1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 16 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 22 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb470 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb480 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb490 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb490] 2[1000000] 3[1018000] | |
| erdp idx 69/seg 0, enq idx 69/seg 0, pcs 1 | |
| (erdp=0x1042a2450, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2458 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2468 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2460, events cnt 0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb4a1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb4a0] type x02 SETUP_STAGE 0:x0079000002000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb4b0 | |
| xhci update ep-ring, addr 1042bb4b1 | |
| pci_xhci: trb[@0xf99580bb4b0] type x03 DATA_STAGE 0:x00000001063ea580 2:x00000079 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb4c0 | |
| xhci update ep-ring, addr 1042bb4c1 | |
| pci_xhci: trb[@0xf99580bb4c0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb4d0 | |
| xhci update ep-ring, addr 1042bb4d1 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 79 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 121 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb4a0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000001042bb4b0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb4c0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb4c0] 2[1000000] 3[1018000] | |
| erdp idx 70/seg 0, enq idx 70/seg 0, pcs 1 | |
| (erdp=0x1042a2460, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2468 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2478 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2470, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb4d1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb4d0] type x02 SETUP_STAGE 0:x00ff040903010680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0xf99580bb4e0 | |
| xhci update ep-ring, addr 1042bb4e1 | |
| pci_xhci: trb[@0xf99580bb4e0] type x03 DATA_STAGE 0:x0000000100f65f00 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0xf99580bb4f0 | |
| xhci update ep-ring, addr 1042bb4f1 | |
| pci_xhci: trb[@0xf99580bb4f0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0xf99580bb500 | |
| xhci update ep-ring, addr 1042bb501 | |
| pci_xhci[1948]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 301 wIndex: 1033 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 229 txlen 26 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb4d0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:229 trb 3 00000001042bb4e0 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[1042bb4e0] 2[d0000e5] 3[1018000] | |
| erdp idx 71/seg 0, enq idx 71/seg 0, pcs 1 | |
| (erdp=0x1042a2470, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000001042bb4f0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb4f0] 2[10000e5] 3[1018000] | |
| erdp idx 71/seg 0, enq idx 72/seg 0, pcs 1 | |
| (erdp=0x1042a2470, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2478 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a2498 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a2490, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042ba000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000000 A:x00000019 7:x00000000 | |
| enable ep[3] 00000000 04000f36 0000000106b70001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[4] 00000000 04000f16 0000000106b81001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1210] 2[1000000] 3[1008401] | |
| erdp idx 73/seg 0, enq idx 73/seg 0, pcs 1 | |
| (erdp=0x1042a2490, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a2498 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a24a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a24a0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb501 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb500] type x02 SETUP_STAGE 0:x0000000000010900 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0xf99580bb510 | |
| xhci update ep-ring, addr 1042bb511 | |
| pci_xhci: trb[@0xf99580bb510] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0xf99580bb520 | |
| xhci update ep-ring, addr 1042bb521 | |
| pci_xhci[1948]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb500 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000001042bb510 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb510] 2[1000000] 3[1018000] | |
| erdp idx 74/seg 0, enq idx 74/seg 0, pcs 1 | |
| (erdp=0x1042a24a0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a24a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a24b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a24b0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042ba000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000018 A:x00000199 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000000 04000f36 00000001069f3001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000000 04000f16 0000000100c10001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[7] 00000000 04000f36 00000001042c3001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[8] 00000000 04000016 00000001042c1001 00000000 | |
| init_ep 8 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1220] 2[1000000] 3[1008401] | |
| erdp idx 75/seg 0, enq idx 75/seg 0, pcs 1 | |
| (erdp=0x1042a24b0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a24b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a24c8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a24c0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000001042bb521 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0xf99580bb520] type x02 SETUP_STAGE 0:x0000000000010b01 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0xf99580bb530 | |
| xhci update ep-ring, addr 1042bb531 | |
| pci_xhci: trb[@0xf99580bb530] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0xf99580bb540 | |
| xhci update ep-ring, addr 1042bb541 | |
| pci_xhci[1948]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000001042b9000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000001042bb520 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000001042bb530 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[1042bb530] 2[1000000] 3[1018000] | |
| erdp idx 76/seg 0, enq idx 76/seg 0, pcs 1 | |
| (erdp=0x1042a24c0, erst=0x1042a2000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a24c8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a24d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a24d0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000001042c4000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000098 A:x00000099 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00008401 04000f36 0000000100c07100 00000000 | |
| init_ep 3 with pstreams 4 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00008401 04000f16 0000000100c07200 00000000 | |
| init_ep 4 with pstreams 4 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00008401 04000f36 0000000100c07000 00000000 | |
| init_ep 7 with pstreams 4 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pci_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[1042a1230] 2[1000000] 3[1008401] | |
| erdp idx 77/seg 0, enq idx 77/seg 0, pcs 1 | |
| (erdp=0x1042a24d0, erst=0x1042a2000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0x42a24d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0x42a24e8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x1042a24e0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x0 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: hostop write offset 0x0: 0x0 | |
| pci_xhci: hostop read offset 0x4 -> 0x1 | |
| pci_xhci: hostop read offset 0x4 -> 0x1 | |
| stop libusb pullthread |
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