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September 3, 2025 14:11
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| fbuf frame buffer base: 0x1c35e9600000 [sz 33554432] | |
| pci_xhci adding device passthru | |
| Init port 1 0xe03 | |
| Init empty port 2 0x2a0 | |
| Init empty port 3 0x2a0 | |
| Init empty port 4 0x2a0 | |
| Init empty port 5 0x2a0 | |
| Init empty port 6 0x2a0 | |
| Init empty port 7 0x2a0 | |
| Init empty port 8 0x2a0 | |
| pci_xhci dboff: 0x4a0, rtsoff: 0xcc0 | |
| xhci reset unassigned slot (2)? | |
| xhci reset unassigned slot (3)? | |
| xhci reset unassigned slot (4)? | |
| xhci reset unassigned slot (5)? | |
| xhci reset unassigned slot (6)? | |
| xhci reset unassigned slot (7)? | |
| xhci reset unassigned slot (8)? | |
| xhci reset unassigned slot (9)? | |
| xhci reset unassigned slot (10)? | |
| xhci reset unassigned slot (11)? | |
| xhci reset unassigned slot (12)? | |
| xhci reset unassigned slot (13)? | |
| xhci reset unassigned slot (14)? | |
| xhci reset unassigned slot (15)? | |
| xhci reset unassigned slot (16)? | |
| xhci reset unassigned slot (17)? | |
| xhci reset unassigned slot (18)? | |
| xhci reset unassigned slot (19)? | |
| xhci reset unassigned slot (20)? | |
| xhci reset unassigned slot (21)? | |
| xhci reset unassigned slot (22)? | |
| xhci reset unassigned slot (23)? | |
| xhci reset unassigned slot (24)? | |
| xhci reset unassigned slot (25)? | |
| xhci reset unassigned slot (26)? | |
| xhci reset unassigned slot (27)? | |
| xhci reset unassigned slot (28)? | |
| xhci reset unassigned slot (29)? | |
| xhci reset unassigned slot (30)? | |
| xhci reset unassigned slot (31)? | |
| xhci reset unassigned slot (32)? | |
| xhci reset unassigned slot (33)? | |
| xhci reset unassigned slot (34)? | |
| xhci reset unassigned slot (35)? | |
| xhci reset unassigned slot (36)? | |
| xhci reset unassigned slot (37)? | |
| xhci reset unassigned slot (38)? | |
| xhci reset unassigned slot (39)? | |
| xhci reset unassigned slot (40)? | |
| xhci reset unassigned slot (41)? | |
| xhci reset unassigned slot (42)? | |
| xhci reset unassigned slot (43)? | |
| xhci reset unassigned slot (44)? | |
| xhci reset unassigned slot (45)? | |
| xhci reset unassigned slot (46)? | |
| xhci reset unassigned slot (47)? | |
| xhci reset unassigned slot (48)? | |
| xhci reset unassigned slot (49)? | |
| xhci reset unassigned slot (50)? | |
| xhci reset unassigned slot (51)? | |
| xhci reset unassigned slot (52)? | |
| xhci reset unassigned slot (53)? | |
| xhci reset unassigned slot (54)? | |
| xhci reset unassigned slot (55)? | |
| xhci reset unassigned slot (56)? | |
| xhci reset unassigned slot (57)? | |
| xhci reset unassigned slot (58)? | |
| xhci reset unassigned slot (59)? | |
| xhci reset unassigned slot (60)? | |
| xhci reset unassigned slot (61)? | |
| xhci reset unassigned slot (62)? | |
| xhci reset unassigned slot (63)? | |
| xhci reset unassigned slot (64)? | |
| start libusb pullthread | |
| pci_xhci pci_emu_alloc: 3456 | |
| pci_xhci: hostcap read offset 0x0 -> 0x1000020 | |
| pci_xhci: hostcap read offset 0x4 -> 0x8000140 | |
| pci_xhci: hostcap read offset 0x8 -> 0x4 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: hostcap read offset 0x14 -> 0x4a0 | |
| pci_xhci: hostcap read offset 0x18 -> 0xcc0 | |
| pci_xhci: hostop read offset 0x8 -> 0x1 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x4 -> 0x20425355 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x14 -> 0x20425355 | |
| pci_xhci: hostop read offset 0x4 -> 0x1 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x2 | |
| xhci reset unassigned slot (2)? | |
| xhci reset unassigned slot (3)? | |
| xhci reset unassigned slot (4)? | |
| xhci reset unassigned slot (5)? | |
| xhci reset unassigned slot (6)? | |
| xhci reset unassigned slot (7)? | |
| xhci reset unassigned slot (8)? | |
| xhci reset unassigned slot (9)? | |
| xhci reset unassigned slot (10)? | |
| xhci reset unassigned slot (11)? | |
| xhci reset unassigned slot (12)? | |
| xhci reset unassigned slot (13)? | |
| xhci reset unassigned slot (14)? | |
| xhci reset unassigned slot (15)? | |
| xhci reset unassigned slot (16)? | |
| xhci reset unassigned slot (17)? | |
| xhci reset unassigned slot (18)? | |
| xhci reset unassigned slot (19)? | |
| xhci reset unassigned slot (20)? | |
| xhci reset unassigned slot (21)? | |
| xhci reset unassigned slot (22)? | |
| xhci reset unassigned slot (23)? | |
| xhci reset unassigned slot (24)? | |
| xhci reset unassigned slot (25)? | |
| xhci reset unassigned slot (26)? | |
| xhci reset unassigned slot (27)? | |
| xhci reset unassigned slot (28)? | |
| xhci reset unassigned slot (29)? | |
| xhci reset unassigned slot (30)? | |
| xhci reset unassigned slot (31)? | |
| xhci reset unassigned slot (32)? | |
| xhci reset unassigned slot (33)? | |
| xhci reset unassigned slot (34)? | |
| xhci reset unassigned slot (35)? | |
| xhci reset unassigned slot (36)? | |
| xhci reset unassigned slot (37)? | |
| xhci reset unassigned slot (38)? | |
| xhci reset unassigned slot (39)? | |
| xhci reset unassigned slot (40)? | |
| xhci reset unassigned slot (41)? | |
| xhci reset unassigned slot (42)? | |
| xhci reset unassigned slot (43)? | |
| xhci reset unassigned slot (44)? | |
| xhci reset unassigned slot (45)? | |
| xhci reset unassigned slot (46)? | |
| xhci reset unassigned slot (47)? | |
| xhci reset unassigned slot (48)? | |
| xhci reset unassigned slot (49)? | |
| xhci reset unassigned slot (50)? | |
| xhci reset unassigned slot (51)? | |
| xhci reset unassigned slot (52)? | |
| xhci reset unassigned slot (53)? | |
| xhci reset unassigned slot (54)? | |
| xhci reset unassigned slot (55)? | |
| xhci reset unassigned slot (56)? | |
| xhci reset unassigned slot (57)? | |
| xhci reset unassigned slot (58)? | |
| xhci reset unassigned slot (59)? | |
| xhci reset unassigned slot (60)? | |
| xhci reset unassigned slot (61)? | |
| xhci reset unassigned slot (62)? | |
| xhci reset unassigned slot (63)? | |
| xhci reset unassigned slot (64)? | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x38: 0x40 | |
| pci_xhci: hostop write offset 0x30: 0xbf13f000 | |
| pci_xhci: hostop write offset 0x34: 0x0 | |
| pci_xhci: opregs dcbaap = 0xbf13f000 (vaddr 0x1c2e60d3f000) | |
| pci_xhci: hostop write offset 0x18: 0xbf140001 | |
| pci_xhci: hostop write offset 0x1c: 0x0 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x0 | |
| pci_xhci: rtsregs read offset 0x0 -> 0x0 | |
| pci_xhci: runtime regs write offset 0x20: 0x0 | |
| pci_xhci: rtsregs read offset 0x0 -> 0x0 | |
| pci_xhci: runtime regs write offset 0x20: 0x1 | |
| pci_xhci: runtime regs write offset 0x28: 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141000 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: runtime regs write offset 0x30: 0xbf13f240 | |
| pci_xhci: runtime regs write offset 0x34: 0x0 | |
| pci_xhci: wr erstba erst (0x1c2e60d3f240) ptr 0xbf141000, sz 512 | |
| pci_xhci: rtsregs read offset 0x0 -> 0x0 | |
| pci_xhci: runtime regs write offset 0x20: 0x2 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x1 | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 0/seg 0, enq idx 0/seg 0, pcs 1 | |
| (erdp=0xbf141000, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x20e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0xe11 | |
| xhci reset port 1 | |
| usb_passthru_reset | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 0/seg 0, enq idx 1/seg 0, pcs 1 | |
| (erdp=0xbf141000, erst=0xbf141000, tblsz=512, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x200e01 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x9, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x00002401, TRB_CYCLE 1/ccs 1 | |
| pci_xhci enable slot (error=0) slot 1 | |
| pcif_xhci: command 0x9 result: 0x1 | |
| pci_xhci: insert event 0[bf140000] 2[1000000] 3[1008401] | |
| erdp idx 0/seg 0, enq idx 2/seg 0, pcs 1 | |
| (erdp=0xbf141000, erst=0xbf141000, tblsz=512, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141008 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141038 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141030, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xb, Trb0 x00000000bf13f280 dwTrb2 x00000000 dwTrb3 x01002c01, TRB_CYCLE 1/ccs 1 | |
| pci_xhci: address device, input ctl: D 0x00000000 A 0x00000003, | |
| slot 08300000 00010000 00000000 00000000 | |
| ep0 00000000 00400026 00000000bf143001 00000008 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: address device, dev ctx | |
| slot 00000000 00000000 00000000 00000000 | |
| usb_passthru_reset | |
| init_ep 1 with no pstreams | |
| init_ep tr DCS 1 | |
| pci_xhci: address device, output ctx | |
| slot 08300000 00010000 00000000 10000001 | |
| ep0 00000001 00400026 00000000bf143001 00000008 | |
| pcif_xhci: command 0xb result: 0x1 | |
| pci_xhci: insert event 0[bf140010] 2[1000000] 3[1008401] | |
| erdp idx 3/seg 0, enq idx 3/seg 0, pcs 1 | |
| (erdp=0xbf141030, erst=0xbf141000, tblsz=512, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141038 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141048 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141040, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 00400026 00000000bf143001 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d43000] type x02 SETUP_STAGE 0:x0008000001000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d43010 | |
| xhci update ep-ring, addr bf143011 | |
| pci_xhci: trb[@0x1c2e60d43010] type x03 DATA_STAGE 0:x00000000bff424a8 2:x00000008 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d43020 | |
| xhci update ep-ring, addr bf143021 | |
| pci_xhci: trb[@0x1c2e60d43020] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d43030 | |
| xhci update ep-ring, addr bf143031 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 8 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143000 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143000] 2[1000000] 3[1018000] | |
| erdp idx 4/seg 0, enq idx 4/seg 0, pcs 1 | |
| (erdp=0xbf141040, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143010 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143010] 2[1000000] 3[1018000] | |
| erdp idx 4/seg 0, enq idx 5/seg 0, pcs 1 | |
| (erdp=0xbf141040, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143020 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143020] 2[1000000] 3[1018000] | |
| erdp idx 4/seg 0, enq idx 6/seg 0, pcs 1 | |
| (erdp=0xbf141040, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141048 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141078 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141070, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 00400026 00000000bf143031 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d43030] type x02 SETUP_STAGE 0:x0012000001000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d43040 | |
| xhci update ep-ring, addr bf143041 | |
| pci_xhci: trb[@0x1c2e60d43040] type x03 DATA_STAGE 0:x00000000bf13de98 2:x00000012 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d43050 | |
| xhci update ep-ring, addr bf143051 | |
| pci_xhci: trb[@0x1c2e60d43050] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d43060 | |
| xhci update ep-ring, addr bf143061 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 12 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 18 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143030 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143030] 2[1000000] 3[1018000] | |
| erdp idx 7/seg 0, enq idx 7/seg 0, pcs 1 | |
| (erdp=0xbf141070, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143040 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143040] 2[1000000] 3[1018000] | |
| erdp idx 7/seg 0, enq idx 8/seg 0, pcs 1 | |
| (erdp=0xbf141070, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143050 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143050] 2[1000000] 3[1018000] | |
| erdp idx 7/seg 0, enq idx 9/seg 0, pcs 1 | |
| (erdp=0xbf141070, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141078 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1410a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1410a0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xd, Trb0 x00000000bf13f280 dwTrb2 x00000000 dwTrb3 x01003401, TRB_CYCLE 1/ccs 1 | |
| pci_xhci: eval ctx, input ctl: D 0x00000000 A 0x00000002, | |
| slot 00000000 00000000 00000000 00000000 | |
| ep0 00000000 02000026 00000000bf143061 00000008 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: eval ctx, dev ctx | |
| slot 08300000 00010000 00000000 10000001 | |
| pci_xhci: eval ctx, output ctx | |
| slot 08300000 00010000 00000000 10000001 | |
| ep0 00000001 02000026 00000000bf143061 00000008 | |
| pcif_xhci: command 0xd result: 0x1 | |
| pci_xhci: insert event 0[bf140020] 2[1000000] 3[1008401] | |
| erdp idx 10/seg 0, enq idx 10/seg 0, pcs 1 | |
| (erdp=0xbf1410a0, erst=0xbf141000, tblsz=512, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf1410a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1410b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1410b0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143061 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d43060] type x02 SETUP_STAGE 0:x0008000002000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d43070 | |
| xhci update ep-ring, addr bf143071 | |
| pci_xhci: trb[@0x1c2e60d43070] type x03 DATA_STAGE 0:x00000000bff424a8 2:x00000008 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d43080 | |
| xhci update ep-ring, addr bf143081 | |
| pci_xhci: trb[@0x1c2e60d43080] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d43090 | |
| xhci update ep-ring, addr bf143091 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 8 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143060 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143060] 2[1000000] 3[1018000] | |
| erdp idx 11/seg 0, enq idx 11/seg 0, pcs 1 | |
| (erdp=0xbf1410b0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143070 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143070] 2[1000000] 3[1018000] | |
| erdp idx 11/seg 0, enq idx 12/seg 0, pcs 1 | |
| (erdp=0xbf1410b0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143080 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143080] 2[1000000] 3[1018000] | |
| erdp idx 11/seg 0, enq idx 13/seg 0, pcs 1 | |
| (erdp=0xbf1410b0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf1410b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1410e8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1410e0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143091 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d43090] type x02 SETUP_STAGE 0:x0079000002000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d430a0 | |
| xhci update ep-ring, addr bf1430a1 | |
| pci_xhci: trb[@0x1c2e60d430a0] type x03 DATA_STAGE 0:x00000000bf13d098 2:x00000079 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d430b0 | |
| xhci update ep-ring, addr bf1430b1 | |
| pci_xhci: trb[@0x1c2e60d430b0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d430c0 | |
| xhci update ep-ring, addr bf1430c1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 79 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 121 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143090 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143090] 2[1000000] 3[1018000] | |
| erdp idx 14/seg 0, enq idx 14/seg 0, pcs 1 | |
| (erdp=0xbf1410e0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf1430a0 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430a0] 2[1000000] 3[1018000] | |
| erdp idx 14/seg 0, enq idx 15/seg 0, pcs 1 | |
| (erdp=0xbf1410e0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf1430b0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430b0] 2[1000000] 3[1018000] | |
| erdp idx 14/seg 0, enq idx 16/seg 0, pcs 1 | |
| (erdp=0xbf1410e0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf1410e8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141118 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141110, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf1430c1 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d430c0] type x02 SETUP_STAGE 0:x0002000003000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d430d0 | |
| xhci update ep-ring, addr bf1430d1 | |
| pci_xhci: trb[@0x1c2e60d430d0] type x03 DATA_STAGE 0:x00000000bff4240c 2:x00000002 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d430e0 | |
| xhci update ep-ring, addr bf1430e1 | |
| pci_xhci: trb[@0x1c2e60d430e0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d430f0 | |
| xhci update ep-ring, addr bf1430f1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 300 wIndex: 0 wLength: 2 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 2 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf1430c0 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430c0] 2[1000000] 3[1018000] | |
| erdp idx 17/seg 0, enq idx 17/seg 0, pcs 1 | |
| (erdp=0xbf141110, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf1430d0 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430d0] 2[1000000] 3[1018000] | |
| erdp idx 17/seg 0, enq idx 18/seg 0, pcs 1 | |
| (erdp=0xbf141110, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf1430e0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430e0] 2[1000000] 3[1018000] | |
| erdp idx 17/seg 0, enq idx 19/seg 0, pcs 1 | |
| (erdp=0xbf141110, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141118 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141148 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141140, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf1430f1 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d430f0] type x02 SETUP_STAGE 0:x0004000003000680 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d43100 | |
| xhci update ep-ring, addr bf143101 | |
| pci_xhci: trb[@0x1c2e60d43100] type x03 DATA_STAGE 0:x00000000bf13cc98 2:x00000004 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d43110 | |
| xhci update ep-ring, addr bf143111 | |
| pci_xhci: trb[@0x1c2e60d43110] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d43120 | |
| xhci update ep-ring, addr bf143121 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 300 wIndex: 0 wLength: 4 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 4 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf1430f0 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1430f0] 2[1000000] 3[1018000] | |
| erdp idx 20/seg 0, enq idx 20/seg 0, pcs 1 | |
| (erdp=0xbf141140, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143100 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143100] 2[1000000] 3[1018000] | |
| erdp idx 20/seg 0, enq idx 21/seg 0, pcs 1 | |
| (erdp=0xbf141140, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143110 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143110] 2[1000000] 3[1018000] | |
| erdp idx 20/seg 0, enq idx 22/seg 0, pcs 1 | |
| (erdp=0xbf141140, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141148 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141178 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141170, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143121 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d43120] type x02 SETUP_STAGE 0:x0000000000010900 2:x00000008 3:x00000861 | |
| pci_xhci: next trb: 0x1c2e60d43130 | |
| xhci update ep-ring, addr bf143131 | |
| pci_xhci: trb[@0x1c2e60d43130] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0x1c2e60d43140 | |
| xhci update ep-ring, addr bf143141 | |
| pci_xhci[1975]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143120 861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143120] 2[1000000] 3[1018000] | |
| erdp idx 23/seg 0, enq idx 23/seg 0, pcs 1 | |
| (erdp=0xbf141170, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 4 00000000bf143130 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143130] 2[1000000] 3[1018000] | |
| erdp idx 23/seg 0, enq idx 24/seg 0, pcs 1 | |
| (erdp=0xbf141170, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141178 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141198 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141190, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x00000000bf13f280 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000000 A:x00000019 7:x00000000 | |
| enable ep[3] 00000000 04000036 00000000bf144001 00001000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[4] 00000000 04000016 00000000bf145001 00001000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20300000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[bf140030] 2[1000000] 3[1008401] | |
| erdp idx 25/seg 0, enq idx 25/seg 0, pcs 1 | |
| (erdp=0xbf141190, erst=0xbf141000, tblsz=512, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141198 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1411a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1411a0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143141 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d43140] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d43150 | |
| xhci update ep-ring, addr bf143151 | |
| pci_xhci: trb[@0x1c2e60d43150] type x03 DATA_STAGE 0:x00000000bff42562 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d43160 | |
| xhci update ep-ring, addr bf143161 | |
| pci_xhci: trb[@0x1c2e60d43160] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d43170 | |
| xhci update ep-ring, addr bf143171 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143140 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143140] 2[1000000] 3[1018000] | |
| erdp idx 26/seg 0, enq idx 26/seg 0, pcs 1 | |
| (erdp=0xbf1411a0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143150 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143150] 2[1000000] 3[1018000] | |
| erdp idx 26/seg 0, enq idx 27/seg 0, pcs 1 | |
| (erdp=0xbf1411a0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143160 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143160] 2[1000000] 3[1018000] | |
| erdp idx 26/seg 0, enq idx 28/seg 0, pcs 1 | |
| (erdp=0xbf1411a0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf1411a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1411d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1411d0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143171 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d43170] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d43180 | |
| xhci update ep-ring, addr bf143181 | |
| pci_xhci: trb[@0x1c2e60d43180] type x03 DATA_STAGE 0:x00000000bff42622 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d43190 | |
| xhci update ep-ring, addr bf143191 | |
| pci_xhci: trb[@0x1c2e60d43190] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d431a0 | |
| xhci update ep-ring, addr bf1431a1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143170 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143170] 2[1000000] 3[1018000] | |
| erdp idx 29/seg 0, enq idx 29/seg 0, pcs 1 | |
| (erdp=0xbf1411d0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143180 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143180] 2[1000000] 3[1018000] | |
| erdp idx 29/seg 0, enq idx 30/seg 0, pcs 1 | |
| (erdp=0xbf1411d0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143190 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143190] 2[1000000] 3[1018000] | |
| erdp idx 29/seg 0, enq idx 31/seg 0, pcs 1 | |
| (erdp=0xbf1411d0, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf1411d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141208 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141200, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf1431a1 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d431a0] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d431b0 | |
| xhci update ep-ring, addr bf1431b1 | |
| pci_xhci: trb[@0x1c2e60d431b0] type x03 DATA_STAGE 0:x00000000bff42652 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d431c0 | |
| xhci update ep-ring, addr bf1431c1 | |
| pci_xhci: trb[@0x1c2e60d431c0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d431d0 | |
| xhci update ep-ring, addr bf1431d1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf1431a0 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431a0] 2[1000000] 3[1018000] | |
| erdp idx 32/seg 0, enq idx 32/seg 0, pcs 1 | |
| (erdp=0xbf141200, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf1431b0 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431b0] 2[1000000] 3[1018000] | |
| erdp idx 32/seg 0, enq idx 33/seg 0, pcs 1 | |
| (erdp=0xbf141200, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf1431c0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431c0] 2[1000000] 3[1018000] | |
| erdp idx 32/seg 0, enq idx 34/seg 0, pcs 1 | |
| (erdp=0xbf141200, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141208 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141238 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141230, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf1431d1 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d431d0] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d431e0 | |
| xhci update ep-ring, addr bf1431e1 | |
| pci_xhci: trb[@0x1c2e60d431e0] type x03 DATA_STAGE 0:x00000000bff42712 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d431f0 | |
| xhci update ep-ring, addr bf1431f1 | |
| pci_xhci: trb[@0x1c2e60d431f0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d43200 | |
| xhci update ep-ring, addr bf143201 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf1431d0 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431d0] 2[1000000] 3[1018000] | |
| erdp idx 35/seg 0, enq idx 35/seg 0, pcs 1 | |
| (erdp=0xbf141230, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf1431e0 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431e0] 2[1000000] 3[1018000] | |
| erdp idx 35/seg 0, enq idx 36/seg 0, pcs 1 | |
| (erdp=0xbf141230, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf1431f0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf1431f0] 2[1000000] 3[1018000] | |
| erdp idx 35/seg 0, enq idx 37/seg 0, pcs 1 | |
| (erdp=0xbf141230, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141238 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141268 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141260, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143201 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d43200] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d43210 | |
| xhci update ep-ring, addr bf143211 | |
| pci_xhci: trb[@0x1c2e60d43210] type x03 DATA_STAGE 0:x00000000bff42802 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d43220 | |
| xhci update ep-ring, addr bf143221 | |
| pci_xhci: trb[@0x1c2e60d43220] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d43230 | |
| xhci update ep-ring, addr bf143231 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143200 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143200] 2[1000000] 3[1018000] | |
| erdp idx 38/seg 0, enq idx 38/seg 0, pcs 1 | |
| (erdp=0xbf141260, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143210 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143210] 2[1000000] 3[1018000] | |
| erdp idx 38/seg 0, enq idx 39/seg 0, pcs 1 | |
| (erdp=0xbf141260, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143220 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143220] 2[1000000] 3[1018000] | |
| erdp idx 38/seg 0, enq idx 40/seg 0, pcs 1 | |
| (erdp=0xbf141260, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141268 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf141298 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf141290, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 00000000bf143231 00000008 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2e60d43230] type x02 SETUP_STAGE 0:x000100000000fea1 2:x00000008 3:x00030861 | |
| pci_xhci: next trb: 0x1c2e60d43240 | |
| xhci update ep-ring, addr bf143241 | |
| pci_xhci: trb[@0x1c2e60d43240] type x03 DATA_STAGE 0:x00000000bff42542 2:x00000001 3:x00010c25 | |
| pci_xhci: next trb: 0x1c2e60d43250 | |
| xhci update ep-ring, addr bf143251 | |
| pci_xhci: trb[@0x1c2e60d43250] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2e60d43260 | |
| xhci update ep-ring, addr bf143261 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: fe bmRequestType: a1 wValue: 0 wIndex: 0 wLength: 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 00000000bf13f6c0 | |
| pci_xhci: xfer[0] done?1:0 trb 2 00000000bf143230 30861 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143230] 2[1000000] 3[1018000] | |
| erdp idx 41/seg 0, enq idx 41/seg 0, pcs 1 | |
| (erdp=0xbf141290, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[1] done?1:0 trb 3 00000000bf143240 10c25 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143240] 2[1000000] 3[1018000] | |
| erdp idx 41/seg 0, enq idx 42/seg 0, pcs 1 | |
| (erdp=0xbf141290, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 00000000bf143250 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[bf143250] 2[1000000] 3[1018000] | |
| erdp idx 41/seg 0, enq idx 43/seg 0, pcs 1 | |
| (erdp=0xbf141290, erst=0xbf141000, tblsz=512, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xbf141298 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x0 | |
| pci_xhci: runtime regs write offset 0x38: 0xbf1412c8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x0 | |
| pci_xhci: erdp 0xbf1412c0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: hostop read offset 0x0 -> 0x1 | |
| pci_xhci: hostop write offset 0x0: 0x0 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostcap read offset 0x0 -> 0x1000020 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x0 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostcap read offset 0x0 -> 0x1000020 | |
| pci_xhci: hostcap read offset 0x18 -> 0xcc0 | |
| pci_xhci: hostcap read offset 0x4 -> 0x8000140 | |
| pci_xhci: hostcap read offset 0x8 -> 0x4 | |
| pci_xhci: hostcap read offset 0xc -> 0x0 | |
| pci_xhci: hostcap read offset 0x0 -> 0x1000020 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x0 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x2 | |
| xhci reset unassigned slot (2)? | |
| xhci reset unassigned slot (3)? | |
| xhci reset unassigned slot (4)? | |
| xhci reset unassigned slot (5)? | |
| xhci reset unassigned slot (6)? | |
| xhci reset unassigned slot (7)? | |
| xhci reset unassigned slot (8)? | |
| xhci reset unassigned slot (9)? | |
| xhci reset unassigned slot (10)? | |
| xhci reset unassigned slot (11)? | |
| xhci reset unassigned slot (12)? | |
| xhci reset unassigned slot (13)? | |
| xhci reset unassigned slot (14)? | |
| xhci reset unassigned slot (15)? | |
| xhci reset unassigned slot (16)? | |
| xhci reset unassigned slot (17)? | |
| xhci reset unassigned slot (18)? | |
| xhci reset unassigned slot (19)? | |
| xhci reset unassigned slot (20)? | |
| xhci reset unassigned slot (21)? | |
| xhci reset unassigned slot (22)? | |
| xhci reset unassigned slot (23)? | |
| xhci reset unassigned slot (24)? | |
| xhci reset unassigned slot (25)? | |
| xhci reset unassigned slot (26)? | |
| xhci reset unassigned slot (27)? | |
| xhci reset unassigned slot (28)? | |
| xhci reset unassigned slot (29)? | |
| xhci reset unassigned slot (30)? | |
| xhci reset unassigned slot (31)? | |
| xhci reset unassigned slot (32)? | |
| xhci reset unassigned slot (33)? | |
| xhci reset unassigned slot (34)? | |
| xhci reset unassigned slot (35)? | |
| xhci reset unassigned slot (36)? | |
| xhci reset unassigned slot (37)? | |
| xhci reset unassigned slot (38)? | |
| xhci reset unassigned slot (39)? | |
| xhci reset unassigned slot (40)? | |
| xhci reset unassigned slot (41)? | |
| xhci reset unassigned slot (42)? | |
| xhci reset unassigned slot (43)? | |
| xhci reset unassigned slot (44)? | |
| xhci reset unassigned slot (45)? | |
| xhci reset unassigned slot (46)? | |
| xhci reset unassigned slot (47)? | |
| xhci reset unassigned slot (48)? | |
| xhci reset unassigned slot (49)? | |
| xhci reset unassigned slot (50)? | |
| xhci reset unassigned slot (51)? | |
| xhci reset unassigned slot (52)? | |
| xhci reset unassigned slot (53)? | |
| xhci reset unassigned slot (54)? | |
| xhci reset unassigned slot (55)? | |
| xhci reset unassigned slot (56)? | |
| xhci reset unassigned slot (57)? | |
| xhci reset unassigned slot (58)? | |
| xhci reset unassigned slot (59)? | |
| xhci reset unassigned slot (60)? | |
| xhci reset unassigned slot (61)? | |
| xhci reset unassigned slot (62)? | |
| xhci reset unassigned slot (63)? | |
| xhci reset unassigned slot (64)? | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop read offset 0x4 -> 0x9 | |
| pci_xhci: hostop read offset 0x8 -> 0x1 | |
| pci_xhci: hostcap read offset 0x4 -> 0x8000140 | |
| pci_xhci: hostop read offset 0x38 -> 0x40 | |
| pci_xhci: hostop write offset 0x38: 0x40 | |
| pci_xhci: hostop write offset 0x30: 0xbef000 | |
| pci_xhci: hostop write offset 0x34: 0x1 | |
| pci_xhci: opregs dcbaap = 0x100bef000 (vaddr 0x1c2ea27ef000) | |
| pci_xhci: hostop read offset 0x18 -> 0x0 | |
| pci_xhci: hostop read offset 0x1c -> 0x0 | |
| pci_xhci: hostop write offset 0x18: 0xc02001 | |
| pci_xhci: hostop write offset 0x1c: 0x1 | |
| pci_xhci: hostcap read offset 0x14 -> 0x4a0 | |
| pci_xhci: rtsregs read offset 0x8 -> 0x1 | |
| pci_xhci: runtime regs write offset 0x28: 0x1 | |
| pci_xhci: rtsregs read offset 0x10 -> 0xbf13f240 | |
| pci_xhci: rtsregs read offset 0x14 -> 0x0 | |
| pci_xhci: runtime regs write offset 0x30: 0xc04000 | |
| pci_xhci: runtime regs write offset 0x34: 0x1 | |
| pci_xhci: wr erstba erst (0x1c2ea2804000) ptr 0x100c03000, sz 256 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03000 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: hostop read offset 0x14 -> 0x0 | |
| pci_xhci: hostop write offset 0x14: 0x2 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03000 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: rtsregs read offset 0x4 -> 0x0 | |
| pci_xhci: runtime regs write offset 0x24: 0xa0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostcap read offset 0x0 -> 0x1000020 | |
| pci_xhci: hostcap read offset 0x18 -> 0xcc0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x8 -> 0x405 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x18 -> 0x401 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: hostop read offset 0x0 -> 0x0 | |
| pci_xhci: hostop write offset 0x0: 0x4 | |
| pci_xhci: rtsregs read offset 0x0 -> 0x2 | |
| pci_xhci: runtime regs write offset 0x20: 0x2 | |
| pci_xhci: hostop read offset 0x0 -> 0x4 | |
| pci_xhci: hostop write offset 0x0: 0x5 | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 0/seg 0, enq idx 0/seg 0, pcs 1 | |
| (erdp=0x100c03000, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop read offset 0x4 -> 0x18 | |
| pci_xhci: hostop write offset 0x4: 0x18 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03008 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03018 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03010, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: hostcap read offset 0xc -> 0x0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x20e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0xe01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 2: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 2 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 3: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 3 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 4: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 4 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x9, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x00002401, TRB_CYCLE 1/ccs 1 | |
| pci_xhci enable slot (error=0) slot 1 | |
| pcif_xhci: command 0x9 result: 0x1 | |
| pci_xhci: insert event 0[100c02000] 2[1000000] 3[1008401] | |
| erdp idx 1/seg 0, enq idx 1/seg 0, pcs 1 | |
| (erdp=0x100c03010, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03018 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03028 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03020, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0xe11 | |
| xhci reset port 1 | |
| usb_passthru_reset | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 2/seg 0, enq idx 2/seg 0, pcs 1 | |
| (erdp=0x100c03020, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03028 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03038 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03030, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x200e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x80e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x400e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x20e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0xa0002a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 8: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 8 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 7: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 7 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 6: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 6 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0xa0002a0 | |
| pci_xhci: portregs wr offset 0x0, port 5: 0x2a0 | |
| pci_xhci: portregs_write to unattached port 5 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: portregs read offset 0x0 port 5 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 6 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 7 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 8 -> 0x2a0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xb, Trb0 x000000010497b000 dwTrb2 x00000000 dwTrb3 x01002c01, TRB_CYCLE 1/ccs 1 | |
| pci_xhci: address device, input ctl: D 0x00000000 A 0x00000003, | |
| slot 08400000 00010000 00000000 00000000 | |
| ep0 00000000 02000026 000000010497c001 00000000 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: address device, dev ctx | |
| slot 00000000 00000000 00000000 00000000 | |
| usb_passthru_reset | |
| init_ep 1 with no pstreams | |
| init_ep tr DCS 1 | |
| pci_xhci: address device, output ctx | |
| slot 08400000 00010000 00000000 10000001 | |
| ep0 00000001 02000026 000000010497c001 00000000 | |
| pcif_xhci: command 0xb result: 0x1 | |
| pci_xhci: insert event 0[100c02010] 2[1000000] 3[1008401] | |
| erdp idx 3/seg 0, enq idx 3/seg 0, pcs 1 | |
| (erdp=0x100c03030, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03038 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03048 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03040, events cnt 0 | |
| pci_xhci: hostop read offset 0x30 -> 0xbef000 | |
| pci_xhci: hostop read offset 0x34 -> 0x1 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c001 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c000] type x02 SETUP_STAGE 0:x0008000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c010 | |
| xhci update ep-ring, addr 10497c011 | |
| pci_xhci: trb[@0x1c2ea657c010] type x03 DATA_STAGE 0:x000000010497dcc0 2:x00000008 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c020 | |
| xhci update ep-ring, addr 10497c021 | |
| pci_xhci: trb[@0x1c2ea657c020] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c030 | |
| xhci update ep-ring, addr 10497c031 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 8 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c000 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c010 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c020 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c020] 2[1000000] 3[1018000] | |
| erdp idx 4/seg 0, enq idx 4/seg 0, pcs 1 | |
| (erdp=0x100c03040, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03048 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03058 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03050, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c031 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c030] type x02 SETUP_STAGE 0:x0000000000283100 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0x1c2ea657c040 | |
| xhci update ep-ring, addr 10497c041 | |
| pci_xhci: trb[@0x1c2ea657c040] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0x1c2ea657c050 | |
| xhci update ep-ring, addr 10497c051 | |
| pci_xhci[1975]: xfer->ndata 2 1 | |
| usb_passthru_request: bRequest: 31 bmRequestType: 0 wValue: 28 wIndex: 0 wLength: 0 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c030 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 000000010497c040 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c040] 2[1000000] 3[1018000] | |
| erdp idx 5/seg 0, enq idx 5/seg 0, pcs 1 | |
| (erdp=0x100c03050, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03058 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03068 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03060, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c051 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c050] type x02 SETUP_STAGE 0:x0012000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c060 | |
| xhci update ep-ring, addr 10497c061 | |
| pci_xhci: trb[@0x1c2ea657c060] type x03 DATA_STAGE 0:x0000000100be5940 2:x00000012 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c070 | |
| xhci update ep-ring, addr 10497c071 | |
| pci_xhci: trb[@0x1c2ea657c070] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c080 | |
| xhci update ep-ring, addr 10497c081 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 12 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 18 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c050 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c060 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c070 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c070] 2[1000000] 3[1018000] | |
| erdp idx 6/seg 0, enq idx 6/seg 0, pcs 1 | |
| (erdp=0x100c03060, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03068 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03078 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03070, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c081 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c080] type x02 SETUP_STAGE 0:x000500000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c090 | |
| xhci update ep-ring, addr 10497c091 | |
| pci_xhci: trb[@0x1c2ea657c090] type x03 DATA_STAGE 0:x0000000100bdaff0 2:x00000005 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c0a0 | |
| xhci update ep-ring, addr 10497c0a1 | |
| pci_xhci: trb[@0x1c2ea657c0a0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c0b0 | |
| xhci update ep-ring, addr 10497c0b1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 5 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 5 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c080 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c090 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c0a0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c0a0] 2[1000000] 3[1018000] | |
| erdp idx 7/seg 0, enq idx 7/seg 0, pcs 1 | |
| (erdp=0x100c03070, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03078 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03088 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03080, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c0b1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c0b0] type x02 SETUP_STAGE 0:x001600000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c0c0 | |
| xhci update ep-ring, addr 10497c0c1 | |
| pci_xhci: trb[@0x1c2ea657c0c0] type x03 DATA_STAGE 0:x0000000100be5940 2:x00000016 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c0d0 | |
| xhci update ep-ring, addr 10497c0d1 | |
| pci_xhci: trb[@0x1c2ea657c0d0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c0e0 | |
| xhci update ep-ring, addr 10497c0e1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 16 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 22 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c0b0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c0c0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c0d0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c0d0] 2[1000000] 3[1018000] | |
| erdp idx 8/seg 0, enq idx 8/seg 0, pcs 1 | |
| (erdp=0x100c03080, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03088 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03098 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03090, events cnt 0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c0e1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c0e0] type x02 SETUP_STAGE 0:x0009000002000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c0f0 | |
| xhci update ep-ring, addr 10497c0f1 | |
| pci_xhci: trb[@0x1c2ea657c0f0] type x03 DATA_STAGE 0:x0000000100be0360 2:x00000009 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c100 | |
| xhci update ep-ring, addr 10497c101 | |
| pci_xhci: trb[@0x1c2ea657c100] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c110 | |
| xhci update ep-ring, addr 10497c111 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 9 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 9 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c0e0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c0f0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c100 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c100] 2[1000000] 3[1018000] | |
| erdp idx 9/seg 0, enq idx 9/seg 0, pcs 1 | |
| (erdp=0x100c03090, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03098 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc030a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c030a0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c111 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c110] type x02 SETUP_STAGE 0:x0079000002000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c120 | |
| xhci update ep-ring, addr 10497c121 | |
| pci_xhci: trb[@0x1c2ea657c120] type x03 DATA_STAGE 0:x0000000100bf7780 2:x00000079 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c130 | |
| xhci update ep-ring, addr 10497c131 | |
| pci_xhci: trb[@0x1c2ea657c130] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c140 | |
| xhci update ep-ring, addr 10497c141 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 79 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 121 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c110 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c120 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c130 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c130] 2[1000000] 3[1018000] | |
| erdp idx 10/seg 0, enq idx 10/seg 0, pcs 1 | |
| (erdp=0x100c030a0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc030a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc030b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c030b0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c141 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c140] type x02 SETUP_STAGE 0:x00ff000003000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c150 | |
| xhci update ep-ring, addr 10497c151 | |
| pci_xhci: trb[@0x1c2ea657c150] type x03 DATA_STAGE 0:x0000000100d53600 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c160 | |
| xhci update ep-ring, addr 10497c161 | |
| pci_xhci: trb[@0x1c2ea657c160] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c170 | |
| xhci update ep-ring, addr 10497c171 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 300 wIndex: 0 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 251 txlen 4 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c140 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:251 trb 3 000000010497c150 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[10497c150] 2[d0000fb] 3[1018000] | |
| erdp idx 11/seg 0, enq idx 11/seg 0, pcs 1 | |
| (erdp=0x100c030b0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c160 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c160] 2[10000fb] 3[1018000] | |
| erdp idx 11/seg 0, enq idx 12/seg 0, pcs 1 | |
| (erdp=0x100c030b0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc030b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc030d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c030d0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c171 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c170] type x02 SETUP_STAGE 0:x00ff040903030680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c180 | |
| xhci update ep-ring, addr 10497c181 | |
| pci_xhci: trb[@0x1c2ea657c180] type x03 DATA_STAGE 0:x0000000100d53600 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c190 | |
| xhci update ep-ring, addr 10497c191 | |
| pci_xhci: trb[@0x1c2ea657c190] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c1a0 | |
| xhci update ep-ring, addr 10497c1a1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 303 wIndex: 1033 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 223 txlen 32 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c170 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:223 trb 3 000000010497c180 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[10497c180] 2[d0000df] 3[1018000] | |
| erdp idx 13/seg 0, enq idx 13/seg 0, pcs 1 | |
| (erdp=0x100c030d0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c190 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c190] 2[10000df] 3[1018000] | |
| erdp idx 13/seg 0, enq idx 14/seg 0, pcs 1 | |
| (erdp=0x100c030d0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc030d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc030f8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c030f0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c1a1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c1a0] type x02 SETUP_STAGE 0:x00ff040903020680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c1b0 | |
| xhci update ep-ring, addr 10497c1b1 | |
| pci_xhci: trb[@0x1c2ea657c1b0] type x03 DATA_STAGE 0:x0000000100d53600 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c1c0 | |
| xhci update ep-ring, addr 10497c1c1 | |
| pci_xhci: trb[@0x1c2ea657c1c0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c1d0 | |
| xhci update ep-ring, addr 10497c1d1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 302 wIndex: 1033 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 237 txlen 18 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c1a0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:237 trb 3 000000010497c1b0 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[10497c1b0] 2[d0000ed] 3[1018000] | |
| erdp idx 15/seg 0, enq idx 15/seg 0, pcs 1 | |
| (erdp=0x100c030f0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c1c0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c1c0] 2[10000ed] 3[1018000] | |
| erdp idx 15/seg 0, enq idx 16/seg 0, pcs 1 | |
| (erdp=0x100c030f0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc030f8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03118 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03110, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c1d1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c1d0] type x02 SETUP_STAGE 0:x00ff040903010680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c1e0 | |
| xhci update ep-ring, addr 10497c1e1 | |
| pci_xhci: trb[@0x1c2ea657c1e0] type x03 DATA_STAGE 0:x0000000100d53600 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c1f0 | |
| xhci update ep-ring, addr 10497c1f1 | |
| pci_xhci: trb[@0x1c2ea657c1f0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c200 | |
| xhci update ep-ring, addr 10497c201 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 301 wIndex: 1033 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 229 txlen 26 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c1d0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:229 trb 3 000000010497c1e0 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[10497c1e0] 2[d0000e5] 3[1018000] | |
| erdp idx 17/seg 0, enq idx 17/seg 0, pcs 1 | |
| (erdp=0x100c03110, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c1f0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c1f0] 2[10000e5] 3[1018000] | |
| erdp idx 17/seg 0, enq idx 18/seg 0, pcs 1 | |
| (erdp=0x100c03110, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03118 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03138 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03130, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x000000010497b000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000000 A:x00000019 7:x00000000 | |
| enable ep[3] 00000000 04000f36 0000000104981001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[4] 00000000 04000f16 0000000104983001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02020] 2[1000000] 3[1008401] | |
| erdp idx 19/seg 0, enq idx 19/seg 0, pcs 1 | |
| (erdp=0x100c03130, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03138 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03148 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03140, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01033c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 3: slot 1: type 15 | |
| pci_xhci: reset ep[3] 00000003 04000f36 0000000104981001 00000000 | |
| pcif_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[100c02030] 2[1000000] 3[1008401] | |
| erdp idx 20/seg 0, enq idx 20/seg 0, pcs 1 | |
| (erdp=0x100c03140, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03148 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03158 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03150, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000104985000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000008 A:x00000009 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000003 04000f36 0000000104981001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02040] 2[1000000] 3[1008401] | |
| erdp idx 21/seg 0, enq idx 21/seg 0, pcs 1 | |
| (erdp=0x100c03150, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03158 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03168 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03160, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01043c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 4: slot 1: type 15 | |
| pci_xhci: reset ep[4] 00000003 04000f16 0000000104983001 00000000 | |
| pcif_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[100c02050] 2[1000000] 3[1008401] | |
| erdp idx 22/seg 0, enq idx 22/seg 0, pcs 1 | |
| (erdp=0x100c03160, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03168 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03178 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03170, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000104985000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000010 A:x00000011 7:x00000000 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000003 04000f16 0000000104983001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02060] 2[1000000] 3[1008401] | |
| erdp idx 23/seg 0, enq idx 23/seg 0, pcs 1 | |
| (erdp=0x100c03170, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03178 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03188 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03180, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c201 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c200] type x02 SETUP_STAGE 0:x0000000000010900 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0x1c2ea657c210 | |
| xhci update ep-ring, addr 10497c211 | |
| pci_xhci: trb[@0x1c2ea657c210] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0x1c2ea657c220 | |
| xhci update ep-ring, addr 10497c221 | |
| pci_xhci[1975]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c200 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 000000010497c210 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c210] 2[1000000] 3[1018000] | |
| erdp idx 24/seg 0, enq idx 24/seg 0, pcs 1 | |
| (erdp=0x100c03180, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03188 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03198 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03190, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x000000010497b000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000018 A:x00000199 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000000 04000f36 0000000107d54001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000000 04000f16 0000000107d56001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[7] 00000000 04000f36 0000000107d58001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[8] 00000000 04000016 0000000107d5a001 00000000 | |
| init_ep 8 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02070] 2[1000000] 3[1008401] | |
| erdp idx 25/seg 0, enq idx 25/seg 0, pcs 1 | |
| (erdp=0x100c03190, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03198 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc031a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c031a0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c221 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c220] type x02 SETUP_STAGE 0:x0000000000010b01 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0x1c2ea657c230 | |
| xhci update ep-ring, addr 10497c231 | |
| pci_xhci: trb[@0x1c2ea657c230] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0x1c2ea657c240 | |
| xhci update ep-ring, addr 10497c241 | |
| pci_xhci[1975]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c220 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 000000010497c230 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c230] 2[1000000] 3[1018000] | |
| erdp idx 26/seg 0, enq idx 26/seg 0, pcs 1 | |
| (erdp=0x100c031a0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc031a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc031b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c031b0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01033c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 3: slot 1: type 15 | |
| pci_xhci: reset ep[3] 00000003 04000f36 0000000107d54001 00000000 | |
| pcif_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[100c02080] 2[1000000] 3[1008401] | |
| erdp idx 27/seg 0, enq idx 27/seg 0, pcs 1 | |
| (erdp=0x100c031b0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc031b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc031c8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c031c0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000104985000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000008 A:x00000009 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000003 04000f36 0000000107d54001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02090] 2[1000000] 3[1008401] | |
| erdp idx 28/seg 0, enq idx 28/seg 0, pcs 1 | |
| (erdp=0x100c031c0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc031c8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc031d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c031d0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01043c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 4: slot 1: type 15 | |
| pci_xhci: reset ep[4] 00000003 04000f16 0000000107d56001 00000000 | |
| pcif_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[100c020a0] 2[1000000] 3[1008401] | |
| erdp idx 29/seg 0, enq idx 29/seg 0, pcs 1 | |
| (erdp=0x100c031d0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc031d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc031e8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c031e0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000104985000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000010 A:x00000011 7:x00000000 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000003 04000f16 0000000107d56001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c020b0] 2[1000000] 3[1008401] | |
| erdp idx 30/seg 0, enq idx 30/seg 0, pcs 1 | |
| (erdp=0x100c031e0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc031e8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc031f8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c031f0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01073c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 7: slot 1: type 15 | |
| pci_xhci: reset ep[7] 00000003 04000f36 0000000107d58001 00000000 | |
| pcif_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[100c020c0] 2[1000000] 3[1008401] | |
| erdp idx 31/seg 0, enq idx 31/seg 0, pcs 1 | |
| (erdp=0x100c031f0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc031f8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03208 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03200, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000104985000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000080 A:x00000081 7:x00000000 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00000003 04000f36 0000000107d58001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c020d0] 2[1000000] 3[1008401] | |
| erdp idx 32/seg 0, enq idx 32/seg 0, pcs 1 | |
| (erdp=0x100c03200, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03208 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03218 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03210, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01083c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 8: slot 1: type 15 | |
| pci_xhci: reset ep[8] 00000003 04000016 0000000107d5a001 00000000 | |
| pcif_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[100c020e0] 2[1000000] 3[1008401] | |
| erdp idx 33/seg 0, enq idx 33/seg 0, pcs 1 | |
| (erdp=0x100c03210, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03218 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03228 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03220, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000104985000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000100 A:x00000101 7:x00000000 | |
| config ep - dropping ep 8 | |
| pci_xhci disable_ep 8 | |
| enable ep[8] 00000003 04000016 0000000107d5a001 00000000 | |
| init_ep 8 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c020f0] 2[1000000] 3[1008401] | |
| erdp idx 34/seg 0, enq idx 34/seg 0, pcs 1 | |
| (erdp=0x100c03220, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03228 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03238 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03230, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000104985000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000098 A:x00000099 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00008401 04000f36 0000000107d3d100 00000000 | |
| init_ep 3 with pstreams 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00008401 04000f16 0000000107d3d200 00000000 | |
| init_ep 4 with pstreams 1 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00008401 04000f36 0000000107d3d000 00000000 | |
| init_ep 7 with pstreams 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02100] 2[1000000] 3[1008401] | |
| erdp idx 35/seg 0, enq idx 35/seg 0, pcs 1 | |
| (erdp=0x100c03230, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03238 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03248 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03240, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x10007 | |
| pci_xhci doorbell slot 1 epid 7 stream 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[7] 00008401 04000f36 0000000107d3d000 00000000 | |
| pci_xhci: invalid stream 1: 10 | |
| pci_xhci: doorbell write offset 0x1: 0x10003 | |
| pci_xhci doorbell slot 1 epid 3 stream 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[3] 00008401 04000f36 0000000107d3d100 00000000 | |
| pci_xhci: invalid stream 1: 10 | |
| pci_xhci: doorbell write offset 0x1: 0x8 | |
| pci_xhci doorbell slot 1 epid 8 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[8] 00000001 04000016 0000000107d5a001 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea995a000] type x01 NORMAL 0:x0000000106752b00 2:x00000020 3:x00000421 | |
| pci_xhci: next trb: 0x1c2ea995a010 | |
| xhci update ep-ring, addr 107d5a011 | |
| pci_xhci[1975]: xfer->ndata 1 8 | |
| usb_passthru handle data - DIR=OUT|EP=4, blen 32, transfer_type: 2, ndata: 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?0:0 trb 1 0000000107d5a000 421 (err 1) IOC?1 | |
| usb_passthru_data_callback: act_len: 32 blen:0 in:0 epid:4 status: 0 | |
| xhci device interrupt on endpoint 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 1 0000000107d5a000 421 (err 1) IOC?1 | |
| pci_xhci: insert event 0[107d5a000] 2[1000000] 3[1088000] | |
| erdp idx 36/seg 0, enq idx 36/seg 0, pcs 1 | |
| (erdp=0x100c03240, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci doorbell slot 1 epid 8 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[8] 00000001 04000016 0000000107d5a011 00000000 | |
| doorbell, ccs 1, trb ccs 0 | |
| pci_xhci: ring 107d5a011 trb[107d5a010] EP 8 is RESERVED? | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03248 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03258 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03250, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01033c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 3: slot 1: type 15 | |
| pci_xhci: reset ep[3] 00008403 04000f36 0000000107d3d100 00000000 | |
| pcif_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[100c02110] 2[1000000] 3[1008401] | |
| erdp idx 37/seg 0, enq idx 37/seg 0, pcs 1 | |
| (erdp=0x100c03250, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x10, Trb0 x0000000107d38013 dwTrb2 x00010000 dwTrb3 x01034001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci set_tr: new-tr x0000000107d38010, SCT 1 DCS 1 | |
| stream-id 1, slot 1, epid 3, C 1 | |
| pcif_xhci: command 0x10 result: 0xa | |
| pci_xhci: insert event 0[100c02120] 2[a000000] 3[1008401] | |
| erdp idx 37/seg 0, enq idx 38/seg 0, pcs 1 | |
| (erdp=0x100c03250, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03258 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03278 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03270, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03270 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03278 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: hostop read offset 0x4 -> 0x0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01073c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 7: slot 1: type 15 | |
| pci_xhci: reset ep[7] 00008403 04000f36 0000000107d3d000 00000000 | |
| pcif_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[100c02130] 2[1000000] 3[1008401] | |
| erdp idx 39/seg 0, enq idx 39/seg 0, pcs 1 | |
| (erdp=0x100c03270, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x10, Trb0 x0000000104984013 dwTrb2 x00010000 dwTrb3 x01074001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci set_tr: new-tr x0000000104984010, SCT 1 DCS 1 | |
| stream-id 1, slot 1, epid 7, C 1 | |
| pcif_xhci: command 0x10 result: 0xa | |
| pci_xhci: insert event 0[100c02140] 2[a000000] 3[1008401] | |
| erdp idx 39/seg 0, enq idx 40/seg 0, pcs 1 | |
| (erdp=0x100c03270, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03278 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03298 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03290, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03290 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03298 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000107d3c000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000098 A:x00000099 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000003 04000f36 0000000107d54001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000001 04000f16 0000000107d56001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00000003 04000f36 0000000107d58001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02150] 2[1000000] 3[1008401] | |
| erdp idx 41/seg 0, enq idx 41/seg 0, pcs 1 | |
| (erdp=0x100c03290, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03298 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc032a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c032a0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0xe11 | |
| xhci reset port 1 | |
| usb_passthru_reset | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 42/seg 0, enq idx 42/seg 0, pcs 1 | |
| (erdp=0x100c032a0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc032a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc032b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c032b0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x200e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x80e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x400e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x20e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x11, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01004401, TRB_CYCLE 1/ccs 1 | |
| pci_xhci reset device slot 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pcif_xhci: command 0x11 result: 0x1 | |
| pci_xhci: insert event 0[100c02160] 2[1000000] 3[1008401] | |
| erdp idx 43/seg 0, enq idx 43/seg 0, pcs 1 | |
| (erdp=0x100c032b0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc032b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc032c8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c032c0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xb, Trb0 x000000010497b000 dwTrb2 x00000000 dwTrb3 x01002c01, TRB_CYCLE 1/ccs 1 | |
| pci_xhci: address device, input ctl: D 0x00000000 A 0x00000003, | |
| slot 08400000 00010000 00000000 00000000 | |
| ep0 00000000 02000026 000000010497c241 00000000 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: address device, dev ctx | |
| slot 08400000 00010000 00000000 08000001 | |
| usb_passthru_reset | |
| init_ep 1 with no pstreams | |
| init_ep tr DCS 1 | |
| pci_xhci: address device, output ctx | |
| slot 08400000 00010000 00000000 10000001 | |
| ep0 00000001 02000026 000000010497c241 00000000 | |
| pcif_xhci: command 0xb result: 0x1 | |
| pci_xhci: insert event 0[100c02170] 2[1000000] 3[1008401] | |
| erdp idx 44/seg 0, enq idx 44/seg 0, pcs 1 | |
| (erdp=0x100c032c0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc032c8 | |
| pci_xhci: hostop read offset 0x30 -> 0xbef000 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: hostop read offset 0x34 -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc032d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c032d0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c241 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c240] type x02 SETUP_STAGE 0:x0008000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c250 | |
| xhci update ep-ring, addr 10497c251 | |
| pci_xhci: trb[@0x1c2ea657c250] type x03 DATA_STAGE 0:x0000000101959200 2:x00000008 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c260 | |
| xhci update ep-ring, addr 10497c261 | |
| pci_xhci: trb[@0x1c2ea657c260] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c270 | |
| xhci update ep-ring, addr 10497c271 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 8 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c240 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c250 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c260 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c260] 2[1000000] 3[1018000] | |
| erdp idx 45/seg 0, enq idx 45/seg 0, pcs 1 | |
| (erdp=0x100c032d0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc032d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc032e8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c032e0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c271 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c270] type x02 SETUP_STAGE 0:x0000000000283100 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0x1c2ea657c280 | |
| xhci update ep-ring, addr 10497c281 | |
| pci_xhci: trb[@0x1c2ea657c280] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0x1c2ea657c290 | |
| xhci update ep-ring, addr 10497c291 | |
| pci_xhci[1975]: xfer->ndata 2 1 | |
| usb_passthru_request: bRequest: 31 bmRequestType: 0 wValue: 28 wIndex: 0 wLength: 0 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c270 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 000000010497c280 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c280] 2[1000000] 3[1018000] | |
| erdp idx 46/seg 0, enq idx 46/seg 0, pcs 1 | |
| (erdp=0x100c032e0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc032e8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc032f8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c032f0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c291 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c290] type x02 SETUP_STAGE 0:x0012000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c2a0 | |
| xhci update ep-ring, addr 10497c2a1 | |
| pci_xhci: trb[@0x1c2ea657c2a0] type x03 DATA_STAGE 0:x0000000100c1c0c0 2:x00000012 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c2b0 | |
| xhci update ep-ring, addr 10497c2b1 | |
| pci_xhci: trb[@0x1c2ea657c2b0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c2c0 | |
| xhci update ep-ring, addr 10497c2c1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 12 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 18 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c290 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c2a0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c2b0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c2b0] 2[1000000] 3[1018000] | |
| erdp idx 47/seg 0, enq idx 47/seg 0, pcs 1 | |
| (erdp=0x100c032f0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc032f8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03308 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03300, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c2c1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c2c0] type x02 SETUP_STAGE 0:x000500000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c2d0 | |
| xhci update ep-ring, addr 10497c2d1 | |
| pci_xhci: trb[@0x1c2ea657c2d0] type x03 DATA_STAGE 0:x0000000100c19f18 2:x00000005 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c2e0 | |
| xhci update ep-ring, addr 10497c2e1 | |
| pci_xhci: trb[@0x1c2ea657c2e0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c2f0 | |
| xhci update ep-ring, addr 10497c2f1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 5 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 5 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c2c0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c2d0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c2e0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c2e0] 2[1000000] 3[1018000] | |
| erdp idx 48/seg 0, enq idx 48/seg 0, pcs 1 | |
| (erdp=0x100c03300, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03308 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03318 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03310, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c2f1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c2f0] type x02 SETUP_STAGE 0:x001600000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c300 | |
| xhci update ep-ring, addr 10497c301 | |
| pci_xhci: trb[@0x1c2ea657c300] type x03 DATA_STAGE 0:x0000000100c1c0c0 2:x00000016 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c310 | |
| xhci update ep-ring, addr 10497c311 | |
| pci_xhci: trb[@0x1c2ea657c310] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c320 | |
| xhci update ep-ring, addr 10497c321 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 16 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 22 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c2f0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c300 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c310 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c310] 2[1000000] 3[1018000] | |
| erdp idx 49/seg 0, enq idx 49/seg 0, pcs 1 | |
| (erdp=0x100c03310, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03318 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03328 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03320, events cnt 0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c321 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c320] type x02 SETUP_STAGE 0:x0079000002000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c330 | |
| xhci update ep-ring, addr 10497c331 | |
| pci_xhci: trb[@0x1c2ea657c330] type x03 DATA_STAGE 0:x000000010195ab00 2:x00000079 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c340 | |
| xhci update ep-ring, addr 10497c341 | |
| pci_xhci: trb[@0x1c2ea657c340] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c350 | |
| xhci update ep-ring, addr 10497c351 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 79 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 121 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c320 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c330 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c340 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c340] 2[1000000] 3[1018000] | |
| erdp idx 50/seg 0, enq idx 50/seg 0, pcs 1 | |
| (erdp=0x100c03320, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03328 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03338 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03330, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c351 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c350] type x02 SETUP_STAGE 0:x00ff040903010680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c360 | |
| xhci update ep-ring, addr 10497c361 | |
| pci_xhci: trb[@0x1c2ea657c360] type x03 DATA_STAGE 0:x0000000102b65000 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c370 | |
| xhci update ep-ring, addr 10497c371 | |
| pci_xhci: trb[@0x1c2ea657c370] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c380 | |
| xhci update ep-ring, addr 10497c381 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 301 wIndex: 1033 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 229 txlen 26 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c350 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:229 trb 3 000000010497c360 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[10497c360] 2[d0000e5] 3[1018000] | |
| erdp idx 51/seg 0, enq idx 51/seg 0, pcs 1 | |
| (erdp=0x100c03330, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c370 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c370] 2[10000e5] 3[1018000] | |
| erdp idx 51/seg 0, enq idx 52/seg 0, pcs 1 | |
| (erdp=0x100c03330, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03338 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03358 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03350, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x000000010497b000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000000 A:x00000019 7:x00000000 | |
| enable ep[3] 00000000 04000f36 0000000107d5b001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[4] 00000000 04000f16 0000000107d59001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02180] 2[1000000] 3[1008401] | |
| erdp idx 53/seg 0, enq idx 53/seg 0, pcs 1 | |
| (erdp=0x100c03350, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03358 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03368 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03360, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c381 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c380] type x02 SETUP_STAGE 0:x0000000000010900 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0x1c2ea657c390 | |
| xhci update ep-ring, addr 10497c391 | |
| pci_xhci: trb[@0x1c2ea657c390] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0x1c2ea657c3a0 | |
| xhci update ep-ring, addr 10497c3a1 | |
| pci_xhci[1975]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c380 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 000000010497c390 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c390] 2[1000000] 3[1018000] | |
| erdp idx 54/seg 0, enq idx 54/seg 0, pcs 1 | |
| (erdp=0x100c03360, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03368 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03378 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03370, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x000000010497b000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000018 A:x00000199 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000000 04000f36 0000000107d57001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000000 04000f16 0000000107d55001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[7] 00000000 04000f36 0000000107d80001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[8] 00000000 04000016 0000000107d7e001 00000000 | |
| init_ep 8 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02190] 2[1000000] 3[1008401] | |
| erdp idx 55/seg 0, enq idx 55/seg 0, pcs 1 | |
| (erdp=0x100c03370, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03378 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03388 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03380, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c3a1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c3a0] type x02 SETUP_STAGE 0:x0000000000010b01 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0x1c2ea657c3b0 | |
| xhci update ep-ring, addr 10497c3b1 | |
| pci_xhci: trb[@0x1c2ea657c3b0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0x1c2ea657c3c0 | |
| xhci update ep-ring, addr 10497c3c1 | |
| pci_xhci[1975]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c3a0 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 000000010497c3b0 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c3b0] 2[1000000] 3[1018000] | |
| erdp idx 56/seg 0, enq idx 56/seg 0, pcs 1 | |
| (erdp=0x100c03380, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03388 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03398 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03390, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000107d32000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000098 A:x00000099 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00008401 04000f36 0000000107d3d100 00000000 | |
| init_ep 3 with pstreams 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00008401 04000f16 0000000107d3d000 00000000 | |
| init_ep 4 with pstreams 1 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00008401 04000f36 0000000107d3d200 00000000 | |
| init_ep 7 with pstreams 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c021a0] 2[1000000] 3[1008401] | |
| erdp idx 57/seg 0, enq idx 57/seg 0, pcs 1 | |
| (erdp=0x100c03390, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03398 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc033a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c033a0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x10007 | |
| pci_xhci doorbell slot 1 epid 7 stream 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[7] 00008401 04000f36 0000000107d3d200 00000000 | |
| pci_xhci: invalid stream 1: 10 | |
| pci_xhci: doorbell write offset 0x1: 0x8 | |
| pci_xhci doorbell slot 1 epid 8 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[8] 00000001 04000016 0000000107d7e001 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea997e000] type x01 NORMAL 0:x0000000100c1c0c0 2:x00000020 3:x00000421 | |
| pci_xhci: next trb: 0x1c2ea997e010 | |
| xhci update ep-ring, addr 107d7e011 | |
| pci_xhci[1975]: xfer->ndata 1 8 | |
| usb_passthru handle data - DIR=OUT|EP=4, blen 32, transfer_type: 2, ndata: 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?0:0 trb 1 0000000107d7e000 421 (err 1) IOC?1 | |
| pci_xhci: hostop read offset 0x4 -> 0x0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01083c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 8: slot 1: type 15 | |
| pci_xhci: reset ep[8] 00000003 04000016 0000000107d7e011 00000000 | |
| usb_passthru_cancel | |
| pcif_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[100c021b0] 2[1000000] 3[1008401] | |
| erdp idx 58/seg 0, enq idx 58/seg 0, pcs 1 | |
| (erdp=0x100c033a0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc033a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc033b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c033b0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xf, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01073c01, TRB_CYCLE 1/ccs 1 | |
| Stop Endpoint on slot 0 | |
| pci_xhci: reset ep 7: slot 1: type 15 | |
| pci_xhci: reset ep[7] 00008403 04000f36 0000000107d3d200 00000000 | |
| pcif_xhci: command 0xf result: 0x1 | |
| pci_xhci: insert event 0[100c021c0] 2[1000000] 3[1008401] | |
| erdp idx 59/seg 0, enq idx 59/seg 0, pcs 1 | |
| (erdp=0x100c033b0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x10, Trb0 x0000000107d58013 dwTrb2 x00010000 dwTrb3 x01074001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci set_tr: new-tr x0000000107d58010, SCT 1 DCS 1 | |
| stream-id 1, slot 1, epid 7, C 1 | |
| pcif_xhci: command 0x10 result: 0xa | |
| pci_xhci: insert event 0[100c021d0] 2[a000000] 3[1008401] | |
| erdp idx 59/seg 0, enq idx 60/seg 0, pcs 1 | |
| (erdp=0x100c033b0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc033b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc033d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c033d0, events cnt 0 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc033d0 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc033d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000107d39000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000098 A:x00000099 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000001 04000f36 0000000107d57001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000001 04000f16 0000000107d55001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00000003 04000f36 0000000107d80001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c021e0] 2[1000000] 3[1008401] | |
| erdp idx 61/seg 0, enq idx 61/seg 0, pcs 1 | |
| (erdp=0x100c033d0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc033d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc033e8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c033e0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0xe11 | |
| xhci reset port 1 | |
| usb_passthru_reset | |
| pci_xhci: insert event 0[1000000] 2[1000000] 3[8800] | |
| erdp idx 62/seg 0, enq idx 62/seg 0, pcs 1 | |
| (erdp=0x100c033e0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc033e8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc033f8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c033f0, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0x200e03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x200e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x80e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x400e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs wr offset 0x0, port 1: 0x20e01 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0x11, Trb0 x0000000000000000 dwTrb2 x00000000 dwTrb3 x01004401, TRB_CYCLE 1/ccs 1 | |
| pci_xhci reset device slot 1 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pcif_xhci: command 0x11 result: 0x1 | |
| pci_xhci: insert event 0[100c021f0] 2[1000000] 3[1008401] | |
| erdp idx 63/seg 0, enq idx 63/seg 0, pcs 1 | |
| (erdp=0x100c033f0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc033f8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03408 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03400, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xb, Trb0 x000000010497b000 dwTrb2 x00000000 dwTrb3 x01002c01, TRB_CYCLE 1/ccs 1 | |
| pci_xhci: address device, input ctl: D 0x00000000 A 0x00000003, | |
| slot 08400000 00010000 00000000 00000000 | |
| ep0 00000000 02000026 000000010497c3c1 00000000 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: address device, dev ctx | |
| slot 08400000 00010000 00000000 08000001 | |
| usb_passthru_reset | |
| init_ep 1 with no pstreams | |
| init_ep tr DCS 1 | |
| pci_xhci: address device, output ctx | |
| slot 08400000 00010000 00000000 10000001 | |
| ep0 00000001 02000026 000000010497c3c1 00000000 | |
| pcif_xhci: command 0xb result: 0x1 | |
| pci_xhci: insert event 0[100c02200] 2[1000000] 3[1008401] | |
| erdp idx 64/seg 0, enq idx 64/seg 0, pcs 1 | |
| (erdp=0x100c03400, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03408 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03418 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03410, events cnt 0 | |
| pci_xhci: portregs read offset 0x0 port 1 -> 0xe03 | |
| pci_xhci: portregs read offset 0x0 port 2 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 3 -> 0x2a0 | |
| pci_xhci: portregs read offset 0x0 port 4 -> 0x2a0 | |
| pci_xhci: hostop read offset 0x30 -> 0xbef000 | |
| pci_xhci: hostop read offset 0x34 -> 0x1 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c3c1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c3c0] type x02 SETUP_STAGE 0:x0008000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c3d0 | |
| xhci update ep-ring, addr 10497c3d1 | |
| pci_xhci: trb[@0x1c2ea657c3d0] type x03 DATA_STAGE 0:x00000001019597c0 2:x00000008 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c3e0 | |
| xhci update ep-ring, addr 10497c3e1 | |
| pci_xhci: trb[@0x1c2ea657c3e0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c3f0 | |
| xhci update ep-ring, addr 10497c3f1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 8 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 8 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c3c0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c3d0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c3e0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c3e0] 2[1000000] 3[1018000] | |
| erdp idx 65/seg 0, enq idx 65/seg 0, pcs 1 | |
| (erdp=0x100c03410, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03418 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03428 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03420, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c3f1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c3f0] type x02 SETUP_STAGE 0:x0000000000283100 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0x1c2ea657c400 | |
| xhci update ep-ring, addr 10497c401 | |
| pci_xhci: trb[@0x1c2ea657c400] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0x1c2ea657c410 | |
| xhci update ep-ring, addr 10497c411 | |
| pci_xhci[1975]: xfer->ndata 2 1 | |
| usb_passthru_request: bRequest: 31 bmRequestType: 0 wValue: 28 wIndex: 0 wLength: 0 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c3f0 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 000000010497c400 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c400] 2[1000000] 3[1018000] | |
| erdp idx 66/seg 0, enq idx 66/seg 0, pcs 1 | |
| (erdp=0x100c03420, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03428 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03438 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03430, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c411 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c410] type x02 SETUP_STAGE 0:x0012000001000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c420 | |
| xhci update ep-ring, addr 10497c421 | |
| pci_xhci: trb[@0x1c2ea657c420] type x03 DATA_STAGE 0:x0000000100c1c340 2:x00000012 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c430 | |
| xhci update ep-ring, addr 10497c431 | |
| pci_xhci: trb[@0x1c2ea657c430] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c440 | |
| xhci update ep-ring, addr 10497c441 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 100 wIndex: 0 wLength: 12 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 18 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c410 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c420 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c430 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c430] 2[1000000] 3[1018000] | |
| erdp idx 67/seg 0, enq idx 67/seg 0, pcs 1 | |
| (erdp=0x100c03430, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03438 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03448 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03440, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c441 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c440] type x02 SETUP_STAGE 0:x000500000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c450 | |
| xhci update ep-ring, addr 10497c451 | |
| pci_xhci: trb[@0x1c2ea657c450] type x03 DATA_STAGE 0:x0000000100c19f18 2:x00000005 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c460 | |
| xhci update ep-ring, addr 10497c461 | |
| pci_xhci: trb[@0x1c2ea657c460] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c470 | |
| xhci update ep-ring, addr 10497c471 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 5 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 5 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c440 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c450 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c460 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c460] 2[1000000] 3[1018000] | |
| erdp idx 68/seg 0, enq idx 68/seg 0, pcs 1 | |
| (erdp=0x100c03440, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03448 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03458 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03450, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c471 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c470] type x02 SETUP_STAGE 0:x001600000f000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c480 | |
| xhci update ep-ring, addr 10497c481 | |
| pci_xhci: trb[@0x1c2ea657c480] type x03 DATA_STAGE 0:x0000000100c1c340 2:x00000016 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c490 | |
| xhci update ep-ring, addr 10497c491 | |
| pci_xhci: trb[@0x1c2ea657c490] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c4a0 | |
| xhci update ep-ring, addr 10497c4a1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: f00 wIndex: 0 wLength: 16 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 22 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c470 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c480 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c490 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c490] 2[1000000] 3[1018000] | |
| erdp idx 69/seg 0, enq idx 69/seg 0, pcs 1 | |
| (erdp=0x100c03450, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03458 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03468 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03460, events cnt 0 | |
| pci_xhci: hostcap read offset 0x10 -> 0x3401281 | |
| pci_xhci: xecp read offset 0x0 -> 0x2000402 | |
| pci_xhci: xecp read offset 0x10 -> 0x3000002 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c4a1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c4a0] type x02 SETUP_STAGE 0:x0079000002000680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c4b0 | |
| xhci update ep-ring, addr 10497c4b1 | |
| pci_xhci: trb[@0x1c2ea657c4b0] type x03 DATA_STAGE 0:x000000010195af00 2:x00000079 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c4c0 | |
| xhci update ep-ring, addr 10497c4c1 | |
| pci_xhci: trb[@0x1c2ea657c4c0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c4d0 | |
| xhci update ep-ring, addr 10497c4d1 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 200 wIndex: 0 wLength: 79 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 121 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c4a0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 3 000000010497c4b0 10c05 (err 1) IOC?0 | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c4c0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c4c0] 2[1000000] 3[1018000] | |
| erdp idx 70/seg 0, enq idx 70/seg 0, pcs 1 | |
| (erdp=0x100c03460, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03468 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03478 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03470, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c4d1 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c4d0] type x02 SETUP_STAGE 0:x00ff040903010680 2:x00000008 3:x00030841 | |
| pci_xhci: next trb: 0x1c2ea657c4e0 | |
| xhci update ep-ring, addr 10497c4e1 | |
| pci_xhci: trb[@0x1c2ea657c4e0] type x03 DATA_STAGE 0:x0000000102b65000 2:x000000ff 3:x00010c05 | |
| pci_xhci: next trb: 0x1c2ea657c4f0 | |
| xhci update ep-ring, addr 10497c4f1 | |
| pci_xhci: trb[@0x1c2ea657c4f0] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00001021 | |
| pci_xhci: next trb: 0x1c2ea657c500 | |
| xhci update ep-ring, addr 10497c501 | |
| pci_xhci[1975]: xfer->ndata 3 1 | |
| usb_passthru_request: bRequest: 6 bmRequestType: 80 wValue: 301 wIndex: 1033 wLength: ff | |
| usb_passthru request error code 0 (0=ok), blen 229 txlen 26 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c4d0 30841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:229 trb 3 000000010497c4e0 10c05 (err 1) IOC?0 | |
| pci_xhci: insert event 0[10497c4e0] 2[d0000e5] 3[1018000] | |
| erdp idx 71/seg 0, enq idx 71/seg 0, pcs 1 | |
| (erdp=0x100c03470, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci: xfer[2] done?1:0 trb 4 000000010497c4f0 1021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c4f0] 2[10000e5] 3[1018000] | |
| erdp idx 71/seg 0, enq idx 72/seg 0, pcs 1 | |
| (erdp=0x100c03470, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03478 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc03498 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c03490, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x000000010497b000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000000 A:x00000019 7:x00000000 | |
| enable ep[3] 00000000 04000f36 0000000107d7d001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[4] 00000000 04000f16 0000000107d7f001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x20400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02210] 2[1000000] 3[1008401] | |
| erdp idx 73/seg 0, enq idx 73/seg 0, pcs 1 | |
| (erdp=0x100c03490, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc03498 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc034a8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c034a0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c501 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c500] type x02 SETUP_STAGE 0:x0000000000010900 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0x1c2ea657c510 | |
| xhci update ep-ring, addr 10497c511 | |
| pci_xhci: trb[@0x1c2ea657c510] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0x1c2ea657c520 | |
| xhci update ep-ring, addr 10497c521 | |
| pci_xhci[1975]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c500 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 000000010497c510 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c510] 2[1000000] 3[1018000] | |
| erdp idx 74/seg 0, enq idx 74/seg 0, pcs 1 | |
| (erdp=0x100c034a0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc034a8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc034b8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c034b0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x000000010497b000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000018 A:x00000199 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00000000 04000f36 0000000107d54001 00000000 | |
| init_ep 3 with no pstreams | |
| init_ep tr DCS 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00000000 04000f16 0000000107d56001 00000000 | |
| init_ep 4 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[7] 00000000 04000f36 0000000104984001 00000000 | |
| init_ep 7 with no pstreams | |
| init_ep tr DCS 1 | |
| enable ep[8] 00000000 04000016 0000000104982001 00000000 | |
| init_ep 8 with no pstreams | |
| init_ep tr DCS 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02220] 2[1000000] 3[1008401] | |
| erdp idx 75/seg 0, enq idx 75/seg 0, pcs 1 | |
| (erdp=0x100c034b0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc034b8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc034c8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c034c0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x1: 0x1 | |
| pci_xhci doorbell slot 1 epid 1 stream 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: device doorbell ep[1] 00000001 02000026 000000010497c521 00000000 | |
| doorbell, ccs 1, trb ccs 1 | |
| pci_xhci handle_transfer slot 1 | |
| pci_xhci: trb[@0x1c2ea657c520] type x02 SETUP_STAGE 0:x0000000000010b01 2:x00000008 3:x00000841 | |
| pci_xhci: next trb: 0x1c2ea657c530 | |
| xhci update ep-ring, addr 10497c531 | |
| pci_xhci: trb[@0x1c2ea657c530] type x04 STATUS_STAGE 0:x0000000000000000 2:x00000000 3:x00011021 | |
| pci_xhci: next trb: 0x1c2ea657c540 | |
| xhci update ep-ring, addr 10497c541 | |
| pci_xhci[1975]: xfer->ndata 2 1 | |
| usb_passthru request error code 0 (0=ok), blen 0 txlen 0 | |
| pci_xhci: get dev ctx, slot 1 devctx addr 000000010497a000 | |
| pci_xhci: xfer[0] done?1:0 trb 2 000000010497c520 841 (err 1) IOC?0 | |
| pci_xhci: xfer[1] done?1:0 trb 4 000000010497c530 11021 (err 1) IOC?1 | |
| pci_xhci: insert event 0[10497c530] 2[1000000] 3[1018000] | |
| erdp idx 76/seg 0, enq idx 76/seg 0, pcs 1 | |
| (erdp=0x100c034c0, erst=0x100c03000, tblsz=256, do_intr 0) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc034c8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc034d8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c034d0, events cnt 0 | |
| pci_xhci: doorbell write offset 0x0: 0x0 | |
| pci_xhci: cmd type 0xc, Trb0 x0000000104985000 dwTrb2 x00000000 dwTrb3 x01003001, TRB_CYCLE 1/ccs 1 | |
| pci_xhci config_ep slot 1 | |
| pci_xhci: config_ep inputctx: D:x00000098 A:x00000099 7:x00000000 | |
| config ep - dropping ep 3 | |
| pci_xhci disable_ep 3 | |
| enable ep[3] 00008401 04000f36 0000000107d3d100 00000000 | |
| init_ep 3 with pstreams 1 | |
| config ep - dropping ep 4 | |
| pci_xhci disable_ep 4 | |
| enable ep[4] 00008401 04000f16 0000000107d3d200 00000000 | |
| init_ep 4 with pstreams 1 | |
| config ep - dropping ep 7 | |
| pci_xhci disable_ep 7 | |
| enable ep[7] 00008401 04000f36 0000000107d3d000 00000000 | |
| init_ep 7 with pstreams 1 | |
| EP configured; slot 1 [0]=0x40400000 [1]=0x00010000 [2]=0x00000000 [3]=0x18000001 | |
| pcif_xhci: command 0xc result: 0x1 | |
| pci_xhci: insert event 0[100c02230] 2[1000000] 3[1008401] | |
| erdp idx 77/seg 0, enq idx 77/seg 0, pcs 1 | |
| (erdp=0x100c034d0, erst=0x100c03000, tblsz=256, do_intr 1) | |
| pci_xhci_assert_interrupt | |
| pci_xhci: hostop read offset 0x4 -> 0x8 | |
| pci_xhci: hostop write offset 0x4: 0x8 | |
| pci_xhci: rtsregs read offset 0x18 -> 0xc034d8 | |
| pci_xhci: rtsregs read offset 0x1c -> 0x1 | |
| pci_xhci: runtime regs write offset 0x38: 0xc034e8 | |
| pci_xhci: runtime regs write offset 0x3c: 0x1 | |
| pci_xhci: erdp 0x100c034e0, events cnt 0 | |
| Unhandled ps2 mouse command 0xe1 | |
| Unhandled ps2 mouse command 0x0a | |
| Unhandled ps2 mouse command 0x01 | |
| Unhandled ps2 mouse command 0x41 | |
| Unhandled ps2 mouse command 0x88 | |
| pci_xhci: hostop read offset 0x4 -> 0x0 | |
| pci_xhci: hostop read offset 0x0 -> 0x5 | |
| pci_xhci: hostop write offset 0x0: 0x0 | |
| pci_xhci: hostop read offset 0x4 -> 0x1 | |
| pci_xhci: hostop read offset 0x4 -> 0x1 | |
| stop libusb pullthread |
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