PLatch.v

module PLatch(clk,ld,din,dout);
	input clk,ld;
	input [9:0] din;
	output [9:0] dout;
	reg [9:0] dreg;
	
	always @(posedge clk) begin
		if(ld==1'b1)
			dreg=din;
	end
	assign dout=dreg;
endmodule