TimingGenerator.v

module TimingGenerator(clk,cs,shift,ld);
	input clk;
	output cs,shift,ld;
	reg rcs;
	reg [3:0] cnt;
	
	always @(posedge clk) begin
		cnt=cnt+1;
	end
	
	//cs ff
	always @(negedge clk) begin
		if(cnt==4'h0) begin
			rcs=1'b1;
		end
		else begin
			if(cnt==4'd15) begin
				rcs=1'b0;
			end
		end
	end
	assign cs=rcs;
	assign ld=(cnt==4'd15) ? 1'b1 : 1'b0;
	assign shift=((cnt>=4'd5) && (cnt<=4'd14)) ? 1'b1 : 1'b0;
endmodule