dumny1.v

module dummy1(
	/*  specific */
	input clk,
	input rst,
	
	/* WB */
	input [31:0] wb_adr_i,
	input [31:0] wb_dat_i,
		output reg [31:0] wb_dat_o,
	input [3:0] wb_sel_i,
	input wb_cyc_i,
	input wb_stb_i,
	input wb_we_i,
	output reg wb_ack_o
);
reg [31:0] dummy_reg;
reg [31:0] dummy_reg2;
reg dummy_flag_clear;
reg dummy_flag_clear2;
reg next_csr_we;

/*
*  * Logic and CSR interface
*   */

always @(posedge clk) begin
	if(rst) begin
		/* intialization */
		dummy_reg <= 0;
		dummy_flag_clear <= 0;
		dummy_reg2 <= 0;
		dummy_flag_clear2 <= 0;
	end else begin
		/* we are doing more here !! */
		if(dummy_flag_clear) begin
			dummy_reg <= 32'hffffffff;
			dummy_flag_clear <= 0;
			dummy_reg2 <= 32'hffffffff;
			dummy_flag_clear2 <= 0;
		end
	end
	wb_dat_o <= 0;
	/* writes */
	if(next_csr_we) begin
		case(wb_adr_i[9:2])
			/* general porpuse register */
			8'h00 : begin
				dummy_reg <= wb_dat_i[31:0];
			end
			8'h01 : begin
				dummy_reg2 <= wb_dat_i[31:0];
			end
		endcase 
	end
	/* reads */
	case(wb_adr_i[9:2])
		8'h00: begin
			/* general porpuse register */
			wb_dat_o <= dummy_reg;
			dummy_flag_clear <= read_flag_wire;
		end
		8'h01: begin
			/* general porpuse register */
			wb_dat_o <= dummy_reg2;
			dummy_flag_clear2 <= read_flag_wire;
		end
		8'h02: begin
			dummy_flag_clear <= read_flag_wire;
		end 
		8'h02: begin
			dummy_flag_clear2 <= read_flag_wire;
		end 
       endcase
end

wire read_flag_wire;
reg read_flag;
always @(posedge clk) begin
	if (wb_cyc_i & wb_stb_i) begin
		read_flag <= 1'b1;
	end
	else begin
		read_flag <= 1'b0;
	end
end

assign read_flag_wire = read_flag;

/* fsm wishbone */

reg [1:0] state;
reg [1:0] next_state;

parameter IDLE		= 2'd0;
parameter DELAYACK1	= 2'd1;
parameter DELAYACK2	= 2'd2;
parameter ACK		= 2'd3;

always @(posedge clk) begin
	if(rst)
		state <= IDLE;
	else
		state <= next_state;
end

always @(*) begin
	next_state = state;
	
	wb_ack_o = 1'b0;
	next_csr_we = 1'b0;
	
	case(state)
		IDLE: begin
			if(wb_cyc_i & wb_stb_i) begin
				/* We have a request for us */
				next_csr_we = wb_we_i;
				if(wb_we_i)
					next_state = ACK;
				else
					next_state = DELAYACK1;
			end
		end
		DELAYACK1: next_state = DELAYACK2;
		DELAYACK2: next_state = ACK;
		ACK: begin
			wb_ack_o = 1'b1;
			next_state = IDLE;
		end
	endcase
end

endmodule