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lancejpollard/functions.json

Last active January 30, 2021 07:27
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XED ISA as JSON
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functions.json
[
{
"name": "MODRM",
"transforms": [
{
"left": [
"mode64",
"eamode64",
"MODRM64alt32()",
"MEMDISP()"
]
},
{
"left": [
"mode64",
"eamode32",
"MODRM64alt32()",
"MEMDISP()"
]
},
{
"left": [
"mode32",
"eamode32",
"MODRM32()",
"MEMDISP()"
]
},
{
"left": [
"mode32",
"eamode16",
"MODRM16()",
"MEMDISP()"
]
},
{
"left": [
"mode16",
"eamode32",
"MODRM32()",
"MEMDISP()"
]
},
{
"left": [
"mode16",
"eamode16",
"MODRM16()",
"MEMDISP()"
]
}
]
},
{
"name": "MODRM64alt32",
"transforms": [
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b000"
}
],
"right": [
"BASE0=ArAX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b000"
}
],
"right": [
"BASE0=Ar8()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b001"
}
],
"right": [
"BASE0=ArCX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b001"
}
],
"right": [
"BASE0=Ar9()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b010"
}
],
"right": [
"BASE0=ArDX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b010"
}
],
"right": [
"BASE0=Ar10()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b011"
}
],
"right": [
"BASE0=ArBX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b011"
}
],
"right": [
"BASE0=Ar11()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b100"
},
"SIB()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b100"
},
"SIB()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b101"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=rIPa()",
"SEG0=FINAL_DSEG()",
"enc"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b101"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=rIPa()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b110"
}
],
"right": [
"BASE0=ArSI()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b110"
}
],
"right": [
"BASE0=Ar14()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b111"
}
],
"right": [
"BASE0=ArDI()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b111"
}
],
"right": [
"BASE0=Ar15()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b000"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=ArAX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b000"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=Ar8()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b001"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=ArCX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b001"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=Ar9()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b010"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=ArDX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b010"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=Ar10()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b011"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=ArBX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b011"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=Ar11()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b100"
},
"SIB()"
],
"right": [
"NEED_MEMDISP=8"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b100"
},
"SIB()"
],
"right": [
"NEED_MEMDISP=8"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b101"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=ArBP()",
"SEG0=FINAL_SSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b101"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=Ar13()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b110"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=ArSI()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b110"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=Ar14()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b111"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=ArDI()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b111"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=Ar15()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b000"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=ArAX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b000"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=Ar8()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b001"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=ArCX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b001"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=Ar9()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b010"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=ArDX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b010"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=Ar10()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b011"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=ArBX()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b011"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=Ar11()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b100"
},
"SIB()"
],
"right": [
"NEED_MEMDISP=32"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b100"
},
"SIB()"
],
"right": [
"NEED_MEMDISP=32"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b101"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=ArBP()",
"SEG0=FINAL_SSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b101"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=Ar13()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b110"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=ArSI()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b110"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=Ar14()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "0"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b111"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=ArDI()",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "REXB",
"value": "1"
},
{
"key": "MOD",
"value": "0b10"
},
{
"key": "RM",
"value": "0b111"
}
],
"right": [
"NEED_MEMDISP=32",
"BASE0=Ar15()",
"SEG0=FINAL_DSEG()"
]
}
]
},
{
"name": "MODRM32",
"transforms": [
{
"left": [
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b000"
}
],
"right": [
"BASE0=XED_REG_EAX",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b001"
}
],
"right": [
"BASE0=XED_REG_ECX",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b010"
}
],
"right": [
"BASE0=XED_REG_EDX",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b011"
}
],
"right": [
"BASE0=XED_REG_EBX",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b100"
},
"SIB()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b101"
}
],
"right": [
"NEED_MEMDISP=32",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b110"
}
],
"right": [
"BASE0=XED_REG_ESI",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b00"
},
{
"key": "RM",
"value": "0b111"
}
],
"right": [
"BASE0=XED_REG_EDI",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b000"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=XED_REG_EAX",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b001"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=XED_REG_ECX",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b010"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=XED_REG_EDX",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b011"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=XED_REG_EBX",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b100"
},
"SIB()"
],
"right": [
"NEED_MEMDISP=8"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b101"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=XED_REG_EBP",
"SEG0=FINAL_SSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b110"
}
],
"right": [
"NEED_MEMDISP=8",
"BASE0=XED_REG_ESI",
"SEG0=FINAL_DSEG()"
]
},
{
"left": [
{
"key": "MOD",
"value": "0b01"
},
{
"key": "RM",
"value": "0b111"
}
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},
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},
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},
{
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},
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}
]
},
{
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},
{
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{
"name": "BRANCH_HINT",
"transforms": [
{
"left": [
"otherwise",
"->",
"nothing"
]
}
]
},
{
"name": "CET_NO_TRACK",
"transforms": [
{
"left": [
"otherwise",
"->",
"nothing"
]
}
]
},
{
"name": "REMOVE_SEGMENT",
"transforms": [
{
"left": [
"mode16"
],
"right": [
"SEG0=XED_REG_INVALID"
]
},
{
"left": [
"mode32"
],
"right": [
"SEG0=XED_REG_INVALID"
]
},
{
"left": [
"mode64"
],
"right": [
"SEG0=XED_REG_INVALID"
]
}
]
},
{
"name": "PREFIXES",
"transforms": [
{
"left": [
"mode64",
"0b0100",
"wrxb"
],
"right": [
"XED_RESET",
"REX=1",
"REXW=w",
"REXR=r",
"REXX=x",
"REXB=b"
]
},
{
"left": [
"mode64",
"0xf2",
{
"key": "MODE_FIRST_PREFIX",
"value": "0"
}
],
"right": [
"XED_RESET",
"reset_rex",
"f2_prefix",
"refining_f2"
]
},
{
"left": [
"mode64",
"0xf3",
{
"key": "MODE_FIRST_PREFIX",
"value": "0"
}
],
"right": [
"XED_RESET",
"reset_rex",
"f3_prefix",
"refining_f3"
]
},
{
"left": [
"mode64",
"0xf2",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP",
"value": "0"
}
],
"right": [
"XED_RESET",
"reset_rex",
"f2_prefix",
"refining_f2"
]
},
{
"left": [
"mode64",
"0xf3",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP",
"value": "0"
}
],
"right": [
"XED_RESET",
"reset_rex",
"f3_prefix",
"refining_f3"
]
},
{
"left": [
"mode64",
"0xf2",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP!",
"value": "0"
}
],
"right": [
"XED_RESET",
"reset_rex"
]
},
{
"left": [
"mode64",
"0xf3",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP!",
"value": "0"
}
],
"right": [
"XED_RESET",
"reset_rex"
]
},
{
"left": [
"mode64",
"0x66"
],
"right": [
"XED_RESET",
"66_prefix",
"PREFIX66=1",
"reset_rex"
]
},
{
"left": [
"mode64",
"0x67"
],
"right": [
"XED_RESET",
"67_prefix",
"reset_rex"
]
},
{
"left": [
"mode64",
"0xf0"
],
"right": [
"XED_RESET",
"lock_prefix",
"reset_rex"
]
},
{
"left": [
"mode64",
"0x2e"
],
"right": [
"XED_RESET",
"HINT=1",
"reset_rex"
]
},
{
"left": [
"mode64",
"0x3e"
],
"right": [
"XED_RESET",
"HINT=2",
"reset_rex"
]
},
{
"left": [
"mode64",
"0x26"
],
"right": [
"XED_RESET",
"reset_rex"
]
},
{
"left": [
"mode64",
"0x64"
],
"right": [
"XED_RESET",
"fs_prefix",
"reset_rex"
]
},
{
"left": [
"mode64",
"0x65"
],
"right": [
"XED_RESET",
"gs_prefix",
"reset_rex"
]
},
{
"left": [
"mode64",
"0x36"
],
"right": [
"XED_RESET",
"reset_rex"
]
},
{
"left": [
"mode32",
"0xf2",
{
"key": "MODE_FIRST_PREFIX",
"value": "0"
}
],
"right": [
"XED_RESET",
"f2_prefix",
"refining_f2"
]
},
{
"left": [
"mode32",
"0xf3",
{
"key": "MODE_FIRST_PREFIX",
"value": "0"
}
],
"right": [
"XED_RESET",
"f3_prefix",
"refining_f3"
]
},
{
"left": [
"mode32",
"0xf2",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP",
"value": "0"
}
],
"right": [
"XED_RESET",
"f2_prefix",
"refining_f2"
]
},
{
"left": [
"mode32",
"0xf3",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP",
"value": "0"
}
],
"right": [
"XED_RESET",
"f3_prefix",
"refining_f3"
]
},
{
"left": [
"mode32",
"0xf2",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP!",
"value": "0"
}
],
"right": [
"XED_RESET"
]
},
{
"left": [
"mode32",
"0xf3",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP!",
"value": "0"
}
],
"right": [
"XED_RESET"
]
},
{
"left": [
"mode32",
"0x66"
],
"right": [
"XED_RESET",
"66_prefix",
"PREFIX66=1"
]
},
{
"left": [
"mode32",
"0x67"
],
"right": [
"XED_RESET",
"67_prefix"
]
},
{
"left": [
"mode32",
"0xf0"
],
"right": [
"XED_RESET",
"lock_prefix"
]
},
{
"left": [
"mode32",
"0x2e"
],
"right": [
"XED_RESET",
"cs_prefix",
"HINT=1"
]
},
{
"left": [
"mode32",
"0x3e"
],
"right": [
"XED_RESET",
"ds_prefix",
"HINT=2"
]
},
{
"left": [
"mode32",
"0x26"
],
"right": [
"XED_RESET",
"es_prefix"
]
},
{
"left": [
"mode32",
"0x64"
],
"right": [
"XED_RESET",
"fs_prefix"
]
},
{
"left": [
"mode32",
"0x65"
],
"right": [
"XED_RESET",
"gs_prefix"
]
},
{
"left": [
"mode32",
"0x36"
],
"right": [
"XED_RESET",
"ss_prefix"
]
},
{
"left": [
"mode16",
"0xf2",
{
"key": "MODE_FIRST_PREFIX",
"value": "0"
}
],
"right": [
"XED_RESET",
"f2_prefix",
"refining_f2"
]
},
{
"left": [
"mode16",
"0xf3",
{
"key": "MODE_FIRST_PREFIX",
"value": "0"
}
],
"right": [
"XED_RESET",
"f3_prefix",
"refining_f3"
]
},
{
"left": [
"mode16",
"0xf2",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP",
"value": "0"
}
],
"right": [
"XED_RESET",
"f2_prefix",
"refining_f2"
]
},
{
"left": [
"mode16",
"0xf3",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP",
"value": "0"
}
],
"right": [
"XED_RESET",
"f3_prefix",
"refining_f3"
]
},
{
"left": [
"mode16",
"0xf2",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP!",
"value": "0"
}
],
"right": [
"XED_RESET"
]
},
{
"left": [
"mode16",
"0xf3",
{
"key": "MODE_FIRST_PREFIX",
"value": "1"
},
{
"key": "REP!",
"value": "0"
}
],
"right": [
"XED_RESET"
]
},
{
"left": [
"mode16",
"0x66"
],
"right": [
"XED_RESET",
"66_prefix",
"PREFIX66=1"
]
},
{
"left": [
"mode16",
"0x67"
],
"right": [
"XED_RESET",
"67_prefix"
]
},
{
"left": [
"mode16",
"0xf0"
],
"right": [
"XED_RESET",
"lock_prefix"
]
},
{
"left": [
"mode16",
"0x2e"
],
"right": [
"XED_RESET",
"cs_prefix",
"HINT=1"
]
},
{
"left": [
"mode16",
"0x3e"
],
"right": [
"XED_RESET",
"ds_prefix",
"HINT=2"
]
},
{
"left": [
"mode16",
"0x26"
],
"right": [
"XED_RESET",
"es_prefix"
]
},
{
"left": [
"mode16",
"0x64"
],
"right": [
"XED_RESET",
"fs_prefix"
]
},
{
"left": [
"mode16",
"0x65"
],
"right": [
"XED_RESET",
"gs_prefix"
]
},
{
"left": [
"mode16",
"0x36"
],
"right": [
"XED_RESET",
"ss_prefix"
]
},
{
"left": [
"otherwise"
]
}
]
},
{
"name": "BRANCH_HINT",
"transforms": [
{
"left": [
{
"key": "HINT",
"value": "0"
}
]
},
{
"left": [
{
"key": "HINT",
"value": "1"
}
],
"right": [
"HINT=3"
]
},
{
"left": [
{
"key": "HINT",
"value": "2"
}
],
"right": [
"HINT=4"
]
}
]
},
{
"name": "CET_NO_TRACK",
"transforms": [
{
"left": [
{
"key": "HINT",
"value": "0"
}
]
},
{
"left": [
{
"key": "HINT",
"value": "1"
}
]
},
{
"left": [
{
"key": "HINT",
"value": "2"
}
],
"right": [
"HINT=5"
]
}
]
},
{
"name": "ISA",
"transforms": [
{
"left": [
"PREFIXES()",
"OSZ_NONTERM()",
"ASZ_NONTERM()",
"INSTRUCTIONS()"
]
}
]
}
]
Raw
isa.json
This file has been truncated, but you can view the full file.
[
{
"ICLASS": "V4FMADDPS",
"CPL": "3",
"CATEGORY": "AVX512_4FMAPS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_4FMAPS_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MULTISOURCE4",
"DISP8_TUPLE1_4X",
"MXCSR",
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x9A",
"VF2",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_TUPLE1_4X()"
],
"OPERANDS": [
"REG0=ZMM_R3():rw:zf32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zf32:MULTISOURCE4",
"MEM0:r:dq:f32"
],
"IFORM": "V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512"
},
{
"ICLASS": "V4FMADDSS",
"CPL": "3",
"CATEGORY": "AVX512_4FMAPS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_4FMAPS_SCALAR",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"DISP8_TUPLE1_4X",
"MXCSR",
"MULTISOURCE4",
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"SIMD_SCALAR"
],
"PATTERN": [
"EVV",
"0x9B",
"VF2",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"W0",
"ESIZE_32_BITS()",
"NELEM_TUPLE1_4X()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32:MULTISOURCE4",
"MEM0:r:dq:f32"
],
"IFORM": "V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "V4FNMADDPS",
"CPL": "3",
"CATEGORY": "AVX512_4FMAPS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_4FMAPS_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MULTISOURCE4",
"DISP8_TUPLE1_4X",
"MXCSR",
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xAA",
"VF2",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_TUPLE1_4X()"
],
"OPERANDS": [
"REG0=ZMM_R3():rw:zf32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zf32:MULTISOURCE4",
"MEM0:r:dq:f32"
],
"IFORM": "V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512"
},
{
"ICLASS": "V4FNMADDSS",
"CPL": "3",
"CATEGORY": "AVX512_4FMAPS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_4FMAPS_SCALAR",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"DISP8_TUPLE1_4X",
"MXCSR",
"MULTISOURCE4",
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"SIMD_SCALAR"
],
"PATTERN": [
"EVV",
"0xAB",
"VF2",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"W0",
"ESIZE_32_BITS()",
"NELEM_TUPLE1_4X()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32:MULTISOURCE4",
"MEM0:r:dq:f32"
],
"IFORM": "V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VP4DPWSSD",
"CPL": "3",
"CATEGORY": "AVX512_4VNNIW",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_4VNNIW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MULTISOURCE4",
"DISP8_TUPLE1_4X",
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x52",
"VF2",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"BCRC=0",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_TUPLE1_4X()"
],
"OPERANDS": [
"REG0=ZMM_R3():rw:zi32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zi16:MULTISOURCE4",
"MEM0:r:dq:u32"
],
"IFORM": "VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512"
},
{
"ICLASS": "VP4DPWSSDS",
"CPL": "3",
"CATEGORY": "AVX512_4VNNIW",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_4VNNIW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MULTISOURCE4",
"DISP8_TUPLE1_4X",
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x53",
"VF2",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"BCRC=0",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_TUPLE1_4X()"
],
"OPERANDS": [
"REG0=ZMM_R3():rw:zi32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zi16:MULTISOURCE4",
"MEM0:r:dq:u32"
],
"IFORM": "VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512"
},
{
"ICLASS": "LDTILECFG",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_TILE",
"ISA_SET": "AMX_TILE",
"EXCEPTIONS": "AMX-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX"
],
"PATTERN": [
"VV1",
"0x49",
"VNP",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[0b000]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"mode64",
"NOVSR"
],
"OPERANDS": [
"MEM0:r:zd"
],
"IFORM": "LDTILECFG_MEM"
},
{
"ICLASS": "STTILECFG",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_TILE",
"ISA_SET": "AMX_TILE",
"EXCEPTIONS": "AMX-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX"
],
"PATTERN": [
"VV1",
"0x49",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[0b000]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"mode64",
"NOVSR"
],
"OPERANDS": [
"MEM0:w:zd"
],
"IFORM": "STTILECFG_MEM"
},
{
"ICLASS": "TDPBF16PS",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_BF16",
"ISA_SET": "AMX_BF16",
"EXCEPTIONS": "AMX-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX"
],
"PATTERN": [
"VV1",
"0x5C",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"mode64"
],
"OPERANDS": [
"REG0=TMM_R():rw:tv:f32",
"REG1=TMM_B():r:tv:u32",
"REG2=TMM_N():r:tv:u32"
],
"IFORM": "TDPBF16PS_TMMf32_TMMu32_TMMu32"
},
{
"ICLASS": "TDPBSSD",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_INT8",
"ISA_SET": "AMX_INT8",
"EXCEPTIONS": "AMX-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX"
],
"PATTERN": [
"VV1",
"0x5E",
"VF2",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"mode64"
],
"OPERANDS": [
"REG0=TMM_R():rw:tv:i32",
"REG1=TMM_B():r:tv:u32",
"REG2=TMM_N():r:tv:u32"
],
"IFORM": "TDPBSSD_TMMi32_TMMu32_TMMu32"
},
{
"ICLASS": "TDPBSUD",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_INT8",
"ISA_SET": "AMX_INT8",
"EXCEPTIONS": "AMX-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX"
],
"PATTERN": [
"VV1",
"0x5E",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"mode64"
],
"OPERANDS": [
"REG0=TMM_R():rw:tv:i32",
"REG1=TMM_B():r:tv:u32",
"REG2=TMM_N():r:tv:u32"
],
"IFORM": "TDPBSUD_TMMi32_TMMu32_TMMu32"
},
{
"ICLASS": "TDPBUSD",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_INT8",
"ISA_SET": "AMX_INT8",
"EXCEPTIONS": "AMX-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX"
],
"PATTERN": [
"VV1",
"0x5E",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"mode64"
],
"OPERANDS": [
"REG0=TMM_R():rw:tv:i32",
"REG1=TMM_B():r:tv:u32",
"REG2=TMM_N():r:tv:u32"
],
"IFORM": "TDPBUSD_TMMi32_TMMu32_TMMu32"
},
{
"ICLASS": "TDPBUUD",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_INT8",
"ISA_SET": "AMX_INT8",
"EXCEPTIONS": "AMX-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX"
],
"PATTERN": [
"VV1",
"0x5E",
"VNP",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"mode64"
],
"OPERANDS": [
"REG0=TMM_R():rw:tv:u32",
"REG1=TMM_B():r:tv:u32",
"REG2=TMM_N():r:tv:u32"
],
"IFORM": "TDPBUUD_TMMu32_TMMu32_TMMu32"
},
{
"ICLASS": "TILELOADD",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_TILE",
"ISA_SET": "AMX_TILE",
"EXCEPTIONS": "AMX-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"VV1",
"0x4B",
"VF2",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"MODRM()",
"VL128",
"W0",
"mode64",
"NOVSR"
],
"OPERANDS": [
"REG0=TMM_R():w:tv:u32",
"MEM0:r:ptr:u32"
],
"IFORM": "TILELOADD_TMMu32_MEMu32"
},
{
"ICLASS": "TILELOADDT1",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_TILE",
"ISA_SET": "AMX_TILE",
"EXCEPTIONS": "AMX-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"VV1",
"0x4B",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"MODRM()",
"VL128",
"W0",
"mode64",
"NOVSR"
],
"OPERANDS": [
"REG0=TMM_R():w:tv:u32",
"MEM0:r:ptr:u32"
],
"IFORM": "TILELOADDT1_TMMu32_MEMu32"
},
{
"ICLASS": "TILERELEASE",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_TILE",
"ISA_SET": "AMX_TILE",
"EXCEPTIONS": "AMX-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX"
],
"PATTERN": [
"VV1",
"0x49",
"VNP",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[0b000]",
"RM[0b000]",
"VL128",
"W0",
"mode64",
"NOVSR"
],
"OPERANDS": [
""
],
"IFORM": "TILERELEASE"
},
{
"ICLASS": "TILESTORED",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_TILE",
"ISA_SET": "AMX_TILE",
"EXCEPTIONS": "AMX-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"VV1",
"0x4B",
"VF3",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"MODRM()",
"VL128",
"W0",
"mode64",
"NOVSR"
],
"OPERANDS": [
"MEM0:w:ptr:u32",
"REG0=TMM_R():r:tv:u32"
],
"IFORM": "TILESTORED_MEMu32_TMMu32"
},
{
"ICLASS": "TILEZERO",
"CPL": "3",
"CATEGORY": "AMX_TILE",
"EXTENSION": "AMX_TILE",
"ISA_SET": "AMX_TILE",
"EXCEPTIONS": "AMX-E5",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX"
],
"PATTERN": [
"VV1",
"0x49",
"VF2",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[0b000]",
"VL128",
"W0",
"mode64",
"NOVSR"
],
"OPERANDS": [
"REG0=TMM_R():w:tv:u32"
],
"IFORM": "TILEZERO_TMMu32"
},
{
"ICLASS": "VAESKEYGENASSIST",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AES",
"EXTENSION": "AVXAES",
"PATTERN": [
"VV1",
"0xDF",
"VL128",
"V66",
"V0F3A",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq",
"MEM0:r:dq",
"IMM0:r:b"
]
},
{
"ICLASS": "VAESENC",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AES",
"EXTENSION": "AVXAES",
"PATTERN": [
"VV1",
"0xDC",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R():w:dq",
"REG1=XMM_N():r:dq",
"MEM0:r:dq"
]
},
{
"ICLASS": "VAESENCLAST",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AES",
"EXTENSION": "AVXAES",
"PATTERN": [
"VV1",
"0xDD",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R():w:dq",
"REG1=XMM_N():r:dq",
"MEM0:r:dq"
]
},
{
"ICLASS": "VAESDEC",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AES",
"EXTENSION": "AVXAES",
"PATTERN": [
"VV1",
"0xDE",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R():w:dq",
"REG1=XMM_N():r:dq",
"MEM0:r:dq"
]
},
{
"ICLASS": "VAESDECLAST",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AES",
"EXTENSION": "AVXAES",
"PATTERN": [
"VV1",
"0xDF",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R():w:dq",
"REG1=XMM_N():r:dq",
"MEM0:r:dq"
]
},
{
"ICLASS": "VAESIMC",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AES",
"EXTENSION": "AVXAES",
"PATTERN": [
"VV1",
"0xDB",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq",
"MEM0:r:dq"
]
},
{
"ICLASS": "VADDPD",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x58",
"V66",
"VL256",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64"
]
},
{
"ICLASS": "VADDPS",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x58",
"VNP",
"VL256",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32"
]
},
{
"ICLASS": "VADDSD",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x58",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f64",
"REG1=XMM_N():r:dq:f64",
"REG2=XMM_B():r:q:f64"
]
},
{
"ICLASS": "VADDSS",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x58",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f32",
"REG1=XMM_N():r:dq:f32",
"REG2=XMM_B():r:d:f32"
]
},
{
"ICLASS": "VADDSUBPD",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0xD0",
"VL256",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64"
]
},
{
"ICLASS": "VADDSUBPS",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0xD0",
"VL256",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32"
]
},
{
"ICLASS": "VANDPD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x54",
"VL256",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:u64",
"REG1=YMM_N():r:qq:u64",
"REG2=YMM_B():r:qq:u64"
]
},
{
"ICLASS": "VANDPS",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x54",
"VL256",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq",
"REG1=YMM_N():r:qq",
"REG2=YMM_B():r:qq"
]
},
{
"ICLASS": "VANDNPD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x55",
"VL256",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:u64",
"REG1=YMM_N():r:qq:u64",
"REG2=YMM_B():r:qq:u64"
]
},
{
"ICLASS": "VANDNPS",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x55",
"VL256",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq",
"REG1=YMM_N():r:qq",
"REG2=YMM_B():r:qq"
]
},
{
"ICLASS": "VBLENDPD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x0D",
"VL256",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64",
"IMM0:r:b"
]
},
{
"ICLASS": "VBLENDPS",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x0C",
"VL256",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32",
"IMM0:r:b"
]
},
{
"ICLASS": "VCMPPD",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0xC2",
"V66",
"VL256",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64",
"IMM0:r:b"
]
},
{
"ICLASS": "VCMPPS",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0xC2",
"VNP",
"VL256",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32",
"IMM0:r:b"
]
},
{
"ICLASS": "VCMPSD",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"PATTERN": [
"VV1",
"0xC2",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f64",
"REG1=XMM_N():r:dq:f64",
"REG2=XMM_B():r:q:f64",
"IMM0:r:b"
]
},
{
"ICLASS": "VCMPSS",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"PATTERN": [
"VV1",
"0xC2",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f32",
"REG1=XMM_N():r:dq:f32",
"REG2=XMM_B():r:d:f32",
"IMM0:r:b"
]
},
{
"ICLASS": "VCOMISD",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"FLAGS": {
"klass": "MUST",
"values": [
{
"name": "zf",
"operation": "mod"
},
{
"name": "pf",
"operation": "mod"
},
{
"name": "cf",
"operation": "mod"
},
{
"name": "of",
"operation": "0"
},
{
"name": "af",
"operation": "0"
},
{
"name": "sf",
"operation": "0"
}
]
},
"PATTERN": [
"VV1",
"0x2F",
"V66",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():r:q:f64",
"REG1=XMM_B():r:q:f64"
]
},
{
"ICLASS": "VCOMISS",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"FLAGS": {
"klass": "MUST",
"values": [
{
"name": "zf",
"operation": "mod"
},
{
"name": "pf",
"operation": "mod"
},
{
"name": "cf",
"operation": "mod"
},
{
"name": "of",
"operation": "0"
},
{
"name": "af",
"operation": "0"
},
{
"name": "sf",
"operation": "0"
}
]
},
"PATTERN": [
"VV1",
"0x2F",
"VNP",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():r:d:f32",
"REG1=XMM_B():r:d:f32"
]
},
{
"ICLASS": "VCVTDQ2PD",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"COMMENT": "ignores MXCSR. 32b int fits in f64",
"PATTERN": [
"VV1",
"0xE6",
"VL256",
"VF3",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=XMM_B():r:dq:i32"
]
},
{
"ICLASS": "VCVTDQ2PS",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5B",
"VL256",
"VNP",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_B():r:qq:i32"
]
},
{
"ICLASS": "VCVTPD2DQ",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0xE6",
"VL256",
"VF2",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i32",
"REG1=YMM_B():r:qq:f64"
]
},
{
"ICLASS": "VCVTTPD2DQ",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0xE6",
"VL256",
"V66",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i32",
"REG1=YMM_B():r:qq:f64"
]
},
{
"ICLASS": "VCVTPD2PS",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5A",
"V66",
"VL256",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f32",
"REG1=YMM_B():r:qq:f64"
]
},
{
"ICLASS": "VCVTPS2DQ",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5B",
"VL256",
"V66",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:i32",
"REG1=YMM_B():r:qq:f32"
]
},
{
"ICLASS": "VCVTTPS2DQ",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5B",
"VL256",
"VF3",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:i32",
"REG1=YMM_B():r:qq:f32"
]
},
{
"ICLASS": "VCVTPS2PD",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5A",
"VNP",
"VL256",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=XMM_B():r:dq:f32"
]
},
{
"ICLASS": "VCVTSD2SI",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"COMMENT": "SNB/IVB/HSW require VEX.L=128. Later processors are LIG",
"PATTERN": [
"VV1",
"0x2D",
"VF2",
"V0F",
"NOVSR",
"mode64",
"rexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=GPR64_R():w:q:i64",
"REG1=XMM_B():r:q:f64"
]
},
{
"ICLASS": "VCVTTSD2SI",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"COMMENT": "SNB/IVB/HSW require VEX.L=128. Later processors are LIG",
"PATTERN": [
"VV1",
"0x2C",
"VF2",
"V0F",
"NOVSR",
"mode64",
"rexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=GPR64_R():w:q:i64",
"REG1=XMM_B():r:q:f64"
]
},
{
"ICLASS": "VCVTSS2SI",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"COMMENT": "SNB/IVB/HSW require VEX.L=128. Later processors are LIG",
"PATTERN": [
"VV1",
"0x2D",
"VF3",
"V0F",
"NOVSR",
"mode64",
"rexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=GPR64_R():w:q:i64",
"REG1=XMM_B():r:d:f32"
]
},
{
"ICLASS": "VCVTTSS2SI",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"COMMENT": "SNB/IVB/HSW require VEX.L=128. Later processors are LIG",
"PATTERN": [
"VV1",
"0x2C",
"VF3",
"V0F",
"NOVSR",
"mode64",
"rexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=GPR64_R():w:q:i64",
"REG1=XMM_B():r:d:f32"
]
},
{
"ICLASS": "VCVTSD2SS",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5A",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f32",
"REG1=XMM_N():r:dq:f32",
"REG2=XMM_B():r:q:f64"
]
},
{
"ICLASS": "VCVTSI2SD",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"PATTERN": [
"VV1",
"0x2A",
"VF2",
"V0F",
"mode64",
"rexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f64",
"REG1=XMM_N():r:dq:f64",
"REG2=GPR64_B():r:q:i64"
]
},
{
"ICLASS": "VCVTSI2SS",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"PATTERN": [
"VV1",
"0x2A",
"VF3",
"V0F",
"mode64",
"rexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f32",
"REG1=XMM_N():r:dq:f32",
"REG2=GPR64_B():r:q:i64"
]
},
{
"ICLASS": "VCVTSS2SD",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5A",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f64",
"REG1=XMM_N():r:dq:f64",
"REG2=XMM_B():r:d:f32"
]
},
{
"ICLASS": "VDIVPD",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5E",
"V66",
"V0F",
"VL256",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64"
]
},
{
"ICLASS": "VDIVPS",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5E",
"VNP",
"V0F",
"VL256",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32"
]
},
{
"ICLASS": "VDIVSD",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5E",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f64",
"REG1=XMM_N():r:dq:f64",
"REG2=XMM_B():r:q:f64"
]
},
{
"ICLASS": "VDIVSS",
"EXCEPTIONS": "avx-type-3",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar",
"MXCSR"
],
"PATTERN": [
"VV1",
"0x5E",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f32",
"REG1=XMM_N():r:dq:f32",
"REG2=XMM_B():r:d:f32"
]
},
{
"ICLASS": "VEXTRACTF128",
"EXCEPTIONS": "avx-type-6",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x19",
"norexw_prefix",
"VL256",
"V66",
"V0F3A",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_B():w:dq:f64",
"REG1=YMM_R():r:dq:f64",
"IMM0:r:b"
]
},
{
"ICLASS": "VDPPD",
"EXCEPTIONS": "avx-type-2D",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x41",
"VL128",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f64",
"REG1=XMM_N():r:dq:f64",
"REG2=XMM_B():r:dq:f64",
"IMM0:r:b"
]
},
{
"ICLASS": "VDPPS",
"EXCEPTIONS": "avx-type-2D",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x40",
"VL256",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32",
"IMM0:r:b"
]
},
{
"ICLASS": "VEXTRACTPS",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x17",
"VL128",
"V66",
"V0F3A",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=GPR32_B():w",
"REG1=XMM_R():r:dq:f32",
"IMM0:r:b"
]
},
{
"ICLASS": "VZEROALL",
"EXCEPTIONS": "avx-type-8",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"xmm_state_w"
],
"PATTERN": [
"VV1",
"0x77",
"VNP",
"V0F",
"VL256",
"NOVSR"
]
},
{
"ICLASS": "VZEROUPPER",
"EXCEPTIONS": "avx-type-8",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"xmm_state_w",
"NOTSX",
"#",
"FIXME:",
"should",
"be",
"ymm_state_w?"
],
"PATTERN": [
"VV1",
"0x77",
"VNP",
"V0F",
"VL128",
"NOVSR"
]
},
{
"ICLASS": "VHADDPD",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x7C",
"VL256",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64"
]
},
{
"ICLASS": "VHADDPS",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x7C",
"VL256",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32"
]
},
{
"ICLASS": "VHSUBPD",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x7D",
"VL256",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64"
]
},
{
"ICLASS": "VHSUBPS",
"EXCEPTIONS": "avx-type-2",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0x7D",
"VL256",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32"
]
},
{
"ICLASS": "VPERMILPD",
"EXCEPTIONS": "avx-type-6",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x05",
"VL256",
"V66",
"V0F3A",
"norexw_prefix",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_B():r:qq:f64",
"IMM0:r:b"
]
},
{
"ICLASS": "VPERMILPS",
"EXCEPTIONS": "avx-type-6",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x04",
"VL256",
"V66",
"V0F3A",
"norexw_prefix",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_B():r:qq:f32",
"IMM0:r:b"
]
},
{
"ICLASS": "VPERM2F128",
"EXCEPTIONS": "avx-type-6",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x06",
"VL256",
"V66",
"V0F3A",
"norexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64",
"IMM0:r:b"
]
},
{
"ICLASS": "VBROADCASTSS",
"EXCEPTIONS": "avx-type-6",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x18",
"norexw_prefix",
"VL256",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"MEM0:r:d:f32",
"EMX_BROADCAST_1TO8_32"
]
},
{
"ICLASS": "VBROADCASTSD",
"EXCEPTIONS": "avx-type-6",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x19",
"norexw_prefix",
"VL256",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"MEM0:r:q:f64",
"EMX_BROADCAST_1TO4_64"
]
},
{
"ICLASS": "VBROADCASTF128",
"EXCEPTIONS": "avx-type-6",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX",
"COMMENT": "There is no F128 type. I just set these to f64 for lack of anything better.",
"PATTERN": [
"VV1",
"0x1A",
"norexw_prefix",
"VL256",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"MEM0:r:dq:f64",
"EMX_BROADCAST_2TO4_64"
]
},
{
"ICLASS": "VINSERTF128",
"EXCEPTIONS": "avx-type-6",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x18",
"norexw_prefix",
"VL256",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=XMM_B():r:dq:f64",
"IMM0:r:b",
"EMX_BROADCAST_2TO4_64"
]
},
{
"ICLASS": "VINSERTPS",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x21",
"VL128",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:f32",
"REG1=XMM_N():r:dq:f32",
"REG2=XMM_B():r:dq:f32",
"IMM0:r:b"
]
},
{
"ICLASS": "VLDDQU",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xF0",
"VL256",
"VF2",
"V0F",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq",
"MEM0:r:qq"
]
},
{
"ICLASS": "VMASKMOVPS",
"EXCEPTIONS": "avx-type-6",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"maskop",
"NONTEMPORAL"
],
"PATTERN": [
"VV1",
"0x2E",
"V66",
"V0F38",
"VL256",
"norexw_prefix",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"MEM0:w:qq:f32",
"REG0=YMM_N():r:qq",
"REG1=YMM_R():r:qq:f32"
]
},
{
"ICLASS": "VMASKMOVPD",
"EXCEPTIONS": "avx-type-6",
"CPL": "3",
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"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xF3",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u64",
"REG1=XMM_N():r:dq:u64",
"REG2=XMM_B():r:dq:u64"
]
},
{
"ICLASS": "VPSRLW",
"EXCEPTIONS": "avx-type-7",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xD1",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u16",
"REG1=XMM_N():r:dq:u16",
"REG2=XMM_B():r:dq:u64"
]
},
{
"ICLASS": "VPSRLD",
"EXCEPTIONS": "avx-type-7",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xD2",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u32",
"REG1=XMM_N():r:dq:u32",
"REG2=XMM_B():r:dq:u64"
]
},
{
"ICLASS": "VPSRLQ",
"EXCEPTIONS": "avx-type-7",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xD3",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u64",
"REG1=XMM_N():r:dq:u64",
"REG2=XMM_B():r:dq:u64"
]
},
{
"ICLASS": "VPSRAW",
"EXCEPTIONS": "avx-type-7",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xE1",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i16",
"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:u64"
]
},
{
"ICLASS": "VPSRAD",
"EXCEPTIONS": "avx-type-7",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xE2",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i32",
"REG1=XMM_N():r:dq:i32",
"REG2=XMM_B():r:dq:u64"
]
},
{
"ICLASS": "VPADDB",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xFC",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i8",
"REG1=XMM_N():r:dq:i8",
"REG2=XMM_B():r:dq:i8"
]
},
{
"ICLASS": "VPADDW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xFD",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i16",
"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
]
},
{
"ICLASS": "VPADDD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xFE",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i32",
"REG1=XMM_N():r:dq:i32",
"REG2=XMM_B():r:dq:i32"
]
},
{
"ICLASS": "VPADDQ",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xD4",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i64",
"REG1=XMM_N():r:dq:i64",
"REG2=XMM_B():r:dq:i64"
]
},
{
"ICLASS": "VPADDSB",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xEC",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i8",
"REG1=XMM_N():r:dq:i8",
"REG2=XMM_B():r:dq:i8"
]
},
{
"ICLASS": "VPADDSW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xED",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i16",
"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
]
},
{
"ICLASS": "VPADDUSB",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xDC",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u8",
"REG1=XMM_N():r:dq:u8",
"REG2=XMM_B():r:dq:u8"
]
},
{
"ICLASS": "VPADDUSW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xDD",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
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"OPERANDS": [
"REG0=XMM_R():w:dq:u16",
"REG1=XMM_N():r:dq:u16",
"REG2=XMM_B():r:dq:u16"
]
},
{
"ICLASS": "VPAVGB",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xE0",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u8",
"REG1=XMM_N():r:dq:u8",
"REG2=XMM_B():r:dq:u8"
]
},
{
"ICLASS": "VPAVGW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xE3",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u16",
"REG1=XMM_N():r:dq:u16",
"REG2=XMM_B():r:dq:u16"
]
},
{
"ICLASS": "VPCMPEQB",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x74",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u8",
"REG1=XMM_N():r:dq:u8",
"REG2=XMM_B():r:dq:u8"
]
},
{
"ICLASS": "VPCMPEQW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x75",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
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"OPERANDS": [
"REG0=XMM_R():w:dq:u16",
"REG1=XMM_N():r:dq:u16",
"REG2=XMM_B():r:dq:u16"
]
},
{
"ICLASS": "VPCMPEQD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x76",
"V66",
"V0F",
"VL128",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u32",
"REG1=XMM_N():r:dq:u32",
"REG2=XMM_B():r:dq:u32"
]
},
{
"ICLASS": "VPCMPEQQ",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x29",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
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"OPERANDS": [
"REG0=XMM_R():w:dq:u64",
"REG1=XMM_N():r:dq:u64",
"REG2=XMM_B():r:dq:u64"
]
},
{
"ICLASS": "VPCMPGTB",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x64",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i8",
"REG1=XMM_N():r:dq:i8",
"REG2=XMM_B():r:dq:i8"
]
},
{
"ICLASS": "VPCMPGTW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
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"0x65",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
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"OPERANDS": [
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"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
]
},
{
"ICLASS": "VPCMPGTD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x66",
"V66",
"V0F",
"VL128",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
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"OPERANDS": [
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"REG1=XMM_N():r:dq:i32",
"REG2=XMM_B():r:dq:i32"
]
},
{
"ICLASS": "VPCMPGTQ",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
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"0x37",
"V66",
"V0F38",
"VL128",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
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"REG1=XMM_N():r:dq:i64",
"REG2=XMM_B():r:dq:i64"
]
},
{
"ICLASS": "VPHADDW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
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"0x01",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
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"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
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"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
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{
"ICLASS": "VPHADDD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
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"0x02",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
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"REG1=XMM_N():r:dq:i32",
"REG2=XMM_B():r:dq:i32"
]
},
{
"ICLASS": "VPHADDSW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
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"0x03",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i16",
"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
]
},
{
"ICLASS": "VPHSUBW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x05",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i16",
"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
]
},
{
"ICLASS": "VPHSUBD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x06",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i32",
"REG1=XMM_N():r:dq:i32",
"REG2=XMM_B():r:dq:i32"
]
},
{
"ICLASS": "VPHSUBSW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x07",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i16",
"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
]
},
{
"ICLASS": "VPMULHUW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xE4",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u16",
"REG1=XMM_N():r:dq:u16",
"REG2=XMM_B():r:dq:u16"
]
},
{
"ICLASS": "VPMULHRSW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x0B",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i16",
"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
]
},
{
"ICLASS": "VPMULHW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xE5",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i16",
"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
]
},
{
"ICLASS": "VPMULLW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xD5",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i16",
"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
]
},
{
"ICLASS": "VPMULLD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x40",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
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"REG1=XMM_N():r:dq:i32",
"REG2=XMM_B():r:dq:i32"
]
},
{
"ICLASS": "VPMULUDQ",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xF4",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
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"REG1=XMM_N():r:dq:u32",
"REG2=XMM_B():r:dq:u32"
]
},
{
"ICLASS": "VPMULDQ",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
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"0x28",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
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"REG1=XMM_N():r:dq:i32",
"REG2=XMM_B():r:dq:i32"
]
},
{
"ICLASS": "VPSADBW",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xF6",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u16",
"REG1=XMM_N():r:dq:u8",
"REG2=XMM_B():r:dq:u8"
]
},
{
"ICLASS": "VPSHUFB",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x00",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u8",
"REG1=XMM_N():r:dq:u8",
"REG2=XMM_B():r:dq:u8"
]
},
{
"ICLASS": "VPSIGNB",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x08",
"VL128",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i8",
"REG1=XMM_N():r:dq:i8",
"REG2=XMM_B():r:dq:i8"
]
},
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"REG[rrr]",
"RM[nnn]"
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"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64"
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{
"ICLASS": "VUNPCKHPS",
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"0x15",
"VL256",
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"MOD[0b11]",
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"REG2=XMM_B():r:q:f64"
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{
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"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32"
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{
"ICLASS": "VMULSD",
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"REG2=XMM_B():r:q:f64"
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{
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{
"ICLASS": "VORPD",
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"VL256",
"V66",
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"REG1=YMM_N():r:qq:u64",
"REG2=YMM_B():r:qq:u64"
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{
"ICLASS": "VORPS",
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"VNP",
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"REG1=YMM_N():r:qq:u32",
"REG2=YMM_B():r:qq:u32"
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{
"ICLASS": "VPMAXSB",
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"VL128",
"V66",
"V0F38",
"MOD[0b11]",
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"REG[rrr]",
"RM[nnn]"
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"REG1=XMM_N():r:dq:i8",
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{
"ICLASS": "VPMAXSW",
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"0xEE",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
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"REG[rrr]",
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"REG1=XMM_N():r:dq:i16",
"REG2=XMM_B():r:dq:i16"
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{
"ICLASS": "VPMAXSD",
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"VL128",
"V66",
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"RM[nnn]"
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"REG1=XMM_N():r:dq:i32",
"REG2=XMM_B():r:dq:i32"
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{
"ICLASS": "VPMAXUB",
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"0xDE",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
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"REG[rrr]",
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"OPERANDS": [
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"REG1=XMM_N():r:dq:u8",
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{
"ICLASS": "VPMAXUW",
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"0x3E",
"VL128",
"V66",
"V0F38",
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"REG[rrr]",
"RM[nnn]"
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"REG2=XMM_B():r:dq:u16"
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{
"ICLASS": "VPMAXUD",
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"CPL": "3",
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"VL128",
"V66",
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{
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"VL128",
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{
"ICLASS": "VPMINSW",
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{
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"V66",
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{
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"V66",
"V0F38",
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"REG[rrr]",
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"REG1=XMM_N():r:dq:u32",
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{
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"0xF5",
"VL128",
"V66",
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{
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"REG2=XMM_B():r:dq:i8"
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{
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"VL128",
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"V0F3A",
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{
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"VL128",
"V66",
"V0F",
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"REG1=XMM_B():r:dq:u16",
"IMM0:r:b",
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"NDD"
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{
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"VL128",
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"V0F",
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"UIMM8()"
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"OPERANDS": [
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"REG1=XMM_B():r:dq:u32",
"IMM0:r:b",
"#NDD"
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{
"ICLASS": "VPSLLQ",
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"CPL": "3",
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"VL128",
"V66",
"V0F",
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"UIMM8()"
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"REG1=XMM_B():r:dq:u64",
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{
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"VL128",
"V66",
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"REG[0b100]",
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"REG1=XMM_B():r:dq:i16",
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{
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"IMM0:r:b",
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"NDD"
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{
"ICLASS": "VPSRLW",
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"VL128",
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"REG1=XMM_B():r:dq:u16",
"IMM0:r:b",
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{
"ICLASS": "VPSRLD",
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"VL128",
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"REG[0b010]",
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"REG1=XMM_B():r:dq:u32",
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{
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"0x73",
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{
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"CPL": "3",
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"EXTENSION": "AVX",
"ATTRIBUTES": [
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"values": [
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"name": "zf",
"operation": "mod"
},
{
"name": "pf",
"operation": "mod"
},
{
"name": "cf",
"operation": "mod"
},
{
"name": "of",
"operation": "0"
},
{
"name": "af",
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{
"name": "sf",
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"V66",
"V0F",
"NOVSR",
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{
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"EXTENSION": "AVX",
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"values": [
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"name": "zf",
"operation": "mod"
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{
"name": "pf",
"operation": "mod"
},
{
"name": "cf",
"operation": "mod"
},
{
"name": "of",
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},
{
"name": "af",
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{
"name": "sf",
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"VNP",
"V0F",
"NOVSR",
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"REG[rrr]",
"RM[nnn]"
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{
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"EXTENSION": "AVX",
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"VL256",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64"
]
},
{
"ICLASS": "VUNPCKLPS",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x14",
"VL256",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32"
]
},
{
"ICLASS": "VXORPD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x57",
"V66",
"V0F",
"VL256",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:u64",
"REG1=YMM_N():r:qq:u64",
"REG2=YMM_B():r:qq:u64"
]
},
{
"ICLASS": "VXORPS",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x57",
"VNP",
"V0F",
"VL256",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_R():w:qq",
"REG1=YMM_N():r:qq",
"REG2=YMM_B():r:qq"
]
},
{
"ICLASS": "VMOVSS",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar"
],
"PATTERN": [
"VV1",
"0x11",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_B():w:dq:f32",
"REG1=XMM_N():r:dq:f32",
"REG2=XMM_R():r:d:f32"
],
"IFORM": "VMOVSS_XMMdq_XMMdq_XMMd_11"
},
{
"ICLASS": "VMOVSD",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"simd_scalar"
],
"PATTERN": [
"VV1",
"0x11",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_B():w:dq:f64",
"REG1=XMM_N():r:dq:f64",
"REG2=XMM_R():r:q:f64"
],
"IFORM": "VMOVSD_XMMdq_XMMdq_XMMq_11"
},
{
"ICLASS": "VMOVUPD",
"EXCEPTIONS": "avx-type-4M",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x11",
"V66",
"VL256",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_B():w:qq:f64",
"REG1=YMM_R():r:qq:f64"
],
"IFORM": "VMOVUPD_YMMqq_YMMqq_11"
},
{
"ICLASS": "VMOVUPS",
"EXCEPTIONS": "avx-type-4M",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x11",
"VNP",
"VL256",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=YMM_B():w:qq:f32",
"REG1=YMM_R():r:qq:f32"
],
"IFORM": "VMOVUPS_YMMqq_YMMqq_11"
},
{
"ICLASS": "VMOVLPD",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"COMMENT": "3op version uses high part of XMM_N",
"PATTERN": [
"VV1",
"0x13",
"VL128",
"V66",
"V0F",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"MEM0:w:q:f64",
"REG0=XMM_R():r:q:f64"
]
},
{
"ICLASS": "VMOVLPS",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"COMMENT": "3op version uses high part of XMM_N",
"PATTERN": [
"VV1",
"0x13",
"VL128",
"VNP",
"V0F",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"MEM0:w:q:f32",
"REG0=XMM_R():r:q:f32"
]
},
{
"ICLASS": "VMOVHPD",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"COMMENT": "3op form use low bits of REG1, 2op form uses high bits of REG0",
"PATTERN": [
"VV1",
"0x17",
"VL128",
"V66",
"V0F",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"MEM0:w:q:f64",
"REG0=XMM_R():r:dq:f64"
]
},
{
"ICLASS": "VMOVHPS",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"COMMENT": "3op form use low bits of REG1, 2op form uses high bits of REG0",
"PATTERN": [
"VV1",
"0x17",
"VL128",
"VNP",
"V0F",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"MEM0:w:q:f32",
"REG0=XMM_R():r:dq:f32"
]
},
{
"ICLASS": "VMOVMSKPD",
"EXCEPTIONS": "avx-type-7",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x50",
"VL256",
"V66",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=GPR32_R():w:d",
"REG1=YMM_B():r:qq:f64"
]
},
{
"ICLASS": "VMOVMSKPS",
"EXCEPTIONS": "avx-type-7",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x50",
"VL256",
"VNP",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=GPR32_R():w:d",
"REG1=YMM_B():r:qq:f32"
]
},
{
"ICLASS": "VPMOVMSKB",
"EXCEPTIONS": "avx-type-7",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0xD7",
"VL128",
"V66",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=GPR32_R():w:d:u32",
"REG1=XMM_B():r:dq:i8"
]
},
{
"ICLASS": "VPMOVSXBW",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x20",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i16",
"MEM0:r:q:i8"
]
},
{
"ICLASS": "VPMOVSXBD",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x21",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i32",
"MEM0:r:d:i8"
]
},
{
"ICLASS": "VPMOVSXBQ",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x22",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i64",
"MEM0:r:w:i8"
]
},
{
"ICLASS": "VPMOVSXWD",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x23",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i32",
"MEM0:r:q:i16"
]
},
{
"ICLASS": "VPMOVSXWQ",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x24",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i64",
"MEM0:r:d:i16"
]
},
{
"ICLASS": "VPMOVSXDQ",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x25",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i64",
"MEM0:r:q:i32"
]
},
{
"ICLASS": "VPMOVZXBW",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x30",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u16",
"MEM0:r:q:u8"
]
},
{
"ICLASS": "VPMOVZXBD",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x31",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u32",
"MEM0:r:d:u8"
]
},
{
"ICLASS": "VPMOVZXBQ",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x32",
"V66",
"V0F38",
"VL128",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u64",
"MEM0:r:w:u8"
]
},
{
"ICLASS": "VPMOVZXWD",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x33",
"V66",
"V0F38",
"VL128",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u32",
"MEM0:r:q:u16"
]
},
{
"ICLASS": "VPMOVZXWQ",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x34",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u64",
"MEM0:r:d:u16"
]
},
{
"ICLASS": "VPMOVZXDQ",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x35",
"VL128",
"V66",
"V0F38",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u64",
"MEM0:r:q:u32"
]
},
{
"ICLASS": "VPEXTRB",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"COMMENT": "WIG",
"PATTERN": [
"VV1",
"0x14",
"VL128",
"V66",
"V0F3A",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=GPR32_B():w:d",
"REG1=XMM_R():r:dq:u8",
"IMM0:r:b"
]
},
{
"ICLASS": "VPEXTRW",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"COMMENT": "WIG",
"PATTERN": [
"VV1",
"0xC5",
"VL128",
"V66",
"V0F",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=GPR32_R():w:d",
"REG1=XMM_B():r:dq:u16",
"IMM0:r:b"
],
"IFORM": "VPEXTRW_GPR32d_XMMdq_IMMb_C5"
},
{
"ICLASS": "VPEXTRQ",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x16",
"VL128",
"V66",
"V0F3A",
"mode64",
"rexw_prefix",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=GPR64_B():w:q",
"REG1=XMM_R():r:dq:u64",
"IMM0:r:b"
]
},
{
"ICLASS": "VPEXTRD",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"COMMENT": "SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled.",
"PATTERN": [
"VV1",
"0x16",
"VL128",
"V66",
"V0F3A",
"not64",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=GPR32_B():w:d",
"REG1=XMM_R():r:dq:u32",
"IMM0:r:b"
]
},
{
"ICLASS": "VPINSRB",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"COMMENT": "WIG",
"PATTERN": [
"VV1",
"0x20",
"VL128",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u8",
"REG1=XMM_N():r:dq:u8",
"REG2=GPR32_B():r:d:u8",
"IMM0:r:b"
]
},
{
"ICLASS": "VPINSRW",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"COMMENT": "WIG",
"PATTERN": [
"VV1",
"0xC4",
"VL128",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u16",
"REG1=XMM_N():r:dq:u16",
"REG2=GPR32_B():r:d:u16",
"IMM0:r:b"
]
},
{
"ICLASS": "VPINSRD",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"COMMENT": "SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled",
"PATTERN": [
"VV1",
"0x22",
"VL128",
"V66",
"V0F3A",
"not64",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u32",
"REG1=XMM_N():r:dq:u32",
"REG2=GPR32_B():r:d:u32",
"IMM0:r:b"
]
},
{
"ICLASS": "VPINSRQ",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x22",
"VL128",
"V66",
"V0F3A",
"mode64",
"rexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u64",
"REG1=XMM_N():r:dq:u64",
"REG2=GPR64_B():r:q:u64",
"IMM0:r:b"
]
},
{
"ICLASS": "VPCMPESTRI",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "STTNI",
"EXTENSION": "AVX",
"FLAGS": {
"klass": "MUST",
"values": [
{
"name": "cf",
"operation": "mod"
},
{
"name": "zf",
"operation": "mod"
},
{
"name": "sf",
"operation": "mod"
},
{
"name": "of",
"operation": "mod"
},
{
"name": "af",
"operation": "0"
},
{
"name": "pf",
"operation": "0"
}
]
},
"PATTERN": [
"VV1",
"0x61",
"VL128",
"V66",
"V0F3A",
"NOVSR",
"mode64",
"W0",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():r:dq",
"REG1=XMM_B():r:dq",
"IMM0:r:b",
"REG2=XED_REG_EAX:r:SUPP",
"REG3=XED_REG_EDX:r:SUPP",
"REG4=XED_REG_ECX:w:SUPP"
]
},
{
"ICLASS": "VPCMPESTRI64",
"DISASM": "vpcmpestri",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "STTNI",
"EXTENSION": "AVX",
"FLAGS": {
"klass": "MUST",
"values": [
{
"name": "cf",
"operation": "mod"
},
{
"name": "zf",
"operation": "mod"
},
{
"name": "sf",
"operation": "mod"
},
{
"name": "of",
"operation": "mod"
},
{
"name": "af",
"operation": "0"
},
{
"name": "pf",
"operation": "0"
}
]
},
"PATTERN": [
"VV1",
"0x61",
"VL128",
"V66",
"V0F3A",
"NOVSR",
"mode64",
"W1",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():r:dq",
"REG1=XMM_B():r:dq",
"IMM0:r:b",
"REG2=XED_REG_RAX:r:SUPP",
"REG3=XED_REG_RDX:r:SUPP",
"REG4=XED_REG_RCX:w:SUPP"
]
},
{
"ICLASS": "VPCMPISTRI",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "STTNI",
"EXTENSION": "AVX",
"FLAGS": {
"klass": "MUST",
"values": [
{
"name": "cf",
"operation": "mod"
},
{
"name": "zf",
"operation": "mod"
},
{
"name": "sf",
"operation": "mod"
},
{
"name": "of",
"operation": "mod"
},
{
"name": "af",
"operation": "0"
},
{
"name": "pf",
"operation": "0"
}
]
},
"PATTERN": [
"VV1",
"0x63",
"VL128",
"V66",
"V0F3A",
"NOVSR",
"mode64",
"W0",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():r:dq",
"REG1=XMM_B():r:dq",
"IMM0:r:b",
"REG2=XED_REG_ECX:w:SUPP"
]
},
{
"ICLASS": "VPCMPISTRI64",
"DISASM": "vpcmpistri",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "STTNI",
"EXTENSION": "AVX",
"FLAGS": {
"klass": "MUST",
"values": [
{
"name": "cf",
"operation": "mod"
},
{
"name": "zf",
"operation": "mod"
},
{
"name": "sf",
"operation": "mod"
},
{
"name": "of",
"operation": "mod"
},
{
"name": "af",
"operation": "0"
},
{
"name": "pf",
"operation": "0"
}
]
},
"PATTERN": [
"VV1",
"0x63",
"VL128",
"V66",
"V0F3A",
"NOVSR",
"mode64",
"W1",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():r:dq",
"REG1=XMM_B():r:dq",
"IMM0:r:b",
"REG2=XED_REG_RCX:w:SUPP"
]
},
{
"ICLASS": "VPCMPESTRM",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "STTNI",
"EXTENSION": "AVX",
"FLAGS": {
"klass": "MUST",
"values": [
{
"name": "cf",
"operation": "mod"
},
{
"name": "zf",
"operation": "mod"
},
{
"name": "sf",
"operation": "mod"
},
{
"name": "of",
"operation": "mod"
},
{
"name": "af",
"operation": "0"
},
{
"name": "pf",
"operation": "0"
}
]
},
"PATTERN": [
"VV1",
"0x60",
"VL128",
"V66",
"V0F3A",
"NOVSR",
"mode64",
"W0",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():r:dq",
"REG1=XMM_B():r:dq",
"IMM0:r:b",
"REG2=XED_REG_EAX:r:SUPP",
"REG3=XED_REG_EDX:r:SUPP",
"REG4=XED_REG_XMM0:w:dq:SUPP"
]
},
{
"ICLASS": "VPCMPESTRM64",
"DISASM": "vpcmpestrm",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "STTNI",
"EXTENSION": "AVX",
"FLAGS": {
"klass": "MUST",
"values": [
{
"name": "cf",
"operation": "mod"
},
{
"name": "zf",
"operation": "mod"
},
{
"name": "sf",
"operation": "mod"
},
{
"name": "of",
"operation": "mod"
},
{
"name": "af",
"operation": "0"
},
{
"name": "pf",
"operation": "0"
}
]
},
"PATTERN": [
"VV1",
"0x60",
"VL128",
"V66",
"V0F3A",
"NOVSR",
"mode64",
"W1",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():r:dq",
"REG1=XMM_B():r:dq",
"IMM0:r:b",
"REG2=XED_REG_RAX:r:SUPP",
"REG3=XED_REG_RDX:r:SUPP",
"REG4=XED_REG_XMM0:w:dq:SUPP"
]
},
{
"ICLASS": "VPCMPISTRM",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "STTNI",
"EXTENSION": "AVX",
"FLAGS": {
"klass": "MUST",
"values": [
{
"name": "cf",
"operation": "mod"
},
{
"name": "zf",
"operation": "mod"
},
{
"name": "sf",
"operation": "mod"
},
{
"name": "of",
"operation": "mod"
},
{
"name": "af",
"operation": "0"
},
{
"name": "pf",
"operation": "0"
}
]
},
"PATTERN": [
"VV1",
"0x62",
"VL128",
"V66",
"V0F3A",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():r:dq",
"REG1=XMM_B():r:dq",
"IMM0:r:b",
"REG2=XED_REG_XMM0:w:dq:SUPP"
]
},
{
"ICLASS": "VMASKMOVDQU",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"maskop",
"fixed_base0",
"NOTSX",
"NONTEMPORAL"
],
"PATTERN": [
"VV1",
"0xF7",
"V0F",
"V66",
"VL128",
"NOVSR",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]"
],
"OPERANDS": [
"REG0=XMM_R():r:dq:u8",
"REG1=XMM_B():r:dq:u8",
"MEM0:w:SUPP:dq:u8",
"BASE0=ArDI():r:SUPP",
"SEG0=FINAL_DSEG():r:SUPP"
]
},
{
"ICLASS": "VLDMXCSR",
"EXCEPTIONS": "avx-type-5L",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR"
],
"PATTERN": [
"VV1",
"0xAE",
"VL128",
"VNP",
"V0F",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[0b010]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"MEM0:r:d",
"REG0=XED_REG_MXCSR:w:SUPP"
]
},
{
"ICLASS": "VSTMXCSR",
"EXCEPTIONS": "avx-type-5",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"MXCSR_RD"
],
"PATTERN": [
"VV1",
"0xAE",
"VL128",
"VNP",
"V0F",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[0b011]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"MEM0:w:d",
"REG0=XED_REG_MXCSR:r:SUPP"
]
},
{
"ICLASS": "VPBLENDVB",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x4C",
"VL128",
"V66",
"V0F3A",
"norexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"SE_IMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:i8",
"REG1=XMM_N():r:dq:i8",
"REG2=XMM_B():r:dq:i8",
"REG3=XMM_SE():r:dq:i8"
]
},
{
"ICLASS": "VBLENDVPD",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x4B",
"V66",
"V0F3A",
"VL256",
"norexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"SE_IMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f64",
"REG1=YMM_N():r:qq:f64",
"REG2=YMM_B():r:qq:f64",
"REG3=YMM_SE():r:qq:u64"
]
},
{
"ICLASS": "VBLENDVPS",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x4A",
"V66",
"V0F3A",
"VL256",
"norexw_prefix",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"SE_IMM8()"
],
"OPERANDS": [
"REG0=YMM_R():w:qq:f32",
"REG1=YMM_N():r:qq:f32",
"REG2=YMM_B():r:qq:f32",
"REG3=YMM_SE():r:qq:u32"
]
},
{
"ICLASS": "VMOVNTDQA",
"EXCEPTIONS": "avx-type-1",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"REQUIRES_ALIGNMENT",
"NOTSX",
"NONTEMPORAL"
],
"PATTERN": [
"VV1",
"0x2A",
"V66",
"V0F38",
"VL128",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq",
"MEM0:r:dq"
]
},
{
"ICLASS": "VMOVNTDQ",
"EXCEPTIONS": "avx-type-1",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"REQUIRES_ALIGNMENT",
"NOTSX",
"NONTEMPORAL"
],
"PATTERN": [
"VV1",
"0xE7",
"V66",
"V0F",
"VL128",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"MEM0:w:dq:i32",
"REG0=XMM_R():r:dq:i32"
]
},
{
"ICLASS": "VMOVNTPD",
"EXCEPTIONS": "avx-type-1",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"REQUIRES_ALIGNMENT",
"NOTSX",
"NONTEMPORAL"
],
"PATTERN": [
"VV1",
"0x2B",
"V66",
"V0F",
"VL128",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"MEM0:w:dq:f64",
"REG0=XMM_R():r:dq:f64"
]
},
{
"ICLASS": "VMOVNTPS",
"EXCEPTIONS": "avx-type-1",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX",
"ATTRIBUTES": [
"REQUIRES_ALIGNMENT",
"NOTSX",
"NONTEMPORAL"
],
"PATTERN": [
"VV1",
"0x2B",
"VNP",
"V0F",
"VL128",
"NOVSR",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()"
],
"OPERANDS": [
"MEM0:w:dq:f32",
"REG0=XMM_R():r:dq:f32"
]
},
{
"ICLASS": "VPCLMULQDQ",
"EXCEPTIONS": "avx-type-4",
"CPL": "3",
"CATEGORY": "AVX",
"EXTENSION": "AVX",
"PATTERN": [
"VV1",
"0x44",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R():w:dq:u128",
"REG1=XMM_N():r:dq:u64",
"MEM0:r:dq:u64",
"IMM0:r:b"
]
},
{
"ICLASS": "VPDPBUSD",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x50",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R():rw:dq:i32",
"REG1=XMM_N():r:dq:u32",
"REG2=XMM_B():r:dq:u32"
],
"IFORM": "VPDPBUSD_XMMi32_XMMu32_XMMu32"
},
{
"ICLASS": "VPDPBUSD",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x50",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R():rw:dq:i32",
"REG1=XMM_N():r:dq:u32",
"MEM0:r:dq:u32"
],
"IFORM": "VPDPBUSD_XMMi32_XMMu32_MEMu32"
},
{
"ICLASS": "VPDPBUSD",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x50",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R():rw:qq:i32",
"REG1=YMM_N():r:qq:u32",
"REG2=YMM_B():r:qq:u32"
],
"IFORM": "VPDPBUSD_YMMi32_YMMu32_YMMu32"
},
{
"ICLASS": "VPDPBUSD",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x50",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R():rw:qq:i32",
"REG1=YMM_N():r:qq:u32",
"MEM0:r:qq:u32"
],
"IFORM": "VPDPBUSD_YMMi32_YMMu32_MEMu32"
},
{
"ICLASS": "VPDPBUSDS",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x51",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R():rw:dq:i32",
"REG1=XMM_N():r:dq:u32",
"REG2=XMM_B():r:dq:u32"
],
"IFORM": "VPDPBUSDS_XMMi32_XMMu32_XMMu32"
},
{
"ICLASS": "VPDPBUSDS",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x51",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R():rw:dq:i32",
"REG1=XMM_N():r:dq:u32",
"MEM0:r:dq:u32"
],
"IFORM": "VPDPBUSDS_XMMi32_XMMu32_MEMu32"
},
{
"ICLASS": "VPDPBUSDS",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x51",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R():rw:qq:i32",
"REG1=YMM_N():r:qq:u32",
"REG2=YMM_B():r:qq:u32"
],
"IFORM": "VPDPBUSDS_YMMi32_YMMu32_YMMu32"
},
{
"ICLASS": "VPDPBUSDS",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x51",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R():rw:qq:i32",
"REG1=YMM_N():r:qq:u32",
"MEM0:r:qq:u32"
],
"IFORM": "VPDPBUSDS_YMMi32_YMMu32_MEMu32"
},
{
"ICLASS": "VPDPWSSD",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x52",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R():rw:dq:i32",
"REG1=XMM_N():r:dq:u32",
"REG2=XMM_B():r:dq:u32"
],
"IFORM": "VPDPWSSD_XMMi32_XMMu32_XMMu32"
},
{
"ICLASS": "VPDPWSSD",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x52",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R():rw:dq:i32",
"REG1=XMM_N():r:dq:u32",
"MEM0:r:dq:u32"
],
"IFORM": "VPDPWSSD_XMMi32_XMMu32_MEMu32"
},
{
"ICLASS": "VPDPWSSD",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x52",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R():rw:qq:i32",
"REG1=YMM_N():r:qq:u32",
"REG2=YMM_B():r:qq:u32"
],
"IFORM": "VPDPWSSD_YMMi32_YMMu32_YMMu32"
},
{
"ICLASS": "VPDPWSSD",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x52",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R():rw:qq:i32",
"REG1=YMM_N():r:qq:u32",
"MEM0:r:qq:u32"
],
"IFORM": "VPDPWSSD_YMMi32_YMMu32_MEMu32"
},
{
"ICLASS": "VPDPWSSDS",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x53",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R():rw:dq:i32",
"REG1=XMM_N():r:dq:u32",
"REG2=XMM_B():r:dq:u32"
],
"IFORM": "VPDPWSSDS_XMMi32_XMMu32_XMMu32"
},
{
"ICLASS": "VPDPWSSDS",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x53",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R():rw:dq:i32",
"REG1=XMM_N():r:dq:u32",
"MEM0:r:dq:u32"
],
"IFORM": "VPDPWSSDS_XMMi32_XMMu32_MEMu32"
},
{
"ICLASS": "VPDPWSSDS",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x53",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R():rw:qq:i32",
"REG1=YMM_N():r:qq:u32",
"REG2=YMM_B():r:qq:u32"
],
"IFORM": "VPDPWSSDS_YMMi32_YMMu32_YMMu32"
},
{
"ICLASS": "VPDPWSSDS",
"CPL": "3",
"CATEGORY": "VEX",
"EXTENSION": "AVX_VNNI",
"ISA_SET": "AVX_VNNI",
"EXCEPTIONS": "avx-type-4",
"REAL_OPCODE": "Y",
"PATTERN": [
"VV1",
"0x53",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R():rw:qq:i32",
"REG1=YMM_N():r:qq:u32",
"MEM0:r:qq:u32"
],
"IFORM": "VPDPWSSDS_YMMi32_YMMu32_MEMu32"
},
{
"ICLASS": "VCVTNE2PS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x72",
"VF2",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:bf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VCVTNE2PS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x72",
"VF2",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:bf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128"
},
{
"ICLASS": "VCVTNE2PS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x72",
"VF2",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:bf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VCVTNE2PS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x72",
"VF2",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:bf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256"
},
{
"ICLASS": "VCVTNE2PS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x72",
"VF2",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zbf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zf32",
"REG3=ZMM_B3():r:zf32"
],
"IFORM": "VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512"
},
{
"ICLASS": "VCVTNE2PS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x72",
"VF2",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zbf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zf32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512"
},
{
"ICLASS": "VCVTNEPS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x72",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:bf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTNEPS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x72",
"VF3",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:bf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128"
},
{
"ICLASS": "VCVTNEPS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x72",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:bf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTNEPS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x72",
"VF3",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:bf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256"
},
{
"ICLASS": "VCVTNEPS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x72",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:bf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf32"
],
"IFORM": "VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512"
},
{
"ICLASS": "VCVTNEPS2BF16",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x72",
"VF3",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:bf16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512"
},
{
"ICLASS": "VDPBF16PS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x52",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"REG3=XMM_B3():r:dq:u32"
],
"IFORM": "VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512"
},
{
"ICLASS": "VDPBF16PS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x52",
"VF3",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VDPBF16PS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x52",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=YMM_B3():r:qq:u32"
],
"IFORM": "VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512"
},
{
"ICLASS": "VDPBF16PS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x52",
"VF3",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VDPBF16PS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x52",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0"
],
"OPERANDS": [
"REG0=ZMM_R3():rw:zf32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"REG3=ZMM_B3():r:zu32"
],
"IFORM": "VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512"
},
{
"ICLASS": "VDPBF16PS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512_BF16_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x52",
"VF3",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():rw:zf32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VADDPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x58",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VADDPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x58",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VADDPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x58",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VADDPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x58",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VADDPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x58",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VADDPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x58",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VADDPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x58",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VADDPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x58",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VALIGND",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x03",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"REG3=XMM_B3():r:dq:u32",
"IMM0:r:b"
],
"IFORM": "VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512"
},
{
"ICLASS": "VALIGND",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x03",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512"
},
{
"ICLASS": "VALIGND",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x03",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=YMM_B3():r:qq:u32",
"IMM0:r:b"
],
"IFORM": "VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512"
},
{
"ICLASS": "VALIGND",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x03",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512"
},
{
"ICLASS": "VALIGNQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x03",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"REG3=XMM_B3():r:dq:u64",
"IMM0:r:b"
],
"IFORM": "VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512"
},
{
"ICLASS": "VALIGNQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x03",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512"
},
{
"ICLASS": "VALIGNQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x03",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"REG3=YMM_B3():r:qq:u64",
"IMM0:r:b"
],
"IFORM": "VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512"
},
{
"ICLASS": "VALIGNQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x03",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512"
},
{
"ICLASS": "VANDNPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x55",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"REG3=XMM_B3():r:dq:u64"
],
"IFORM": "VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"
},
{
"ICLASS": "VANDNPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x55",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VANDNPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x55",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"REG3=YMM_B3():r:qq:u64"
],
"IFORM": "VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"
},
{
"ICLASS": "VANDNPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x55",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VANDNPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x55",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu64",
"REG3=ZMM_B3():r:zu64"
],
"IFORM": "VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"
},
{
"ICLASS": "VANDNPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x55",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VANDNPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x55",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"REG3=XMM_B3():r:dq:u32"
],
"IFORM": "VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"
},
{
"ICLASS": "VANDNPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x55",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VANDNPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x55",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=YMM_B3():r:qq:u32"
],
"IFORM": "VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"
},
{
"ICLASS": "VANDNPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x55",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VANDNPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x55",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"REG3=ZMM_B3():r:zu32"
],
"IFORM": "VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"
},
{
"ICLASS": "VANDNPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x55",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VANDPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"REG3=XMM_B3():r:dq:u64"
],
"IFORM": "VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"
},
{
"ICLASS": "VANDPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VANDPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"REG3=YMM_B3():r:qq:u64"
],
"IFORM": "VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"
},
{
"ICLASS": "VANDPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VANDPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu64",
"REG3=ZMM_B3():r:zu64"
],
"IFORM": "VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"
},
{
"ICLASS": "VANDPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VANDPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x54",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"REG3=XMM_B3():r:dq:u32"
],
"IFORM": "VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"
},
{
"ICLASS": "VANDPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x54",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VANDPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x54",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=YMM_B3():r:qq:u32"
],
"IFORM": "VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"
},
{
"ICLASS": "VANDPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x54",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VANDPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x54",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"REG3=ZMM_B3():r:zu32"
],
"IFORM": "VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"
},
{
"ICLASS": "VANDPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x54",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VBLENDMPD",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x65",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VBLENDMPD",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x65",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VBLENDMPD",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x65",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VBLENDMPD",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x65",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VBLENDMPS",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x65",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VBLENDMPS",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x65",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VBLENDMPS",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x65",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VBLENDMPS",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x65",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VBROADCASTF32X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32",
"EMX_BROADCAST_2TO8_32"
],
"IFORM": "VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VBROADCASTF32X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:q:f32",
"EMX_BROADCAST_2TO8_32"
],
"IFORM": "VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VBROADCASTF32X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32",
"EMX_BROADCAST_2TO16_32"
],
"IFORM": "VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VBROADCASTF32X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:q:f32",
"EMX_BROADCAST_2TO16_32"
],
"IFORM": "VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VBROADCASTF32X4",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE4"
],
"PATTERN": [
"EVV",
"0x1A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE4()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f32",
"EMX_BROADCAST_4TO8_32"
],
"IFORM": "VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VBROADCASTF32X8",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE8"
],
"PATTERN": [
"EVV",
"0x1B",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE8()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:f32",
"EMX_BROADCAST_8TO16_32"
],
"IFORM": "VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VBROADCASTF64X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x1A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f64",
"EMX_BROADCAST_2TO4_64"
],
"IFORM": "VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VBROADCASTF64X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x1A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f64",
"EMX_BROADCAST_2TO8_64"
],
"IFORM": "VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VBROADCASTI32X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u32",
"EMX_BROADCAST_2TO4_32"
],
"IFORM": "VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VBROADCASTI32X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:q:u32",
"EMX_BROADCAST_2TO4_32"
],
"IFORM": "VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VBROADCASTI32X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u32",
"EMX_BROADCAST_2TO8_32"
],
"IFORM": "VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VBROADCASTI32X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:q:u32",
"EMX_BROADCAST_2TO8_32"
],
"IFORM": "VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VBROADCASTI32X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u32",
"EMX_BROADCAST_2TO16_32"
],
"IFORM": "VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VBROADCASTI32X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:q:u32",
"EMX_BROADCAST_2TO16_32"
],
"IFORM": "VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VBROADCASTI32X4",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE4"
],
"PATTERN": [
"EVV",
"0x5A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE4()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:u32",
"EMX_BROADCAST_4TO8_32"
],
"IFORM": "VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VBROADCASTI32X8",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE8"
],
"PATTERN": [
"EVV",
"0x5B",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE8()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:u32",
"EMX_BROADCAST_8TO16_32"
],
"IFORM": "VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VBROADCASTI64X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x5A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:u64",
"EMX_BROADCAST_2TO4_64"
],
"IFORM": "VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VBROADCASTI64X2",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x5A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:u64",
"EMX_BROADCAST_2TO8_64"
],
"IFORM": "VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VBROADCASTSD",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_TUPLE1()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:q:f64",
"EMX_BROADCAST_1TO4_64"
],
"IFORM": "VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VBROADCASTSD",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64",
"EMX_BROADCAST_1TO4_64"
],
"IFORM": "VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VBROADCASTSS",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1"
],
"PATTERN": [
"EVV",
"0x18",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE1()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:d:f32",
"EMX_BROADCAST_1TO4_32"
],
"IFORM": "VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VBROADCASTSS",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x18",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32",
"EMX_BROADCAST_1TO4_32"
],
"IFORM": "VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VBROADCASTSS",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1"
],
"PATTERN": [
"EVV",
"0x18",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE1()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:d:f32",
"EMX_BROADCAST_1TO8_32"
],
"IFORM": "VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VBROADCASTSS",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x18",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32",
"EMX_BROADCAST_1TO8_32"
],
"IFORM": "VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCMPPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xC2",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64",
"IMM0:r:b"
],
"IFORM": "VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"
},
{
"ICLASS": "VCMPPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xC2",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ZEROING=0",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512"
},
{
"ICLASS": "VCMPPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xC2",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64",
"IMM0:r:b"
],
"IFORM": "VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"
},
{
"ICLASS": "VCMPPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xC2",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ZEROING=0",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512"
},
{
"ICLASS": "VCMPPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xC2",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32",
"IMM0:r:b"
],
"IFORM": "VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"
},
{
"ICLASS": "VCMPPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xC2",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ZEROING=0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512"
},
{
"ICLASS": "VCMPPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xC2",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32",
"IMM0:r:b"
],
"IFORM": "VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"
},
{
"ICLASS": "VCMPPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xC2",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ZEROING=0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512"
},
{
"ICLASS": "VCOMPRESSPD",
"CPL": "3",
"CATEGORY": "COMPRESS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_GSCAT",
"MASK_VARIABLE_MEMOP"
],
"PATTERN": [
"EVV",
"0x8A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"MEM0:w:dq:f64",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:f64"
],
"IFORM": "VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VCOMPRESSPD",
"CPL": "3",
"CATEGORY": "COMPRESS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x8A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:f64"
],
"IFORM": "VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VCOMPRESSPD",
"CPL": "3",
"CATEGORY": "COMPRESS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_GSCAT",
"MASK_VARIABLE_MEMOP"
],
"PATTERN": [
"EVV",
"0x8A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"MEM0:w:qq:f64",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:f64"
],
"IFORM": "VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VCOMPRESSPD",
"CPL": "3",
"CATEGORY": "COMPRESS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x8A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:f64"
],
"IFORM": "VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VCOMPRESSPS",
"CPL": "3",
"CATEGORY": "COMPRESS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_GSCAT",
"MASK_VARIABLE_MEMOP"
],
"PATTERN": [
"EVV",
"0x8A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"MEM0:w:dq:f32",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:f32"
],
"IFORM": "VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCOMPRESSPS",
"CPL": "3",
"CATEGORY": "COMPRESS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x8A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:f32"
],
"IFORM": "VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCOMPRESSPS",
"CPL": "3",
"CATEGORY": "COMPRESS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_GSCAT",
"MASK_VARIABLE_MEMOP"
],
"PATTERN": [
"EVV",
"0x8A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"MEM0:w:qq:f32",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:f32"
],
"IFORM": "VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCOMPRESSPS",
"CPL": "3",
"CATEGORY": "COMPRESS",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x8A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:f32"
],
"IFORM": "VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTDQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E5",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:i32"
],
"IFORM": "VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512"
},
{
"ICLASS": "VCVTDQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E5",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:i32:TXT=BCASTSTR"
],
"IFORM": "VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512"
},
{
"ICLASS": "VCVTDQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E5",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:i32"
],
"IFORM": "VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512"
},
{
"ICLASS": "VCVTDQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E5",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:i32:TXT=BCASTSTR"
],
"IFORM": "VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512"
},
{
"ICLASS": "VCVTDQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:i32"
],
"IFORM": "VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512"
},
{
"ICLASS": "VCVTDQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:i32:TXT=BCASTSTR"
],
"IFORM": "VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512"
},
{
"ICLASS": "VCVTDQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:i32"
],
"IFORM": "VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512"
},
{
"ICLASS": "VCVTDQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:i32:TXT=BCASTSTR"
],
"IFORM": "VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512"
},
{
"ICLASS": "VCVTPD2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xE6",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128"
},
{
"ICLASS": "VCVTPD2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xE6",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128"
},
{
"ICLASS": "VCVTPD2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xE6",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256"
},
{
"ICLASS": "VCVTPD2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xE6",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256"
},
{
"ICLASS": "VCVTPD2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5A",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128"
},
{
"ICLASS": "VCVTPD2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5A",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128"
},
{
"ICLASS": "VCVTPD2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5A",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256"
},
{
"ICLASS": "VCVTPD2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5A",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256"
},
{
"ICLASS": "VCVTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VCVTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VCVTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf64"
],
"IFORM": "VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"
},
{
"ICLASS": "VCVTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"FIX_ROUND_LEN512()",
"AVX512_ROUND()",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64:TXT=ROUNDC",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf64"
],
"IFORM": "VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"
},
{
"ICLASS": "VCVTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTPD2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128"
},
{
"ICLASS": "VCVTPD2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x79",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128"
},
{
"ICLASS": "VCVTPD2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256"
},
{
"ICLASS": "VCVTPD2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x79",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256"
},
{
"ICLASS": "VCVTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VCVTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VCVTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf64"
],
"IFORM": "VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"
},
{
"ICLASS": "VCVTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"FIX_ROUND_LEN512()",
"AVX512_ROUND()",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64:TXT=ROUNDC",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf64"
],
"IFORM": "VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"
},
{
"ICLASS": "VCVTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTPH2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E11",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x13",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f16"
],
"IFORM": "VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512"
},
{
"ICLASS": "VCVTPH2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E11",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"MXCSR",
"DISP8_HALFMEM"
],
"PATTERN": [
"EVV",
"0x13",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_HALFMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:q:f16"
],
"IFORM": "VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512"
},
{
"ICLASS": "VCVTPH2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E11",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x13",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f16"
],
"IFORM": "VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512"
},
{
"ICLASS": "VCVTPH2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E11",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"MXCSR",
"DISP8_HALFMEM"
],
"PATTERN": [
"EVV",
"0x13",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_HALFMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f16"
],
"IFORM": "VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512"
},
{
"ICLASS": "VCVTPS2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5A",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5A",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5A",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5A",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2PH",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E11",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x1D",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:f32",
"IMM0:r:b"
],
"IFORM": "VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512"
},
{
"ICLASS": "VCVTPS2PH",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E11",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"MXCSR",
"DISP8_HALFMEM"
],
"PATTERN": [
"EVV",
"0x1D",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_16_BITS()",
"NELEM_HALFMEM()"
],
"OPERANDS": [
"MEM0:w:q:f16",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:f32",
"IMM0:r:b"
],
"IFORM": "VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512"
},
{
"ICLASS": "VCVTPS2PH",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E11",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x1D",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:f32",
"IMM0:r:b"
],
"IFORM": "VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512"
},
{
"ICLASS": "VCVTPS2PH",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E11",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"MXCSR",
"DISP8_HALFMEM"
],
"PATTERN": [
"EVV",
"0x1D",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_16_BITS()",
"NELEM_HALFMEM()"
],
"OPERANDS": [
"MEM0:w:dq:f16",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:f32",
"IMM0:r:b"
],
"IFORM": "VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512"
},
{
"ICLASS": "VCVTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"FIX_ROUND_LEN512()",
"AVX512_ROUND()",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64:TXT=ROUNDC",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x79",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x79",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"FIX_ROUND_LEN512()",
"AVX512_ROUND()",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64:TXT=ROUNDC",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VCVTQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VCVTQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf64"
],
"IFORM": "VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512"
},
{
"ICLASS": "VCVTQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"W1",
"NOEVSR",
"FIX_ROUND_LEN512()",
"AVX512_ROUND()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64:TXT=ROUNDC",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf64"
],
"IFORM": "VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512"
},
{
"ICLASS": "VCVTQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xE6",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u64"
],
"IFORM": "VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128"
},
{
"ICLASS": "VCVTQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128"
},
{
"ICLASS": "VCVTQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:u64"
],
"IFORM": "VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256"
},
{
"ICLASS": "VCVTQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256"
},
{
"ICLASS": "VCVTQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zu64"
],
"IFORM": "VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"
},
{
"ICLASS": "VCVTQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"FIX_ROUND_LEN512()",
"AVX512_ROUND()",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32:TXT=ROUNDC",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zu64"
],
"IFORM": "VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"
},
{
"ICLASS": "VCVTQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5B",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512"
},
{
"ICLASS": "VCVTTPD2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xE6",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128"
},
{
"ICLASS": "VCVTTPD2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xE6",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128"
},
{
"ICLASS": "VCVTTPD2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xE6",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256"
},
{
"ICLASS": "VCVTTPD2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xE6",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256"
},
{
"ICLASS": "VCVTTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf64"
],
"IFORM": "VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"FIX_ROUND_LEN512()",
"SAE()",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64:TXT=SAESTR",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf64"
],
"IFORM": "VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128"
},
{
"ICLASS": "VCVTTPD2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x78",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128"
},
{
"ICLASS": "VCVTTPD2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256"
},
{
"ICLASS": "VCVTTPD2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x78",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256"
},
{
"ICLASS": "VCVTTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf64"
],
"IFORM": "VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"FIX_ROUND_LEN512()",
"SAE()",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64:TXT=SAESTR",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zf64"
],
"IFORM": "VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512"
},
{
"ICLASS": "VCVTTPD2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VCVTTPS2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5B",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5B",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5B",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2DQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5B",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"FIX_ROUND_LEN512()",
"SAE()",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64:TXT=SAESTR",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2QQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x78",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UDQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x78",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"FIX_ROUND_LEN512()",
"SAE()",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64:TXT=SAESTR",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VCVTTPS2UQQ",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E3",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VCVTUDQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E5",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u32"
],
"IFORM": "VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VCVTUDQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E5",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VCVTUDQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E5",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u32"
],
"IFORM": "VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VCVTUDQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E5",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_HALF",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_HALF()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VCVTUDQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u32"
],
"IFORM": "VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VCVTUDQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VCVTUDQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:u32"
],
"IFORM": "VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512"
},
{
"ICLASS": "VCVTUDQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VCVTUQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u64"
],
"IFORM": "VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512"
},
{
"ICLASS": "VCVTUQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VCVTUQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:u64"
],
"IFORM": "VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512"
},
{
"ICLASS": "VCVTUQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VCVTUQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zu64"
],
"IFORM": "VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512"
},
{
"ICLASS": "VCVTUQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"W1",
"NOEVSR",
"FIX_ROUND_LEN512()",
"AVX512_ROUND()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf64:TXT=ROUNDC",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zu64"
],
"IFORM": "VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512"
},
{
"ICLASS": "VCVTUQQ2PD",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VCVTUQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u64"
],
"IFORM": "VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128"
},
{
"ICLASS": "VCVTUQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128"
},
{
"ICLASS": "VCVTUQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:u64"
],
"IFORM": "VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256"
},
{
"ICLASS": "VCVTUQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256"
},
{
"ICLASS": "VCVTUQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zu64"
],
"IFORM": "VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"
},
{
"ICLASS": "VCVTUQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=1",
"REG[rrr]",
"RM[nnn]",
"FIX_ROUND_LEN512()",
"AVX512_ROUND()",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32:TXT=ROUNDC",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zu64"
],
"IFORM": "VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512"
},
{
"ICLASS": "VCVTUQQ2PS",
"CPL": "3",
"CATEGORY": "CONVERT",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x7A",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512"
},
{
"ICLASS": "VDBPSADBW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"REG3=XMM_B3():r:dq:u8",
"IMM0:r:b"
],
"IFORM": "VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"
},
{
"ICLASS": "VDBPSADBW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"UIMM8()",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"MEM0:r:dq:u8",
"IMM0:r:b"
],
"IFORM": "VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512"
},
{
"ICLASS": "VDBPSADBW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"REG3=YMM_B3():r:qq:u8",
"IMM0:r:b"
],
"IFORM": "VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"
},
{
"ICLASS": "VDBPSADBW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"UIMM8()",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"MEM0:r:qq:u8",
"IMM0:r:b"
],
"IFORM": "VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512"
},
{
"ICLASS": "VDBPSADBW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"REG3=ZMM_B3():r:zu8",
"IMM0:r:b"
],
"IFORM": "VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"
},
{
"ICLASS": "VDBPSADBW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"UIMM8()",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"MEM0:r:zd:u8",
"IMM0:r:b"
],
"IFORM": "VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512"
},
{
"ICLASS": "VDIVPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5E",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VDIVPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5E",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VDIVPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5E",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VDIVPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5E",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VDIVPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5E",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VDIVPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5E",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VDIVPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5E",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VDIVPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5E",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VEXPANDPD",
"CPL": "3",
"CATEGORY": "EXPAND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_GSCAT",
"MASK_VARIABLE_MEMOP"
],
"PATTERN": [
"EVV",
"0x88",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f64"
],
"IFORM": "VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VEXPANDPD",
"CPL": "3",
"CATEGORY": "EXPAND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x88",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VEXPANDPD",
"CPL": "3",
"CATEGORY": "EXPAND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_GSCAT",
"MASK_VARIABLE_MEMOP"
],
"PATTERN": [
"EVV",
"0x88",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:f64"
],
"IFORM": "VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VEXPANDPD",
"CPL": "3",
"CATEGORY": "EXPAND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x88",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VEXPANDPS",
"CPL": "3",
"CATEGORY": "EXPAND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_GSCAT",
"MASK_VARIABLE_MEMOP"
],
"PATTERN": [
"EVV",
"0x88",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f32"
],
"IFORM": "VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VEXPANDPS",
"CPL": "3",
"CATEGORY": "EXPAND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x88",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VEXPANDPS",
"CPL": "3",
"CATEGORY": "EXPAND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_GSCAT",
"MASK_VARIABLE_MEMOP"
],
"PATTERN": [
"EVV",
"0x88",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:f32"
],
"IFORM": "VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VEXPANDPS",
"CPL": "3",
"CATEGORY": "EXPAND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x88",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VEXTRACTF32X4",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:f32",
"IMM0:r:b"
],
"IFORM": "VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTF32X4",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE4"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_TUPLE4()"
],
"OPERANDS": [
"MEM0:w:dq:f32",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:f32",
"IMM0:r:b"
],
"IFORM": "VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTF32X8",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1B",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_R3():r:zf32",
"IMM0:r:b"
],
"IFORM": "VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTF32X8",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE8"
],
"PATTERN": [
"EVV",
"0x1B",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_TUPLE8()"
],
"OPERANDS": [
"MEM0:w:qq:f32",
"REG0=MASK1():r:mskw",
"REG1=ZMM_R3():r:zf32",
"IMM0:r:b"
],
"IFORM": "VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTF64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:f64",
"IMM0:r:b"
],
"IFORM": "VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTF64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"MEM0:w:dq:f64",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:f64",
"IMM0:r:b"
],
"IFORM": "VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTF64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_R3():r:zf64",
"IMM0:r:b"
],
"IFORM": "VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTF64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x19",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"MEM0:w:dq:f64",
"REG0=MASK1():r:mskw",
"REG1=ZMM_R3():r:zf64",
"IMM0:r:b"
],
"IFORM": "VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTI32X4",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x39",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:u32",
"IMM0:r:b"
],
"IFORM": "VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTI32X4",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE4"
],
"PATTERN": [
"EVV",
"0x39",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_TUPLE4()"
],
"OPERANDS": [
"MEM0:w:dq:u32",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:u32",
"IMM0:r:b"
],
"IFORM": "VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTI32X8",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x3B",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_R3():r:zu32",
"IMM0:r:b"
],
"IFORM": "VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTI32X8",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE8"
],
"PATTERN": [
"EVV",
"0x3B",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_TUPLE8()"
],
"OPERANDS": [
"MEM0:w:qq:u32",
"REG0=MASK1():r:mskw",
"REG1=ZMM_R3():r:zu32",
"IMM0:r:b"
],
"IFORM": "VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTI64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x39",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:u64",
"IMM0:r:b"
],
"IFORM": "VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTI64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x39",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"MEM0:w:dq:u64",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:u64",
"IMM0:r:b"
],
"IFORM": "VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTI64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x39",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_R3():r:zu64",
"IMM0:r:b"
],
"IFORM": "VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512"
},
{
"ICLASS": "VEXTRACTI64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x39",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"MEM0:w:dq:u64",
"REG0=MASK1():r:mskw",
"REG1=ZMM_R3():r:zu64",
"IMM0:r:b"
],
"IFORM": "VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512"
},
{
"ICLASS": "VFIXUPIMMPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64",
"IMM0:r:b"
],
"IFORM": "VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512"
},
{
"ICLASS": "VFIXUPIMMPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512"
},
{
"ICLASS": "VFIXUPIMMPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64",
"IMM0:r:b"
],
"IFORM": "VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512"
},
{
"ICLASS": "VFIXUPIMMPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512"
},
{
"ICLASS": "VFIXUPIMMPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32",
"IMM0:r:b"
],
"IFORM": "VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512"
},
{
"ICLASS": "VFIXUPIMMPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512"
},
{
"ICLASS": "VFIXUPIMMPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32",
"IMM0:r:b"
],
"IFORM": "VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512"
},
{
"ICLASS": "VFIXUPIMMPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x54",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512"
},
{
"ICLASS": "VFMADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x98",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x98",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x98",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x98",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x98",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x98",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x98",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x98",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA8",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA8",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA8",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA8",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA8",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA8",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA8",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA8",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB8",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB8",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB8",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB8",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB8",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB8",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB8",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB8",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x96",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x96",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x96",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x96",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x96",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x96",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x96",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x96",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA6",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA6",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA6",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA6",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA6",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA6",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA6",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA6",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB6",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB6",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB6",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB6",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMADDSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB6",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB6",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB6",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMADDSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB6",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAA",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAA",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAA",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAA",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAA",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAA",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAA",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAA",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBA",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBA",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBA",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBA",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBA",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBA",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBA",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBA",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x97",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x97",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x97",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x97",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x97",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x97",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x97",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x97",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA7",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA7",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA7",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA7",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA7",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA7",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xA7",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xA7",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB7",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB7",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB7",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB7",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFMSUBADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB7",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB7",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xB7",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFMSUBADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xB7",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFNMADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9C",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFNMADD132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9C",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFNMADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9C",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFNMADD132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9C",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAC",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFNMADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAC",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAC",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFNMADD213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAC",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAC",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFNMADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAC",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAC",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFNMADD213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAC",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBC",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFNMADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBC",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBC",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFNMADD231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBC",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBC",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFNMADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBC",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBC",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFNMADD231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBC",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9E",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFNMSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9E",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9E",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFNMSUB132PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9E",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9E",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFNMSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9E",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x9E",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFNMSUB132PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x9E",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAE",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFNMSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAE",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAE",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFNMSUB213PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAE",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAE",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFNMSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAE",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xAE",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFNMSUB213PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xAE",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBE",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VFNMSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBE",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBE",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VFNMSUB231PD",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBE",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VFNMSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBE",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VFNMSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBE",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():rw:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFNMSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0xBE",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VFNMSUB231PS",
"CPL": "3",
"CATEGORY": "VFMA",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xBE",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():rw:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VFPCLASSPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=XMM_B3():r:dq:f64",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512"
},
{
"ICLASS": "VFPCLASSPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"MEM0:r:vv:f64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128"
},
{
"ICLASS": "VFPCLASSPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=YMM_B3():r:qq:f64",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512"
},
{
"ICLASS": "VFPCLASSPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"MEM0:r:vv:f64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256"
},
{
"ICLASS": "VFPCLASSPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=ZMM_B3():r:zf64",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512"
},
{
"ICLASS": "VFPCLASSPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"MEM0:r:vv:f64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512"
},
{
"ICLASS": "VFPCLASSPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=XMM_B3():r:dq:f32",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512"
},
{
"ICLASS": "VFPCLASSPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"MEM0:r:vv:f32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128"
},
{
"ICLASS": "VFPCLASSPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=YMM_B3():r:qq:f32",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512"
},
{
"ICLASS": "VFPCLASSPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"MEM0:r:vv:f32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256"
},
{
"ICLASS": "VFPCLASSPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=ZMM_B3():r:zf32",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512"
},
{
"ICLASS": "VFPCLASSPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"MEM0:r:vv:f32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512"
},
{
"ICLASS": "VFPCLASSSD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_SCALAR",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR",
"SIMD_SCALAR"
],
"PATTERN": [
"EVV",
"0x67",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=XMM_B3():r:dq:f64",
"IMM0:r:b"
],
"IFORM": "VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512"
},
{
"ICLASS": "VFPCLASSSD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_SCALAR",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"MXCSR",
"SIMD_SCALAR",
"DISP8_SCALAR"
],
"PATTERN": [
"EVV",
"0x67",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"W1",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_SCALAR()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"MEM0:r:q:f64",
"IMM0:r:b"
],
"IFORM": "VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512"
},
{
"ICLASS": "VFPCLASSSS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_SCALAR",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR",
"SIMD_SCALAR"
],
"PATTERN": [
"EVV",
"0x67",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=XMM_B3():r:dq:f32",
"IMM0:r:b"
],
"IFORM": "VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512"
},
{
"ICLASS": "VFPCLASSSS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_SCALAR",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"MXCSR",
"SIMD_SCALAR",
"DISP8_SCALAR"
],
"PATTERN": [
"EVV",
"0x67",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"W0",
"NOEVSR",
"ZEROING=0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_SCALAR()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"MEM0:r:d:f32",
"IMM0:r:b"
],
"IFORM": "VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512"
},
{
"ICLASS": "VGATHERDPD",
"CPL": "3",
"CATEGORY": "GATHER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E12",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"DWORD_INDICES",
"GATHER",
"DISP8_GSCAT",
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"EVV",
"0x92",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"RM=4",
"BCRC=0",
"VL128",
"W1",
"UISA_VMODRM_XMM()",
"eanot16",
"NOVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASKNOT0():rw:mskw",
"MEM0:r:q:f64"
],
"IFORM": "VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128"
},
{
"ICLASS": "VGATHERDPD",
"CPL": "3",
"CATEGORY": "GATHER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E12",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"DWORD_INDICES",
"GATHER",
"DISP8_GSCAT",
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"EVV",
"0x92",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"RM=4",
"BCRC=0",
"VL256",
"W1",
"UISA_VMODRM_XMM()",
"eanot16",
"NOVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASKNOT0():rw:mskw",
"MEM0:r:q:f64"
],
"IFORM": "VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256"
},
{
"ICLASS": "VGATHERDPS",
"CPL": "3",
"CATEGORY": "GATHER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E12",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"DWORD_INDICES",
"GATHER",
"DISP8_GSCAT",
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"EVV",
"0x92",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"RM=4",
"BCRC=0",
"VL128",
"W0",
"UISA_VMODRM_XMM()",
"eanot16",
"NOVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASKNOT0():rw:mskw",
"MEM0:r:d:f32"
],
"IFORM": "VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128"
},
{
"ICLASS": "VGATHERDPS",
"CPL": "3",
"CATEGORY": "GATHER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E12",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"DWORD_INDICES",
"GATHER",
"DISP8_GSCAT",
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"EVV",
"0x92",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"RM=4",
"BCRC=0",
"VL256",
"W0",
"UISA_VMODRM_YMM()",
"eanot16",
"NOVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASKNOT0():rw:mskw",
"MEM0:r:d:f32"
],
"IFORM": "VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256"
},
{
"ICLASS": "VGATHERQPD",
"CPL": "3",
"CATEGORY": "GATHER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E12",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"GATHER",
"QWORD_INDICES",
"DISP8_GSCAT",
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"EVV",
"0x93",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"RM=4",
"BCRC=0",
"VL128",
"W1",
"UISA_VMODRM_XMM()",
"eanot16",
"NOVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASKNOT0():rw:mskw",
"MEM0:r:q:f64"
],
"IFORM": "VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128"
},
{
"ICLASS": "VGATHERQPD",
"CPL": "3",
"CATEGORY": "GATHER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E12",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"GATHER",
"QWORD_INDICES",
"DISP8_GSCAT",
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"EVV",
"0x93",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"RM=4",
"BCRC=0",
"VL256",
"W1",
"UISA_VMODRM_YMM()",
"eanot16",
"NOVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASKNOT0():rw:mskw",
"MEM0:r:q:f64"
],
"IFORM": "VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256"
},
{
"ICLASS": "VGATHERQPS",
"CPL": "3",
"CATEGORY": "GATHER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E12",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"GATHER",
"QWORD_INDICES",
"DISP8_GSCAT",
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"EVV",
"0x93",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"RM=4",
"BCRC=0",
"VL128",
"W0",
"UISA_VMODRM_XMM()",
"eanot16",
"NOVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASKNOT0():rw:mskw",
"MEM0:r:d:f32"
],
"IFORM": "VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128"
},
{
"ICLASS": "VGATHERQPS",
"CPL": "3",
"CATEGORY": "GATHER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E12",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"GATHER",
"QWORD_INDICES",
"DISP8_GSCAT",
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"SPECIAL_AGEN_REQUIRED"
],
"PATTERN": [
"EVV",
"0x93",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[0b100]",
"RM=4",
"BCRC=0",
"VL256",
"W0",
"UISA_VMODRM_YMM()",
"eanot16",
"NOVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_GSCAT()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASKNOT0():rw:mskw",
"MEM0:r:d:f32"
],
"IFORM": "VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256"
},
{
"ICLASS": "VGETEXPPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VGETEXPPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VGETEXPPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VGETEXPPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VGETEXPPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VGETEXPPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VGETEXPPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VGETEXPPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x42",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VGETMANTPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x26",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64",
"IMM0:r:b"
],
"IFORM": "VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512"
},
{
"ICLASS": "VGETMANTPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x26",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512"
},
{
"ICLASS": "VGETMANTPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x26",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64",
"IMM0:r:b"
],
"IFORM": "VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512"
},
{
"ICLASS": "VGETMANTPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x26",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f64:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512"
},
{
"ICLASS": "VGETMANTPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x26",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32",
"IMM0:r:b"
],
"IFORM": "VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512"
},
{
"ICLASS": "VGETMANTPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x26",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512"
},
{
"ICLASS": "VGETMANTPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x26",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32",
"IMM0:r:b"
],
"IFORM": "VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512"
},
{
"ICLASS": "VGETMANTPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x26",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:f32:TXT=BCASTSTR",
"IMM0:r:b"
],
"IFORM": "VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512"
},
{
"ICLASS": "VINSERTF32X4",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x18",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=XMM_B3():r:dq:f32",
"IMM0:r:b"
],
"IFORM": "VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512"
},
{
"ICLASS": "VINSERTF32X4",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE4"
],
"PATTERN": [
"EVV",
"0x18",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_TUPLE4()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:dq:f32",
"IMM0:r:b"
],
"IFORM": "VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512"
},
{
"ICLASS": "VINSERTF32X8",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1A",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zf32",
"REG3=YMM_B3():r:qq:f32",
"IMM0:r:b"
],
"IFORM": "VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512"
},
{
"ICLASS": "VINSERTF32X8",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE8"
],
"PATTERN": [
"EVV",
"0x1A",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_TUPLE8()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zf32",
"MEM0:r:qq:f32",
"IMM0:r:b"
],
"IFORM": "VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512"
},
{
"ICLASS": "VINSERTF64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x18",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=XMM_B3():r:dq:f64",
"IMM0:r:b"
],
"IFORM": "VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512"
},
{
"ICLASS": "VINSERTF64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x18",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:dq:f64",
"IMM0:r:b"
],
"IFORM": "VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512"
},
{
"ICLASS": "VINSERTF64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x18",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"UIMM8()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zf64",
"REG3=XMM_B3():r:dq:f64",
"IMM0:r:b"
],
"IFORM": "VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512"
},
{
"ICLASS": "VINSERTF64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x18",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W1",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zf64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zf64",
"MEM0:r:dq:f64",
"IMM0:r:b"
],
"IFORM": "VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512"
},
{
"ICLASS": "VINSERTI32X4",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x38",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=XMM_B3():r:dq:u32",
"IMM0:r:b"
],
"IFORM": "VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512"
},
{
"ICLASS": "VINSERTI32X4",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE4"
],
"PATTERN": [
"EVV",
"0x38",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_TUPLE4()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:dq:u32",
"IMM0:r:b"
],
"IFORM": "VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512"
},
{
"ICLASS": "VINSERTI32X8",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x3A",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"UIMM8()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"REG3=YMM_B3():r:qq:u32",
"IMM0:r:b"
],
"IFORM": "VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512"
},
{
"ICLASS": "VINSERTI32X8",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE8"
],
"PATTERN": [
"EVV",
"0x3A",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"UIMM8()",
"ESIZE_32_BITS()",
"NELEM_TUPLE8()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"MEM0:r:qq:u32",
"IMM0:r:b"
],
"IFORM": "VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512"
},
{
"ICLASS": "VINSERTI64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x38",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"REG3=XMM_B3():r:dq:u64",
"IMM0:r:b"
],
"IFORM": "VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512"
},
{
"ICLASS": "VINSERTI64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x38",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"MEM0:r:dq:u64",
"IMM0:r:b"
],
"IFORM": "VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512"
},
{
"ICLASS": "VINSERTI64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x38",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"UIMM8()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu64",
"REG3=XMM_B3():r:dq:u64",
"IMM0:r:b"
],
"IFORM": "VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512"
},
{
"ICLASS": "VINSERTI64X2",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_TUPLE2"
],
"PATTERN": [
"EVV",
"0x38",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W1",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_TUPLE2()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu64",
"MEM0:r:dq:u64",
"IMM0:r:b"
],
"IFORM": "VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512"
},
{
"ICLASS": "VMAXPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5F",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VMAXPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5F",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VMAXPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5F",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VMAXPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5F",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VMAXPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5F",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VMAXPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5F",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VMAXPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5F",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VMAXPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5F",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VMINPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5D",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VMINPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5D",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VMINPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5D",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VMINPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5D",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VMINPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5D",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VMINPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5D",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VMINPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x5D",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VMINPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x5D",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VMOVAPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x28",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VMOVAPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x28",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f64"
],
"IFORM": "VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VMOVAPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x29",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:f64"
],
"IFORM": "VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VMOVAPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x29",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:f64",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:f64"
],
"IFORM": "VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VMOVAPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x28",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VMOVAPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x28",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:f64"
],
"IFORM": "VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VMOVAPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x29",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:f64"
],
"IFORM": "VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VMOVAPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x29",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:f64",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:f64"
],
"IFORM": "VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VMOVAPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x28",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VMOVAPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x28",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f32"
],
"IFORM": "VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VMOVAPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x29",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:f32"
],
"IFORM": "VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VMOVAPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x29",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:f32",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:f32"
],
"IFORM": "VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VMOVAPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x28",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VMOVAPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x28",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:f32"
],
"IFORM": "VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VMOVAPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x29",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:f32"
],
"IFORM": "VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VMOVAPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x29",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:f32",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:f32"
],
"IFORM": "VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VMOVDDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E5NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x12",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VMOVDDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E5NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_MOVDDUP"
],
"PATTERN": [
"EVV",
"0x12",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_MOVDDUP()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:q:f64"
],
"IFORM": "VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VMOVDDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E5NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x12",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VMOVDDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E5NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_MOVDDUP"
],
"PATTERN": [
"EVV",
"0x12",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_MOVDDUP()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:f64"
],
"IFORM": "VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VMOVDQA32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u32"
],
"IFORM": "VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VMOVDQA32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:u32"
],
"IFORM": "VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VMOVDQA32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:u32"
],
"IFORM": "VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VMOVDQA32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:u32",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:u32"
],
"IFORM": "VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VMOVDQA32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:u32"
],
"IFORM": "VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512"
},
{
"ICLASS": "VMOVDQA32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:u32"
],
"IFORM": "VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VMOVDQA32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:u32"
],
"IFORM": "VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512"
},
{
"ICLASS": "VMOVDQA32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:u32",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:u32"
],
"IFORM": "VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512"
},
{
"ICLASS": "VMOVDQA64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u64"
],
"IFORM": "VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512"
},
{
"ICLASS": "VMOVDQA64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:u64"
],
"IFORM": "VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VMOVDQA64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:u64"
],
"IFORM": "VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512"
},
{
"ICLASS": "VMOVDQA64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:u64",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:u64"
],
"IFORM": "VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512"
},
{
"ICLASS": "VMOVDQA64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:u64"
],
"IFORM": "VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512"
},
{
"ICLASS": "VMOVDQA64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:u64"
],
"IFORM": "VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VMOVDQA64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:u64"
],
"IFORM": "VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512"
},
{
"ICLASS": "VMOVDQA64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:u64",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:u64"
],
"IFORM": "VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u16"
],
"IFORM": "VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:u16"
],
"IFORM": "VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:u16"
],
"IFORM": "VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:u16",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:u16"
],
"IFORM": "VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:u16"
],
"IFORM": "VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:u16"
],
"IFORM": "VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:u16"
],
"IFORM": "VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:u16",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:u16"
],
"IFORM": "VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zu16"
],
"IFORM": "VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:zd:u16"
],
"IFORM": "VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_B3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_R3():r:zu16"
],
"IFORM": "VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512"
},
{
"ICLASS": "VMOVDQU16",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:zd:u16",
"REG0=MASK1():r:mskw",
"REG1=ZMM_R3():r:zu16"
],
"IFORM": "VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512"
},
{
"ICLASS": "VMOVDQU32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u32"
],
"IFORM": "VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VMOVDQU32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:u32"
],
"IFORM": "VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VMOVDQU32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:u32"
],
"IFORM": "VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VMOVDQU32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:u32",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:u32"
],
"IFORM": "VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VMOVDQU32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:u32"
],
"IFORM": "VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512"
},
{
"ICLASS": "VMOVDQU32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:u32"
],
"IFORM": "VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VMOVDQU32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:u32"
],
"IFORM": "VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512"
},
{
"ICLASS": "VMOVDQU32",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:u32",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:u32"
],
"IFORM": "VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512"
},
{
"ICLASS": "VMOVDQU64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u64"
],
"IFORM": "VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512"
},
{
"ICLASS": "VMOVDQU64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:u64"
],
"IFORM": "VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VMOVDQU64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:u64"
],
"IFORM": "VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512"
},
{
"ICLASS": "VMOVDQU64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:u64",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:u64"
],
"IFORM": "VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512"
},
{
"ICLASS": "VMOVDQU64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:u64"
],
"IFORM": "VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512"
},
{
"ICLASS": "VMOVDQU64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:u64"
],
"IFORM": "VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VMOVDQU64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:u64"
],
"IFORM": "VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512"
},
{
"ICLASS": "VMOVDQU64",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:u64",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:u64"
],
"IFORM": "VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u8"
],
"IFORM": "VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:u8"
],
"IFORM": "VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:u8"
],
"IFORM": "VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:u8",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:u8"
],
"IFORM": "VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:u8"
],
"IFORM": "VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:u8"
],
"IFORM": "VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:u8"
],
"IFORM": "VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:u8",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:u8"
],
"IFORM": "VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zu8"
],
"IFORM": "VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x6F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:zd:u8"
],
"IFORM": "VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_B3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_R3():r:zu8"
],
"IFORM": "VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512"
},
{
"ICLASS": "VMOVDQU8",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x7F",
"VF2",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:zd:u8",
"REG0=MASK1():r:mskw",
"REG1=ZMM_R3():r:zu8"
],
"IFORM": "VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512"
},
{
"ICLASS": "VMOVNTDQ",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM",
"NONTEMPORAL"
],
"PATTERN": [
"EVV",
"0xE7",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"MASK=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:u32",
"REG0=XMM_R3():r:dq:u32"
],
"IFORM": "VMOVNTDQ_MEMu32_XMMu32_AVX512"
},
{
"ICLASS": "VMOVNTDQ",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM",
"NONTEMPORAL"
],
"PATTERN": [
"EVV",
"0xE7",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"MASK=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:u32",
"REG0=YMM_R3():r:qq:u32"
],
"IFORM": "VMOVNTDQ_MEMu32_YMMu32_AVX512"
},
{
"ICLASS": "VMOVNTDQA",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM",
"NONTEMPORAL"
],
"PATTERN": [
"EVV",
"0x2A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"MASK=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"MEM0:r:dq:u32"
],
"IFORM": "VMOVNTDQA_XMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VMOVNTDQA",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM",
"NONTEMPORAL"
],
"PATTERN": [
"EVV",
"0x2A",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"MASK=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"MEM0:r:qq:u32"
],
"IFORM": "VMOVNTDQA_YMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VMOVNTPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM",
"NONTEMPORAL"
],
"PATTERN": [
"EVV",
"0x2B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ZEROING=0",
"MASK=0",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:f64",
"REG0=XMM_R3():r:dq:f64"
],
"IFORM": "VMOVNTPD_MEMf64_XMMf64_AVX512"
},
{
"ICLASS": "VMOVNTPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM",
"NONTEMPORAL"
],
"PATTERN": [
"EVV",
"0x2B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"MASK=0",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:f64",
"REG0=YMM_R3():r:qq:f64"
],
"IFORM": "VMOVNTPD_MEMf64_YMMf64_AVX512"
},
{
"ICLASS": "VMOVNTPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E1NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM",
"NONTEMPORAL"
],
"PATTERN": [
"EVV",
"0x2B",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"MASK=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:f32",
"REG0=XMM_R3():r:dq:f32"
],
"IFORM": "VMOVNTPS_MEMf32_XMMf32_AVX512"
},
{
"ICLASS": "VMOVNTPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E1NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"NOTSX",
"REQUIRES_ALIGNMENT",
"DISP8_FULLMEM",
"NONTEMPORAL"
],
"PATTERN": [
"EVV",
"0x2B",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"MASK=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:f32",
"REG0=YMM_R3():r:qq:f32"
],
"IFORM": "VMOVNTPS_MEMf32_YMMf32_AVX512"
},
{
"ICLASS": "VMOVSHDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x16",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VMOVSHDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x16",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f32"
],
"IFORM": "VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VMOVSHDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x16",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VMOVSHDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x16",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:f32"
],
"IFORM": "VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VMOVSLDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x12",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VMOVSLDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x12",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f32"
],
"IFORM": "VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VMOVSLDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x12",
"VF3",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VMOVSLDUP",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x12",
"VF3",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:f32"
],
"IFORM": "VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VMOVUPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x10",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f64"
],
"IFORM": "VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VMOVUPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x10",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f64"
],
"IFORM": "VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VMOVUPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x11",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:f64"
],
"IFORM": "VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VMOVUPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x11",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:f64",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:f64"
],
"IFORM": "VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512"
},
{
"ICLASS": "VMOVUPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x10",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f64"
],
"IFORM": "VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VMOVUPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x10",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:f64"
],
"IFORM": "VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512"
},
{
"ICLASS": "VMOVUPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x11",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:f64"
],
"IFORM": "VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VMOVUPD",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x11",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:f64",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:f64"
],
"IFORM": "VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512"
},
{
"ICLASS": "VMOVUPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x10",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:f32"
],
"IFORM": "VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VMOVUPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x10",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:f32"
],
"IFORM": "VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VMOVUPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x11",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_B3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_R3():r:dq:f32"
],
"IFORM": "VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VMOVUPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x11",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:dq:f32",
"REG0=MASK1():r:mskw",
"REG1=XMM_R3():r:dq:f32"
],
"IFORM": "VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512"
},
{
"ICLASS": "VMOVUPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x10",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:f32"
],
"IFORM": "VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VMOVUPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x10",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:f32"
],
"IFORM": "VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512"
},
{
"ICLASS": "VMOVUPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x11",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_B3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_R3():r:qq:f32"
],
"IFORM": "VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VMOVUPS",
"CPL": "3",
"CATEGORY": "DATAXFER",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x11",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"ESIZE_32_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"MEM0:w:qq:f32",
"REG0=MASK1():r:mskw",
"REG1=YMM_R3():r:qq:f32"
],
"IFORM": "VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512"
},
{
"ICLASS": "VMULPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"REG3=XMM_B3():r:dq:f64"
],
"IFORM": "VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512"
},
{
"ICLASS": "VMULPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VMULPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"REG3=YMM_B3():r:qq:f64"
],
"IFORM": "VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512"
},
{
"ICLASS": "VMULPD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f64",
"MEM0:r:vv:f64:TXT=BCASTSTR"
],
"IFORM": "VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512"
},
{
"ICLASS": "VMULPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x59",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"REG3=XMM_B3():r:dq:f32"
],
"IFORM": "VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512"
},
{
"ICLASS": "VMULPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x59",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VMULPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MXCSR"
],
"PATTERN": [
"EVV",
"0x59",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"REG3=YMM_B3():r:qq:f32"
],
"IFORM": "VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512"
},
{
"ICLASS": "VMULPS",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E2",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"MXCSR",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x59",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:f32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:f32",
"MEM0:r:vv:f32:TXT=BCASTSTR"
],
"IFORM": "VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512"
},
{
"ICLASS": "VORPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x56",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"REG3=XMM_B3():r:dq:u64"
],
"IFORM": "VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"
},
{
"ICLASS": "VORPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x56",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VORPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x56",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"REG3=YMM_B3():r:qq:u64"
],
"IFORM": "VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"
},
{
"ICLASS": "VORPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x56",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VORPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x56",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu64",
"REG3=ZMM_B3():r:zu64"
],
"IFORM": "VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512"
},
{
"ICLASS": "VORPD",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x56",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VORPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x56",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"REG3=XMM_B3():r:dq:u32"
],
"IFORM": "VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"
},
{
"ICLASS": "VORPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x56",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VORPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x56",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=YMM_B3():r:qq:u32"
],
"IFORM": "VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"
},
{
"ICLASS": "VORPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x56",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VORPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x56",
"VNP",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"REG3=ZMM_B3():r:zu32"
],
"IFORM": "VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512"
},
{
"ICLASS": "VORPS",
"CPL": "3",
"CATEGORY": "LOGICAL_FP",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512DQ_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x56",
"VNP",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPABSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:i8"
],
"IFORM": "VPABSB_XMMi8_MASKmskw_XMMi8_AVX512"
},
{
"ICLASS": "VPABSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x1C",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"NOEVSR",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:i8"
],
"IFORM": "VPABSB_XMMi8_MASKmskw_MEMi8_AVX512"
},
{
"ICLASS": "VPABSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:i8"
],
"IFORM": "VPABSB_YMMi8_MASKmskw_YMMi8_AVX512"
},
{
"ICLASS": "VPABSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x1C",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"NOEVSR",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:i8"
],
"IFORM": "VPABSB_YMMi8_MASKmskw_MEMi8_AVX512"
},
{
"ICLASS": "VPABSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zi8"
],
"IFORM": "VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512"
},
{
"ICLASS": "VPABSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x1C",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"NOEVSR",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:zd:i8"
],
"IFORM": "VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512"
},
{
"ICLASS": "VPABSD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1E",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:i32"
],
"IFORM": "VPABSD_XMMi32_MASKmskw_XMMi32_AVX512"
},
{
"ICLASS": "VPABSD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x1E",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:i32:TXT=BCASTSTR"
],
"IFORM": "VPABSD_XMMi32_MASKmskw_MEMi32_AVX512"
},
{
"ICLASS": "VPABSD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1E",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:i32"
],
"IFORM": "VPABSD_YMMi32_MASKmskw_YMMi32_AVX512"
},
{
"ICLASS": "VPABSD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x1E",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:i32:TXT=BCASTSTR"
],
"IFORM": "VPABSD_YMMi32_MASKmskw_MEMi32_AVX512"
},
{
"ICLASS": "VPABSQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1F",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:i64"
],
"IFORM": "VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512"
},
{
"ICLASS": "VPABSQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x1F",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:i64:TXT=BCASTSTR"
],
"IFORM": "VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512"
},
{
"ICLASS": "VPABSQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1F",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:i64"
],
"IFORM": "VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512"
},
{
"ICLASS": "VPABSQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x1F",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:vv:i64:TXT=BCASTSTR"
],
"IFORM": "VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512"
},
{
"ICLASS": "VPABSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1D",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:i16"
],
"IFORM": "VPABSW_XMMi16_MASKmskw_XMMi16_AVX512"
},
{
"ICLASS": "VPABSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x1D",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:dq:i16"
],
"IFORM": "VPABSW_XMMi16_MASKmskw_MEMi16_AVX512"
},
{
"ICLASS": "VPABSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1D",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_B3():r:qq:i16"
],
"IFORM": "VPABSW_YMMi16_MASKmskw_YMMi16_AVX512"
},
{
"ICLASS": "VPABSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x1D",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:qq:i16"
],
"IFORM": "VPABSW_YMMi16_MASKmskw_MEMi16_AVX512"
},
{
"ICLASS": "VPABSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x1D",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_B3():r:zi16"
],
"IFORM": "VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512"
},
{
"ICLASS": "VPABSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x1D",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:zd:i16"
],
"IFORM": "VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512"
},
{
"ICLASS": "VPACKSSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:i32",
"REG3=XMM_B3():r:dq:i32"
],
"IFORM": "VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512"
},
{
"ICLASS": "VPACKSSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x6B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:i32",
"MEM0:r:vv:i32:TXT=BCASTSTR"
],
"IFORM": "VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512"
},
{
"ICLASS": "VPACKSSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:i32",
"REG3=YMM_B3():r:qq:i32"
],
"IFORM": "VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512"
},
{
"ICLASS": "VPACKSSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x6B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:i32",
"MEM0:r:vv:i32:TXT=BCASTSTR"
],
"IFORM": "VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512"
},
{
"ICLASS": "VPACKSSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x6B",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zi32",
"REG3=ZMM_B3():r:zi32"
],
"IFORM": "VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512"
},
{
"ICLASS": "VPACKSSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x6B",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zi32",
"MEM0:r:vv:i32:TXT=BCASTSTR"
],
"IFORM": "VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512"
},
{
"ICLASS": "VPACKSSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x63",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:i16",
"REG3=XMM_B3():r:dq:i16"
],
"IFORM": "VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512"
},
{
"ICLASS": "VPACKSSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x63",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:i16",
"MEM0:r:dq:i16"
],
"IFORM": "VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512"
},
{
"ICLASS": "VPACKSSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x63",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:i16",
"REG3=YMM_B3():r:qq:i16"
],
"IFORM": "VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512"
},
{
"ICLASS": "VPACKSSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x63",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:i16",
"MEM0:r:qq:i16"
],
"IFORM": "VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512"
},
{
"ICLASS": "VPACKSSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x63",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zi16",
"REG3=ZMM_B3():r:zi16"
],
"IFORM": "VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512"
},
{
"ICLASS": "VPACKSSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x63",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zi16",
"MEM0:r:zd:i16"
],
"IFORM": "VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512"
},
{
"ICLASS": "VPACKUSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x2B",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"REG3=XMM_B3():r:dq:u32"
],
"IFORM": "VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512"
},
{
"ICLASS": "VPACKUSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x2B",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPACKUSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x2B",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=YMM_B3():r:qq:u32"
],
"IFORM": "VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512"
},
{
"ICLASS": "VPACKUSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x2B",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPACKUSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x2B",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"REG3=ZMM_B3():r:zu32"
],
"IFORM": "VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512"
},
{
"ICLASS": "VPACKUSDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0x2B",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL512",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPACKUSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x67",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u16",
"REG3=XMM_B3():r:dq:u16"
],
"IFORM": "VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512"
},
{
"ICLASS": "VPACKUSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x67",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u16",
"MEM0:r:dq:u16"
],
"IFORM": "VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPACKUSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x67",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u16",
"REG3=YMM_B3():r:qq:u16"
],
"IFORM": "VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512"
},
{
"ICLASS": "VPACKUSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x67",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u16",
"MEM0:r:qq:u16"
],
"IFORM": "VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPACKUSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x67",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu16",
"REG3=ZMM_B3():r:zu16"
],
"IFORM": "VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512"
},
{
"ICLASS": "VPACKUSWB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x67",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu16",
"MEM0:r:zd:u16"
],
"IFORM": "VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPADDB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xFC",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"REG3=XMM_B3():r:dq:u8"
],
"IFORM": "VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"
},
{
"ICLASS": "VPADDB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xFC",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"MEM0:r:dq:u8"
],
"IFORM": "VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPADDB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xFC",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"REG3=YMM_B3():r:qq:u8"
],
"IFORM": "VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"
},
{
"ICLASS": "VPADDB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xFC",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"MEM0:r:qq:u8"
],
"IFORM": "VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPADDB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xFC",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"REG3=ZMM_B3():r:zu8"
],
"IFORM": "VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"
},
{
"ICLASS": "VPADDB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xFC",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"MEM0:r:zd:u8"
],
"IFORM": "VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPADDD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xFE",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"REG3=XMM_B3():r:dq:u32"
],
"IFORM": "VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"
},
{
"ICLASS": "VPADDD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xFE",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPADDD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xFE",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=YMM_B3():r:qq:u32"
],
"IFORM": "VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"
},
{
"ICLASS": "VPADDD",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xFE",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPADDQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xD4",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"REG3=XMM_B3():r:dq:u64"
],
"IFORM": "VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"
},
{
"ICLASS": "VPADDQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xD4",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VPADDQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xD4",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"REG3=YMM_B3():r:qq:u64"
],
"IFORM": "VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"
},
{
"ICLASS": "VPADDQ",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xD4",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VPADDSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xEC",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:i8",
"REG3=XMM_B3():r:dq:i8"
],
"IFORM": "VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512"
},
{
"ICLASS": "VPADDSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xEC",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:i8",
"MEM0:r:dq:i8"
],
"IFORM": "VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512"
},
{
"ICLASS": "VPADDSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xEC",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:i8",
"REG3=YMM_B3():r:qq:i8"
],
"IFORM": "VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512"
},
{
"ICLASS": "VPADDSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xEC",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:i8",
"MEM0:r:qq:i8"
],
"IFORM": "VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512"
},
{
"ICLASS": "VPADDSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xEC",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zi8",
"REG3=ZMM_B3():r:zi8"
],
"IFORM": "VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512"
},
{
"ICLASS": "VPADDSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xEC",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zi8",
"MEM0:r:zd:i8"
],
"IFORM": "VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512"
},
{
"ICLASS": "VPADDSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xED",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:i16",
"REG3=XMM_B3():r:dq:i16"
],
"IFORM": "VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512"
},
{
"ICLASS": "VPADDSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xED",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:i16",
"MEM0:r:dq:i16"
],
"IFORM": "VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512"
},
{
"ICLASS": "VPADDSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xED",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:i16",
"REG3=YMM_B3():r:qq:i16"
],
"IFORM": "VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512"
},
{
"ICLASS": "VPADDSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xED",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:i16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:i16",
"MEM0:r:qq:i16"
],
"IFORM": "VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512"
},
{
"ICLASS": "VPADDSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xED",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zi16",
"REG3=ZMM_B3():r:zi16"
],
"IFORM": "VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512"
},
{
"ICLASS": "VPADDSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xED",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zi16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zi16",
"MEM0:r:zd:i16"
],
"IFORM": "VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512"
},
{
"ICLASS": "VPADDUSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDC",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"REG3=XMM_B3():r:dq:u8"
],
"IFORM": "VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"
},
{
"ICLASS": "VPADDUSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xDC",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"MEM0:r:dq:u8"
],
"IFORM": "VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPADDUSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDC",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"REG3=YMM_B3():r:qq:u8"
],
"IFORM": "VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"
},
{
"ICLASS": "VPADDUSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xDC",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"MEM0:r:qq:u8"
],
"IFORM": "VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPADDUSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDC",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"REG3=ZMM_B3():r:zu8"
],
"IFORM": "VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"
},
{
"ICLASS": "VPADDUSB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xDC",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"MEM0:r:zd:u8"
],
"IFORM": "VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPADDUSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDD",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u16",
"REG3=XMM_B3():r:dq:u16"
],
"IFORM": "VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"
},
{
"ICLASS": "VPADDUSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xDD",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u16",
"MEM0:r:dq:u16"
],
"IFORM": "VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPADDUSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDD",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u16",
"REG3=YMM_B3():r:qq:u16"
],
"IFORM": "VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"
},
{
"ICLASS": "VPADDUSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xDD",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u16",
"MEM0:r:qq:u16"
],
"IFORM": "VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPADDUSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDD",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu16",
"REG3=ZMM_B3():r:zu16"
],
"IFORM": "VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"
},
{
"ICLASS": "VPADDUSW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xDD",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu16",
"MEM0:r:zd:u16"
],
"IFORM": "VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPADDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xFD",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u16",
"REG3=XMM_B3():r:dq:u16"
],
"IFORM": "VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"
},
{
"ICLASS": "VPADDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xFD",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u16",
"MEM0:r:dq:u16"
],
"IFORM": "VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPADDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xFD",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u16",
"REG3=YMM_B3():r:qq:u16"
],
"IFORM": "VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"
},
{
"ICLASS": "VPADDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xFD",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u16",
"MEM0:r:qq:u16"
],
"IFORM": "VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPADDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xFD",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu16",
"REG3=ZMM_B3():r:zu16"
],
"IFORM": "VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"
},
{
"ICLASS": "VPADDW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xFD",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu16",
"MEM0:r:zd:u16"
],
"IFORM": "VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPALIGNR",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x0F",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"UIMM8()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"REG3=XMM_B3():r:dq:u8",
"IMM0:r:b"
],
"IFORM": "VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512"
},
{
"ICLASS": "VPALIGNR",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x0F",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"MEM0:r:dq:u8",
"IMM0:r:b"
],
"IFORM": "VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512"
},
{
"ICLASS": "VPALIGNR",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x0F",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"UIMM8()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"REG3=YMM_B3():r:qq:u8",
"IMM0:r:b"
],
"IFORM": "VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512"
},
{
"ICLASS": "VPALIGNR",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x0F",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"MEM0:r:qq:u8",
"IMM0:r:b"
],
"IFORM": "VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512"
},
{
"ICLASS": "VPALIGNR",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x0F",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"UIMM8()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"REG3=ZMM_B3():r:zu8",
"IMM0:r:b"
],
"IFORM": "VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512"
},
{
"ICLASS": "VPALIGNR",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4NF",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x0F",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"UIMM8()",
"ESIZE_64_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"MEM0:r:zd:u8",
"IMM0:r:b"
],
"IFORM": "VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512"
},
{
"ICLASS": "VPANDD",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDB",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"REG3=XMM_B3():r:dq:u32"
],
"IFORM": "VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"
},
{
"ICLASS": "VPANDD",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xDB",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPANDD",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDB",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=YMM_B3():r:qq:u32"
],
"IFORM": "VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"
},
{
"ICLASS": "VPANDD",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xDB",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPANDND",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDF",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"REG3=XMM_B3():r:dq:u32"
],
"IFORM": "VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"
},
{
"ICLASS": "VPANDND",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xDF",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPANDND",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDF",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=YMM_B3():r:qq:u32"
],
"IFORM": "VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"
},
{
"ICLASS": "VPANDND",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xDF",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPANDNQ",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDF",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"REG3=XMM_B3():r:dq:u64"
],
"IFORM": "VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"
},
{
"ICLASS": "VPANDNQ",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xDF",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VPANDNQ",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDF",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"REG3=YMM_B3():r:qq:u64"
],
"IFORM": "VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"
},
{
"ICLASS": "VPANDNQ",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xDF",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VPANDQ",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDB",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"REG3=XMM_B3():r:dq:u64"
],
"IFORM": "VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"
},
{
"ICLASS": "VPANDQ",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xDB",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VPANDQ",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xDB",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"REG3=YMM_B3():r:qq:u64"
],
"IFORM": "VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"
},
{
"ICLASS": "VPANDQ",
"CPL": "3",
"CATEGORY": "LOGICAL",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED"
],
"PATTERN": [
"EVV",
"0xDB",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VPAVGB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xE0",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"REG3=XMM_B3():r:dq:u8"
],
"IFORM": "VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"
},
{
"ICLASS": "VPAVGB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xE0",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"MEM0:r:dq:u8"
],
"IFORM": "VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPAVGB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xE0",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"REG3=YMM_B3():r:qq:u8"
],
"IFORM": "VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"
},
{
"ICLASS": "VPAVGB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xE0",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"MEM0:r:qq:u8"
],
"IFORM": "VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPAVGB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xE0",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"REG3=ZMM_B3():r:zu8"
],
"IFORM": "VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"
},
{
"ICLASS": "VPAVGB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xE0",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"MEM0:r:zd:u8"
],
"IFORM": "VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPAVGW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xE3",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u16",
"REG3=XMM_B3():r:dq:u16"
],
"IFORM": "VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"
},
{
"ICLASS": "VPAVGW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xE3",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u16",
"MEM0:r:dq:u16"
],
"IFORM": "VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPAVGW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xE3",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u16",
"REG3=YMM_B3():r:qq:u16"
],
"IFORM": "VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"
},
{
"ICLASS": "VPAVGW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xE3",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u16",
"MEM0:r:qq:u16"
],
"IFORM": "VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPAVGW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0xE3",
"V66",
"V0F",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu16",
"REG3=ZMM_B3():r:zu16"
],
"IFORM": "VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"
},
{
"ICLASS": "VPAVGW",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0xE3",
"V66",
"V0F",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu16",
"MEM0:r:zd:u16"
],
"IFORM": "VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPBLENDMB",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"REG3=XMM_B3():r:dq:u8"
],
"IFORM": "VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512"
},
{
"ICLASS": "VPBLENDMB",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u8",
"MEM0:r:dq:u8"
],
"IFORM": "VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPBLENDMB",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"REG3=YMM_B3():r:qq:u8"
],
"IFORM": "VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512"
},
{
"ICLASS": "VPBLENDMB",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u8",
"MEM0:r:qq:u8"
],
"IFORM": "VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPBLENDMB",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"REG3=ZMM_B3():r:zu8"
],
"IFORM": "VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512"
},
{
"ICLASS": "VPBLENDMB",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu8",
"MEM0:r:zd:u8"
],
"IFORM": "VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512"
},
{
"ICLASS": "VPBLENDMD",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x64",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"REG3=XMM_B3():r:dq:u32"
],
"IFORM": "VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512"
},
{
"ICLASS": "VPBLENDMD",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x64",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPBLENDMD",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x64",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"REG3=YMM_B3():r:qq:u32"
],
"IFORM": "VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512"
},
{
"ICLASS": "VPBLENDMD",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x64",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W0",
"ESIZE_32_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u32",
"MEM0:r:vv:u32:TXT=BCASTSTR"
],
"IFORM": "VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512"
},
{
"ICLASS": "VPBLENDMQ",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x64",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"REG3=XMM_B3():r:dq:u64"
],
"IFORM": "VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512"
},
{
"ICLASS": "VPBLENDMQ",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x64",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL128",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VPBLENDMQ",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x64",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"REG3=YMM_B3():r:qq:u64"
],
"IFORM": "VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512"
},
{
"ICLASS": "VPBLENDMQ",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULL",
"BROADCAST_ENABLED",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x64",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"MODRM()",
"VL256",
"W1",
"ESIZE_64_BITS()",
"NELEM_FULL()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u64",
"MEM0:r:vv:u64:TXT=BCASTSTR"
],
"IFORM": "VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512"
},
{
"ICLASS": "VPBLENDMW",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u16",
"REG3=XMM_B3():r:dq:u16"
],
"IFORM": "VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512"
},
{
"ICLASS": "VPBLENDMW",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_N3():r:dq:u16",
"MEM0:r:dq:u16"
],
"IFORM": "VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPBLENDMW",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u16",
"REG3=YMM_B3():r:qq:u16"
],
"IFORM": "VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512"
},
{
"ICLASS": "VPBLENDMW",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=YMM_N3():r:qq:u16",
"MEM0:r:qq:u16"
],
"IFORM": "VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPBLENDMW",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W1"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu16",
"REG3=ZMM_B3():r:zu16"
],
"IFORM": "VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512"
},
{
"ICLASS": "VPBLENDMW",
"CPL": "3",
"CATEGORY": "BLEND",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM",
"MASK_AS_CONTROL"
],
"PATTERN": [
"EVV",
"0x66",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W1",
"ESIZE_16_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=ZMM_N3():r:zu16",
"MEM0:r:zd:u16"
],
"IFORM": "VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512"
},
{
"ICLASS": "VPBROADCASTB",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u8",
"EMX_BROADCAST_1TO16_8"
],
"IFORM": "VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512"
},
{
"ICLASS": "VPBROADCASTB",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1_BYTE"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_8_BITS()",
"NELEM_TUPLE1_BYTE()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:b:u8",
"EMX_BROADCAST_1TO16_8"
],
"IFORM": "VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512"
},
{
"ICLASS": "VPBROADCASTB",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E7NM",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=GPR32_B():r:d:u8",
"EMX_BROADCAST_1TO16_8"
],
"IFORM": "VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512"
},
{
"ICLASS": "VPBROADCASTB",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u8",
"EMX_BROADCAST_1TO32_8"
],
"IFORM": "VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512"
},
{
"ICLASS": "VPBROADCASTB",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1_BYTE"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_8_BITS()",
"NELEM_TUPLE1_BYTE()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:b:u8",
"EMX_BROADCAST_1TO32_8"
],
"IFORM": "VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512"
},
{
"ICLASS": "VPBROADCASTB",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E7NM",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=GPR32_B():r:d:u8",
"EMX_BROADCAST_1TO32_8"
],
"IFORM": "VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512"
},
{
"ICLASS": "VPBROADCASTB",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u8",
"EMX_BROADCAST_1TO64_8"
],
"IFORM": "VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512"
},
{
"ICLASS": "VPBROADCASTB",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1_BYTE"
],
"PATTERN": [
"EVV",
"0x78",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_8_BITS()",
"NELEM_TUPLE1_BYTE()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:b:u8",
"EMX_BROADCAST_1TO64_8"
],
"IFORM": "VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512"
},
{
"ICLASS": "VPBROADCASTB",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E7NM",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7A",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu8",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=GPR32_B():r:d:u8",
"EMX_BROADCAST_1TO64_8"
],
"IFORM": "VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512"
},
{
"ICLASS": "VPBROADCASTD",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1"
],
"PATTERN": [
"EVV",
"0x58",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE1()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:d:u32",
"EMX_BROADCAST_1TO4_32"
],
"IFORM": "VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VPBROADCASTD",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x58",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u32",
"EMX_BROADCAST_1TO4_32"
],
"IFORM": "VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VPBROADCASTD",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E7NM",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"mode64",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=GPR32_B():r:d:u32",
"EMX_BROADCAST_1TO4_32"
],
"IFORM": "VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512"
},
{
"ICLASS": "VPBROADCASTD",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1"
],
"PATTERN": [
"EVV",
"0x58",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_32_BITS()",
"NELEM_TUPLE1()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:d:u32",
"EMX_BROADCAST_1TO8_32"
],
"IFORM": "VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512"
},
{
"ICLASS": "VPBROADCASTD",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x58",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u32",
"EMX_BROADCAST_1TO8_32"
],
"IFORM": "VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512"
},
{
"ICLASS": "VPBROADCASTD",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E7NM",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"mode64",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=GPR32_B():r:d:u32",
"EMX_BROADCAST_1TO8_32"
],
"IFORM": "VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512"
},
{
"ICLASS": "VPBROADCASTMB2Q",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512CD_128",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"PATTERN": [
"EVV",
"0x2A",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR",
"ZEROING=0",
"MASK=0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK_B():r:mskw:u64",
"EMX_BROADCAST_1TO2_8"
],
"IFORM": "VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512"
},
{
"ICLASS": "VPBROADCASTMB2Q",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512CD_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"PATTERN": [
"EVV",
"0x2A",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR",
"ZEROING=0",
"MASK=0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK_B():r:mskw:u64",
"EMX_BROADCAST_1TO4_8"
],
"IFORM": "VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512"
},
{
"ICLASS": "VPBROADCASTMW2D",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512CD_128",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"PATTERN": [
"EVV",
"0x3A",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR",
"ZEROING=0",
"MASK=0"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u32",
"REG1=MASK_B():r:mskw:u32",
"EMX_BROADCAST_1TO4_16"
],
"IFORM": "VPBROADCASTMW2D_XMMu32_MASKu32_AVX512"
},
{
"ICLASS": "VPBROADCASTMW2D",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512CD_256",
"EXCEPTIONS": "AVX512-E6NF",
"REAL_OPCODE": "Y",
"PATTERN": [
"EVV",
"0x3A",
"VF3",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR",
"ZEROING=0",
"MASK=0"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u32",
"REG1=MASK_B():r:mskw:u32",
"EMX_BROADCAST_1TO8_16"
],
"IFORM": "VPBROADCASTMW2D_YMMu32_MASKu32_AVX512"
},
{
"ICLASS": "VPBROADCASTQ",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_TUPLE1()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:q:u64",
"EMX_BROADCAST_1TO2_64"
],
"IFORM": "VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VPBROADCASTQ",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u64",
"EMX_BROADCAST_1TO2_64"
],
"IFORM": "VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512"
},
{
"ICLASS": "VPBROADCASTQ",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_128",
"EXCEPTIONS": "AVX512-E7NM",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W1",
"mode64",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=GPR64_B():r:q:u64",
"EMX_BROADCAST_1TO2_64"
],
"IFORM": "VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512"
},
{
"ICLASS": "VPBROADCASTQ",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W1",
"NOEVSR",
"ESIZE_64_BITS()",
"NELEM_TUPLE1()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:q:u64",
"EMX_BROADCAST_1TO4_64"
],
"IFORM": "VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512"
},
{
"ICLASS": "VPBROADCASTQ",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x59",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u64",
"EMX_BROADCAST_1TO4_64"
],
"IFORM": "VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512"
},
{
"ICLASS": "VPBROADCASTQ",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512F_256",
"EXCEPTIONS": "AVX512-E7NM",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7C",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W1",
"mode64",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u64",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=GPR64_B():r:q:u64",
"EMX_BROADCAST_1TO4_64"
],
"IFORM": "VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512"
},
{
"ICLASS": "VPBROADCASTW",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u16",
"EMX_BROADCAST_1TO8_16"
],
"IFORM": "VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512"
},
{
"ICLASS": "VPBROADCASTW",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1_WORD"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_TUPLE1_WORD()"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:wrd:u16",
"EMX_BROADCAST_1TO8_16"
],
"IFORM": "VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512"
},
{
"ICLASS": "VPBROADCASTW",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E7NM",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=XMM_R3():w:dq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=GPR32_B():r:d:u16",
"EMX_BROADCAST_1TO8_16"
],
"IFORM": "VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512"
},
{
"ICLASS": "VPBROADCASTW",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u16",
"EMX_BROADCAST_1TO16_16"
],
"IFORM": "VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512"
},
{
"ICLASS": "VPBROADCASTW",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1_WORD"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_TUPLE1_WORD()"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:wrd:u16",
"EMX_BROADCAST_1TO16_16"
],
"IFORM": "VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512"
},
{
"ICLASS": "VPBROADCASTW",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E7NM",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=YMM_R3():w:qq:u16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=GPR32_B():r:d:u16",
"EMX_BROADCAST_1TO16_16"
],
"IFORM": "VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512"
},
{
"ICLASS": "VPBROADCASTW",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=XMM_B3():r:dq:u16",
"EMX_BROADCAST_1TO32_16"
],
"IFORM": "VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512"
},
{
"ICLASS": "VPBROADCASTW",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E6",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_TUPLE1_WORD"
],
"PATTERN": [
"EVV",
"0x79",
"V66",
"V0F38",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL512",
"W0",
"NOEVSR",
"ESIZE_16_BITS()",
"NELEM_TUPLE1_WORD()"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"MEM0:r:wrd:u16",
"EMX_BROADCAST_1TO32_16"
],
"IFORM": "VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512"
},
{
"ICLASS": "VPBROADCASTW",
"CPL": "3",
"CATEGORY": "BROADCAST",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E7NM",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x7B",
"V66",
"V0F38",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL512",
"W0",
"NOEVSR"
],
"OPERANDS": [
"REG0=ZMM_R3():w:zu16",
"REG1=MASK1():r:mskw:TXT=ZEROSTR",
"REG2=GPR32_B():r:d:u16",
"EMX_BROADCAST_1TO32_16"
],
"IFORM": "VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512"
},
{
"ICLASS": "VPCMPB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x3F",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL128",
"W0",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=XMM_N3():r:dq:i8",
"REG3=XMM_B3():r:dq:i8",
"IMM0:r:b"
],
"IFORM": "VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512"
},
{
"ICLASS": "VPCMPB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_128",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x3F",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL128",
"W0",
"ZEROING=0",
"UIMM8()",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=XMM_N3():r:dq:i8",
"MEM0:r:dq:i8",
"IMM0:r:b"
],
"IFORM": "VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512"
},
{
"ICLASS": "VPCMPB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x3F",
"V66",
"V0F3A",
"MOD[0b11]",
"MOD=3",
"BCRC=0",
"REG[rrr]",
"RM[nnn]",
"VL256",
"W0",
"ZEROING=0",
"UIMM8()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=YMM_N3():r:qq:i8",
"REG3=YMM_B3():r:qq:i8",
"IMM0:r:b"
],
"IFORM": "VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512"
},
{
"ICLASS": "VPCMPB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_256",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MEMORY_FAULT_SUPPRESSION",
"MASKOP_EVEX",
"DISP8_FULLMEM"
],
"PATTERN": [
"EVV",
"0x3F",
"V66",
"V0F3A",
"MOD[mm]",
"MOD!=3",
"REG[rrr]",
"RM[nnn]",
"BCRC=0",
"MODRM()",
"VL256",
"W0",
"ZEROING=0",
"UIMM8()",
"ESIZE_8_BITS()",
"NELEM_FULLMEM()"
],
"OPERANDS": [
"REG0=MASK_R():w:mskw",
"REG1=MASK1():r:mskw",
"REG2=YMM_N3():r:qq:i8",
"MEM0:r:qq:i8",
"IMM0:r:b"
],
"IFORM": "VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512"
},
{
"ICLASS": "VPCMPB",
"CPL": "3",
"CATEGORY": "AVX512",
"EXTENSION": "AVX512EVEX",
"ISA_SET": "AVX512BW_512",
"EXCEPTIONS": "AVX512-E4",
"REAL_OPCODE": "Y",
"ATTRIBUTES": [
"MASKOP_EVEX"
],
"PATTERN": [
"EVV",
"0x3F",
"V66",
"V0F3A",
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