xilinx_kcu116.v

wire sys_rst;

// ---------- Line 17407 ----------

always @(posedge ic_clk) begin
          sys_rst <= 1'd1;
          if (main_crg_idelayctrl_ic_ready) begin
                  if ((main_crg_idelayctrl_ic_ready_counter != 1'd0)) begin
                          main_crg_idelayctrl_ic_ready_counter <= (main_crg_idelayctrl_ic_ready_counter - 1'd1);
                  end else begin
                          sys_rst <= 1'd0;
                  end
          end
          if (ic_rst) begin
                  sys_rst <= 1'd0;
                  main_crg_idelayctrl_ic_ready_counter <= 6'd63;
          end
  end

  // ---------- Line 17407 ----------


  (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
          .INIT(1'd1)
  ) FDPE (
          .C(sys_clk),
          .CE(1'd1),
          .D(1'd0),
          .PRE(builder_xilinxasyncresetsynchronizerimpl0),
          .Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
  );

  (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
          .INIT(1'd1)
  ) FDPE_1 (
          .C(sys_clk),
          .CE(1'd1),
          .D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
          .PRE(builder_xilinxasyncresetsynchronizerimpl0),
          .Q(sys_rst)
  );