Created
March 8, 2016 10:01
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mp-ring pmu output (second run: showing 1/2/3 process output together)
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| @@@@ processes 1 | |
| @@@@ events l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 518,749,764 51.875 | |
| ref_cycles 0 0.000 | |
| instructions 587,055,371 58.706 | |
| l2_rqsts.all_code_rd 141,671 0.014 | |
| l2_rqsts.all_demand_data_rd 1,013,425 0.101 | |
| l2_rqsts.all_demand_miss 1,813,018 0.181 | |
| l2_rqsts.all_demand_references 2,953,413 0.295 | |
| l2_rqsts.all_pf 1,816,785 0.182 | |
| l2_rqsts.all_rfo 1,798,316 0.180 | |
| l2_rqsts.code_rd_hit 136,865 0.014 | |
| l2_rqsts.code_rd_miss 4,777 0.000 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| 66.66 Mpps ring throughput per process | |
| @@@@ processes 2 | |
| @@@@ events l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 6,662,711,493 666.271 | |
| ref_cycles 0 0.000 | |
| instructions 593,444,647 59.344 | |
| l2_rqsts.all_code_rd 149,164 0.015 | |
| l2_rqsts.all_demand_data_rd 39,003,168 3.900 | |
| l2_rqsts.all_demand_miss 69,252,570 6.925 | |
| l2_rqsts.all_demand_references 80,174,971 8.017 | |
| l2_rqsts.all_pf 66,454,003 6.645 | |
| l2_rqsts.all_rfo 41,022,638 4.102 | |
| l2_rqsts.code_rd_hit 139,881 0.014 | |
| l2_rqsts.code_rd_miss 9,221 0.001 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| 5.25 Mpps ring throughput per process | |
| @@@@ processes 3 | |
| @@@@ events l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 8,060,793,915 806.079 | |
| ref_cycles 0 0.000 | |
| instructions 572,613,917 57.261 | |
| l2_rqsts.all_code_rd 27,037 0.003 | |
| l2_rqsts.all_demand_data_rd 41,862,959 4.186 | |
| l2_rqsts.all_demand_miss 72,621,732 7.262 | |
| l2_rqsts.all_demand_references 82,841,043 8.284 | |
| l2_rqsts.all_pf 70,998,318 7.100 | |
| l2_rqsts.all_rfo 40,951,047 4.095 | |
| l2_rqsts.code_rd_hit 18,422 0.002 | |
| l2_rqsts.code_rd_miss 7,656 0.001 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| 4.34 Mpps ring throughput per process | |
| @@@@ processes 1 | |
| @@@@ events l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 514,882,994 51.488 | |
| ref_cycles 0 0.000 | |
| instructions 587,042,902 58.704 | |
| l2_trans.all_pf 2,054,510 0.205 | |
| l2_trans.all_requests 14,971,587 1.497 | |
| l2_trans.code_rd 138,382 0.014 | |
| l2_trans.demand_data_rd 1,331,650 0.133 | |
| l2_trans.l1d_wb 515,642 0.052 | |
| l2_trans.l2_fill 3,495,905 0.350 | |
| l2_trans.l2_wb 1,580 0.000 | |
| l2_trans.rfo 1,981,668 0.198 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| 67.30 Mpps ring throughput per process | |
| @@@@ processes 2 | |
| @@@@ events l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 6,609,444,414 660.944 | |
| ref_cycles 0 0.000 | |
| instructions 593,112,063 59.311 | |
| l2_trans.all_pf 54,269,864 5.427 | |
| l2_trans.all_requests 393,628,340 39.363 | |
| l2_trans.code_rd 144,216 0.014 | |
| l2_trans.demand_data_rd 31,224,906 3.122 | |
| l2_trans.l1d_wb 430,806 0.043 | |
| l2_trans.l2_fill 108,355,009 10.836 | |
| l2_trans.l2_wb 1,880 0.000 | |
| l2_trans.rfo 41,737,530 4.174 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| 5.29 Mpps ring throughput per process | |
| @@@@ processes 3 | |
| @@@@ events l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 7,626,750,487 762.675 | |
| ref_cycles 0 0.000 | |
| instructions 3,566,455,661 356.646 | |
| l2_trans.all_pf 68,552,612 6.855 | |
| l2_trans.all_requests 451,124,145 45.112 | |
| l2_trans.code_rd 148,487 0.015 | |
| l2_trans.demand_data_rd 40,161,392 4.016 | |
| l2_trans.l1d_wb 9,546,012 0.955 | |
| l2_trans.l2_fill 120,947,897 12.095 | |
| l2_trans.l2_wb 2,561 0.000 | |
| l2_trans.rfo 44,435,421 4.444 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| 4.59 Mpps ring throughput per process | |
| @@@@ processes 1 | |
| @@@@ events mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 546,635,716 54.664 | |
| ref_cycles 0 0.000 | |
| instructions 587,057,747 58.706 | |
| mem_trans_retired.load_latency_gt_128 0 0.000 | |
| mem_trans_retired.load_latency_gt_16 0 0.000 | |
| mem_trans_retired.load_latency_gt_256 0 0.000 | |
| mem_trans_retired.load_latency_gt_32 0 0.000 | |
| mem_trans_retired.load_latency_gt_4 0 0.000 | |
| mem_trans_retired.load_latency_gt_512 0 0.000 | |
| mem_trans_retired.load_latency_gt_64 0 0.000 | |
| mem_trans_retired.load_latency_gt_8 0 0.000 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| 63.43 Mpps ring throughput per process | |
| @@@@ processes 2 | |
| @@@@ events mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 6,671,960,431 667.196 | |
| ref_cycles 0 0.000 | |
| instructions 593,401,545 59.340 | |
| mem_trans_retired.load_latency_gt_128 0 0.000 | |
| mem_trans_retired.load_latency_gt_16 0 0.000 | |
| mem_trans_retired.load_latency_gt_256 0 0.000 | |
| mem_trans_retired.load_latency_gt_32 0 0.000 | |
| mem_trans_retired.load_latency_gt_4 0 0.000 | |
| mem_trans_retired.load_latency_gt_512 0 0.000 | |
| mem_trans_retired.load_latency_gt_64 0 0.000 | |
| mem_trans_retired.load_latency_gt_8 0 0.000 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| 5.24 Mpps ring throughput per process | |
| @@@@ processes 3 | |
| @@@@ events mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 7,752,190,598 775.219 | |
| ref_cycles 0 0.000 | |
| instructions 596,138,869 59.614 | |
| mem_trans_retired.load_latency_gt_128 0 0.000 | |
| mem_trans_retired.load_latency_gt_16 0 0.000 | |
| mem_trans_retired.load_latency_gt_256 0 0.000 | |
| mem_trans_retired.load_latency_gt_32 0 0.000 | |
| mem_trans_retired.load_latency_gt_4 0 0.000 | |
| mem_trans_retired.load_latency_gt_512 0 0.000 | |
| mem_trans_retired.load_latency_gt_64 0 0.000 | |
| mem_trans_retired.load_latency_gt_8 0 0.000 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| 4.51 Mpps ring throughput per process | |
| @@@@ processes 1 | |
| @@@@ events cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 551,134,994 55.113 | |
| ref_cycles 0 0.000 | |
| instructions 587,461,069 58.746 | |
| cycle_activity.cycles_l1d_pending 0 0.000 | |
| cycle_activity.cycles_l2_pending 1,709,020 0.171 | |
| cycle_activity.cycles_ldm_pending 513,246,736 51.325 | |
| cycle_activity.cycles_no_execute 1,283,608,212 128.361 | |
| cycle_activity.stalls_l1d_pending 1,283,608,220 128.361 | |
| cycle_activity.stalls_l2_pending 1,285,317,240 128.532 | |
| cycle_activity.stalls_ldm_pending 1,796,854,956 179.685 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| 62.98 Mpps ring throughput per process | |
| @@@@ processes 2 | |
| @@@@ events cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 6,539,607,131 653.961 | |
| ref_cycles 0 0.000 | |
| instructions 593,000,407 59.300 | |
| cycle_activity.cycles_l1d_pending 0 0.000 | |
| cycle_activity.cycles_l2_pending 3,760,645,024 376.065 | |
| cycle_activity.cycles_ldm_pending 8,785,157,244 878.516 | |
| cycle_activity.cycles_no_execute 24,078,009,752 2407.801 | |
| cycle_activity.stalls_l1d_pending 24,078,009,760 2407.801 | |
| cycle_activity.stalls_l2_pending 27,838,654,784 2783.865 | |
| cycle_activity.stalls_ldm_pending 32,863,167,004 3286.317 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| 5.35 Mpps ring throughput per process | |
| @@@@ processes 3 | |
| @@@@ events cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 7,558,957,039 755.896 | |
| ref_cycles 0 0.000 | |
| instructions 596,832,860 59.683 | |
| cycle_activity.cycles_l1d_pending 0 0.000 | |
| cycle_activity.cycles_l2_pending 3,631,162,469 363.116 | |
| cycle_activity.cycles_ldm_pending 11,592,599,692 1159.260 | |
| cycle_activity.cycles_no_execute 28,343,776,764 2834.378 | |
| cycle_activity.stalls_l1d_pending 28,343,776,764 2834.378 | |
| cycle_activity.stalls_l2_pending 31,974,939,233 3197.494 | |
| cycle_activity.stalls_ldm_pending 39,936,376,456 3993.638 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| 4.63 Mpps ring throughput per process |
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