Created
March 8, 2016 09:56
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mp-ring pmu output
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| @@@@ processes 1 | |
| @@@@ events l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 447,262,250 44.726 | |
| ref_cycles 0 0.000 | |
| instructions 562,040,278 56.204 | |
| l2_rqsts.all_code_rd 13,136 0.001 | |
| l2_rqsts.all_demand_data_rd 1,437,560 0.144 | |
| l2_rqsts.all_demand_miss 1,746,014 0.175 | |
| l2_rqsts.all_demand_references 3,180,017 0.318 | |
| l2_rqsts.all_pf 1,711,779 0.171 | |
| l2_rqsts.all_rfo 1,729,321 0.173 | |
| l2_rqsts.code_rd_hit 9,953 0.001 | |
| l2_rqsts.code_rd_miss 3,153 0.000 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| 73.78 Mpps ring throughput per process | |
| @@@@ processes 1 | |
| @@@@ events l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 436,999,412 43.700 | |
| ref_cycles 0 0.000 | |
| instructions 562,588,505 56.259 | |
| l2_trans.all_pf 1,941,541 0.194 | |
| l2_trans.all_requests 13,079,124 1.308 | |
| l2_trans.code_rd 12,742 0.001 | |
| l2_trans.demand_data_rd 724,961 0.072 | |
| l2_trans.l1d_wb 264,151 0.026 | |
| l2_trans.l2_fill 3,179,414 0.318 | |
| l2_trans.l2_wb 651 0.000 | |
| l2_trans.rfo 1,897,334 0.190 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| 79.16 Mpps ring throughput per process | |
| @@@@ processes 1 | |
| @@@@ events mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 576,874,989 57.687 | |
| ref_cycles 0 0.000 | |
| instructions 587,100,003 58.710 | |
| mem_trans_retired.load_latency_gt_128 0 0.000 | |
| mem_trans_retired.load_latency_gt_16 0 0.000 | |
| mem_trans_retired.load_latency_gt_256 0 0.000 | |
| mem_trans_retired.load_latency_gt_32 0 0.000 | |
| mem_trans_retired.load_latency_gt_4 0 0.000 | |
| mem_trans_retired.load_latency_gt_512 0 0.000 | |
| mem_trans_retired.load_latency_gt_64 0 0.000 | |
| mem_trans_retired.load_latency_gt_8 0 0.000 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| 60.12 Mpps ring throughput per process | |
| @@@@ processes 1 | |
| @@@@ events cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 450,072,876 45.007 | |
| ref_cycles 0 0.000 | |
| instructions 586,978,737 58.698 | |
| cycle_activity.cycles_l1d_pending 0 0.000 | |
| cycle_activity.cycles_l2_pending 1,168,396 0.117 | |
| cycle_activity.cycles_ldm_pending 505,363,526 50.536 | |
| cycle_activity.cycles_no_execute 894,733,884 89.473 | |
| cycle_activity.stalls_l1d_pending 894,733,884 89.473 | |
| cycle_activity.stalls_l2_pending 895,902,280 89.590 | |
| cycle_activity.stalls_ldm_pending 1,400,097,410 140.010 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 1 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| 76.99 Mpps ring throughput per process | |
| @@@@ processes 2 | |
| @@@@ events l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 6,536,174,918 653.617 | |
| ref_cycles 0 0.000 | |
| instructions 593,370,416 59.337 | |
| l2_rqsts.all_code_rd 151,495 0.015 | |
| l2_rqsts.all_demand_data_rd 36,986,583 3.699 | |
| l2_rqsts.all_demand_miss 67,382,757 6.738 | |
| l2_rqsts.all_demand_references 78,468,236 7.847 | |
| l2_rqsts.all_pf 59,919,560 5.992 | |
| l2_rqsts.all_rfo 41,330,158 4.133 | |
| l2_rqsts.code_rd_hit 142,091 0.014 | |
| l2_rqsts.code_rd_miss 9,254 0.001 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| 5.35 Mpps ring throughput per process | |
| @@@@ processes 2 | |
| @@@@ events l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 6,607,369,117 660.737 | |
| ref_cycles 0 0.000 | |
| instructions 593,276,916 59.328 | |
| l2_trans.all_pf 56,692,406 5.669 | |
| l2_trans.all_requests 416,666,022 41.667 | |
| l2_trans.code_rd 146,557 0.015 | |
| l2_trans.demand_data_rd 36,139,870 3.614 | |
| l2_trans.l1d_wb 10,035,335 1.004 | |
| l2_trans.l2_fill 108,884,840 10.888 | |
| l2_trans.l2_wb 2,042 0.000 | |
| l2_trans.rfo 41,633,174 4.163 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| 5.30 Mpps ring throughput per process | |
| @@@@ processes 2 | |
| @@@@ events mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 6,530,423,283 653.042 | |
| ref_cycles 0 0.000 | |
| instructions 593,385,696 59.339 | |
| mem_trans_retired.load_latency_gt_128 0 0.000 | |
| mem_trans_retired.load_latency_gt_16 0 0.000 | |
| mem_trans_retired.load_latency_gt_256 0 0.000 | |
| mem_trans_retired.load_latency_gt_32 0 0.000 | |
| mem_trans_retired.load_latency_gt_4 0 0.000 | |
| mem_trans_retired.load_latency_gt_512 0 0.000 | |
| mem_trans_retired.load_latency_gt_64 0 0.000 | |
| mem_trans_retired.load_latency_gt_8 0 0.000 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| 5.36 Mpps ring throughput per process | |
| @@@@ processes 2 | |
| @@@@ events cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 6,684,321,110 668.432 | |
| ref_cycles 0 0.000 | |
| instructions 593,065,462 59.307 | |
| cycle_activity.cycles_l1d_pending 0 0.000 | |
| cycle_activity.cycles_l2_pending 3,673,422,358 367.342 | |
| cycle_activity.cycles_ldm_pending 8,704,851,772 870.485 | |
| cycle_activity.cycles_no_execute 24,643,683,744 2464.368 | |
| cycle_activity.stalls_l1d_pending 24,643,683,744 2464.368 | |
| cycle_activity.stalls_l2_pending 28,317,106,102 2831.711 | |
| cycle_activity.stalls_ldm_pending 33,348,535,516 3334.854 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 2 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| 5.23 Mpps ring throughput per process | |
| @@@@ processes 3 | |
| @@@@ events l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 7,844,604,239 784.460 | |
| ref_cycles 0 0.000 | |
| instructions 4,251,187,674 425.119 | |
| l2_rqsts.all_code_rd 24,787 0.002 | |
| l2_rqsts.all_demand_data_rd 42,479,470 4.248 | |
| l2_rqsts.all_demand_miss 76,963,237 7.696 | |
| l2_rqsts.all_demand_references 86,797,940 8.680 | |
| l2_rqsts.all_pf 73,248,060 7.325 | |
| l2_rqsts.all_rfo 44,293,683 4.429 | |
| l2_rqsts.code_rd_hit 19,882 0.002 | |
| l2_rqsts.code_rd_miss 4,728 0.000 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_rqsts | |
| 4.46 Mpps ring throughput per process | |
| @@@@ processes 3 | |
| @@@@ events l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 7,713,413,892 771.341 | |
| ref_cycles 0 0.000 | |
| instructions 754,596,597 75.460 | |
| l2_trans.all_pf 57,968,723 5.797 | |
| l2_trans.all_requests 411,229,890 41.123 | |
| l2_trans.code_rd 146,132 0.015 | |
| l2_trans.demand_data_rd 34,782,183 3.478 | |
| l2_trans.l1d_wb 145,901 0.015 | |
| l2_trans.l2_fill 110,701,185 11.070 | |
| l2_trans.l2_wb 2,225 0.000 | |
| l2_trans.rfo 41,763,904 4.176 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: l2_trans | |
| 4.52 Mpps ring throughput per process | |
| @@@@ processes 3 | |
| @@@@ events mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 7,866,510,221 786.651 | |
| ref_cycles 0 0.000 | |
| instructions 4,588,927,105 458.893 | |
| mem_trans_retired.load_latency_gt_128 0 0.000 | |
| mem_trans_retired.load_latency_gt_16 0 0.000 | |
| mem_trans_retired.load_latency_gt_256 0 0.000 | |
| mem_trans_retired.load_latency_gt_32 0 0.000 | |
| mem_trans_retired.load_latency_gt_4 0 0.000 | |
| mem_trans_retired.load_latency_gt_512 0 0.000 | |
| mem_trans_retired.load_latency_gt_64 0 0.000 | |
| mem_trans_retired.load_latency_gt_8 0 0.000 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: mem_trans_retired[.]load_latency_gt_ | |
| 4.45 Mpps ring throughput per process | |
| @@@@ processes 3 | |
| @@@@ events cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| PMU report for child #0: | |
| EVENT TOTAL /packet | |
| cycles 7,709,926,446 770.993 | |
| ref_cycles 0 0.000 | |
| instructions 595,939,581 59.594 | |
| cycle_activity.cycles_l1d_pending 0 0.000 | |
| cycle_activity.cycles_l2_pending 4,201,616,641 420.162 | |
| cycle_activity.cycles_ldm_pending 9,988,456,894 998.846 | |
| cycle_activity.cycles_no_execute 28,901,166,176 2890.117 | |
| cycle_activity.stalls_l1d_pending 28,901,166,176 2890.117 | |
| cycle_activity.stalls_l2_pending 33,102,782,817 3310.278 | |
| cycle_activity.stalls_ldm_pending 38,889,623,070 3888.962 | |
| packet 10,000,000 1.000 | |
| Benchmark configuration: | |
| burst: 100 | |
| writebytes: 0 | |
| processes: 3 | |
| readbytes: 0 | |
| packets: 10000000 | |
| mode: basic | |
| pmuevents: cycle_activity | |
| 4.54 Mpps ring throughput per process |
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