strings fip.bin

gistfile1.txt

➜  boot $ strings fip.bin
CVBL01
WBI"
u>;U
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WGM7
WGM7
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Agcs
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dBi#
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7gu1
77G&
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7gtc
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2024-05-07T08:13:20+00:00
Jb2829:gbeb1483-dirty
2OPENSBI: next_addr=0x%lx arg1=0x%lx
0 E:RESET:%s:%d
0 E:ra=0x%lx
panic
2RSC.
2PLLS/OD.
2PLLS.
2PLLE.
2By pass rtc mode switch
2Use internal 32k
2Switch RTC mode to xtal32k
2st_on_reason=%x
2st_off_reason=%x
2wait idle timeout
2efuse power on fail
2efuse refresh shadow fail
2lock efuse chipsn fail
2efuse power off fail
2P2S/0x%lx/%p.
1 W:LP2_NOMAGIC
0 E:param2_cksum (0x%x/0x%x)
2P2E.
2DPS/0x%x/0x%x.
0 E:ddr_param_cksum (0x%x/0x%x)
2DPE.
1 W:DL cancelled. Load flash. (%d).
0 E:Failed to load DDR param (%d).
2C2S/0x%x/0x%x/0x%x.
2No C906L image.
0 E:blcp_2nd_runaddr (0x%x) is not in DRAM.
0 E:blcp_2nd_size (0x%x) is not in DRAM.
0 E:blcp_2nd_cksum (0x%x/0x%x)
0 E:verify blcp 2nd (%d)
2C2E.
2MS/0x%x/0x%x/0x%x.
2No monitor.
0 E:monitor_runaddr (0x%x) is not in DRAM.
0 E:monitor_size (0x%x) is not in DRAM.
0 E:monitor_cksum (0x%x/0x%x)
0 E:verify monitor (%d)
2ME.
2L2/0x%x.
2L2/0x%x/0x%x/0x%lx/0x%x/0x%x
2COMP/%d.
0 E:loader_2nd_cksum (0x%x/0x%x)
0 E:verify loader 2nd (%d)
0 E:Failed to decompress loader_2nd (%d/%lu)
2Loader_2nd loaded.
0 E:Failed to load rest (%d).
2Jump to monitor at 0x%lx.
2Jump to loader_2nd at 0x%lx.
CVLD02
0 E:%s can't alloc %lu bytes
0 E:%s: dst_size is NULL.
3 I:LZMA1/%p/%p.
3 I:LZMA2/uncomp_size=0x%lx
0 E:LzmaDecode ERROR: %d (status=%d)
3 I:LZMA9/0x%lx
3 I:LZ4/%p/%p.
0 E:dctxStatus=%lu
3 I:dst_size=%lu src_size=%lu ret=%zd
0 E:LZ4F_decompress=%lu
2DCP/%p/0x%lx/%p/0x%lx/%d.
2DCP/0x%lx/%d.
SzAlloc
decompress_lzma
FSBL %s:%s
3 I:sw_info=0x%x
3 I:fip_param1: param_cksum=0x%x param2_loadaddr=0x%x
3 I:CP_STATE_REG=0x%x
2BL2 end.
2DDR init.
2ddr_param[0]=0x%x.
2pkg_type=%x
22nd
2unknown pkg_type=0x%x
2D%x_%x_%x
2DDR2
2DDR3
2unknown vendor=%d
2-512M
2-1G
2-2G
2-4G
2-unknown capacity=%d
2-QFN
2-BGA
2-unknown pkg=%d
0 E:ERROR bist_fail
0 E:bist_result = %x, err_data_odd = %lx, err_data_even = %lx
2DDR BIST FAIL
2DDR BIST PASS
2Data rate=%d.
CVLD02
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<-rq-
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U0s(@;s
U0s(P;s
U0s(`;s
U0s(p;s
U0s(
U0s(
U0s(
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U0s(
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U0s(0<s
U0s(@<s
U0s(P<s
U0s(`<s
U0s(p<s
U0s(
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U0s(
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U0s(
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U0s(
U0s(
U0s( =s
U0s(0=s
U0s(@=s
U0s(P=s
U0s(`=s
U0s(p=s
U0s(
U0s(
U0s(
U0s(
U0s(
U0s(
U0s(
U0s(
U0s(
U0s(
U0s( >s
U0s(0>s
U0s(@>s
U0s(P>s
U0s(`>s
U0s(p>s
U0s(
U0s(
U0s(
U0s(
U0s(
U0s(
U0s(
U0s(
U0s(@
U0s(p
X0s%
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X0s%0
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X0s%P
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(`0s
)@0s`D0	I
Gcg7
pBt!a
pBt!a
Fj	a
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zB{ea
W0s&
W0"d
W0s&
W0"dF
W0s&
W0"d
W0s&
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W0s&
W0"d
W0s&
W0"dA
W0s&
W0"dA
W0s&
W0"dA
W0s&
W0"d
W0s&
W0"dF
W0s&
W0"dA
W0s&
W0"dF
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G,c8k
pBt&
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Byaa
jBkaa
0pN
pBt!a
pBt!a
0Pj
pBt!a
%"dA
"dqEA
GqEc|
&EFce
aUci
AUW#
1+;
3	9A&
0Ach
%c	U
kBl&
jBk&
jBk&
'=Gcs
'=Gcl
'=Gcl
pBtY
)# *
|Bmf
Wc]
jBk>
}Wc
`BdMU
dBiEa
dBiMUEa
jBk&
43	%A
jBkaa
=Gch
E"dA
E"dA
kBl%a
jBk>
kBl>
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E"#(
iBj!a
PV#<
B}Ia
iBj!a
iA#$i
  @cN
|F}n
s*`0c
'``3z
}Gci
`Bd&
`DAc
`Bd	E
kBl&
"d3e
;	9A
;	9AQ
jBkaa
jBk&
jBk&
'AGf
jBkaa
dBi.
iBj&
cvitek,cv181x
&Milk-V DuoS
top_misc_ctrl@3000000
syscon
clk-reset-controller
cvitek,clk-reset
oscillator
fixed-clock
Zosc
clock-controller
cvitek,cv181x-clk
reset-controller
cvitek,reset
restart-controller
cvitek,restart
cvitek,tpu
|tdma
clk_tpu_axi
clk_tpu_fab
res_tdma
res_tpu
res_tpusys
tiu_irq
tdma_irq
cvitek,mon
|pcmon
ddr_ctrl
ddr_phyd
ddr_aximon
ddr_top
mon_irq
wiegand0
cvitek,wiegand
|wiegand
clk_wgn
clk_wgn1
res_wgn
wiegand1
cvitek,wiegand
|wiegand
clk_wgn
clk_wgn1
res_wgn
wiegand2
cvitek,wiegand
|wiegand
clk_wgn
clk_wgn1
res_wgn
saradc
cvitek,saradc
|top_domain_saradc
rtc_domain_saradc
clk_saradc
res_saradc
cvitek,rtc
clk_rtc
sysdma_remap
cvitek,sysdma_remap
dma@0x4330000
snps,dmac-bm
clk_sdma_axi
cv-wd@0x3010000
snps,dw-wdt
pwm@3060000
cvitek,cvi-pwm
pwm@3061000
cvitek,cvi-pwm
pwm@3062000
cvitek,cvi-pwm
pwm@3063000
cvitek,cvi-pwm
pclk
fixed-clock
cvi-spif@10000000
cvitek,cvi-spif
|spif
spiflash
jedec,spi-nor
spi0@04180000
snps,dw-apb-ssi
disabled
spidev@0
rohm,dh2228fv
spi1@04190000
snps,dw-apb-ssi
disabled
spidev@0
rohm,dh2228fv
spi2@041A0000
snps,dw-apb-ssi
disabled
spidev@0
rohm,dh2228fv
spi3@041B0000
snps,dw-apb-ssi
okay
spidev@0
rohm,dh2228fv
okay
serial@04140000
snps,dw-apb-uart
okay
serial@04150000
snps,dw-apb-uart
disabled
serial@04160000
snps,dw-apb-uart
disabled
serial@04170000
snps,dw-apb-uart
disabled
serial@041C0000
snps,dw-apb-uart
okay
gpio@03020000
snps,dw-apb-gpio
gpio-controller@0
snps,dw-apb-gpio-port
porta
wifi_pwr
gpio@03021000
snps,dw-apb-gpio
gpio-controller@1
snps,dw-apb-gpio-port
portb
gpio@03022000
snps,dw-apb-gpio
gpio-controller@2
snps,dw-apb-gpio-port
portc
gpio@03023000
snps,dw-apb-gpio
gpio-controller@3
snps,dw-apb-gpio-port
portd
gpio@05021000
snps,dw-apb-gpio
gpio-controller@4
snps,dw-apb-gpio-port
porte
i2c@04000000
snps,designware-i2c
i2c0
disabled
i2c@04010000
snps,designware-i2c
i2c1
disabled
i2c@04020000
snps,designware-i2c
i2c2
i2c@04030000
snps,designware-i2c
i2c3
i2c@04040000
snps,designware-i2c
i2c4
eth_csrclk
Zeth_csrclk
fixed-clock
eth_ptpclk
Zeth_ptpclk
fixed-clock
stmmac-axi-config
rx-queues-config
queue0
tx-queues-config
queue0
ethernet@4070000
cvitek,ethernet
stmmaceth
ptp_ref
Hrmii
macirq
cv-sd@4310000
cvitek,cv181x-sd
|core_mem
sdhci
wifi-sd@4320000
cvitek,cv181x-sdio
core_mem
okay
i2s_mclk
Zi2s_mclk
fixed-clock
i2s_subsys
cvitek,i2s_tdm_subsys
i2sclk
clk_a0pll
clk_sdma_aud0
clk_sdma_aud1
clk_sdma_aud2
clk_sdma_aud3
i2s@04100000
cvitek,cv1835-i2s
i2sclk
zfalse
i2s@04130000
cvitek,cv1835-i2s
i2sclk
ztrue
adc@0300A100
cvitek,cv182xaadc
i2sclk
dac@0300A000
cvitek,cv182xadac
i2sclk
pdm@0x041D0C00
cvitek,cv1835pdm
i2sclk
sound_adc
cvitek,cv182xa-adc
CV182XA
cv182xa_adc
sound_dac
cvitek,cv182xa-dac
CV182XA
cv182xa_dac
cvitek,cif
|csi_mac0
csi_wrap0
csi_mac1
csi_mac2
pad_ctrl
phy0
phy1
phy-apb0
phy-apb1
clk_cam0
clk_cam1
clk_sys_2
clk_mipimpll
clk_disppll
clk_fpll
csi0
csi1
mipi_tx
cvitek,mipi_tx
clk_disp
clk_dsi
cvitek,sys
base
cvitek,base
|vip_sys
cvitek,vi
clk_sys_0
clk_sys_1
clk_sys_2
clk_sys_3
clk_axi
clk_csi_be
clk_raw
clk_isp_top
clk_csi_mac0
clk_csi_mac1
clk_csi_mac2
vpss
cvitek,vpss
clk_sys_0
clk_sys_1
clk_sys_2
clk_img_d
clk_img_v
clk_sc_top
clk_sc_d
clk_sc_v1
clk_sc_v2
clk_sc_v3
cvitek,ive
|ive_base
ive_irq
cvitek,vo
vip_sys
dphy
clk_disp
clk_dsi
clk_bt
reserved-memory
cvifb
rproc
vdev0vring0
shared-dma-pool
vdev0vring1
shared-dma-pool
vdev0buffer
shared-dma-pool
cvifb
cvitek,fb
|disp
cvitek,dwa
|dwa
clk_sys_0
clk_sys_1
clk_sys_2
clk_sys_3
clk_sys_4
clk_dwa
cvitek,rgn
vcodec
cvitek,asic-vcodec
|h265
h264
vc_ctrl
vc_sbm
vc_addr_remap
clk_axi_video_codec
clk_h264c
clk_apb_h264c
clk_h265c
clk_apb_h265c
clk_vc_src0
clk_vc_src1
clk_vc_src2
clk_cfg_reg_vc
h265
h264
cvitek,asic-jpeg
|jpeg
vc_ctrl
vc_sbm
clk_axi_video_codec
clk_jpeg
clk_apb_jpeg
clk_vc_src0
clk_vc_src1
clk_vc_src2
clk_cfg_reg_vc
jpeg
jpeg
cvi_vc_drv
cvitek,cvi_vc_drv
|vc_ctrl
vc_sbm
vc_addr_remap
rtos_cmdqu
cvitek,rtos_cmdqu
|mailbox
mailbox
usb@04340000
cvitek,cv182x-usb
clk_axi
clk_apb
clk_125m
clk_33k
clk_12m
okay
thermal@030E0000
cvitek,cv181x-thermal
clk_tempsen
tempsen
tempsen
thermal-zones
soc_thermal_0
trips
soc_thermal_trip_0
passive
soc_thermal_trip_1
passive
soc_thermal_crtical_0
critical
cooling-maps
map0
map1
cviaudio_core
cvitek,audio
audio_clock
fixed-clock
aliases
/i2c@04000000
/i2c@04010000
/i2c@04020000
/i2c@04030000
/i2c@04040000
/serial@04140000
/serial@04150000
/serial@04160000
/serial@04170000
/serial@041C0000
/ethernet@4070000
chosen
!serial0
cpus
cpu-map
cluster0
core0
cpu@0
Dcpu
okay
riscv
Prv64imafdvcsu
Zriscv,sv39
interrupt-controller
riscv,cpu-intc
simple-bus
interrupt-controller@70000000
|control
riscv,plic0
clint@74000000
riscv,clint0
cv181x_cooling
clk_cpu
clk_tpu_axi
cvitek,cv181x-cooling
memory@80000000
Dmemory
leds
gpio-leds
led0
heartbeat
heartbeat
blue
led1
netdev
heartbeat
orange
led2
stmmac-0:00:link
heartbeat
green
	compatible
#size-cells
#address-cells
model
#reset-cells
#clock-cells
clock-frequency
clock-output-names
phandle
clocks
reg-names
clock-names
resets
reset-names
interrupts
interrupt-names
interrupt-parent
ch-remap
int_mux_base
int_mux
dma-channels
#dma-cells
dma-requests
chan_allocation_order
chan_priority
block_size
dma-masters
data-width
axi_tr_width
block-ts
#pwm-cells
bus-num
sck-div
sck_mhz
spi-max-frequency
spi-rx-bus-width
spi-tx-bus-width
status
num-cs
reg-shift
reg-io-width
bank-name
gpio-controller
#gpio-cells
snps,nr-gpios
interrupt-controller
gpio-hog
output-high
snps,wr_osr_lmt
snps,rd_osr_lmt
snps,blen
snps,rx-queues-to-use
snps,tx-queues-to-use
tx-fifo-depth
rx-fifo-depth
snps,multicast-filter-bins
snps,perfect-filter-entries
snps,txpbl
snps,rxpbl
snps,aal
snps,axi-config
snps,mtl-rx-config
snps,mtl-tx-config
phy-mode
cap-sd-highspeed
cap-mmc-highspeed
sd-uhs-sdr12
sd-uhs-sdr25
sd-uhs-sdr50
sd-uhs-sdr104
no-sdio
no-mmc
src-frequency
min-frequency
64_addressing
reset_tx_rx_phy
pll_index
pll_reg
cvi-cd-gpios
reg_names
non-removable
no-sd
sd-uhs-ddr50
master_base
dev-id
#sound-dai-cells
dmas
dma-names
capability
mclk_out
clk_source
cvi,model
cvi,card_name
snsr-reset
reset-gpio
pwm-gpio
power-ct-gpio
clock-freq-vip-sys1
ranges
alloc-ranges
no-map
memory-region
dr_mode
g-use-dma
g-rx-fifo-size
g-np-tx-fifo-size
g-tx-fifo-size
vbus-gpio
#thermal-sensor-cells
polling-delay-passive
polling-delay
thermal-sensors
temperature
hysteresis
type
trip
cooling-device
i2c0
i2c1
i2c2
i2c3
i2c4
serial0
serial1
serial2
serial3
serial4
ethernet0
stdout-path
timebase-frequency
device_type
riscv,isa
mmu-type
#interrupt-cells
riscv,ndev
riscv,max-priority
interrupts-extended
clint,has-no-64bit-mmio
dev-freqs
#cooling-cells
linux,default-trigger
function
label
INIT_COUNT
OpenSBI v%d.%d
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|
%s: platform irqchip init failed (error %d)
%s: ipi init failed (error %d)
%s: tlb init failed (error %d)
%s: timer init failed (error %d)
%s: ecall init failed (error %d)
Platform Name             : %s
Platform Features         : %s
Platform HART Count       : %u
Platform IPI Device       : %s
Platform Timer Device     : %s
Platform Console Device   : %s
Platform HSM Device       : %s
Platform SysReset Device  : %s
Firmware Base             : 0x%lx
Firmware Size             : %d KB
Runtime SBI Version       : %d.%d
%s: domain finalize failed (error %d)

%s: PMP configure failed (error %d)
%s: platform final init failed (error %d)
Error %d getting MISA XLEN
Boot HART ID              : %u
Boot HART Domain          : %s
Boot HART ISA             : %s
Boot HART Features        : %s
Boot HART PMP Count       : %d
Boot HART PMP Granularity : %lu
Boot HART PMP Address Bits: %d
Boot HART MHPM Count      : %d

Boot HART
Unknown
init_coldboot
IPI_DATA
mfdeleg
none
TIME_DELTA
hart%d: hart%d tlb fifo full
IPI_TLB_SYNC
IPI_TLB_FIFO
IPI_TLB_FIFO_MEM
trap handler failed
illegal instruction handler failed
misaligned load handler failed
misaligned store handler failed
ecall handler failed
unhandled external interrupt
%s: hart%d: %s (error %d)
%s: hart%d: mcause=0x%016lx mtval=0x%016lx
%s: hart%d: mtval2=0x%016lx mtinst=0x%016lx
%s: hart%d: mepc=0x%016lx mstatus=0x%016lx
%s: hart%d: %s=0x%016lx %s=0x%016lx
%s: hart%d: %s=0x%016lx
sbi_trap_error
model
/cpus
sifive,fu540
sifive,fu540g
sifive,fu540-c000
sifive,hifive-unleashed-a00
iemafdqclbjtpvnsuhkorwxyzg
(null)
%s: %s possible HART mask is NULL
%s: %s possible HART mask has invalid hart %d
%s: %s regions is NULL
%s: %s has invalid region base=0x%lx order=%lu flags=0x%lx
%s: %s does not have firmware region
%s: %s conflict between regions (base=0x%lx order=%lu flags=0x%lx) and (base=0x%lx order=%lu flags=0x%lx)
%s: %s invalid next booting stage mode 0x%lx
%s: %s next booting stage addres 0x%lx can't execute
Domain%d Name        %s: %s
Domain%d Boot HART   %s: %d
Domain%d HARTs       %s:
%s%d%s
Domain%d Next Address%s: 0x%016lx
Domain%d Next Arg1   %s: 0x%016lx
Domain%d Next Mode   %s:
Domain%d Region%02d    %s: 0x%016lx-0x%016lx
M-mode
S-mode
U-mode
Unknown
Domain%d SysReset    %s: %s
%s: No room for %s
%s: sanity checks failed for %s (error %d)
Domain%d Boot HARTID forced to %d
%s: platform domains_init() failed (error %d)
%s: failed to start boot HART %d for %s (error %d)
sanitize_domain
sbi_domain_register
sbi_domain_root_add_memregion
sbi_domain_finalize
%s: Invalid error %d for ext=0x%lx func=0x%lx
sbi_ecall_handler
%sMIDELEG%s: 0x%016lx
%sMEDELEG%s: 0x%016lx
Can not configure pmp for domain %s
because memory region address %lx or size %lx is not in range
mcounteren
time
scounteren
HART_FEATURES
HART_DATA
ERR: Failed stop hart [%u]
%s: ERR: The hart is in invalid state [%u]
sbi_hsm_hart_stop
sbi_hsm_hart_resume_start
sbi_hsm_hart_resume_finish
sbi_hsm_hart_suspend
riscv,clint0
sifive,clint0
/chosen
stdout-path
ucb,htif0
shakti,uart0
sifive,fu540-c000-uart
sifive,uart0
snps,dw-apb-uart
ns16550
ns16550a
sifive,test1
csr-copy
plic-delegate
using-csr-reset
entry-reg
entry-cnt
control-reg
control-val
thead,reset-sample
/aliases
phandle
linux,phandle
compatible
interrupts-extended
riscv,plic0
sifive,plic-1.0.0
base
order
mmio
devices
disabled
status
opensbi,domain,config
opensbi,domain,instance
regions
opensbi,domain,memregion
possible-harts
boot-hart
next-arg1
next-addr
next-mode
system-reset-allowed
opensbi-domain
ranges
invalid address translation
device_type
clock-frequency
current-speed
reg-shift
reg-io-width
riscv,ndev
clint,has-no-64bit-mmio
mmu-type
/reserved-memory
reserved-memory
#size-cells
#address-cells
mmode_resv%d@%x,%x
mmode_resv%d@%x
no-map
%s: hartid%d: invalid csr_num=0x%x
sbi_emulate_csr_read
sbi_emulate_csr_write
ecall_legacy
sbi_tlb_local_hfence_vvma_asid
ecall_time
fdt_irqchip_plic
ecall_base
fdt_reset_sifive
ecall_ipi
sbi_tlb_local_hfence_gvma_vmid
sbi_tlb_local_sfence_vma_asid
__reset_thead_csr_stub
hartid_to_domain_table
hartid_to_scratch_table
ecall_hsm
sbi_tlb_local_fence_i
sbi_tlb_local_hfence_gvma
sbi_hart_expected_trap
sbi_tlb_local_hfence_vvma
fdt_serial_uart8250
root
sifive_fu540
ecall_srst
__fdt_reset_thead_csrr
fdt_ipi_clint
last_hartid_having_scratch
ecall_vendor
__sbi_expected_trap_hext
fdt_timer_clint
sbi_tlb_local_sfence_vma
__thead_pre_start_warm
ecall_rfence
S'F?!
`!C5
IPI_SMODE
IPI_HALT
IPI_TLB
Generic
root
TSRS
TSRS
CNFR
CNFR
EMIT
EMIT
clint
clint
shakti_uart
sifive_uart
uart8250
thead_reset
htif
htif
sifive_test
B3MA
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