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How fast can rust analyzer / emacs lsp-mode autocomplete from a file with 32k pub items?
Raw
1_readme.md

I'm trying to autocomplete from a bindgen module that has about 32k pub entries, the esp idf system library.

Autocompleting a symbol takes 5--10 seconds, is this normal?

The Emacs profiler (below) shows about 2GB of memory usage when trying to autocomplete. Once Emacs actually has the data (i.e., the helm/company thing pops up), searches are fast. The delay seems to be in the communication with rust analyzer and/or parsing the results.

2020 Mac M1 with 16 GB of RAM.

GNU Emacs 28.2 (build 1, aarch64-apple-darwin21.3.0, Carbon Version 165 AppKit 2113.3) of 2022-09-13 from https://ports.macports.org/port/emacs-mac-app/

both (functionp 'json-serialize) and (native-comp-available-p) eval true as per https://www.masteringemacs.org/article/speed-up-emacs-libjansson-native-elisp-compilation

lsp-mode 20220916.806
rust-analyzer 0.3.1203-standalone (2e9f1204c 2022-09-11)
Raw
2_cpu_profile
1185 79% - ...
954 63% - completion-boundaries
954 63% - #<lambda 0x1a8b13a2f1eec54c>
954 63% - if
954 63% - complete-with-action
954 63% - funcall
954 63% - #<lambda 0x9df4bb6abdacc0>
954 63% - let
954 63% - catch
954 63% - let
954 63% - cond
954 63% - let*
604 40% - lsp-request-while-no-input
604 40% + if
282 18% - if
282 18% - let
282 18% - let
264 17% - -map
264 17% - mapcar
261 17% - #<lambda 0x729131f138d43b1>
250 16% - lsp-put
245 16% - or
238 15% - lsp-completion--guess-prefix
229 15% - let*
229 15% - cond
191 12% - lsp-insert-replace-edit?
191 12% - cond
179 11% - -all?
126 8% - let
117 7% - ht-keys
108 7% - ht-map
98 6% - let
98 6% - maphash
53 3% - #<lambda 0x1347068f311b3de4>
53 3% - setq
39 2% - cons
39 2% funcall
47 3% - and
42 2% - let
14 0% - let
14 0% - while
14 0% - and
14 0% - setq
14 0% - funcall
1 0% #<lambda 0x138d7489bf8f6d1>
29 1% - lsp--position-to-point
15 1% - let*
11 0% - lsp--line-character-to-point
11 0% - or
7 0% - let
7 0% - if
7 0% - let*
7 0% - save-restriction
7 0% save-excursion
3 0% lsp:range-start
5 0% - prog1
5 0% puthash
18 1% - if
18 1% - lsp-completion--sort-completions
18 1% - sort
17 1% - #<lambda 0x56884038344e144>
11 0% - let*
2 0% if
68 4% - progn
68 4% - setq
68 4% - lsp-completion--filter-candidates
44 2% - let*
44 2% - if
44 2% - -map
38 2% - if
38 2% - let
38 2% - let
33 2% - -keep
33 2% - let
33 2% - let
33 2% - while
33 2% - let
33 2% - funcall
32 2% - #<lambda 0x5c4ba64c53232fa>
10 0% - let*
6 0% - let*
6 0% - if
6 0% progn
1 0% - #<lambda 0x879ae3325>
1 0% - with-lsp-workspace
1 0% - let
1 0% - lsp:completion-options-resolve-provider?
1 0% - lsp--capability-for-method
1 0% - let*
1 0% - or
1 0% - and
1 0% - lsp--capability
1 0% - lsp-get
1 0% - or
1 0% - lsp--server-capabilities
1 0% - apply
1 0% - lsp-merge
1 0% let
3 0% - if
3 0% - sort
2 0% - #<lambda 0x19ff42949351d875>
1 0% >
2 0% - -map
1 0% - mapcar
1 0% #<lambda 0x73c98daa164>
6 0% - mapcar
6 0% - #<lambda 0x19fe1fa2efd62661>
6 0% - lsp-completion--make-item
6 0% - let*
5 0% - progn
3 0% - let
3 0% - while
2 0% cond
24 1% - cond
24 1% - lsp-completion--to-internal
24 1% - let
24 1% - -map
24 1% - mapcar
21 1% - #<lambda -0xd1e0ba879da1d58>
13 0% - let*
2 0% - list
2 0% - or
2 0% if
222 14% Automatic GC
9 0% - #<lambda -0x159400fb77a5510e>
9 0% - lsp--parser-on-message
9 0% - condition-case
9 0% - let
9 0% - let*
9 0% - let*
9 0% - cond
9 0% - let
8 0% - lsp--on-notification
8 0% - let*
8 0% - let
6 0% - let*
6 0% - let
6 0% - if
6 0% - let
5 0% - if
5 0% - gethash
5 0% - lsp-find-session-folder
5 0% - let
5 0% - -max-by
5 0% - let
5 0% - let
5 0% - while
5 0% - if
5 0% - and
5 0% - or
4 0% - and
2 0% f-dir?
2 0% - lsp-f-ancestor-of?
2 0% - if
2 0% - lsp-f-same?
2 0% - if
2 0% - and
2 0% f-exists?
1 0% - lsp-f-same?
1 0% - if
1 0% - and
1 0% f-exists?
1 0% - funcall
1 0% - lsp--on-diagnostics
1 0% - let*
1 0% let
2 0% - let
2 0% - while
2 0% - if
2 0% - let
2 0% - or
2 0% - if
2 0% - progn
2 0% - lsp--capability
2 0% - lsp-get
2 0% - or
2 0% - lsp--server-capabilities
2 0% - apply
2 0% - lsp-merge
2 0% let
1 0% - lsp--on-request
1 0% - let*
1 0% - let*
1 0% - if
1 0% - lsp--send-request-response
1 0% - let*
1 0% - lsp--send-no-wait
1 0% condition-case
303 20% + command-execute
2 0% + timer-event-handler
2 0% + jit-lock--antiblink-post-command
2 0% + #<lambda -0x18f80c0a9cd6c5d0>
1 0% company-post-command
Raw
2_mem_profile
2,611,841,810 99% - command-execute
2,611,841,810 99% - funcall-interactively
2,603,659,118 99% - helm-company
2,556,678,195 97% - if
2,556,678,195 97% - company-complete
2,556,678,163 97% - company-manual-begin
2,556,678,163 97% - company-auto-begin
2,556,678,163 97% - company--perform
2,556,678,163 97% - company--begin-new
2,556,677,107 97% - company-calculate-candidates
2,556,670,635 97% - company--fetch-candidates
2,556,670,635 97% - company-call-backend-raw
2,556,670,635 97% - apply
2,556,670,635 97% - company-capf
2,556,670,635 97% - company-capf--candidates
2,556,670,635 97% - completion-all-completions
2,556,670,635 97% - completion--nth-completion
2,556,670,635 97% - completion--some
2,556,670,635 97% - #<compiled -0x74f34961ab1ba22>
2,455,664,200 93% - completion-emacs22-all-completions
2,455,664,152 93% - completion-boundaries
2,455,664,152 93% - #<lambda -0x1eef8a0e9457086b>
2,455,664,152 93% - if
2,455,664,152 93% - complete-with-action
2,455,664,152 93% - funcall
2,455,664,152 93% - #<lambda 0x4e4a84b197dd77d>
2,455,664,152 93% - let
2,455,664,152 93% - catch
2,455,664,152 93% - let
2,455,664,152 93% - cond
2,455,664,152 93% - let*
2,455,664,152 93% - lsp-request-while-no-input
2,455,621,664 93% - if
2,371,677,824 90% - lsp-request
2,371,677,824 90% - let*
2,371,677,824 90% - progn
2,371,677,824 90% - if
2,371,677,824 90% - let*
2,371,677,696 90% - unwind-protect
2,371,677,696 90% - progn
2,371,646,284 90% - while
2,371,646,212 90% - catch
641,377,580 24% - accept-process-output
641,353,340 24% - #<lambda -0x18f80c0a9cd6c5d0>
641,353,340 24% - let
641,353,340 24% - while
641,353,340 24% + if
Raw
bindings.rs
This file has been truncated, but you can view the full file.
/* automatically generated by rust-bindgen 0.60.1 */
#[repr(C)]
#[derive(Copy, Clone, Debug, Default, Eq, Hash, Ord, PartialEq, PartialOrd)]
pub struct __BindgenBitfieldUnit<Storage> {
storage: Storage,
}
impl<Storage> __BindgenBitfieldUnit<Storage> {
#[inline]
pub const fn new(storage: Storage) -> Self {
Self { storage }
}
}
impl<Storage> __BindgenBitfieldUnit<Storage>
where
Storage: AsRef<[u8]> + AsMut<[u8]>,
{
#[inline]
pub fn get_bit(&self, index: usize) -> bool {
debug_assert!(index / 8 < self.storage.as_ref().len());
let byte_index = index / 8;
let byte = self.storage.as_ref()[byte_index];
let bit_index = if cfg!(target_endian = "big") {
7 - (index % 8)
} else {
index % 8
};
let mask = 1 << bit_index;
byte & mask == mask
}
#[inline]
pub fn set_bit(&mut self, index: usize, val: bool) {
debug_assert!(index / 8 < self.storage.as_ref().len());
let byte_index = index / 8;
let byte = &mut self.storage.as_mut()[byte_index];
let bit_index = if cfg!(target_endian = "big") {
7 - (index % 8)
} else {
index % 8
};
let mask = 1 << bit_index;
if val {
*byte |= mask;
} else {
*byte &= !mask;
}
}
#[inline]
pub fn get(&self, bit_offset: usize, bit_width: u8) -> u64 {
debug_assert!(bit_width <= 64);
debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
let mut val = 0;
for i in 0..(bit_width as usize) {
if self.get_bit(i + bit_offset) {
let index = if cfg!(target_endian = "big") {
bit_width as usize - 1 - i
} else {
i
};
val |= 1 << index;
}
}
val
}
#[inline]
pub fn set(&mut self, bit_offset: usize, bit_width: u8, val: u64) {
debug_assert!(bit_width <= 64);
debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
for i in 0..(bit_width as usize) {
let mask = 1 << i;
let val_bit_is_set = val & mask == mask;
let index = if cfg!(target_endian = "big") {
bit_width as usize - 1 - i
} else {
i
};
self.set_bit(index + bit_offset, val_bit_is_set);
}
}
}
#[repr(C)]
#[derive(Default)]
pub struct __IncompleteArrayField<T>(::core::marker::PhantomData<T>, [T; 0]);
impl<T> __IncompleteArrayField<T> {
#[inline]
pub const fn new() -> Self {
__IncompleteArrayField(::core::marker::PhantomData, [])
}
#[inline]
pub fn as_ptr(&self) -> *const T {
self as *const _ as *const T
}
#[inline]
pub fn as_mut_ptr(&mut self) -> *mut T {
self as *mut _ as *mut T
}
#[inline]
pub unsafe fn as_slice(&self, len: usize) -> &[T] {
::core::slice::from_raw_parts(self.as_ptr(), len)
}
#[inline]
pub unsafe fn as_mut_slice(&mut self, len: usize) -> &mut [T] {
::core::slice::from_raw_parts_mut(self.as_mut_ptr(), len)
}
}
impl<T> ::core::fmt::Debug for __IncompleteArrayField<T> {
fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
fmt.write_str("__IncompleteArrayField")
}
}
#[repr(C)]
pub struct __BindgenUnionField<T>(::core::marker::PhantomData<T>);
impl<T> __BindgenUnionField<T> {
#[inline]
pub const fn new() -> Self {
__BindgenUnionField(::core::marker::PhantomData)
}
#[inline]
pub unsafe fn as_ref(&self) -> &T {
::core::mem::transmute(self)
}
#[inline]
pub unsafe fn as_mut(&mut self) -> &mut T {
::core::mem::transmute(self)
}
}
impl<T> ::core::default::Default for __BindgenUnionField<T> {
#[inline]
fn default() -> Self {
Self::new()
}
}
impl<T> ::core::clone::Clone for __BindgenUnionField<T> {
#[inline]
fn clone(&self) -> Self {
Self::new()
}
}
impl<T> ::core::marker::Copy for __BindgenUnionField<T> {}
impl<T> ::core::fmt::Debug for __BindgenUnionField<T> {
fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
fmt.write_str("__BindgenUnionField")
}
}
impl<T> ::core::hash::Hash for __BindgenUnionField<T> {
fn hash<H: ::core::hash::Hasher>(&self, _state: &mut H) {}
}
impl<T> ::core::cmp::PartialEq for __BindgenUnionField<T> {
fn eq(&self, _other: &__BindgenUnionField<T>) -> bool {
true
}
}
impl<T> ::core::cmp::Eq for __BindgenUnionField<T> {}
pub const _NEWLIB_VERSION_H__: u32 = 1;
pub const _NEWLIB_VERSION: &[u8; 6usize] = b"3.3.0\0";
pub const __NEWLIB__: u32 = 3;
pub const __NEWLIB_MINOR__: u32 = 3;
pub const __NEWLIB_PATCHLEVEL__: u32 = 0;
pub const _DEFAULT_SOURCE: u32 = 1;
pub const _POSIX_SOURCE: u32 = 1;
pub const _POSIX_C_SOURCE: u32 = 200809;
pub const _ATFILE_SOURCE: u32 = 1;
pub const __ATFILE_VISIBLE: u32 = 1;
pub const __BSD_VISIBLE: u32 = 1;
pub const __GNU_VISIBLE: u32 = 0;
pub const __ISO_C_VISIBLE: u32 = 2011;
pub const __LARGEFILE_VISIBLE: u32 = 0;
pub const __MISC_VISIBLE: u32 = 1;
pub const __POSIX_VISIBLE: u32 = 200809;
pub const __SVID_VISIBLE: u32 = 1;
pub const __XSI_VISIBLE: u32 = 0;
pub const __SSP_FORTIFY_LEVEL: u32 = 0;
pub const _POSIX_THREADS: u32 = 1;
pub const _POSIX_TIMEOUTS: u32 = 1;
pub const _POSIX_TIMERS: u32 = 1;
pub const _POSIX_MONOTONIC_CLOCK: u32 = 200112;
pub const _POSIX_CLOCK_SELECTION: u32 = 200112;
pub const _UNIX98_THREAD_MUTEX_ATTRIBUTES: u32 = 1;
pub const __have_longlong64: u32 = 1;
pub const __have_long32: u32 = 1;
pub const ___int8_t_defined: u32 = 1;
pub const ___int16_t_defined: u32 = 1;
pub const ___int32_t_defined: u32 = 1;
pub const ___int64_t_defined: u32 = 1;
pub const ___int_least8_t_defined: u32 = 1;
pub const ___int_least16_t_defined: u32 = 1;
pub const ___int_least32_t_defined: u32 = 1;
pub const ___int_least64_t_defined: u32 = 1;
pub const __int20: u32 = 2;
pub const __int20__: u32 = 2;
pub const __INT8: &[u8; 3usize] = b"hh\0";
pub const __INT16: &[u8; 2usize] = b"h\0";
pub const __INT64: &[u8; 3usize] = b"ll\0";
pub const __FAST8: &[u8; 3usize] = b"hh\0";
pub const __FAST16: &[u8; 2usize] = b"h\0";
pub const __FAST64: &[u8; 3usize] = b"ll\0";
pub const __LEAST8: &[u8; 3usize] = b"hh\0";
pub const __LEAST16: &[u8; 2usize] = b"h\0";
pub const __LEAST64: &[u8; 3usize] = b"ll\0";
pub const __int8_t_defined: u32 = 1;
pub const __int16_t_defined: u32 = 1;
pub const __int32_t_defined: u32 = 1;
pub const __int64_t_defined: u32 = 1;
pub const __int_least8_t_defined: u32 = 1;
pub const __int_least16_t_defined: u32 = 1;
pub const __int_least32_t_defined: u32 = 1;
pub const __int_least64_t_defined: u32 = 1;
pub const __int_fast8_t_defined: u32 = 1;
pub const __int_fast16_t_defined: u32 = 1;
pub const __int_fast32_t_defined: u32 = 1;
pub const __int_fast64_t_defined: u32 = 1;
pub const WINT_MIN: u32 = 0;
pub const true_: u32 = 1;
pub const false_: u32 = 0;
pub const __bool_true_false_are_defined: u32 = 1;
pub const __NEWLIB_H__: u32 = 1;
pub const _WANT_IO_C99_FORMATS: u32 = 1;
pub const _WANT_IO_LONG_LONG: u32 = 1;
pub const _WANT_IO_POS_ARGS: u32 = 1;
pub const _WANT_REENT_SMALL: u32 = 1;
pub const _REENT_CHECK_VERIFY: u32 = 1;
pub const _MB_LEN_MAX: u32 = 1;
pub const _ICONV_ENABLED: u32 = 1;
pub const HAVE_INITFINI_ARRAY: u32 = 1;
pub const _ATEXIT_DYNAMIC_ALLOC: u32 = 1;
pub const _HAVE_LONG_DOUBLE: u32 = 1;
pub const _HAVE_CC_INHIBIT_LOOP_TO_LIBCALL: u32 = 1;
pub const _LDBL_EQ_DBL: u32 = 1;
pub const _FVWRITE_IN_STREAMIO: u32 = 1;
pub const _FSEEK_OPTIMIZATION: u32 = 1;
pub const _UNBUF_STREAM_OPT: u32 = 1;
pub const _RETARGETABLE_LOCKING: u32 = 1;
pub const _WANT_USE_LONG_TIME_T: u32 = 1;
pub const __OBSOLETE_MATH_DEFAULT: u32 = 1;
pub const __OBSOLETE_MATH: u32 = 1;
pub const __BUFSIZ__: u32 = 128;
pub const __RAND_MAX: u32 = 2147483647;
pub const __GNUCLIKE_ASM: u32 = 3;
pub const __GNUCLIKE___TYPEOF: u32 = 1;
pub const __GNUCLIKE___OFFSETOF: u32 = 1;
pub const __GNUCLIKE___SECTION: u32 = 1;
pub const __GNUCLIKE_CTOR_SECTION_HANDLING: u32 = 1;
pub const __GNUCLIKE_BUILTIN_CONSTANT_P: u32 = 1;
pub const __GNUCLIKE_BUILTIN_VARARGS: u32 = 1;
pub const __GNUCLIKE_BUILTIN_STDARG: u32 = 1;
pub const __GNUCLIKE_BUILTIN_VAALIST: u32 = 1;
pub const __GNUC_VA_LIST_COMPATIBILITY: u32 = 1;
pub const __GNUCLIKE_BUILTIN_NEXT_ARG: u32 = 1;
pub const __GNUCLIKE_BUILTIN_MEMCPY: u32 = 1;
pub const __CC_SUPPORTS_INLINE: u32 = 1;
pub const __CC_SUPPORTS___INLINE: u32 = 1;
pub const __CC_SUPPORTS___INLINE__: u32 = 1;
pub const __CC_SUPPORTS___FUNC__: u32 = 1;
pub const __CC_SUPPORTS_WARNING: u32 = 1;
pub const __CC_SUPPORTS_VARADIC_XXX: u32 = 1;
pub const __CC_SUPPORTS_DYNAMIC_ARRAY_INIT: u32 = 1;
pub const __GNUC_VA_LIST: u32 = 1;
pub const _NULL: u32 = 0;
pub const _ATEXIT_SIZE: u32 = 32;
pub const _RAND48_SEED_0: u32 = 13070;
pub const _RAND48_SEED_1: u32 = 43981;
pub const _RAND48_SEED_2: u32 = 4660;
pub const _RAND48_MULT_0: u32 = 58989;
pub const _RAND48_MULT_1: u32 = 57068;
pub const _RAND48_MULT_2: u32 = 5;
pub const _RAND48_ADD: u32 = 11;
pub const _REENT_EMERGENCY_SIZE: u32 = 25;
pub const _REENT_ASCTIME_SIZE: u32 = 26;
pub const _REENT_SIGNAL_SIZE: u32 = 24;
pub const CONFIG_IDF_CMAKE: u32 = 1;
pub const CONFIG_IDF_TARGET_ARCH_XTENSA: u32 = 1;
pub const CONFIG_IDF_TARGET: &[u8; 8usize] = b"esp32s3\0";
pub const CONFIG_IDF_TARGET_ESP32S3: u32 = 1;
pub const CONFIG_IDF_FIRMWARE_CHIP_ID: u32 = 9;
pub const CONFIG_SDK_TOOLPREFIX: &[u8; 20usize] = b"xtensa-esp32s3-elf-\0";
pub const CONFIG_APP_BUILD_TYPE_APP_2NDBOOT: u32 = 1;
pub const CONFIG_APP_BUILD_GENERATE_BINARIES: u32 = 1;
pub const CONFIG_APP_BUILD_BOOTLOADER: u32 = 1;
pub const CONFIG_APP_BUILD_USE_FLASH_SECTIONS: u32 = 1;
pub const CONFIG_APP_COMPILE_TIME_DATE: u32 = 1;
pub const CONFIG_APP_RETRIEVE_LEN_ELF_SHA: u32 = 16;
pub const CONFIG_BOOTLOADER_OFFSET_IN_FLASH: u32 = 0;
pub const CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE: u32 = 1;
pub const CONFIG_BOOTLOADER_LOG_LEVEL_INFO: u32 = 1;
pub const CONFIG_BOOTLOADER_LOG_LEVEL: u32 = 3;
pub const CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V: u32 = 1;
pub const CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE: u32 = 1;
pub const CONFIG_BOOTLOADER_WDT_ENABLE: u32 = 1;
pub const CONFIG_BOOTLOADER_WDT_TIME_MS: u32 = 9000;
pub const CONFIG_BOOTLOADER_RESERVE_RTC_SIZE: u32 = 0;
pub const CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT: u32 = 1;
pub const CONFIG_SECURE_BOOT_SUPPORTS_RSA: u32 = 1;
pub const CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE: u32 = 1;
pub const CONFIG_BOOT_ROM_LOG_ALWAYS_ON: u32 = 1;
pub const CONFIG_ESPTOOLPY_BAUD_OTHER_VAL: u32 = 115200;
pub const CONFIG_ESPTOOLPY_FLASHMODE_DIO: u32 = 1;
pub const CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR: u32 = 1;
pub const CONFIG_ESPTOOLPY_FLASHMODE: &[u8; 4usize] = b"dio\0";
pub const CONFIG_ESPTOOLPY_FLASHFREQ_80M: u32 = 1;
pub const CONFIG_ESPTOOLPY_FLASHFREQ: &[u8; 4usize] = b"80m\0";
pub const CONFIG_ESPTOOLPY_FLASHSIZE_2MB: u32 = 1;
pub const CONFIG_ESPTOOLPY_FLASHSIZE: &[u8; 4usize] = b"2MB\0";
pub const CONFIG_ESPTOOLPY_FLASHSIZE_DETECT: u32 = 1;
pub const CONFIG_ESPTOOLPY_BEFORE_RESET: u32 = 1;
pub const CONFIG_ESPTOOLPY_BEFORE: &[u8; 14usize] = b"default_reset\0";
pub const CONFIG_ESPTOOLPY_AFTER_RESET: u32 = 1;
pub const CONFIG_ESPTOOLPY_AFTER: &[u8; 11usize] = b"hard_reset\0";
pub const CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B: u32 = 1;
pub const CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL: u32 = 115200;
pub const CONFIG_ESPTOOLPY_MONITOR_BAUD: u32 = 115200;
pub const CONFIG_PARTITION_TABLE_SINGLE_APP: u32 = 1;
pub const CONFIG_PARTITION_TABLE_CUSTOM_FILENAME: &[u8; 15usize] = b"partitions.csv\0";
pub const CONFIG_PARTITION_TABLE_FILENAME: &[u8; 25usize] = b"partitions_singleapp.csv\0";
pub const CONFIG_PARTITION_TABLE_OFFSET: u32 = 32768;
pub const CONFIG_PARTITION_TABLE_MD5: u32 = 1;
pub const CONFIG_COMPILER_OPTIMIZATION_SIZE: u32 = 1;
pub const CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE: u32 = 1;
pub const CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL: u32 = 2;
pub const CONFIG_COMPILER_HIDE_PATHS_MACROS: u32 = 1;
pub const CONFIG_COMPILER_CXX_EXCEPTIONS: u32 = 1;
pub const CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE: u32 = 0;
pub const CONFIG_COMPILER_STACK_CHECK_MODE_NONE: u32 = 1;
pub const CONFIG_APPTRACE_DEST_NONE: u32 = 1;
pub const CONFIG_APPTRACE_LOCK_ENABLE: u32 = 1;
pub const CONFIG_COAP_MBEDTLS_PSK: u32 = 1;
pub const CONFIG_COAP_LOG_DEFAULT_LEVEL: u32 = 0;
pub const CONFIG_ADC_DISABLE_DAC: u32 = 1;
pub const CONFIG_SPI_MASTER_ISR_IN_IRAM: u32 = 1;
pub const CONFIG_SPI_SLAVE_ISR_IN_IRAM: u32 = 1;
pub const CONFIG_EFUSE_MAX_BLK_LEN: u32 = 256;
pub const CONFIG_ESP_TLS_USING_MBEDTLS: u32 = 1;
pub const CONFIG_ESP_TLS_USE_DS_PERIPHERAL: u32 = 1;
pub const CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160: u32 = 1;
pub const CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ: u32 = 160;
pub const CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB: u32 = 1;
pub const CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE: u32 = 16384;
pub const CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS: u32 = 1;
pub const CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS: u32 = 8;
pub const CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B: u32 = 1;
pub const CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE: u32 = 32;
pub const CONFIG_ESP32S3_DATA_CACHE_32KB: u32 = 1;
pub const CONFIG_ESP32S3_DATA_CACHE_SIZE: u32 = 32768;
pub const CONFIG_ESP32S3_DATA_CACHE_8WAYS: u32 = 1;
pub const CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS: u32 = 8;
pub const CONFIG_ESP32S3_DATA_CACHE_LINE_32B: u32 = 1;
pub const CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE: u32 = 32;
pub const CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM: u32 = 0;
pub const CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM: u32 = 0;
pub const CONFIG_ESP32S3_DEBUG_OCDAWARE: u32 = 1;
pub const CONFIG_ESP32S3_BROWNOUT_DET: u32 = 1;
pub const CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7: u32 = 1;
pub const CONFIG_ESP32S3_BROWNOUT_DET_LVL: u32 = 7;
pub const CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1: u32 = 1;
pub const CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC: u32 = 1;
pub const CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES: u32 = 1024;
pub const CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY: u32 = 2000;
pub const CONFIG_ESP_ERR_TO_NAME_LOOKUP: u32 = 1;
pub const CONFIG_ETH_ENABLED: u32 = 1;
pub const CONFIG_ETH_USE_SPI_ETHERNET: u32 = 1;
pub const CONFIG_ESP_EVENT_POST_FROM_ISR: u32 = 1;
pub const CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR: u32 = 1;
pub const CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS: u32 = 1;
pub const CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH: u32 = 1;
pub const CONFIG_HTTPD_MAX_REQ_HDR_LEN: u32 = 512;
pub const CONFIG_HTTPD_MAX_URI_LEN: u32 = 512;
pub const CONFIG_HTTPD_ERR_RESP_NO_DELAY: u32 = 1;
pub const CONFIG_HTTPD_PURGE_BUF_LEN: u32 = 32;
pub const CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA: u32 = 1;
pub const CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP: u32 = 1;
pub const CONFIG_ESP_MAC_ADDR_UNIVERSE_BT: u32 = 1;
pub const CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH: u32 = 1;
pub const CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR: u32 = 1;
pub const CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES: u32 = 4;
pub const CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND: u32 = 1;
pub const CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND: u32 = 1;
pub const CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND: u32 = 1;
pub const CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU: u32 = 1;
pub const CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB: u32 = 1;
pub const CONFIG_ESP_IPC_TASK_STACK_SIZE: u32 = 1536;
pub const CONFIG_ESP_IPC_USES_CALLERS_PRIORITY: u32 = 1;
pub const CONFIG_ESP_IPC_ISR_ENABLE: u32 = 1;
pub const CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE: u32 = 32;
pub const CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL: u32 = 120;
pub const CONFIG_ESP_NETIF_TCPIP_LWIP: u32 = 1;
pub const CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER: u32 = 1;
pub const CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE: u32 = 1;
pub const CONFIG_ESP_PHY_MAX_WIFI_TX_POWER: u32 = 20;
pub const CONFIG_ESP_PHY_MAX_TX_POWER: u32 = 20;
pub const CONFIG_ESP_PHY_ENABLE_USB: u32 = 1;
pub const CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP: u32 = 1;
pub const CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP: u32 = 1;
pub const CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT: u32 = 1;
pub const CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK: u32 = 1;
pub const CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP: u32 = 1;
pub const CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE: u32 = 32;
pub const CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE: u32 = 4608;
pub const CONFIG_ESP_MAIN_TASK_STACK_SIZE: u32 = 16000;
pub const CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0: u32 = 1;
pub const CONFIG_ESP_MAIN_TASK_AFFINITY: u32 = 0;
pub const CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE: u32 = 2048;
pub const CONFIG_ESP_CONSOLE_UART_DEFAULT: u32 = 1;
pub const CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG: u32 = 1;
pub const CONFIG_ESP_CONSOLE_UART: u32 = 1;
pub const CONFIG_ESP_CONSOLE_MULTIPLE_UART: u32 = 1;
pub const CONFIG_ESP_CONSOLE_UART_NUM: u32 = 0;
pub const CONFIG_ESP_CONSOLE_UART_BAUDRATE: u32 = 115200;
pub const CONFIG_ESP_INT_WDT: u32 = 1;
pub const CONFIG_ESP_INT_WDT_TIMEOUT_MS: u32 = 300;
pub const CONFIG_ESP_INT_WDT_CHECK_CPU1: u32 = 1;
pub const CONFIG_ESP_TASK_WDT: u32 = 1;
pub const CONFIG_ESP_TASK_WDT_TIMEOUT_S: u32 = 5;
pub const CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0: u32 = 1;
pub const CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1: u32 = 1;
pub const CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4: u32 = 1;
pub const CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER: u32 = 1;
pub const CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER: u32 = 1;
pub const CONFIG_ESP_TIMER_TASK_STACK_SIZE: u32 = 3584;
pub const CONFIG_ESP_TIMER_INTERRUPT_LEVEL: u32 = 1;
pub const CONFIG_ESP_TIMER_IMPL_SYSTIMER: u32 = 1;
pub const CONFIG_ESP32_WIFI_ENABLED: u32 = 1;
pub const CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM: u32 = 10;
pub const CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM: u32 = 32;
pub const CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER: u32 = 1;
pub const CONFIG_ESP32_WIFI_TX_BUFFER_TYPE: u32 = 1;
pub const CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM: u32 = 32;
pub const CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED: u32 = 1;
pub const CONFIG_ESP32_WIFI_TX_BA_WIN: u32 = 6;
pub const CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED: u32 = 1;
pub const CONFIG_ESP32_WIFI_RX_BA_WIN: u32 = 6;
pub const CONFIG_ESP32_WIFI_NVS_ENABLED: u32 = 1;
pub const CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0: u32 = 1;
pub const CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN: u32 = 752;
pub const CONFIG_ESP32_WIFI_MGMT_SBUF_NUM: u32 = 32;
pub const CONFIG_ESP32_WIFI_IRAM_OPT: u32 = 1;
pub const CONFIG_ESP32_WIFI_RX_IRAM_OPT: u32 = 1;
pub const CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE: u32 = 1;
pub const CONFIG_ESP_WIFI_SOFTAP_SUPPORT: u32 = 1;
pub const CONFIG_ESP_COREDUMP_ENABLE_TO_NONE: u32 = 1;
pub const CONFIG_FATFS_CODEPAGE_437: u32 = 1;
pub const CONFIG_FATFS_CODEPAGE: u32 = 437;
pub const CONFIG_FATFS_LFN_NONE: u32 = 1;
pub const CONFIG_FATFS_FS_LOCK: u32 = 0;
pub const CONFIG_FATFS_TIMEOUT_MS: u32 = 10000;
pub const CONFIG_FATFS_PER_FILE_CACHE: u32 = 1;
pub const CONFIG_FMB_COMM_MODE_TCP_EN: u32 = 1;
pub const CONFIG_FMB_TCP_PORT_DEFAULT: u32 = 502;
pub const CONFIG_FMB_TCP_PORT_MAX_CONN: u32 = 5;
pub const CONFIG_FMB_TCP_CONNECTION_TOUT_SEC: u32 = 20;
pub const CONFIG_FMB_COMM_MODE_RTU_EN: u32 = 1;
pub const CONFIG_FMB_COMM_MODE_ASCII_EN: u32 = 1;
pub const CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND: u32 = 150;
pub const CONFIG_FMB_MASTER_DELAY_MS_CONVERT: u32 = 200;
pub const CONFIG_FMB_QUEUE_LENGTH: u32 = 20;
pub const CONFIG_FMB_PORT_TASK_STACK_SIZE: u32 = 4096;
pub const CONFIG_FMB_SERIAL_BUF_SIZE: u32 = 256;
pub const CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB: u32 = 8;
pub const CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS: u32 = 1000;
pub const CONFIG_FMB_PORT_TASK_PRIO: u32 = 10;
pub const CONFIG_FMB_PORT_TASK_AFFINITY_CPU0: u32 = 1;
pub const CONFIG_FMB_PORT_TASK_AFFINITY: u32 = 0;
pub const CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT: u32 = 1;
pub const CONFIG_FMB_CONTROLLER_SLAVE_ID: u32 = 1122867;
pub const CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT: u32 = 20;
pub const CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE: u32 = 20;
pub const CONFIG_FMB_CONTROLLER_STACK_SIZE: u32 = 4096;
pub const CONFIG_FMB_EVENT_QUEUE_TIMEOUT: u32 = 20;
pub const CONFIG_FMB_TIMER_GROUP: u32 = 0;
pub const CONFIG_FMB_TIMER_INDEX: u32 = 0;
pub const CONFIG_FMB_MASTER_TIMER_GROUP: u32 = 0;
pub const CONFIG_FMB_MASTER_TIMER_INDEX: u32 = 0;
pub const CONFIG_FREERTOS_NO_AFFINITY: u32 = 2147483647;
pub const CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER: u32 = 1;
pub const CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1: u32 = 1;
pub const CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER: u32 = 1;
pub const CONFIG_FREERTOS_HZ: u32 = 100;
pub const CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION: u32 = 1;
pub const CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY: u32 = 1;
pub const CONFIG_FREERTOS_INTERRUPT_BACKTRACE: u32 = 1;
pub const CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS: u32 = 1;
pub const CONFIG_FREERTOS_ASSERT_FAIL_ABORT: u32 = 1;
pub const CONFIG_FREERTOS_IDLE_TASK_STACKSIZE: u32 = 1536;
pub const CONFIG_FREERTOS_ISR_STACKSIZE: u32 = 1536;
pub const CONFIG_FREERTOS_MAX_TASK_NAME_LEN: u32 = 16;
pub const CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION: u32 = 1;
pub const CONFIG_FREERTOS_TIMER_TASK_PRIORITY: u32 = 1;
pub const CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH: u32 = 2048;
pub const CONFIG_FREERTOS_TIMER_QUEUE_LENGTH: u32 = 10;
pub const CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE: u32 = 0;
pub const CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER: u32 = 1;
pub const CONFIG_FREERTOS_DEBUG_OCDAWARE: u32 = 1;
pub const CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT: u32 = 1;
pub const CONFIG_HAL_ASSERTION_EQUALS_SYSTEM: u32 = 1;
pub const CONFIG_HAL_DEFAULT_ASSERTION_LEVEL: u32 = 2;
pub const CONFIG_HEAP_POISONING_DISABLED: u32 = 1;
pub const CONFIG_HEAP_TRACING_OFF: u32 = 1;
pub const CONFIG_LOG_DEFAULT_LEVEL_DEBUG: u32 = 1;
pub const CONFIG_LOG_DEFAULT_LEVEL: u32 = 4;
pub const CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT: u32 = 1;
pub const CONFIG_LOG_MAXIMUM_LEVEL: u32 = 4;
pub const CONFIG_LOG_COLORS: u32 = 1;
pub const CONFIG_LOG_TIMESTAMP_SOURCE_RTOS: u32 = 1;
pub const CONFIG_LWIP_LOCAL_HOSTNAME: &[u8; 10usize] = b"espressif\0";
pub const CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES: u32 = 1;
pub const CONFIG_LWIP_TIMERS_ONDEMAND: u32 = 1;
pub const CONFIG_LWIP_MAX_SOCKETS: u32 = 10;
pub const CONFIG_LWIP_SO_REUSE: u32 = 1;
pub const CONFIG_LWIP_SO_REUSE_RXTOALL: u32 = 1;
pub const CONFIG_LWIP_IP4_FRAG: u32 = 1;
pub const CONFIG_LWIP_IP6_FRAG: u32 = 1;
pub const CONFIG_LWIP_ESP_GRATUITOUS_ARP: u32 = 1;
pub const CONFIG_LWIP_GARP_TMR_INTERVAL: u32 = 60;
pub const CONFIG_LWIP_TCPIP_RECVMBOX_SIZE: u32 = 32;
pub const CONFIG_LWIP_DHCP_DOES_ARP_CHECK: u32 = 1;
pub const CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID: u32 = 1;
pub const CONFIG_LWIP_DHCP_OPTIONS_LEN: u32 = 68;
pub const CONFIG_LWIP_DHCPS: u32 = 1;
pub const CONFIG_LWIP_DHCPS_LEASE_UNIT: u32 = 60;
pub const CONFIG_LWIP_DHCPS_MAX_STATION_NUM: u32 = 8;
pub const CONFIG_LWIP_IPV6: u32 = 1;
pub const CONFIG_LWIP_IPV6_NUM_ADDRESSES: u32 = 3;
pub const CONFIG_LWIP_NETIF_LOOPBACK: u32 = 1;
pub const CONFIG_LWIP_LOOPBACK_MAX_PBUFS: u32 = 8;
pub const CONFIG_LWIP_MAX_ACTIVE_TCP: u32 = 16;
pub const CONFIG_LWIP_MAX_LISTENING_TCP: u32 = 16;
pub const CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION: u32 = 1;
pub const CONFIG_LWIP_TCP_MAXRTX: u32 = 12;
pub const CONFIG_LWIP_TCP_SYNMAXRTX: u32 = 12;
pub const CONFIG_LWIP_TCP_MSS: u32 = 1440;
pub const CONFIG_LWIP_TCP_TMR_INTERVAL: u32 = 250;
pub const CONFIG_LWIP_TCP_MSL: u32 = 60000;
pub const CONFIG_LWIP_TCP_SND_BUF_DEFAULT: u32 = 5744;
pub const CONFIG_LWIP_TCP_WND_DEFAULT: u32 = 5744;
pub const CONFIG_LWIP_TCP_RECVMBOX_SIZE: u32 = 6;
pub const CONFIG_LWIP_TCP_QUEUE_OOSEQ: u32 = 1;
pub const CONFIG_LWIP_TCP_OVERSIZE_MSS: u32 = 1;
pub const CONFIG_LWIP_TCP_RTO_TIME: u32 = 1500;
pub const CONFIG_LWIP_MAX_UDP_PCBS: u32 = 16;
pub const CONFIG_LWIP_UDP_RECVMBOX_SIZE: u32 = 6;
pub const CONFIG_LWIP_CHECKSUM_CHECK_ICMP: u32 = 1;
pub const CONFIG_LWIP_TCPIP_TASK_STACK_SIZE: u32 = 3072;
pub const CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY: u32 = 1;
pub const CONFIG_LWIP_TCPIP_TASK_AFFINITY: u32 = 2147483647;
pub const CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE: u32 = 3;
pub const CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS: u32 = 5;
pub const CONFIG_LWIP_ICMP: u32 = 1;
pub const CONFIG_LWIP_MAX_RAW_PCBS: u32 = 16;
pub const CONFIG_LWIP_SNTP_MAX_SERVERS: u32 = 1;
pub const CONFIG_LWIP_SNTP_UPDATE_DELAY: u32 = 3600000;
pub const CONFIG_LWIP_ESP_LWIP_ASSERT: u32 = 1;
pub const CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT: u32 = 1;
pub const CONFIG_LWIP_HOOK_IP6_ROUTE_NONE: u32 = 1;
pub const CONFIG_LWIP_HOOK_ND6_GET_GW_NONE: u32 = 1;
pub const CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE: u32 = 1;
pub const CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC: u32 = 1;
pub const CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN: u32 = 1;
pub const CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN: u32 = 16384;
pub const CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN: u32 = 4096;
pub const CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE: u32 = 1;
pub const CONFIG_MBEDTLS_CERTIFICATE_BUNDLE: u32 = 1;
pub const CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL: u32 = 1;
pub const CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS: u32 = 200;
pub const CONFIG_MBEDTLS_HARDWARE_AES: u32 = 1;
pub const CONFIG_MBEDTLS_AES_USE_INTERRUPT: u32 = 1;
pub const CONFIG_MBEDTLS_HARDWARE_MPI: u32 = 1;
pub const CONFIG_MBEDTLS_HARDWARE_SHA: u32 = 1;
pub const CONFIG_MBEDTLS_ROM_MD5: u32 = 1;
pub const CONFIG_MBEDTLS_HAVE_TIME: u32 = 1;
pub const CONFIG_MBEDTLS_ECDSA_DETERMINISTIC: u32 = 1;
pub const CONFIG_MBEDTLS_SHA512_C: u32 = 1;
pub const CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT: u32 = 1;
pub const CONFIG_MBEDTLS_TLS_SERVER: u32 = 1;
pub const CONFIG_MBEDTLS_TLS_CLIENT: u32 = 1;
pub const CONFIG_MBEDTLS_TLS_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_RSA: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA: u32 = 1;
pub const CONFIG_MBEDTLS_SSL_RENEGOTIATION: u32 = 1;
pub const CONFIG_MBEDTLS_SSL_PROTO_TLS1: u32 = 1;
pub const CONFIG_MBEDTLS_SSL_PROTO_TLS1_1: u32 = 1;
pub const CONFIG_MBEDTLS_SSL_PROTO_TLS1_2: u32 = 1;
pub const CONFIG_MBEDTLS_SSL_ALPN: u32 = 1;
pub const CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS: u32 = 1;
pub const CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE: u32 = 1;
pub const CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE: u32 = 1;
pub const CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS: u32 = 1;
pub const CONFIG_MBEDTLS_AES_C: u32 = 1;
pub const CONFIG_MBEDTLS_RC4_DISABLED: u32 = 1;
pub const CONFIG_MBEDTLS_CCM_C: u32 = 1;
pub const CONFIG_MBEDTLS_GCM_C: u32 = 1;
pub const CONFIG_MBEDTLS_PEM_PARSE_C: u32 = 1;
pub const CONFIG_MBEDTLS_PEM_WRITE_C: u32 = 1;
pub const CONFIG_MBEDTLS_X509_CRL_PARSE_C: u32 = 1;
pub const CONFIG_MBEDTLS_X509_CSR_PARSE_C: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_C: u32 = 1;
pub const CONFIG_MBEDTLS_ECDH_C: u32 = 1;
pub const CONFIG_MBEDTLS_ECDSA_C: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_NIST_OPTIM: u32 = 1;
pub const CONFIG_MDNS_MAX_SERVICES: u32 = 10;
pub const CONFIG_MDNS_TASK_PRIORITY: u32 = 1;
pub const CONFIG_MDNS_TASK_STACK_SIZE: u32 = 4096;
pub const CONFIG_MDNS_TASK_AFFINITY_CPU0: u32 = 1;
pub const CONFIG_MDNS_TASK_AFFINITY: u32 = 0;
pub const CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS: u32 = 2000;
pub const CONFIG_MDNS_TIMER_PERIOD_MS: u32 = 100;
pub const CONFIG_MDNS_MULTIPLE_INSTANCE: u32 = 1;
pub const CONFIG_MQTT_PROTOCOL_311: u32 = 1;
pub const CONFIG_MQTT_TRANSPORT_SSL: u32 = 1;
pub const CONFIG_MQTT_TRANSPORT_WEBSOCKET: u32 = 1;
pub const CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE: u32 = 1;
pub const CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF: u32 = 1;
pub const CONFIG_NEWLIB_STDIN_LINE_ENDING_CR: u32 = 1;
pub const CONFIG_OPENSSL_ERROR_STACK: u32 = 1;
pub const CONFIG_OPENSSL_ASSERT_EXIT: u32 = 1;
pub const CONFIG_PTHREAD_TASK_PRIO_DEFAULT: u32 = 5;
pub const CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT: u32 = 3072;
pub const CONFIG_PTHREAD_STACK_MIN: u32 = 768;
pub const CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY: u32 = 1;
pub const CONFIG_PTHREAD_TASK_CORE_DEFAULT: i32 = -1;
pub const CONFIG_PTHREAD_TASK_NAME_DEFAULT: &[u8; 8usize] = b"pthread\0";
pub const CONFIG_SPI_FLASH_ROM_DRIVER_PATCH: u32 = 1;
pub const CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS: u32 = 1;
pub const CONFIG_SPI_FLASH_YIELD_DURING_ERASE: u32 = 1;
pub const CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS: u32 = 20;
pub const CONFIG_SPI_FLASH_ERASE_YIELD_TICKS: u32 = 1;
pub const CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE: u32 = 8192;
pub const CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP: u32 = 1;
pub const CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP: u32 = 1;
pub const CONFIG_SPI_FLASH_SUPPORT_GD_CHIP: u32 = 1;
pub const CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP: u32 = 1;
pub const CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP: u32 = 1;
pub const CONFIG_SPI_FLASH_SUPPORT_TH_CHIP: u32 = 1;
pub const CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP: u32 = 1;
pub const CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE: u32 = 1;
pub const CONFIG_SPIFFS_MAX_PARTITIONS: u32 = 3;
pub const CONFIG_SPIFFS_CACHE: u32 = 1;
pub const CONFIG_SPIFFS_CACHE_WR: u32 = 1;
pub const CONFIG_SPIFFS_PAGE_CHECK: u32 = 1;
pub const CONFIG_SPIFFS_GC_MAX_RUNS: u32 = 10;
pub const CONFIG_SPIFFS_PAGE_SIZE: u32 = 256;
pub const CONFIG_SPIFFS_OBJ_NAME_LEN: u32 = 32;
pub const CONFIG_SPIFFS_USE_MAGIC: u32 = 1;
pub const CONFIG_SPIFFS_USE_MAGIC_LENGTH: u32 = 1;
pub const CONFIG_SPIFFS_META_LENGTH: u32 = 4;
pub const CONFIG_SPIFFS_USE_MTIME: u32 = 1;
pub const CONFIG_WS_TRANSPORT: u32 = 1;
pub const CONFIG_WS_BUFFER_SIZE: u32 = 1024;
pub const CONFIG_UNITY_ENABLE_FLOAT: u32 = 1;
pub const CONFIG_UNITY_ENABLE_DOUBLE: u32 = 1;
pub const CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER: u32 = 1;
pub const CONFIG_USB_OTG_SUPPORTED: u32 = 1;
pub const CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE: u32 = 256;
pub const CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED: u32 = 1;
pub const CONFIG_VFS_SUPPORT_IO: u32 = 1;
pub const CONFIG_VFS_SUPPORT_DIR: u32 = 1;
pub const CONFIG_VFS_SUPPORT_SELECT: u32 = 1;
pub const CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT: u32 = 1;
pub const CONFIG_VFS_SUPPORT_TERMIOS: u32 = 1;
pub const CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS: u32 = 1;
pub const CONFIG_WL_SECTOR_SIZE_4096: u32 = 1;
pub const CONFIG_WL_SECTOR_SIZE: u32 = 4096;
pub const CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES: u32 = 16;
pub const CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT: u32 = 30;
pub const CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION: u32 = 1;
pub const CONFIG_WPA_MBEDTLS_CRYPTO: u32 = 1;
pub const CONFIG_ADC2_DISABLE_DAC: u32 = 1;
pub const CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE: u32 = 1;
pub const CONFIG_CONSOLE_UART_DEFAULT: u32 = 1;
pub const CONFIG_CXX_EXCEPTIONS: u32 = 1;
pub const CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE: u32 = 0;
pub const CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND: u32 = 1;
pub const CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP: u32 = 1;
pub const CONFIG_ESP32S2_PANIC_PRINT_REBOOT: u32 = 1;
pub const CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP: u32 = 1;
pub const CONFIG_ESP32_APPTRACE_DEST_NONE: u32 = 1;
pub const CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY: u32 = 1;
pub const CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE: u32 = 1;
pub const CONFIG_ESP32_PANIC_PRINT_REBOOT: u32 = 1;
pub const CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE: u32 = 1;
pub const CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER: u32 = 20;
pub const CONFIG_ESP32_PTHREAD_STACK_MIN: u32 = 768;
pub const CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT: &[u8; 8usize] = b"pthread\0";
pub const CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT: u32 = 5;
pub const CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT: u32 = 3072;
pub const CONFIG_ESP_GRATUITOUS_ARP: u32 = 1;
pub const CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU: u32 = 1;
pub const CONFIG_FLASHMODE_DIO: u32 = 1;
pub const CONFIG_GARP_TMR_INTERVAL: u32 = 60;
pub const CONFIG_INT_WDT: u32 = 1;
pub const CONFIG_INT_WDT_CHECK_CPU1: u32 = 1;
pub const CONFIG_INT_WDT_TIMEOUT_MS: u32 = 300;
pub const CONFIG_IPC_TASK_STACK_SIZE: u32 = 1536;
pub const CONFIG_LOG_BOOTLOADER_LEVEL_INFO: u32 = 1;
pub const CONFIG_MAIN_TASK_STACK_SIZE: u32 = 16000;
pub const CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE: u32 = 20;
pub const CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT: u32 = 20;
pub const CONFIG_MB_CONTROLLER_SLAVE_ID: u32 = 1122867;
pub const CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT: u32 = 1;
pub const CONFIG_MB_CONTROLLER_STACK_SIZE: u32 = 4096;
pub const CONFIG_MB_EVENT_QUEUE_TIMEOUT: u32 = 20;
pub const CONFIG_MB_MASTER_DELAY_MS_CONVERT: u32 = 200;
pub const CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND: u32 = 150;
pub const CONFIG_MB_QUEUE_LENGTH: u32 = 20;
pub const CONFIG_MB_SERIAL_BUF_SIZE: u32 = 256;
pub const CONFIG_MB_SERIAL_TASK_PRIO: u32 = 10;
pub const CONFIG_MB_SERIAL_TASK_STACK_SIZE: u32 = 4096;
pub const CONFIG_MB_TIMER_GROUP: u32 = 0;
pub const CONFIG_MB_TIMER_INDEX: u32 = 0;
pub const CONFIG_MONITOR_BAUD_115200B: u32 = 1;
pub const CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED: u32 = 1;
pub const CONFIG_OPTIMIZATION_LEVEL_RELEASE: u32 = 1;
pub const CONFIG_POST_EVENTS_FROM_IRAM_ISR: u32 = 1;
pub const CONFIG_POST_EVENTS_FROM_ISR: u32 = 1;
pub const CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS: u32 = 1;
pub const CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS: u32 = 1;
pub const CONFIG_STACK_CHECK_NONE: u32 = 1;
pub const CONFIG_SUPPORT_TERMIOS: u32 = 1;
pub const CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT: u32 = 1;
pub const CONFIG_SYSTEM_EVENT_QUEUE_SIZE: u32 = 32;
pub const CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE: u32 = 4608;
pub const CONFIG_TASK_WDT: u32 = 1;
pub const CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0: u32 = 1;
pub const CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1: u32 = 1;
pub const CONFIG_TASK_WDT_TIMEOUT_S: u32 = 5;
pub const CONFIG_TCPIP_RECVMBOX_SIZE: u32 = 32;
pub const CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY: u32 = 1;
pub const CONFIG_TCPIP_TASK_STACK_SIZE: u32 = 3072;
pub const CONFIG_TCP_MAXRTX: u32 = 12;
pub const CONFIG_TCP_MSL: u32 = 60000;
pub const CONFIG_TCP_MSS: u32 = 1440;
pub const CONFIG_TCP_OVERSIZE_MSS: u32 = 1;
pub const CONFIG_TCP_QUEUE_OOSEQ: u32 = 1;
pub const CONFIG_TCP_RECVMBOX_SIZE: u32 = 6;
pub const CONFIG_TCP_SND_BUF_DEFAULT: u32 = 5744;
pub const CONFIG_TCP_SYNMAXRTX: u32 = 12;
pub const CONFIG_TCP_WND_DEFAULT: u32 = 5744;
pub const CONFIG_TIMER_QUEUE_LENGTH: u32 = 10;
pub const CONFIG_TIMER_TASK_PRIORITY: u32 = 1;
pub const CONFIG_TIMER_TASK_STACK_DEPTH: u32 = 2048;
pub const CONFIG_TIMER_TASK_STACK_SIZE: u32 = 3584;
pub const CONFIG_TOOLPREFIX: &[u8; 20usize] = b"xtensa-esp32s3-elf-\0";
pub const CONFIG_UDP_RECVMBOX_SIZE: u32 = 6;
pub const EXIT_FAILURE: u32 = 1;
pub const EXIT_SUCCESS: u32 = 0;
pub const RAND_MAX: u32 = 2147483647;
pub const __BIT_TYPES_DEFINED__: u32 = 1;
pub const _LITTLE_ENDIAN: u32 = 1234;
pub const _BIG_ENDIAN: u32 = 4321;
pub const _PDP_ENDIAN: u32 = 3412;
pub const _BYTE_ORDER: u32 = 1234;
pub const _QUAD_HIGHWORD: u32 = 1;
pub const _QUAD_LOWWORD: u32 = 0;
pub const LITTLE_ENDIAN: u32 = 1234;
pub const BIG_ENDIAN: u32 = 4321;
pub const PDP_ENDIAN: u32 = 3412;
pub const BYTE_ORDER: u32 = 1234;
pub const FD_SETSIZE: u32 = 64;
pub const SCHED_OTHER: u32 = 0;
pub const SCHED_FIFO: u32 = 1;
pub const SCHED_RR: u32 = 2;
pub const PTHREAD_SCOPE_PROCESS: u32 = 0;
pub const PTHREAD_SCOPE_SYSTEM: u32 = 1;
pub const PTHREAD_INHERIT_SCHED: u32 = 1;
pub const PTHREAD_EXPLICIT_SCHED: u32 = 2;
pub const PTHREAD_CREATE_DETACHED: u32 = 0;
pub const PTHREAD_CREATE_JOINABLE: u32 = 1;
pub const PTHREAD_MUTEX_NORMAL: u32 = 0;
pub const PTHREAD_MUTEX_RECURSIVE: u32 = 1;
pub const PTHREAD_MUTEX_ERRORCHECK: u32 = 2;
pub const PTHREAD_MUTEX_DEFAULT: u32 = 3;
pub const __SLBF: u32 = 1;
pub const __SNBF: u32 = 2;
pub const __SRD: u32 = 4;
pub const __SWR: u32 = 8;
pub const __SRW: u32 = 16;
pub const __SEOF: u32 = 32;
pub const __SERR: u32 = 64;
pub const __SMBF: u32 = 128;
pub const __SAPP: u32 = 256;
pub const __SSTR: u32 = 512;
pub const __SOPT: u32 = 1024;
pub const __SNPT: u32 = 2048;
pub const __SOFF: u32 = 4096;
pub const __SORD: u32 = 8192;
pub const __SL64: u32 = 32768;
pub const __SNLK: u32 = 1;
pub const __SWID: u32 = 8192;
pub const _IOFBF: u32 = 0;
pub const _IOLBF: u32 = 1;
pub const _IONBF: u32 = 2;
pub const EOF: i32 = -1;
pub const BUFSIZ: u32 = 128;
pub const FOPEN_MAX: u32 = 20;
pub const FILENAME_MAX: u32 = 1024;
pub const L_tmpnam: u32 = 1024;
pub const P_tmpdir: &[u8; 5usize] = b"/tmp\0";
pub const SEEK_SET: u32 = 0;
pub const SEEK_CUR: u32 = 1;
pub const SEEK_END: u32 = 2;
pub const TMP_MAX: u32 = 26;
pub const L_ctermid: u32 = 16;
pub const ESP_OK: i32 = 0;
pub const ESP_FAIL: i32 = -1;
pub const ESP_ERR_NO_MEM: i32 = 257;
pub const ESP_ERR_INVALID_ARG: i32 = 258;
pub const ESP_ERR_INVALID_STATE: i32 = 259;
pub const ESP_ERR_INVALID_SIZE: i32 = 260;
pub const ESP_ERR_NOT_FOUND: i32 = 261;
pub const ESP_ERR_NOT_SUPPORTED: i32 = 262;
pub const ESP_ERR_TIMEOUT: i32 = 263;
pub const ESP_ERR_INVALID_RESPONSE: i32 = 264;
pub const ESP_ERR_INVALID_CRC: i32 = 265;
pub const ESP_ERR_INVALID_VERSION: i32 = 266;
pub const ESP_ERR_INVALID_MAC: i32 = 267;
pub const ESP_ERR_NOT_FINISHED: i32 = 268;
pub const ESP_ERR_WIFI_BASE: i32 = 12288;
pub const ESP_ERR_MESH_BASE: i32 = 16384;
pub const ESP_ERR_FLASH_BASE: i32 = 24576;
pub const ESP_ERR_HW_CRYPTO_BASE: i32 = 49152;
pub const ESP_ERR_MEMPROT_BASE: i32 = 53248;
pub const BIT31: u32 = 2147483648;
pub const BIT30: u32 = 1073741824;
pub const BIT29: u32 = 536870912;
pub const BIT28: u32 = 268435456;
pub const BIT27: u32 = 134217728;
pub const BIT26: u32 = 67108864;
pub const BIT25: u32 = 33554432;
pub const BIT24: u32 = 16777216;
pub const BIT23: u32 = 8388608;
pub const BIT22: u32 = 4194304;
pub const BIT21: u32 = 2097152;
pub const BIT20: u32 = 1048576;
pub const BIT19: u32 = 524288;
pub const BIT18: u32 = 262144;
pub const BIT17: u32 = 131072;
pub const BIT16: u32 = 65536;
pub const BIT15: u32 = 32768;
pub const BIT14: u32 = 16384;
pub const BIT13: u32 = 8192;
pub const BIT12: u32 = 4096;
pub const BIT11: u32 = 2048;
pub const BIT10: u32 = 1024;
pub const BIT9: u32 = 512;
pub const BIT8: u32 = 256;
pub const BIT7: u32 = 128;
pub const BIT6: u32 = 64;
pub const BIT5: u32 = 32;
pub const BIT4: u32 = 16;
pub const BIT3: u32 = 8;
pub const BIT2: u32 = 4;
pub const BIT1: u32 = 2;
pub const BIT0: u32 = 1;
pub const BIT63: i64 = -9223372036854775808;
pub const BIT62: u64 = 4611686018427387904;
pub const BIT61: u64 = 2305843009213693952;
pub const BIT60: u64 = 1152921504606846976;
pub const BIT59: u64 = 576460752303423488;
pub const BIT58: u64 = 288230376151711744;
pub const BIT57: u64 = 144115188075855872;
pub const BIT56: u64 = 72057594037927936;
pub const BIT55: u64 = 36028797018963968;
pub const BIT54: u64 = 18014398509481984;
pub const BIT53: u64 = 9007199254740992;
pub const BIT52: u64 = 4503599627370496;
pub const BIT51: u64 = 2251799813685248;
pub const BIT50: u64 = 1125899906842624;
pub const BIT49: u64 = 562949953421312;
pub const BIT48: u64 = 281474976710656;
pub const BIT47: u64 = 140737488355328;
pub const BIT46: u64 = 70368744177664;
pub const BIT45: u64 = 35184372088832;
pub const BIT44: u64 = 17592186044416;
pub const BIT43: u64 = 8796093022208;
pub const BIT42: u64 = 4398046511104;
pub const BIT41: u64 = 2199023255552;
pub const BIT40: u64 = 1099511627776;
pub const BIT39: u64 = 549755813888;
pub const BIT38: u64 = 274877906944;
pub const BIT37: u64 = 137438953472;
pub const BIT36: u64 = 68719476736;
pub const BIT35: u64 = 34359738368;
pub const BIT34: u64 = 17179869184;
pub const BIT33: u64 = 8589934592;
pub const BIT32: u64 = 4294967296;
pub const ESP_IDF_VERSION_MAJOR: u32 = 4;
pub const ESP_IDF_VERSION_MINOR: u32 = 4;
pub const ESP_IDF_VERSION_PATCH: u32 = 2;
pub const TWO_UNIVERSAL_MAC_ADDR: u32 = 2;
pub const FOUR_UNIVERSAL_MAC_ADDR: u32 = 4;
pub const UNIVERSAL_MAC_ADDR_NUM: u32 = 4;
pub const PRO_CPU_NUM: u32 = 0;
pub const APP_CPU_NUM: u32 = 1;
pub const PRO_CPUID: u32 = 52685;
pub const APP_CPUID: u32 = 43947;
pub const DR_REG_UART_BASE: u32 = 1610612736;
pub const DR_REG_SPI1_BASE: u32 = 1610620928;
pub const DR_REG_SPI0_BASE: u32 = 1610625024;
pub const DR_REG_GPIO_BASE: u32 = 1610629120;
pub const DR_REG_GPIO_SD_BASE: u32 = 1610632960;
pub const DR_REG_FE2_BASE: u32 = 1610633216;
pub const DR_REG_FE_BASE: u32 = 1610637312;
pub const DR_REG_EFUSE_BASE: u32 = 1610641408;
pub const DR_REG_RTCCNTL_BASE: u32 = 1610645504;
pub const DR_REG_RTCIO_BASE: u32 = 1610646528;
pub const DR_REG_SENS_BASE: u32 = 1610647552;
pub const DR_REG_RTC_I2C_BASE: u32 = 1610648576;
pub const DR_REG_IO_MUX_BASE: u32 = 1610649600;
pub const DR_REG_HINF_BASE: u32 = 1610657792;
pub const DR_REG_UHCI1_BASE: u32 = 1610661888;
pub const DR_REG_I2S_BASE: u32 = 1610674176;
pub const DR_REG_UART1_BASE: u32 = 1610678272;
pub const DR_REG_BT_BASE: u32 = 1610682368;
pub const DR_REG_I2C_EXT_BASE: u32 = 1610690560;
pub const DR_REG_UHCI0_BASE: u32 = 1610694656;
pub const DR_REG_SLCHOST_BASE: u32 = 1610698752;
pub const DR_REG_RMT_BASE: u32 = 1610702848;
pub const DR_REG_PCNT_BASE: u32 = 1610706944;
pub const DR_REG_SLC_BASE: u32 = 1610711040;
pub const DR_REG_LEDC_BASE: u32 = 1610715136;
pub const DR_REG_NRX_BASE: u32 = 1610730496;
pub const DR_REG_BB_BASE: u32 = 1610731520;
pub const DR_REG_PWM0_BASE: u32 = 1610735616;
pub const DR_REG_TIMERGROUP0_BASE: u32 = 1610739712;
pub const DR_REG_TIMERGROUP1_BASE: u32 = 1610743808;
pub const DR_REG_RTC_SLOWMEM_BASE: u32 = 1610747904;
pub const DR_REG_SYSTIMER_BASE: u32 = 1610756096;
pub const DR_REG_SPI2_BASE: u32 = 1610760192;
pub const DR_REG_SPI3_BASE: u32 = 1610764288;
pub const DR_REG_SYSCON_BASE: u32 = 1610768384;
pub const DR_REG_APB_CTRL_BASE: u32 = 1610768384;
pub const DR_REG_I2C1_EXT_BASE: u32 = 1610772480;
pub const DR_REG_SDMMC_BASE: u32 = 1610776576;
pub const DR_REG_PERI_BACKUP_BASE: u32 = 1610784768;
pub const DR_REG_TWAI_BASE: u32 = 1610788864;
pub const DR_REG_PWM1_BASE: u32 = 1610792960;
pub const DR_REG_I2S1_BASE: u32 = 1610797056;
pub const DR_REG_UART2_BASE: u32 = 1610801152;
pub const DR_REG_USB_DEVICE_BASE: u32 = 1610842112;
pub const DR_REG_USB_WRAP_BASE: u32 = 1610846208;
pub const DR_REG_AES_BASE: u32 = 1610850304;
pub const DR_REG_SHA_BASE: u32 = 1610854400;
pub const DR_REG_RSA_BASE: u32 = 1610858496;
pub const DR_REG_HMAC_BASE: u32 = 1610866688;
pub const DR_REG_DIGITAL_SIGNATURE_BASE: u32 = 1610862592;
pub const DR_REG_GDMA_BASE: u32 = 1610870784;
pub const DR_REG_APB_SARADC_BASE: u32 = 1610874880;
pub const DR_REG_LCD_CAM_BASE: u32 = 1610878976;
pub const DR_REG_SYSTEM_BASE: u32 = 1611399168;
pub const DR_REG_SENSITIVE_BASE: u32 = 1611403264;
pub const DR_REG_INTERRUPT_BASE: u32 = 1611407360;
pub const DR_REG_EXTMEM_BASE: u32 = 1611415552;
pub const DR_REG_MMU_TABLE: u32 = 1611419648;
pub const DR_REG_ITAG_TABLE: u32 = 1611423744;
pub const DR_REG_DTAG_TABLE: u32 = 1611431936;
pub const DR_REG_EXT_MEM_ENC: u32 = 1611448320;
pub const DR_REG_ASSIST_DEBUG_BASE: u32 = 1611456512;
pub const DR_REG_WORLD_CNTL_BASE: u32 = 1611464704;
pub const DR_REG_DPORT_END: u32 = 1611481084;
pub const APB_CLK_FREQ_ROM: u32 = 40000000;
pub const CPU_CLK_FREQ_ROM: u32 = 40000000;
pub const UART_CLK_FREQ_ROM: u32 = 40000000;
pub const EFUSE_CLK_FREQ_ROM: u32 = 20000000;
pub const APB_CLK_FREQ: u32 = 80000000;
pub const REF_CLK_FREQ: u32 = 1000000;
pub const RTC_CLK_FREQ: u32 = 20000000;
pub const XTAL_CLK_FREQ: u32 = 40000000;
pub const UART_CLK_FREQ: u32 = 80000000;
pub const WDT_CLK_FREQ: u32 = 80000000;
pub const TIMER_CLK_FREQ: u32 = 5000000;
pub const SPI_CLK_DIV: u32 = 4;
pub const TICKS_PER_US_ROM: u32 = 40;
pub const GPIO_MATRIX_DELAY_NS: u32 = 0;
pub const SOC_DROM_LOW: u32 = 1006632960;
pub const SOC_DROM_HIGH: u32 = 1023410176;
pub const SOC_IROM_LOW: u32 = 1107296256;
pub const SOC_IROM_HIGH: u32 = 1140850688;
pub const SOC_IRAM_LOW: u32 = 1077346304;
pub const SOC_IRAM_HIGH: u32 = 1077805056;
pub const SOC_DRAM_LOW: u32 = 1070104576;
pub const SOC_DRAM_HIGH: u32 = 1070596096;
pub const SOC_RTC_IRAM_LOW: u32 = 1611653120;
pub const SOC_RTC_IRAM_HIGH: u32 = 1611661312;
pub const SOC_RTC_DRAM_LOW: u32 = 1611653120;
pub const SOC_RTC_DRAM_HIGH: u32 = 1611661312;
pub const SOC_RTC_DATA_LOW: u32 = 1342177280;
pub const SOC_RTC_DATA_HIGH: u32 = 1342185472;
pub const SOC_EXTRAM_DATA_LOW: u32 = 1023410176;
pub const SOC_EXTRAM_DATA_HIGH: u32 = 1040187392;
pub const SOC_IROM_MASK_LOW: u32 = 1073741824;
pub const SOC_IROM_MASK_HIGH: u32 = 1073848576;
pub const SOC_EXTRAM_DATA_SIZE: u32 = 16777216;
pub const SOC_MAX_CONTIGUOUS_RAM_SIZE: u32 = 16777216;
pub const SOC_DIRAM_IRAM_LOW: u32 = 1077379072;
pub const SOC_DIRAM_IRAM_HIGH: u32 = 1077805056;
pub const SOC_DIRAM_DRAM_LOW: u32 = 1070104576;
pub const SOC_DIRAM_DRAM_HIGH: u32 = 1070530560;
pub const SOC_I_D_OFFSET: u32 = 7274496;
pub const SOC_DMA_LOW: u32 = 1070104576;
pub const SOC_DMA_HIGH: u32 = 1070596096;
pub const SOC_DMA_EXT_LOW: u32 = 1023410176;
pub const SOC_DMA_EXT_HIGH: u32 = 1040187392;
pub const SOC_BYTE_ACCESSIBLE_LOW: u32 = 1070104576;
pub const SOC_BYTE_ACCESSIBLE_HIGH: u32 = 1070596096;
pub const SOC_MEM_INTERNAL_LOW: u32 = 1070104576;
pub const SOC_MEM_INTERNAL_HIGH: u32 = 1077813248;
pub const SOC_ROM_STACK_START: u32 = 1070511888;
pub const SOC_ROM_STACK_SIZE: u32 = 8192;
pub const ETS_WMAC_INUM: u32 = 0;
pub const ETS_BT_HOST_INUM: u32 = 1;
pub const ETS_WBB_INUM: u32 = 4;
pub const ETS_TG0_T1_INUM: u32 = 10;
pub const ETS_FRC1_INUM: u32 = 22;
pub const ETS_T1_WDT_INUM: u32 = 24;
pub const ETS_CACHEERR_INUM: u32 = 25;
pub const ETS_IPC_ISR_INUM: u32 = 28;
pub const ETS_SLC_INUM: u32 = 1;
pub const ETS_UART0_INUM: u32 = 5;
pub const ETS_UART1_INUM: u32 = 5;
pub const ETS_SPI2_INUM: u32 = 1;
pub const ETS_FRC_TIMER2_INUM: u32 = 10;
pub const ETS_GPIO_INUM: u32 = 4;
pub const ETS_INVALID_INUM: u32 = 6;
pub const MACSTR: &[u8; 30usize] = b"%02x:%02x:%02x:%02x:%02x:%02x\0";
pub const LOG_LOCAL_LEVEL: u32 = 4;
pub const LOG_COLOR_BLACK: &[u8; 3usize] = b"30\0";
pub const LOG_COLOR_RED: &[u8; 3usize] = b"31\0";
pub const LOG_COLOR_GREEN: &[u8; 3usize] = b"32\0";
pub const LOG_COLOR_BROWN: &[u8; 3usize] = b"33\0";
pub const LOG_COLOR_BLUE: &[u8; 3usize] = b"34\0";
pub const LOG_COLOR_PURPLE: &[u8; 3usize] = b"35\0";
pub const LOG_COLOR_CYAN: &[u8; 3usize] = b"36\0";
pub const LOG_RESET_COLOR: &[u8; 5usize] = b"\x1B[0m\0";
pub const SOC_ADC_SUPPORTED: u32 = 1;
pub const SOC_PCNT_SUPPORTED: u32 = 1;
pub const SOC_TWAI_SUPPORTED: u32 = 1;
pub const SOC_GDMA_SUPPORTED: u32 = 1;
pub const SOC_LCDCAM_SUPPORTED: u32 = 1;
pub const SOC_MCPWM_SUPPORTED: u32 = 1;
pub const SOC_DEDICATED_GPIO_SUPPORTED: u32 = 1;
pub const SOC_CPU_CORES_NUM: u32 = 2;
pub const SOC_CACHE_SUPPORT_WRAP: u32 = 1;
pub const SOC_ULP_SUPPORTED: u32 = 1;
pub const SOC_RISCV_COPROC_SUPPORTED: u32 = 1;
pub const SOC_BT_SUPPORTED: u32 = 1;
pub const SOC_USB_OTG_SUPPORTED: u32 = 1;
pub const SOC_USB_SERIAL_JTAG_SUPPORTED: u32 = 1;
pub const SOC_RTC_SLOW_MEM_SUPPORTED: u32 = 1;
pub const SOC_CCOMP_TIMER_SUPPORTED: u32 = 1;
pub const SOC_DIG_SIGN_SUPPORTED: u32 = 1;
pub const SOC_HMAC_SUPPORTED: u32 = 1;
pub const SOC_ASYNC_MEMCPY_SUPPORTED: u32 = 1;
pub const SOC_SUPPORTS_SECURE_DL_MODE: u32 = 1;
pub const SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS: u32 = 3;
pub const SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS: u32 = 1;
pub const SOC_SDMMC_HOST_SUPPORTED: u32 = 1;
pub const SOC_FLASH_ENCRYPTION_XTS_AES: u32 = 1;
pub const SOC_FLASH_ENCRYPTION_XTS_AES_256: u32 = 1;
pub const SOC_PSRAM_DMA_CAPABLE: u32 = 1;
pub const SOC_XT_WDT_SUPPORTED: u32 = 1;
pub const SOC_TEMP_SENSOR_SUPPORTED: u32 = 1;
pub const SOC_APPCPU_HAS_CLOCK_GATING_BUG: u32 = 1;
pub const SOC_ADC_RTC_CTRL_SUPPORTED: u32 = 1;
pub const SOC_ADC_DIG_CTRL_SUPPORTED: u32 = 1;
pub const SOC_ADC_ARBITER_SUPPORTED: u32 = 1;
pub const SOC_ADC_FILTER_SUPPORTED: u32 = 1;
pub const SOC_ADC_MONITOR_SUPPORTED: u32 = 1;
pub const SOC_ADC_PERIPH_NUM: u32 = 2;
pub const SOC_ADC_MAX_CHANNEL_NUM: u32 = 10;
pub const SOC_ADC_DIGI_CONTROLLER_NUM: u32 = 2;
pub const SOC_ADC_PATT_LEN_MAX: u32 = 24;
pub const SOC_ADC_DIGI_MAX_BITWIDTH: u32 = 12;
pub const SOC_ADC_DIGI_RESULT_BYTES: u32 = 4;
pub const SOC_ADC_DIGI_DATA_BYTES_PER_CONV: u32 = 4;
pub const SOC_ADC_SAMPLE_FREQ_THRES_HIGH: u32 = 83333;
pub const SOC_ADC_SAMPLE_FREQ_THRES_LOW: u32 = 611;
pub const SOC_ADC_MAX_BITWIDTH: u32 = 12;
pub const SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256: u32 = 1;
pub const SOC_ADC_CALIBRATION_V1_SUPPORTED: u32 = 1;
pub const SOC_APB_BACKUP_DMA: u32 = 1;
pub const SOC_BROWNOUT_RESET_SUPPORTED: u32 = 1;
pub const SOC_CPU_BREAKPOINTS_NUM: u32 = 2;
pub const SOC_CPU_WATCHPOINTS_NUM: u32 = 2;
pub const SOC_CPU_WATCHPOINT_SIZE: u32 = 64;
pub const SOC_CPU_HAS_FPU: u32 = 1;
pub const SOC_DS_SIGNATURE_MAX_BIT_LEN: u32 = 4096;
pub const SOC_DS_KEY_PARAM_MD_IV_LENGTH: u32 = 16;
pub const SOC_DS_KEY_CHECK_MAX_WAIT_US: u32 = 1100;
pub const SOC_GDMA_GROUPS: u32 = 1;
pub const SOC_GDMA_PAIRS_PER_GROUP: u32 = 5;
pub const SOC_GDMA_SUPPORT_PSRAM: u32 = 1;
pub const SOC_GDMA_PSRAM_MIN_ALIGN: u32 = 16;
pub const SOC_GPIO_PORT: u32 = 1;
pub const SOC_GPIO_PIN_COUNT: u32 = 49;
pub const SOC_GPIO_SUPPORT_RTC_INDEPENDENT: u32 = 1;
pub const SOC_GPIO_SUPPORT_FORCE_HOLD: u32 = 1;
pub const SOC_GPIO_VALID_GPIO_MASK: u64 = 562949890506751;
pub const SOC_GPIO_VALID_OUTPUT_GPIO_MASK: u64 = 562949890506751;
pub const SOC_GPIO_SUPPORT_SLP_SWITCH: u32 = 1;
pub const SOC_DEDIC_GPIO_OUT_CHANNELS_NUM: u32 = 8;
pub const SOC_DEDIC_GPIO_IN_CHANNELS_NUM: u32 = 8;
pub const SOC_DEDIC_GPIO_OUT_AUTO_ENABLE: u32 = 1;
pub const SOC_I2C_NUM: u32 = 2;
pub const SOC_I2C_FIFO_LEN: u32 = 32;
pub const SOC_I2C_SUPPORT_HW_CLR_BUS: u32 = 1;
pub const SOC_I2C_SUPPORT_XTAL: u32 = 1;
pub const SOC_I2C_SUPPORT_RTC: u32 = 1;
pub const SOC_I2S_NUM: u32 = 2;
pub const SOC_I2S_SUPPORTS_PCM: u32 = 1;
pub const SOC_I2S_SUPPORTS_PDM_TX: u32 = 1;
pub const SOC_I2S_SUPPORTS_PDM_RX: u32 = 1;
pub const SOC_I2S_SUPPORTS_PDM_CODEC: u32 = 1;
pub const SOC_I2S_SUPPORTS_TDM: u32 = 1;
pub const SOC_LEDC_HAS_TIMER_SPECIFIC_MUX: u32 = 1;
pub const SOC_LEDC_SUPPORT_REF_TICK: u32 = 1;
pub const SOC_LEDC_SUPPORT_XTAL_CLOCK: u32 = 1;
pub const SOC_LEDC_CHANNEL_NUM: u32 = 8;
pub const SOC_LEDC_TIMER_BIT_WIDE_NUM: u32 = 14;
pub const SOC_MCPWM_GROUPS: u32 = 2;
pub const SOC_MCPWM_TIMERS_PER_GROUP: u32 = 3;
pub const SOC_MCPWM_OPERATORS_PER_GROUP: u32 = 3;
pub const SOC_MCPWM_COMPARATORS_PER_OPERATOR: u32 = 2;
pub const SOC_MCPWM_GENERATORS_PER_OPERATOR: u32 = 2;
pub const SOC_MCPWM_TRIGGERS_PER_OPERATOR: u32 = 2;
pub const SOC_MCPWM_GPIO_FAULTS_PER_GROUP: u32 = 3;
pub const SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP: u32 = 1;
pub const SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER: u32 = 3;
pub const SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP: u32 = 3;
pub const SOC_MCPWM_SWSYNC_CAN_PROPAGATE: u32 = 1;
pub const SOC_MCPWM_BASE_CLK_HZ: u32 = 160000000;
pub const SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED: u32 = 0;
pub const SOC_MPU_MIN_REGION_SIZE: u32 = 536870912;
pub const SOC_MPU_REGIONS_MAX_NUM: u32 = 8;
pub const SOC_MPU_REGION_RO_SUPPORTED: u32 = 0;
pub const SOC_MPU_REGION_WO_SUPPORTED: u32 = 0;
pub const SOC_PCNT_GROUPS: u32 = 1;
pub const SOC_PCNT_UNITS_PER_GROUP: u32 = 4;
pub const SOC_PCNT_CHANNELS_PER_UNIT: u32 = 2;
pub const SOC_PCNT_THRES_POINT_PER_UNIT: u32 = 2;
pub const SOC_RMT_GROUPS: u32 = 1;
pub const SOC_RMT_TX_CANDIDATES_PER_GROUP: u32 = 4;
pub const SOC_RMT_RX_CANDIDATES_PER_GROUP: u32 = 4;
pub const SOC_RMT_CHANNELS_PER_GROUP: u32 = 8;
pub const SOC_RMT_MEM_WORDS_PER_CHANNEL: u32 = 48;
pub const SOC_RMT_SUPPORT_RX_PINGPONG: u32 = 1;
pub const SOC_RMT_SUPPORT_RX_DEMODULATION: u32 = 1;
pub const SOC_RMT_SUPPORT_TX_LOOP_COUNT: u32 = 1;
pub const SOC_RMT_SUPPORT_TX_LOOP_AUTOSTOP: u32 = 1;
pub const SOC_RMT_SUPPORT_TX_SYNCHRO: u32 = 1;
pub const SOC_RMT_SUPPORT_XTAL: u32 = 1;
pub const SOC_LCD_I80_SUPPORTED: u32 = 1;
pub const SOC_LCD_RGB_SUPPORTED: u32 = 1;
pub const SOC_LCD_I80_BUSES: u32 = 1;
pub const SOC_LCD_RGB_PANELS: u32 = 1;
pub const SOC_LCD_I80_BUS_WIDTH: u32 = 16;
pub const SOC_LCD_RGB_DATA_WIDTH: u32 = 16;
pub const SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH: u32 = 128;
pub const SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM: u32 = 549;
pub const SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN: u32 = 16;
pub const SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE: u32 = 16;
pub const SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE: u32 = 8784;
pub const SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH: u32 = 128;
pub const SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN: u32 = 16;
pub const SOC_RTCIO_PIN_COUNT: u32 = 22;
pub const SOC_RTCIO_INPUT_OUTPUT_SUPPORTED: u32 = 1;
pub const SOC_RTCIO_HOLD_SUPPORTED: u32 = 1;
pub const SOC_RTCIO_WAKE_SUPPORTED: u32 = 1;
pub const SOC_SIGMADELTA_NUM: u32 = 1;
pub const SOC_SIGMADELTA_CHANNEL_NUM: u32 = 8;
pub const SOC_SPI_PERIPH_NUM: u32 = 3;
pub const SOC_SPI_DMA_CHAN_NUM: u32 = 3;
pub const SOC_SPI_MAXIMUM_BUFFER_SIZE: u32 = 64;
pub const SOC_SPI_SUPPORT_DDRCLK: u32 = 1;
pub const SOC_SPI_SLAVE_SUPPORT_SEG_TRANS: u32 = 1;
pub const SOC_SPI_SUPPORT_CD_SIG: u32 = 1;
pub const SOC_SPI_SUPPORT_CONTINUOUS_TRANS: u32 = 1;
pub const SOC_SPI_SUPPORT_SLAVE_HD_VER2: u32 = 1;
pub const SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT: u32 = 1;
pub const SOC_MEMSPI_IS_INDEPENDENT: u32 = 1;
pub const SOC_SPI_MAX_PRE_DIVIDER: u32 = 16;
pub const SOC_SPI_SUPPORT_OCT: u32 = 1;
pub const SOC_SPIRAM_SUPPORTED: u32 = 1;
pub const SOC_TOUCH_VERSION_2: u32 = 1;
pub const SOC_SYSTIMER_COUNTER_NUM: u32 = 2;
pub const SOC_SYSTIMER_ALARM_NUM: u32 = 3;
pub const SOC_SYSTIMER_BIT_WIDTH_LO: u32 = 32;
pub const SOC_SYSTIMER_BIT_WIDTH_HI: u32 = 20;
pub const SOC_SYSTIMER_FIXED_TICKS_US: u32 = 16;
pub const SOC_SYSTIMER_INT_LEVEL: u32 = 1;
pub const SOC_SYSTIMER_ALARM_MISS_COMPENSATE: u32 = 1;
pub const SOC_TIMER_GROUPS: u32 = 2;
pub const SOC_TIMER_GROUP_TIMERS_PER_GROUP: u32 = 2;
pub const SOC_TIMER_GROUP_COUNTER_BIT_WIDTH: u32 = 54;
pub const SOC_TIMER_GROUP_SUPPORT_XTAL: u32 = 1;
pub const SOC_TIMER_GROUP_TOTAL_TIMERS: u32 = 4;
pub const SOC_TOUCH_SENSOR_NUM: u32 = 15;
pub const SOC_TOUCH_PROXIMITY_CHANNEL_NUM: u32 = 3;
pub const SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED: u32 = 1;
pub const SOC_TOUCH_PAD_THRESHOLD_MAX: u32 = 2097151;
pub const SOC_TOUCH_PAD_MEASURE_WAIT_MAX: u32 = 255;
pub const SOC_TWAI_BRP_MIN: u32 = 2;
pub const SOC_TWAI_BRP_MAX: u32 = 16384;
pub const SOC_TWAI_SUPPORTS_RX_STATUS: u32 = 1;
pub const SOC_UART_FIFO_LEN: u32 = 128;
pub const SOC_UART_BITRATE_MAX: u32 = 5000000;
pub const SOC_UART_NUM: u32 = 3;
pub const SOC_UART_SUPPORT_FSM_TX_WAIT_SEND: u32 = 1;
pub const SOC_UART_SUPPORT_RTC_CLK: u32 = 1;
pub const SOC_UART_SUPPORT_XTAL_CLK: u32 = 1;
pub const SOC_UART_REQUIRE_CORE_RESET: u32 = 1;
pub const SOC_USB_PERIPH_NUM: u32 = 1;
pub const SOC_SHA_DMA_MAX_BUFFER_SIZE: u32 = 3968;
pub const SOC_SHA_SUPPORT_DMA: u32 = 1;
pub const SOC_SHA_SUPPORT_RESUME: u32 = 1;
pub const SOC_SHA_GDMA: u32 = 1;
pub const SOC_SHA_SUPPORT_SHA1: u32 = 1;
pub const SOC_SHA_SUPPORT_SHA224: u32 = 1;
pub const SOC_SHA_SUPPORT_SHA256: u32 = 1;
pub const SOC_SHA_SUPPORT_SHA384: u32 = 1;
pub const SOC_SHA_SUPPORT_SHA512: u32 = 1;
pub const SOC_SHA_SUPPORT_SHA512_224: u32 = 1;
pub const SOC_SHA_SUPPORT_SHA512_256: u32 = 1;
pub const SOC_SHA_SUPPORT_SHA512_T: u32 = 1;
pub const SOC_RSA_MAX_BIT_LEN: u32 = 4096;
pub const SOC_AES_SUPPORT_DMA: u32 = 1;
pub const SOC_AES_GDMA: u32 = 1;
pub const SOC_AES_SUPPORT_AES_128: u32 = 1;
pub const SOC_AES_SUPPORT_AES_256: u32 = 1;
pub const SOC_PM_SUPPORT_EXT_WAKEUP: u32 = 1;
pub const SOC_PM_SUPPORT_WIFI_WAKEUP: u32 = 1;
pub const SOC_PM_SUPPORT_BT_WAKEUP: u32 = 1;
pub const SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP: u32 = 1;
pub const SOC_PM_SUPPORT_CPU_PD: u32 = 1;
pub const SOC_PM_SUPPORT_TAGMEM_PD: u32 = 1;
pub const SOC_PM_SUPPORT_RTC_PERIPH_PD: u32 = 1;
pub const SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY: u32 = 1;
pub const SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX: u32 = 64;
pub const SOC_WIFI_HW_TSF: u32 = 1;
pub const SOC_PHY_DIG_REGS_MEM_SIZE: u32 = 84;
pub const SOC_MAC_BB_PD_MEM_SIZE: u32 = 768;
pub const SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH: u32 = 12;
pub const SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE: u32 = 1;
pub const SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND: u32 = 1;
pub const SOC_SPI_MEM_SUPPORT_AUTO_RESUME: u32 = 1;
pub const SOC_SPI_MEM_SUPPORT_SW_SUSPEND: u32 = 1;
pub const SOC_SPI_MEM_SUPPORT_OPI_MODE: u32 = 1;
pub const SOC_SPI_MEM_SUPPORT_TIME_TUNING: u32 = 1;
pub const SOC_COEX_HW_PTI: u32 = 1;
pub const SOC_SDMMC_USE_GPIO_MATRIX: u32 = 1;
pub const SOC_SDMMC_NUM_SLOTS: u32 = 2;
pub const SOC_SDMMC_SUPPORT_XTAL_CLOCK: u32 = 1;
pub const XTHAL_RELEASE_MAJOR: u32 = 12000;
pub const XTHAL_RELEASE_MINOR: u32 = 9;
pub const XTHAL_RELEASE_NAME: &[u8; 7usize] = b"12.0.9\0";
pub const XTHAL_REL_12: u32 = 1;
pub const XTHAL_REL_12_0: u32 = 1;
pub const XTHAL_REL_12_0_9: u32 = 1;
pub const XTHAL_MAJOR_REV: u32 = 12000;
pub const XTHAL_MINOR_REV: u32 = 9;
pub const XTHAL_MAYBE: i32 = -1;
pub const XTHAL_MAX_CPS: u32 = 8;
pub const XTHAL_LITTLEENDIAN: u32 = 0;
pub const XTHAL_BIGENDIAN: u32 = 1;
pub const XTHAL_PREFETCH_ENABLE: i32 = -1;
pub const XTHAL_PREFETCH_DISABLE: u32 = 4294901760;
pub const XTHAL_DCACHE_PREFETCH_L1_OFF: u32 = 2415919104;
pub const XTHAL_DCACHE_PREFETCH_L1: u32 = 2415923200;
pub const XTHAL_ICACHE_PREFETCH_L1_OFF: u32 = 2684354560;
pub const XTHAL_ICACHE_PREFETCH_L1: u32 = 2684362752;
pub const XTHAL_DISASM_BUFSIZE: u32 = 80;
pub const XTHAL_DISASM_OPT_ADDR: u32 = 1;
pub const XTHAL_DISASM_OPT_OPHEX: u32 = 2;
pub const XTHAL_DISASM_OPT_OPCODE: u32 = 4;
pub const XTHAL_DISASM_OPT_PARMS: u32 = 8;
pub const XTHAL_DISASM_OPT_ALL: u32 = 4095;
pub const XTHAL_MAX_INTERRUPTS: u32 = 32;
pub const XTHAL_MAX_INTLEVELS: u32 = 16;
pub const XTHAL_MAX_TIMERS: u32 = 4;
pub const XTHAL_INTTYPE_UNCONFIGURED: u32 = 0;
pub const XTHAL_INTTYPE_SOFTWARE: u32 = 1;
pub const XTHAL_INTTYPE_EXTERN_EDGE: u32 = 2;
pub const XTHAL_INTTYPE_EXTERN_LEVEL: u32 = 3;
pub const XTHAL_INTTYPE_TIMER: u32 = 4;
pub const XTHAL_INTTYPE_NMI: u32 = 5;
pub const XTHAL_INTTYPE_WRITE_ERROR: u32 = 6;
pub const XTHAL_INTTYPE_PROFILING: u32 = 7;
pub const XTHAL_INTTYPE_IDMA_DONE: u32 = 8;
pub const XTHAL_INTTYPE_IDMA_ERR: u32 = 9;
pub const XTHAL_INTTYPE_GS_ERR: u32 = 10;
pub const XTHAL_INTTYPE_SG_ERR: u32 = 10;
pub const XTHAL_MAX_INTTYPES: u32 = 11;
pub const XTHAL_TIMER_UNCONFIGURED: i32 = -1;
pub const XTHAL_TIMER_UNASSIGNED: i32 = -1;
pub const XTHAL_MEMEP_PARITY: u32 = 1;
pub const XTHAL_MEMEP_ECC: u32 = 2;
pub const XTHAL_MEMEP_F_LOCAL: u32 = 0;
pub const XTHAL_MEMEP_F_DCACHE_DATA: u32 = 4;
pub const XTHAL_MEMEP_F_DCACHE_TAG: u32 = 5;
pub const XTHAL_MEMEP_F_ICACHE_DATA: u32 = 6;
pub const XTHAL_MEMEP_F_ICACHE_TAG: u32 = 7;
pub const XTHAL_MEMEP_F_CORRECTABLE: u32 = 16;
pub const XTHAL_AMB_EXCEPTION: u32 = 0;
pub const XTHAL_AMB_HITCACHE: u32 = 1;
pub const XTHAL_AMB_ALLOCATE: u32 = 2;
pub const XTHAL_AMB_WRITETHRU: u32 = 3;
pub const XTHAL_AMB_ISOLATE: u32 = 4;
pub const XTHAL_AMB_GUARD: u32 = 5;
pub const XTHAL_AMB_COHERENT: u32 = 6;
pub const XTHAL_AM_EXCEPTION: u32 = 1;
pub const XTHAL_AM_HITCACHE: u32 = 2;
pub const XTHAL_AM_ALLOCATE: u32 = 4;
pub const XTHAL_AM_WRITETHRU: u32 = 8;
pub const XTHAL_AM_ISOLATE: u32 = 16;
pub const XTHAL_AM_GUARD: u32 = 32;
pub const XTHAL_AM_COHERENT: u32 = 64;
pub const XTHAL_FAM_EXCEPTION: u32 = 1;
pub const XTHAL_FAM_BYPASS: u32 = 0;
pub const XTHAL_FAM_CACHED: u32 = 6;
pub const XTHAL_LAM_EXCEPTION: u32 = 1;
pub const XTHAL_LAM_ISOLATE: u32 = 18;
pub const XTHAL_LAM_BYPASS: u32 = 0;
pub const XTHAL_LAM_BYPASSG: u32 = 32;
pub const XTHAL_LAM_CACHED_NOALLOC: u32 = 2;
pub const XTHAL_LAM_NACACHED: u32 = 2;
pub const XTHAL_LAM_NACACHEDG: u32 = 34;
pub const XTHAL_LAM_CACHED: u32 = 6;
pub const XTHAL_LAM_COHCACHED: u32 = 70;
pub const XTHAL_SAM_EXCEPTION: u32 = 1;
pub const XTHAL_SAM_ISOLATE: u32 = 50;
pub const XTHAL_SAM_BYPASS: u32 = 40;
pub const XTHAL_SAM_WRITETHRU: u32 = 42;
pub const XTHAL_SAM_WRITEBACK: u32 = 38;
pub const XTHAL_SAM_WRITEBACK_NOALLOC: u32 = 34;
pub const XTHAL_SAM_COHWRITEBACK: u32 = 102;
pub const XTHAL_PAM_BYPASS: u32 = 0;
pub const XTHAL_PAM_BYPASS_BUF: u32 = 16;
pub const XTHAL_PAM_CACHED_NOALLOC: u32 = 48;
pub const XTHAL_PAM_WRITETHRU: u32 = 176;
pub const XTHAL_PAM_WRITEBACK_NOALLOC: u32 = 240;
pub const XTHAL_PAM_WRITEBACK: u32 = 496;
pub const XTHAL_CAFLAG_EXPAND: u32 = 256;
pub const XTHAL_CAFLAG_EXACT: u32 = 512;
pub const XTHAL_CAFLAG_NO_PARTIAL: u32 = 1024;
pub const XTHAL_CAFLAG_NO_AUTO_WB: u32 = 2048;
pub const XTHAL_CAFLAG_NO_AUTO_INV: u32 = 4096;
pub const XTHAL_SUCCESS: u32 = 0;
pub const XTHAL_NO_REGIONS_COVERED: i32 = -1;
pub const XTHAL_INEXACT: i32 = -2;
pub const XTHAL_INVALID_ADDRESS: i32 = -3;
pub const XTHAL_UNSUPPORTED: i32 = -4;
pub const XTHAL_ADDRESS_MISALIGNED: i32 = -5;
pub const XTHAL_NO_MAPPING: i32 = -6;
pub const XTHAL_BAD_ACCESS_RIGHTS: i32 = -7;
pub const XTHAL_BAD_MEMORY_TYPE: i32 = -8;
pub const XTHAL_MAP_NOT_ALIGNED: i32 = -9;
pub const XTHAL_OUT_OF_ENTRIES: i32 = -10;
pub const XTHAL_OUT_OF_ORDER_MAP: i32 = -11;
pub const XTHAL_INVALID: i32 = -12;
pub const XTHAL_ZERO_SIZED_REGION: i32 = -13;
pub const XTHAL_INVALID_ADDRESS_RANGE: i32 = -14;
pub const XCHAL_SUCCESS: u32 = 0;
pub const XCHAL_ADDRESS_MISALIGNED: i32 = -5;
pub const XCHAL_INEXACT: i32 = -2;
pub const XCHAL_INVALID_ADDRESS: i32 = -3;
pub const XCHAL_UNSUPPORTED_ON_THIS_ARCH: i32 = -4;
pub const XCHAL_NO_PAGES_MAPPED: i32 = -1;
pub const XTHAL_AR_NONE: u32 = 0;
pub const XTHAL_AR_R: u32 = 4;
pub const XTHAL_AR_RX: u32 = 5;
pub const XTHAL_AR_RW: u32 = 6;
pub const XTHAL_AR_RWX: u32 = 7;
pub const XTHAL_AR_Ww: u32 = 8;
pub const XTHAL_AR_RWrwx: u32 = 9;
pub const XTHAL_AR_RWr: u32 = 10;
pub const XTHAL_AR_RWXrx: u32 = 11;
pub const XTHAL_AR_Rr: u32 = 12;
pub const XTHAL_AR_RXrx: u32 = 13;
pub const XTHAL_AR_RWrw: u32 = 14;
pub const XTHAL_AR_RWXrwx: u32 = 15;
pub const XTHAL_AR_WIDTH: u32 = 4;
pub const XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS: u32 = 8192;
pub const XTHAL_MPU_USE_EXISTING_MEMORY_TYPE: u32 = 16384;
pub const XTHAL_MEM_DEVICE: u32 = 32768;
pub const XTHAL_MEM_NON_CACHEABLE: u32 = 589824;
pub const XTHAL_MEM_WRITETHRU_NOALLOC: u32 = 524288;
pub const XTHAL_MEM_WRITETHRU: u32 = 262144;
pub const XTHAL_MEM_WRITETHRU_WRITEALLOC: u32 = 393216;
pub const XTHAL_MEM_WRITEBACK_NOALLOC: u32 = 327680;
pub const XTHAL_MEM_WRITEBACK: u32 = 458752;
pub const XTHAL_MEM_INTERRUPTIBLE: u32 = 134217728;
pub const XTHAL_MEM_BUFFERABLE: u32 = 16777216;
pub const XTHAL_MEM_NON_SHAREABLE: u32 = 0;
pub const XTHAL_MEM_INNER_SHAREABLE: u32 = 33554432;
pub const XTHAL_MEM_OUTER_SHAREABLE: u32 = 67108864;
pub const XTHAL_MEM_SYSTEM_SHAREABLE: u32 = 100663296;
pub const _XTHAL_SYSTEM_CACHE_BITS: u32 = 983040;
pub const _XTHAL_LOCAL_CACHE_BITS: u32 = 15728640;
pub const _XTHAL_MEM_SYSTEM_RWC_MASK: u32 = 458752;
pub const _XTHAL_MEM_LOCAL_RWC_MASK: u32 = 7340032;
pub const _XTHAL_SHIFT_RWC: u32 = 16;
pub const XTHAL_MEM_NON_CACHED: u32 = 589824;
pub const XTHAL_MEM_NON_SHARED: u32 = 0;
pub const XTHAL_MEM_INNER_SHARED: u32 = 33554432;
pub const XTHAL_MEM_OUTER_SHARED: u32 = 67108864;
pub const XTHAL_MEM_SYSTEM_SHARED: u32 = 100663296;
pub const XTHAL_MEM_SW_SHAREABLE: u32 = 0;
pub const XTENSA_HWVERSION_T1020_0: u32 = 102000;
pub const XTENSA_HWCIDSCHEME_T1020_0: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_0: u32 = 2;
pub const XTENSA_HWVERSION_T1020_1: u32 = 102001;
pub const XTENSA_HWCIDSCHEME_T1020_1: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_1: u32 = 3;
pub const XTENSA_HWVERSION_T1020_2: u32 = 102002;
pub const XTENSA_HWCIDSCHEME_T1020_2: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_2: u32 = 4;
pub const XTENSA_HWVERSION_T1020_2B: u32 = 102002;
pub const XTENSA_HWCIDSCHEME_T1020_2B: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_2B: u32 = 5;
pub const XTENSA_HWVERSION_T1020_3: u32 = 102003;
pub const XTENSA_HWCIDSCHEME_T1020_3: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_3: u32 = 6;
pub const XTENSA_HWVERSION_T1020_4: u32 = 102004;
pub const XTENSA_HWCIDSCHEME_T1020_4: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_4: u32 = 7;
pub const XTENSA_HWVERSION_T1030_0: u32 = 103000;
pub const XTENSA_HWCIDSCHEME_T1030_0: u32 = 10;
pub const XTENSA_HWCIDVERS_T1030_0: u32 = 9;
pub const XTENSA_HWVERSION_T1030_1: u32 = 103001;
pub const XTENSA_HWCIDSCHEME_T1030_1: u32 = 10;
pub const XTENSA_HWCIDVERS_T1030_1: u32 = 10;
pub const XTENSA_HWVERSION_T1030_2: u32 = 103002;
pub const XTENSA_HWCIDSCHEME_T1030_2: u32 = 10;
pub const XTENSA_HWCIDVERS_T1030_2: u32 = 11;
pub const XTENSA_HWVERSION_T1030_3: u32 = 103003;
pub const XTENSA_HWCIDSCHEME_T1030_3: u32 = 10;
pub const XTENSA_HWCIDVERS_T1030_3: u32 = 12;
pub const XTENSA_HWVERSION_T1040_0: u32 = 104000;
pub const XTENSA_HWCIDSCHEME_T1040_0: u32 = 10;
pub const XTENSA_HWCIDVERS_T1040_0: u32 = 15;
pub const XTENSA_HWVERSION_T1040_1: u32 = 104001;
pub const XTENSA_HWCIDSCHEME_T1040_1: u32 = 1;
pub const XTENSA_HWCIDVERS_T1040_1: u32 = 32;
pub const XTENSA_HWVERSION_T1040_1P: u32 = 104001;
pub const XTENSA_HWCIDSCHEME_T1040_1P: u32 = 10;
pub const XTENSA_HWCIDVERS_T1040_1P: u32 = 16;
pub const XTENSA_HWVERSION_T1040_2: u32 = 104002;
pub const XTENSA_HWCIDSCHEME_T1040_2: u32 = 1;
pub const XTENSA_HWCIDVERS_T1040_2: u32 = 33;
pub const XTENSA_HWVERSION_T1040_3: u32 = 104003;
pub const XTENSA_HWCIDSCHEME_T1040_3: u32 = 1;
pub const XTENSA_HWCIDVERS_T1040_3: u32 = 34;
pub const XTENSA_HWVERSION_T1050_0: u32 = 105000;
pub const XTENSA_HWCIDSCHEME_T1050_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_0: u32 = 1;
pub const XTENSA_HWVERSION_T1050_1: u32 = 105001;
pub const XTENSA_HWCIDSCHEME_T1050_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_1: u32 = 2;
pub const XTENSA_HWVERSION_T1050_2: u32 = 105002;
pub const XTENSA_HWCIDSCHEME_T1050_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_2: u32 = 4;
pub const XTENSA_HWVERSION_T1050_3: u32 = 105003;
pub const XTENSA_HWCIDSCHEME_T1050_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_3: u32 = 6;
pub const XTENSA_HWVERSION_T1050_4: u32 = 105004;
pub const XTENSA_HWCIDSCHEME_T1050_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_4: u32 = 7;
pub const XTENSA_HWVERSION_T1050_5: u32 = 105005;
pub const XTENSA_HWCIDSCHEME_T1050_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_5: u32 = 8;
pub const XTENSA_HWVERSION_RA_2004_1: u32 = 210000;
pub const XTENSA_HWCIDSCHEME_RA_2004_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2004_1: u32 = 3;
pub const XTENSA_HWVERSION_RA_2005_1: u32 = 210001;
pub const XTENSA_HWCIDSCHEME_RA_2005_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2005_1: u32 = 20;
pub const XTENSA_HWVERSION_RA_2005_2: u32 = 210002;
pub const XTENSA_HWCIDSCHEME_RA_2005_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2005_2: u32 = 21;
pub const XTENSA_HWVERSION_RA_2005_3: u32 = 210003;
pub const XTENSA_HWCIDSCHEME_RA_2005_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2005_3: u32 = 22;
pub const XTENSA_HWVERSION_RA_2006_4: u32 = 210004;
pub const XTENSA_HWCIDSCHEME_RA_2006_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2006_4: u32 = 23;
pub const XTENSA_HWVERSION_RA_2006_5: u32 = 210005;
pub const XTENSA_HWCIDSCHEME_RA_2006_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2006_5: u32 = 24;
pub const XTENSA_HWVERSION_RA_2006_6: u32 = 210006;
pub const XTENSA_HWCIDSCHEME_RA_2006_6: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2006_6: u32 = 25;
pub const XTENSA_HWVERSION_RA_2007_7: u32 = 210007;
pub const XTENSA_HWCIDSCHEME_RA_2007_7: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2007_7: u32 = 26;
pub const XTENSA_HWVERSION_RA_2008_8: u32 = 210008;
pub const XTENSA_HWCIDSCHEME_RA_2008_8: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2008_8: u32 = 27;
pub const XTENSA_HWVERSION_RB_2006_0: u32 = 220000;
pub const XTENSA_HWCIDSCHEME_RB_2006_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2006_0: u32 = 48;
pub const XTENSA_HWVERSION_RB_2007_1: u32 = 220001;
pub const XTENSA_HWCIDSCHEME_RB_2007_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2007_1: u32 = 49;
pub const XTENSA_HWVERSION_RB_2007_2: u32 = 221000;
pub const XTENSA_HWCIDSCHEME_RB_2007_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2007_2: u32 = 52;
pub const XTENSA_HWVERSION_RB_2008_3: u32 = 221001;
pub const XTENSA_HWCIDSCHEME_RB_2008_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2008_3: u32 = 53;
pub const XTENSA_HWVERSION_RB_2008_4: u32 = 221002;
pub const XTENSA_HWCIDSCHEME_RB_2008_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2008_4: u32 = 54;
pub const XTENSA_HWVERSION_RB_2009_5: u32 = 221003;
pub const XTENSA_HWCIDSCHEME_RB_2009_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2009_5: u32 = 55;
pub const XTENSA_HWVERSION_RB_2007_2_MP: u32 = 221100;
pub const XTENSA_HWCIDSCHEME_RB_2007_2_MP: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2007_2_MP: u32 = 64;
pub const XTENSA_HWVERSION_RC_2009_0: u32 = 230000;
pub const XTENSA_HWCIDSCHEME_RC_2009_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RC_2009_0: u32 = 65;
pub const XTENSA_HWVERSION_RC_2010_1: u32 = 230001;
pub const XTENSA_HWCIDSCHEME_RC_2010_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RC_2010_1: u32 = 66;
pub const XTENSA_HWVERSION_RC_2010_2: u32 = 230002;
pub const XTENSA_HWCIDSCHEME_RC_2010_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RC_2010_2: u32 = 67;
pub const XTENSA_HWVERSION_RC_2011_3: u32 = 230003;
pub const XTENSA_HWCIDSCHEME_RC_2011_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RC_2011_3: u32 = 68;
pub const XTENSA_HWVERSION_RD_2010_0: u32 = 240000;
pub const XTENSA_HWCIDSCHEME_RD_2010_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2010_0: u32 = 80;
pub const XTENSA_HWVERSION_RD_2011_1: u32 = 240001;
pub const XTENSA_HWCIDSCHEME_RD_2011_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2011_1: u32 = 81;
pub const XTENSA_HWVERSION_RD_2011_2: u32 = 240002;
pub const XTENSA_HWCIDSCHEME_RD_2011_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2011_2: u32 = 82;
pub const XTENSA_HWVERSION_RD_2011_3: u32 = 240003;
pub const XTENSA_HWCIDSCHEME_RD_2011_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2011_3: u32 = 83;
pub const XTENSA_HWVERSION_RD_2012_4: u32 = 240004;
pub const XTENSA_HWCIDSCHEME_RD_2012_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2012_4: u32 = 84;
pub const XTENSA_HWVERSION_RD_2012_5: u32 = 240005;
pub const XTENSA_HWCIDSCHEME_RD_2012_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2012_5: u32 = 85;
pub const XTENSA_HWVERSION_RE_2012_0: u32 = 250000;
pub const XTENSA_HWCIDSCHEME_RE_2012_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2012_0: u32 = 96;
pub const XTENSA_HWVERSION_RE_2012_1: u32 = 250001;
pub const XTENSA_HWCIDSCHEME_RE_2012_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2012_1: u32 = 97;
pub const XTENSA_HWVERSION_RE_2013_2: u32 = 250002;
pub const XTENSA_HWCIDSCHEME_RE_2013_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2013_2: u32 = 98;
pub const XTENSA_HWVERSION_RE_2013_3: u32 = 250003;
pub const XTENSA_HWCIDSCHEME_RE_2013_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2013_3: u32 = 99;
pub const XTENSA_HWVERSION_RE_2013_4: u32 = 250004;
pub const XTENSA_HWCIDSCHEME_RE_2013_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2013_4: u32 = 100;
pub const XTENSA_HWVERSION_RE_2014_5: u32 = 250005;
pub const XTENSA_HWCIDSCHEME_RE_2014_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2014_5: u32 = 101;
pub const XTENSA_HWVERSION_RE_2015_6: u32 = 250006;
pub const XTENSA_HWCIDSCHEME_RE_2015_6: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2015_6: u32 = 102;
pub const XTENSA_HWVERSION_RF_2014_0: u32 = 260000;
pub const XTENSA_HWCIDSCHEME_RF_2014_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RF_2014_0: u32 = 112;
pub const XTENSA_HWVERSION_RF_2014_1: u32 = 260001;
pub const XTENSA_HWCIDSCHEME_RF_2014_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RF_2014_1: u32 = 113;
pub const XTENSA_HWVERSION_RF_2015_2: u32 = 260002;
pub const XTENSA_HWCIDSCHEME_RF_2015_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RF_2015_2: u32 = 114;
pub const XTENSA_HWVERSION_RF_2015_3: u32 = 260003;
pub const XTENSA_HWCIDSCHEME_RF_2015_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RF_2015_3: u32 = 115;
pub const XTENSA_HWVERSION_RF_2016_4: u32 = 260004;
pub const XTENSA_HWCIDSCHEME_RF_2016_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_RF_2016_4: u32 = 116;
pub const XTENSA_HWVERSION_RG_2015_0: u32 = 270000;
pub const XTENSA_HWCIDSCHEME_RG_2015_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2015_0: u32 = 128;
pub const XTENSA_HWVERSION_RG_2015_1: u32 = 270001;
pub const XTENSA_HWCIDSCHEME_RG_2015_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2015_1: u32 = 129;
pub const XTENSA_HWVERSION_RG_2015_2: u32 = 270002;
pub const XTENSA_HWCIDSCHEME_RG_2015_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2015_2: u32 = 130;
pub const XTENSA_HWVERSION_RG_2016_3: u32 = 270003;
pub const XTENSA_HWCIDSCHEME_RG_2016_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2016_3: u32 = 131;
pub const XTENSA_HWVERSION_RG_2016_4: u32 = 270004;
pub const XTENSA_HWCIDSCHEME_RG_2016_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2016_4: u32 = 132;
pub const XTENSA_HWVERSION_RG_2017_5: u32 = 270005;
pub const XTENSA_HWCIDSCHEME_RG_2017_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2017_5: u32 = 133;
pub const XTENSA_HWVERSION_RG_2017_6: u32 = 270006;
pub const XTENSA_HWCIDSCHEME_RG_2017_6: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2017_6: u32 = 134;
pub const XTENSA_HWVERSION_RG_2017_7: u32 = 270007;
pub const XTENSA_HWCIDSCHEME_RG_2017_7: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2017_7: u32 = 135;
pub const XTENSA_HWVERSION_RG_2017_8: u32 = 270008;
pub const XTENSA_HWCIDSCHEME_RG_2017_8: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2017_8: u32 = 136;
pub const XTENSA_HWVERSION_RG_2018_9: u32 = 270009;
pub const XTENSA_HWCIDSCHEME_RG_2018_9: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2018_9: u32 = 137;
pub const XTENSA_HWVERSION_RH_2016_0: u32 = 280000;
pub const XTENSA_HWCIDSCHEME_RH_2016_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RH_2016_0: u32 = 144;
pub const XTENSA_SWVERSION_T1020_0: u32 = 102000;
pub const XTENSA_SWVERSION_T1020_1: u32 = 102001;
pub const XTENSA_SWVERSION_T1020_2: u32 = 102002;
pub const XTENSA_SWVERSION_T1020_2B: u32 = 102002;
pub const XTENSA_SWVERSION_T1020_3: u32 = 102003;
pub const XTENSA_SWVERSION_T1020_4: u32 = 102004;
pub const XTENSA_SWVERSION_T1030_0: u32 = 103000;
pub const XTENSA_SWVERSION_T1030_1: u32 = 103001;
pub const XTENSA_SWVERSION_T1030_2: u32 = 103002;
pub const XTENSA_SWVERSION_T1030_3: u32 = 103003;
pub const XTENSA_SWVERSION_T1040_0: u32 = 104000;
pub const XTENSA_SWVERSION_T1040_1: u32 = 104001;
pub const XTENSA_SWVERSION_T1040_1P: u32 = 104001;
pub const XTENSA_SWVERSION_T1040_2: u32 = 104002;
pub const XTENSA_SWVERSION_T1040_3: u32 = 104003;
pub const XTENSA_SWVERSION_T1050_0: u32 = 105000;
pub const XTENSA_SWVERSION_T1050_1: u32 = 105001;
pub const XTENSA_SWVERSION_T1050_2: u32 = 105002;
pub const XTENSA_SWVERSION_T1050_3: u32 = 105003;
pub const XTENSA_SWVERSION_T1050_4: u32 = 105004;
pub const XTENSA_SWVERSION_T1050_5: u32 = 105005;
pub const XTENSA_SWVERSION_RA_2004_1: u32 = 600000;
pub const XTENSA_SWVERSION_RA_2005_1: u32 = 600001;
pub const XTENSA_SWVERSION_RA_2005_2: u32 = 600002;
pub const XTENSA_SWVERSION_RA_2005_3: u32 = 600003;
pub const XTENSA_SWVERSION_RA_2006_4: u32 = 600004;
pub const XTENSA_SWVERSION_RA_2006_5: u32 = 600005;
pub const XTENSA_SWVERSION_RA_2006_6: u32 = 600006;
pub const XTENSA_SWVERSION_RA_2007_7: u32 = 600007;
pub const XTENSA_SWVERSION_RA_2008_8: u32 = 600008;
pub const XTENSA_SWVERSION_RB_2006_0: u32 = 700000;
pub const XTENSA_SWVERSION_RB_2007_1: u32 = 700001;
pub const XTENSA_SWVERSION_RB_2007_2: u32 = 701000;
pub const XTENSA_SWVERSION_RB_2008_3: u32 = 701001;
pub const XTENSA_SWVERSION_RB_2008_4: u32 = 701002;
pub const XTENSA_SWVERSION_RB_2009_5: u32 = 701003;
pub const XTENSA_SWVERSION_RB_2007_2_MP: u32 = 701100;
pub const XTENSA_SWVERSION_RC_2009_0: u32 = 800000;
pub const XTENSA_SWVERSION_RC_2010_1: u32 = 800001;
pub const XTENSA_SWVERSION_RC_2010_2: u32 = 800002;
pub const XTENSA_SWVERSION_RC_2011_3: u32 = 800003;
pub const XTENSA_SWVERSION_RD_2010_0: u32 = 900000;
pub const XTENSA_SWVERSION_RD_2011_1: u32 = 900001;
pub const XTENSA_SWVERSION_RD_2011_2: u32 = 900002;
pub const XTENSA_SWVERSION_RD_2011_3: u32 = 900003;
pub const XTENSA_SWVERSION_RD_2012_4: u32 = 900004;
pub const XTENSA_SWVERSION_RD_2012_5: u32 = 900005;
pub const XTENSA_SWVERSION_RE_2012_0: u32 = 1000000;
pub const XTENSA_SWVERSION_RE_2012_1: u32 = 1000001;
pub const XTENSA_SWVERSION_RE_2013_2: u32 = 1000002;
pub const XTENSA_SWVERSION_RE_2013_3: u32 = 1000003;
pub const XTENSA_SWVERSION_RE_2013_4: u32 = 1000004;
pub const XTENSA_SWVERSION_RE_2014_5: u32 = 1000005;
pub const XTENSA_SWVERSION_RE_2015_6: u32 = 1000006;
pub const XTENSA_SWVERSION_RF_2014_0: u32 = 1100000;
pub const XTENSA_SWVERSION_RF_2014_1: u32 = 1100001;
pub const XTENSA_SWVERSION_RF_2015_2: u32 = 1100002;
pub const XTENSA_SWVERSION_RF_2015_3: u32 = 1100003;
pub const XTENSA_SWVERSION_RF_2016_4: u32 = 1100004;
pub const XTENSA_SWVERSION_RG_2015_0: u32 = 1200000;
pub const XTENSA_SWVERSION_RG_2015_1: u32 = 1200001;
pub const XTENSA_SWVERSION_RG_2015_2: u32 = 1200002;
pub const XTENSA_SWVERSION_RG_2016_3: u32 = 1200003;
pub const XTENSA_SWVERSION_RG_2016_4: u32 = 1200004;
pub const XTENSA_SWVERSION_RG_2017_5: u32 = 1200005;
pub const XTENSA_SWVERSION_RG_2017_6: u32 = 1200006;
pub const XTENSA_SWVERSION_RG_2017_7: u32 = 1200007;
pub const XTENSA_SWVERSION_RG_2017_8: u32 = 1200008;
pub const XTENSA_SWVERSION_RG_2018_9: u32 = 1200009;
pub const XTENSA_SWVERSION_RH_2016_0: u32 = 1300000;
pub const XTENSA_SWVERSION_T1040_1_PREHOTFIX: u32 = 104001;
pub const XTENSA_SWVERSION_6_0_0: u32 = 600000;
pub const XTENSA_SWVERSION_6_0_1: u32 = 600001;
pub const XTENSA_SWVERSION_6_0_2: u32 = 600002;
pub const XTENSA_SWVERSION_6_0_3: u32 = 600003;
pub const XTENSA_SWVERSION_6_0_4: u32 = 600004;
pub const XTENSA_SWVERSION_6_0_5: u32 = 600005;
pub const XTENSA_SWVERSION_6_0_6: u32 = 600006;
pub const XTENSA_SWVERSION_6_0_7: u32 = 600007;
pub const XTENSA_SWVERSION_6_0_8: u32 = 600008;
pub const XTENSA_SWVERSION_7_0_0: u32 = 700000;
pub const XTENSA_SWVERSION_7_0_1: u32 = 700001;
pub const XTENSA_SWVERSION_7_1_0: u32 = 701000;
pub const XTENSA_SWVERSION_7_1_1: u32 = 701001;
pub const XTENSA_SWVERSION_7_1_2: u32 = 701002;
pub const XTENSA_SWVERSION_7_1_3: u32 = 701003;
pub const XTENSA_SWVERSION_7_1_8_MP: u32 = 701100;
pub const XTENSA_SWVERSION_8_0_0: u32 = 800000;
pub const XTENSA_SWVERSION_8_0_1: u32 = 800001;
pub const XTENSA_SWVERSION_8_0_2: u32 = 800002;
pub const XTENSA_SWVERSION_8_0_3: u32 = 800003;
pub const XTENSA_SWVERSION_9_0_0: u32 = 900000;
pub const XTENSA_SWVERSION_9_0_1: u32 = 900001;
pub const XTENSA_SWVERSION_9_0_2: u32 = 900002;
pub const XTENSA_SWVERSION_9_0_3: u32 = 900003;
pub const XTENSA_SWVERSION_9_0_4: u32 = 900004;
pub const XTENSA_SWVERSION_9_0_5: u32 = 900005;
pub const XTENSA_SWVERSION_10_0_0: u32 = 1000000;
pub const XTENSA_SWVERSION_10_0_1: u32 = 1000001;
pub const XTENSA_SWVERSION_10_0_2: u32 = 1000002;
pub const XTENSA_SWVERSION_10_0_3: u32 = 1000003;
pub const XTENSA_SWVERSION_10_0_4: u32 = 1000004;
pub const XTENSA_SWVERSION_10_0_5: u32 = 1000005;
pub const XTENSA_SWVERSION_10_0_6: u32 = 1000006;
pub const XTENSA_SWVERSION_11_0_0: u32 = 1100000;
pub const XTENSA_SWVERSION_11_0_1: u32 = 1100001;
pub const XTENSA_SWVERSION_11_0_2: u32 = 1100002;
pub const XTENSA_SWVERSION_11_0_3: u32 = 1100003;
pub const XTENSA_SWVERSION_11_0_4: u32 = 1100004;
pub const XTENSA_SWVERSION_12_0_0: u32 = 1200000;
pub const XTENSA_SWVERSION_12_0_1: u32 = 1200001;
pub const XTENSA_SWVERSION_12_0_2: u32 = 1200002;
pub const XTENSA_SWVERSION_12_0_3: u32 = 1200003;
pub const XTENSA_SWVERSION_12_0_4: u32 = 1200004;
pub const XTENSA_SWVERSION_12_0_5: u32 = 1200005;
pub const XTENSA_SWVERSION_12_0_6: u32 = 1200006;
pub const XTENSA_SWVERSION_12_0_7: u32 = 1200007;
pub const XTENSA_SWVERSION_12_0_8: u32 = 1200008;
pub const XTENSA_SWVERSION_12_0_9: u32 = 1200009;
pub const XTENSA_SWVERSION_13_0_0: u32 = 1300000;
pub const XTENSA_RELEASE_NAME: &[u8; 10usize] = b"RG-2018.9\0";
pub const XTENSA_RELEASE_CANONICAL_NAME: &[u8; 10usize] = b"RG-2018.9\0";
pub const XTENSA_SWVERSION: u32 = 1200009;
pub const XTENSA_SWVERSION_NAME: &[u8; 7usize] = b"12.0.9\0";
pub const XTENSA_SWVERSION_CANONICAL_NAME: &[u8; 7usize] = b"12.0.9\0";
pub const XTENSA_SWVERSION_MAJORMID_NAME: &[u8; 5usize] = b"12.0\0";
pub const XTENSA_SWVERSION_MAJOR_NAME: &[u8; 3usize] = b"12\0";
pub const XTENSA_SWVERSION_LICENSE_NAME: &[u8; 5usize] = b"12.0\0";
pub const XCHAL_HAVE_BE: u32 = 0;
pub const XCHAL_HAVE_WINDOWED: u32 = 1;
pub const XCHAL_NUM_AREGS: u32 = 64;
pub const XCHAL_NUM_AREGS_LOG2: u32 = 6;
pub const XCHAL_MAX_INSTRUCTION_SIZE: u32 = 4;
pub const XCHAL_HAVE_DEBUG: u32 = 1;
pub const XCHAL_HAVE_DENSITY: u32 = 1;
pub const XCHAL_HAVE_LOOPS: u32 = 1;
pub const XCHAL_LOOP_BUFFER_SIZE: u32 = 256;
pub const XCHAL_HAVE_NSA: u32 = 1;
pub const XCHAL_HAVE_MINMAX: u32 = 1;
pub const XCHAL_HAVE_SEXT: u32 = 1;
pub const XCHAL_HAVE_DEPBITS: u32 = 0;
pub const XCHAL_HAVE_CLAMPS: u32 = 1;
pub const XCHAL_HAVE_MUL16: u32 = 1;
pub const XCHAL_HAVE_MUL32: u32 = 1;
pub const XCHAL_HAVE_MUL32_HIGH: u32 = 1;
pub const XCHAL_HAVE_DIV32: u32 = 1;
pub const XCHAL_HAVE_L32R: u32 = 1;
pub const XCHAL_HAVE_ABSOLUTE_LITERALS: u32 = 0;
pub const XCHAL_HAVE_CONST16: u32 = 0;
pub const XCHAL_HAVE_ADDX: u32 = 1;
pub const XCHAL_HAVE_EXCLUSIVE: u32 = 0;
pub const XCHAL_HAVE_WIDE_BRANCHES: u32 = 0;
pub const XCHAL_HAVE_PREDICTED_BRANCHES: u32 = 0;
pub const XCHAL_HAVE_CALL4AND12: u32 = 1;
pub const XCHAL_HAVE_ABS: u32 = 1;
pub const XCHAL_HAVE_RELEASE_SYNC: u32 = 1;
pub const XCHAL_HAVE_S32C1I: u32 = 1;
pub const XCHAL_HAVE_SPECULATION: u32 = 0;
pub const XCHAL_HAVE_FULL_RESET: u32 = 1;
pub const XCHAL_NUM_CONTEXTS: u32 = 1;
pub const XCHAL_NUM_MISC_REGS: u32 = 4;
pub const XCHAL_HAVE_TAP_MASTER: u32 = 0;
pub const XCHAL_HAVE_PRID: u32 = 1;
pub const XCHAL_HAVE_EXTERN_REGS: u32 = 1;
pub const XCHAL_HAVE_MX: u32 = 0;
pub const XCHAL_HAVE_MP_INTERRUPTS: u32 = 0;
pub const XCHAL_HAVE_MP_RUNSTALL: u32 = 0;
pub const XCHAL_HAVE_PSO: u32 = 0;
pub const XCHAL_HAVE_PSO_CDM: u32 = 0;
pub const XCHAL_HAVE_PSO_FULL_RETENTION: u32 = 0;
pub const XCHAL_HAVE_THREADPTR: u32 = 1;
pub const XCHAL_HAVE_BOOLEANS: u32 = 1;
pub const XCHAL_HAVE_CP: u32 = 1;
pub const XCHAL_CP_MAXCFG: u32 = 8;
pub const XCHAL_HAVE_MAC16: u32 = 1;
pub const XCHAL_HAVE_FUSION: u32 = 0;
pub const XCHAL_HAVE_FUSION_FP: u32 = 0;
pub const XCHAL_HAVE_FUSION_LOW_POWER: u32 = 0;
pub const XCHAL_HAVE_FUSION_AES: u32 = 0;
pub const XCHAL_HAVE_FUSION_CONVENC: u32 = 0;
pub const XCHAL_HAVE_FUSION_LFSR_CRC: u32 = 0;
pub const XCHAL_HAVE_FUSION_BITOPS: u32 = 0;
pub const XCHAL_HAVE_FUSION_AVS: u32 = 0;
pub const XCHAL_HAVE_FUSION_16BIT_BASEBAND: u32 = 0;
pub const XCHAL_HAVE_FUSION_VITERBI: u32 = 0;
pub const XCHAL_HAVE_FUSION_SOFTDEMAP: u32 = 0;
pub const XCHAL_HAVE_HIFIPRO: u32 = 0;
pub const XCHAL_HAVE_HIFI5: u32 = 0;
pub const XCHAL_HAVE_HIFI5_NN_MAC: u32 = 0;
pub const XCHAL_HAVE_HIFI5_VFPU: u32 = 0;
pub const XCHAL_HAVE_HIFI5_HP_VFPU: u32 = 0;
pub const XCHAL_HAVE_HIFI4: u32 = 0;
pub const XCHAL_HAVE_HIFI4_VFPU: u32 = 0;
pub const XCHAL_HAVE_HIFI3: u32 = 0;
pub const XCHAL_HAVE_HIFI3_VFPU: u32 = 0;
pub const XCHAL_HAVE_HIFI3Z: u32 = 0;
pub const XCHAL_HAVE_HIFI3Z_VFPU: u32 = 0;
pub const XCHAL_HAVE_HIFI2: u32 = 0;
pub const XCHAL_HAVE_HIFI2EP: u32 = 0;
pub const XCHAL_HAVE_HIFI_MINI: u32 = 0;
pub const XCHAL_HAVE_VECTORFPU2005: u32 = 0;
pub const XCHAL_HAVE_USER_DPFPU: u32 = 0;
pub const XCHAL_HAVE_USER_SPFPU: u32 = 0;
pub const XCHAL_HAVE_FP: u32 = 1;
pub const XCHAL_HAVE_FP_DIV: u32 = 1;
pub const XCHAL_HAVE_FP_RECIP: u32 = 1;
pub const XCHAL_HAVE_FP_SQRT: u32 = 1;
pub const XCHAL_HAVE_FP_RSQRT: u32 = 1;
pub const XCHAL_HAVE_DFP: u32 = 0;
pub const XCHAL_HAVE_DFP_DIV: u32 = 0;
pub const XCHAL_HAVE_DFP_RECIP: u32 = 0;
pub const XCHAL_HAVE_DFP_SQRT: u32 = 0;
pub const XCHAL_HAVE_DFP_RSQRT: u32 = 0;
pub const XCHAL_HAVE_DFP_ACCEL: u32 = 0;
pub const XCHAL_HAVE_DFP_accel: u32 = 0;
pub const XCHAL_HAVE_DFPU_SINGLE_ONLY: u32 = 1;
pub const XCHAL_HAVE_DFPU_SINGLE_DOUBLE: u32 = 0;
pub const XCHAL_HAVE_VECTRA1: u32 = 0;
pub const XCHAL_HAVE_VECTRALX: u32 = 0;
pub const XCHAL_HAVE_FUSIONG: u32 = 0;
pub const XCHAL_HAVE_FUSIONG3: u32 = 0;
pub const XCHAL_HAVE_FUSIONG6: u32 = 0;
pub const XCHAL_HAVE_FUSIONG_SP_VFPU: u32 = 0;
pub const XCHAL_HAVE_FUSIONG_DP_VFPU: u32 = 0;
pub const XCHAL_FUSIONG_SIMD32: u32 = 0;
pub const XCHAL_HAVE_PDX: u32 = 0;
pub const XCHAL_PDX_SIMD32: u32 = 0;
pub const XCHAL_HAVE_PDX4: u32 = 0;
pub const XCHAL_HAVE_PDX8: u32 = 0;
pub const XCHAL_HAVE_PDX16: u32 = 0;
pub const XCHAL_HAVE_CONNXD2: u32 = 0;
pub const XCHAL_HAVE_CONNXD2_DUALLSFLIX: u32 = 0;
pub const XCHAL_HAVE_BBE16: u32 = 0;
pub const XCHAL_HAVE_BBE16_RSQRT: u32 = 0;
pub const XCHAL_HAVE_BBE16_VECDIV: u32 = 0;
pub const XCHAL_HAVE_BBE16_DESPREAD: u32 = 0;
pub const XCHAL_HAVE_BBENEP: u32 = 0;
pub const XCHAL_HAVE_BBENEP_SP_VFPU: u32 = 0;
pub const XCHAL_HAVE_BSP3: u32 = 0;
pub const XCHAL_HAVE_BSP3_TRANSPOSE: u32 = 0;
pub const XCHAL_HAVE_SSP16: u32 = 0;
pub const XCHAL_HAVE_SSP16_VITERBI: u32 = 0;
pub const XCHAL_HAVE_TURBO16: u32 = 0;
pub const XCHAL_HAVE_BBP16: u32 = 0;
pub const XCHAL_HAVE_FLIX3: u32 = 0;
pub const XCHAL_HAVE_GRIVPEP: u32 = 0;
pub const XCHAL_HAVE_GRIVPEP_HISTOGRAM: u32 = 0;
pub const XCHAL_HAVE_VISION: u32 = 0;
pub const XCHAL_VISION_SIMD16: u32 = 0;
pub const XCHAL_VISION_TYPE: u32 = 0;
pub const XCHAL_VISION_QUAD_MAC_TYPE: u32 = 0;
pub const XCHAL_HAVE_VISION_HISTOGRAM: u32 = 0;
pub const XCHAL_HAVE_VISION_SP_VFPU: u32 = 0;
pub const XCHAL_HAVE_VISION_HP_VFPU: u32 = 0;
pub const XCHAL_HAVE_VISIONC: u32 = 0;
pub const XCHAL_NUM_LOADSTORE_UNITS: u32 = 1;
pub const XCHAL_NUM_WRITEBUFFER_ENTRIES: u32 = 4;
pub const XCHAL_INST_FETCH_WIDTH: u32 = 4;
pub const XCHAL_DATA_WIDTH: u32 = 16;
pub const XCHAL_DATA_PIPE_DELAY: u32 = 1;
pub const XCHAL_CLOCK_GATING_GLOBAL: u32 = 1;
pub const XCHAL_CLOCK_GATING_FUNCUNIT: u32 = 1;
pub const XCHAL_UNALIGNED_LOAD_EXCEPTION: u32 = 0;
pub const XCHAL_UNALIGNED_STORE_EXCEPTION: u32 = 0;
pub const XCHAL_UNALIGNED_LOAD_HW: u32 = 1;
pub const XCHAL_UNALIGNED_STORE_HW: u32 = 1;
pub const XCHAL_SW_VERSION: u32 = 1200012;
pub const XCHAL_CORE_ID: &[u8; 16usize] = b"LX7_ESP32_S3_MP\0";
pub const XCHAL_BUILD_UNIQUE_ID: u32 = 593695;
pub const XCHAL_HW_CONFIGID0: u32 = 3270574078;
pub const XCHAL_HW_CONFIGID1: u32 = 587796255;
pub const XCHAL_HW_VERSION_NAME: &[u8; 9usize] = b"LX7.0.12\0";
pub const XCHAL_HW_VERSION_MAJOR: u32 = 2700;
pub const XCHAL_HW_VERSION_MINOR: u32 = 12;
pub const XCHAL_HW_VERSION: u32 = 270012;
pub const XCHAL_HW_REL_LX7: u32 = 1;
pub const XCHAL_HW_REL_LX7_0: u32 = 1;
pub const XCHAL_HW_REL_LX7_0_12: u32 = 1;
pub const XCHAL_HW_CONFIGID_RELIABLE: u32 = 1;
pub const XCHAL_HW_MIN_VERSION_MAJOR: u32 = 2700;
pub const XCHAL_HW_MIN_VERSION_MINOR: u32 = 12;
pub const XCHAL_HW_MIN_VERSION: u32 = 270012;
pub const XCHAL_HW_MAX_VERSION_MAJOR: u32 = 2700;
pub const XCHAL_HW_MAX_VERSION_MINOR: u32 = 12;
pub const XCHAL_HW_MAX_VERSION: u32 = 270012;
pub const XCHAL_ICACHE_LINESIZE: u32 = 4;
pub const XCHAL_DCACHE_LINESIZE: u32 = 16;
pub const XCHAL_ICACHE_LINEWIDTH: u32 = 2;
pub const XCHAL_DCACHE_LINEWIDTH: u32 = 4;
pub const XCHAL_ICACHE_SIZE: u32 = 0;
pub const XCHAL_DCACHE_SIZE: u32 = 0;
pub const XCHAL_DCACHE_IS_WRITEBACK: u32 = 0;
pub const XCHAL_DCACHE_IS_COHERENT: u32 = 0;
pub const XCHAL_HAVE_PREFETCH: u32 = 0;
pub const XCHAL_HAVE_PREFETCH_L1: u32 = 0;
pub const XCHAL_PREFETCH_CASTOUT_LINES: u32 = 0;
pub const XCHAL_PREFETCH_ENTRIES: u32 = 0;
pub const XCHAL_PREFETCH_BLOCK_ENTRIES: u32 = 0;
pub const XCHAL_HAVE_CACHE_BLOCKOPS: u32 = 0;
pub const XCHAL_HAVE_ICACHE_TEST: u32 = 0;
pub const XCHAL_HAVE_DCACHE_TEST: u32 = 0;
pub const XCHAL_HAVE_ICACHE_DYN_WAYS: u32 = 0;
pub const XCHAL_HAVE_DCACHE_DYN_WAYS: u32 = 0;
pub const XCHAL_HAVE_PIF: u32 = 1;
pub const XCHAL_HAVE_AXI: u32 = 0;
pub const XCHAL_HAVE_AXI_ECC: u32 = 0;
pub const XCHAL_HAVE_ACELITE: u32 = 0;
pub const XCHAL_HAVE_PIF_WR_RESP: u32 = 0;
pub const XCHAL_HAVE_PIF_REQ_ATTR: u32 = 1;
pub const XCHAL_ICACHE_SETWIDTH: u32 = 0;
pub const XCHAL_DCACHE_SETWIDTH: u32 = 0;
pub const XCHAL_ICACHE_WAYS: u32 = 1;
pub const XCHAL_DCACHE_WAYS: u32 = 1;
pub const XCHAL_ICACHE_LINE_LOCKABLE: u32 = 0;
pub const XCHAL_DCACHE_LINE_LOCKABLE: u32 = 0;
pub const XCHAL_ICACHE_ECC_PARITY: u32 = 0;
pub const XCHAL_DCACHE_ECC_PARITY: u32 = 0;
pub const XCHAL_ICACHE_ECC_WIDTH: u32 = 1;
pub const XCHAL_DCACHE_ECC_WIDTH: u32 = 1;
pub const XCHAL_ICACHE_ACCESS_SIZE: u32 = 1;
pub const XCHAL_DCACHE_ACCESS_SIZE: u32 = 1;
pub const XCHAL_DCACHE_BANKS: u32 = 0;
pub const XCHAL_CA_BITS: u32 = 4;
pub const XCHAL_NUM_INSTROM: u32 = 0;
pub const XCHAL_NUM_INSTRAM: u32 = 1;
pub const XCHAL_NUM_DATAROM: u32 = 0;
pub const XCHAL_NUM_DATARAM: u32 = 1;
pub const XCHAL_NUM_URAM: u32 = 0;
pub const XCHAL_NUM_XLMI: u32 = 0;
pub const XCHAL_INSTRAM0_VADDR: u32 = 1073741824;
pub const XCHAL_INSTRAM0_PADDR: u32 = 1073741824;
pub const XCHAL_INSTRAM0_SIZE: u32 = 67108864;
pub const XCHAL_INSTRAM0_ECC_PARITY: u32 = 0;
pub const XCHAL_HAVE_INSTRAM0: u32 = 1;
pub const XCHAL_INSTRAM0_HAVE_IDMA: u32 = 0;
pub const XCHAL_DATARAM0_VADDR: u32 = 1006632960;
pub const XCHAL_DATARAM0_PADDR: u32 = 1006632960;
pub const XCHAL_DATARAM0_SIZE: u32 = 67108864;
pub const XCHAL_DATARAM0_ECC_PARITY: u32 = 0;
pub const XCHAL_DATARAM0_BANKS: u32 = 1;
pub const XCHAL_HAVE_DATARAM0: u32 = 1;
pub const XCHAL_DATARAM0_HAVE_IDMA: u32 = 0;
pub const XCHAL_HAVE_IDMA: u32 = 0;
pub const XCHAL_HAVE_IDMA_TRANSPOSE: u32 = 0;
pub const XCHAL_HAVE_IMEM_LOADSTORE: u32 = 1;
pub const XCHAL_HAVE_INTERRUPTS: u32 = 1;
pub const XCHAL_HAVE_HIGHPRI_INTERRUPTS: u32 = 1;
pub const XCHAL_HAVE_NMI: u32 = 1;
pub const XCHAL_HAVE_CCOUNT: u32 = 1;
pub const XCHAL_NUM_TIMERS: u32 = 3;
pub const XCHAL_NUM_INTERRUPTS: u32 = 32;
pub const XCHAL_NUM_INTERRUPTS_LOG2: u32 = 5;
pub const XCHAL_NUM_EXTINTERRUPTS: u32 = 26;
pub const XCHAL_NUM_INTLEVELS: u32 = 6;
pub const XCHAL_EXCM_LEVEL: u32 = 3;
pub const XCHAL_INTLEVEL1_MASK: u32 = 407551;
pub const XCHAL_INTLEVEL2_MASK: u32 = 3670016;
pub const XCHAL_INTLEVEL3_MASK: u32 = 683706368;
pub const XCHAL_INTLEVEL4_MASK: u32 = 1392508928;
pub const XCHAL_INTLEVEL5_MASK: u32 = 2214658048;
pub const XCHAL_INTLEVEL6_MASK: u32 = 0;
pub const XCHAL_INTLEVEL7_MASK: u32 = 16384;
pub const XCHAL_INTLEVEL1_ANDBELOW_MASK: u32 = 407551;
pub const XCHAL_INTLEVEL2_ANDBELOW_MASK: u32 = 4077567;
pub const XCHAL_INTLEVEL3_ANDBELOW_MASK: u32 = 687783935;
pub const XCHAL_INTLEVEL4_ANDBELOW_MASK: u32 = 2080292863;
pub const XCHAL_INTLEVEL5_ANDBELOW_MASK: u32 = 4294950911;
pub const XCHAL_INTLEVEL6_ANDBELOW_MASK: u32 = 4294950911;
pub const XCHAL_INTLEVEL7_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INT0_LEVEL: u32 = 1;
pub const XCHAL_INT1_LEVEL: u32 = 1;
pub const XCHAL_INT2_LEVEL: u32 = 1;
pub const XCHAL_INT3_LEVEL: u32 = 1;
pub const XCHAL_INT4_LEVEL: u32 = 1;
pub const XCHAL_INT5_LEVEL: u32 = 1;
pub const XCHAL_INT6_LEVEL: u32 = 1;
pub const XCHAL_INT7_LEVEL: u32 = 1;
pub const XCHAL_INT8_LEVEL: u32 = 1;
pub const XCHAL_INT9_LEVEL: u32 = 1;
pub const XCHAL_INT10_LEVEL: u32 = 1;
pub const XCHAL_INT11_LEVEL: u32 = 3;
pub const XCHAL_INT12_LEVEL: u32 = 1;
pub const XCHAL_INT13_LEVEL: u32 = 1;
pub const XCHAL_INT14_LEVEL: u32 = 7;
pub const XCHAL_INT15_LEVEL: u32 = 3;
pub const XCHAL_INT16_LEVEL: u32 = 5;
pub const XCHAL_INT17_LEVEL: u32 = 1;
pub const XCHAL_INT18_LEVEL: u32 = 1;
pub const XCHAL_INT19_LEVEL: u32 = 2;
pub const XCHAL_INT20_LEVEL: u32 = 2;
pub const XCHAL_INT21_LEVEL: u32 = 2;
pub const XCHAL_INT22_LEVEL: u32 = 3;
pub const XCHAL_INT23_LEVEL: u32 = 3;
pub const XCHAL_INT24_LEVEL: u32 = 4;
pub const XCHAL_INT25_LEVEL: u32 = 4;
pub const XCHAL_INT26_LEVEL: u32 = 5;
pub const XCHAL_INT27_LEVEL: u32 = 3;
pub const XCHAL_INT28_LEVEL: u32 = 4;
pub const XCHAL_INT29_LEVEL: u32 = 3;
pub const XCHAL_INT30_LEVEL: u32 = 4;
pub const XCHAL_INT31_LEVEL: u32 = 5;
pub const XCHAL_DEBUGLEVEL: u32 = 6;
pub const XCHAL_HAVE_DEBUG_EXTERN_INT: u32 = 1;
pub const XCHAL_NMILEVEL: u32 = 7;
pub const XCHAL_INT0_TYPE: u32 = 3;
pub const XCHAL_INT1_TYPE: u32 = 3;
pub const XCHAL_INT2_TYPE: u32 = 3;
pub const XCHAL_INT3_TYPE: u32 = 3;
pub const XCHAL_INT4_TYPE: u32 = 3;
pub const XCHAL_INT5_TYPE: u32 = 3;
pub const XCHAL_INT6_TYPE: u32 = 4;
pub const XCHAL_INT7_TYPE: u32 = 1;
pub const XCHAL_INT8_TYPE: u32 = 3;
pub const XCHAL_INT9_TYPE: u32 = 3;
pub const XCHAL_INT10_TYPE: u32 = 2;
pub const XCHAL_INT11_TYPE: u32 = 7;
pub const XCHAL_INT12_TYPE: u32 = 3;
pub const XCHAL_INT13_TYPE: u32 = 3;
pub const XCHAL_INT14_TYPE: u32 = 5;
pub const XCHAL_INT15_TYPE: u32 = 4;
pub const XCHAL_INT16_TYPE: u32 = 4;
pub const XCHAL_INT17_TYPE: u32 = 3;
pub const XCHAL_INT18_TYPE: u32 = 3;
pub const XCHAL_INT19_TYPE: u32 = 3;
pub const XCHAL_INT20_TYPE: u32 = 3;
pub const XCHAL_INT21_TYPE: u32 = 3;
pub const XCHAL_INT22_TYPE: u32 = 2;
pub const XCHAL_INT23_TYPE: u32 = 3;
pub const XCHAL_INT24_TYPE: u32 = 3;
pub const XCHAL_INT25_TYPE: u32 = 3;
pub const XCHAL_INT26_TYPE: u32 = 3;
pub const XCHAL_INT27_TYPE: u32 = 3;
pub const XCHAL_INT28_TYPE: u32 = 2;
pub const XCHAL_INT29_TYPE: u32 = 1;
pub const XCHAL_INT30_TYPE: u32 = 2;
pub const XCHAL_INT31_TYPE: u32 = 3;
pub const XCHAL_INTTYPE_MASK_UNCONFIGURED: u32 = 0;
pub const XCHAL_INTTYPE_MASK_SOFTWARE: u32 = 536871040;
pub const XCHAL_INTTYPE_MASK_EXTERN_EDGE: u32 = 1346372608;
pub const XCHAL_INTTYPE_MASK_EXTERN_LEVEL: u32 = 2411606847;
pub const XCHAL_INTTYPE_MASK_TIMER: u32 = 98368;
pub const XCHAL_INTTYPE_MASK_NMI: u32 = 16384;
pub const XCHAL_INTTYPE_MASK_WRITE_ERROR: u32 = 0;
pub const XCHAL_INTTYPE_MASK_PROFILING: u32 = 2048;
pub const XCHAL_INTTYPE_MASK_IDMA_DONE: u32 = 0;
pub const XCHAL_INTTYPE_MASK_IDMA_ERR: u32 = 0;
pub const XCHAL_INTTYPE_MASK_GS_ERR: u32 = 0;
pub const XCHAL_TIMER0_INTERRUPT: u32 = 6;
pub const XCHAL_TIMER1_INTERRUPT: u32 = 15;
pub const XCHAL_TIMER2_INTERRUPT: u32 = 16;
pub const XCHAL_TIMER3_INTERRUPT: i32 = -1;
pub const XCHAL_NMI_INTERRUPT: u32 = 14;
pub const XCHAL_PROFILING_INTERRUPT: u32 = 11;
pub const XCHAL_INTLEVEL7_NUM: u32 = 14;
pub const XCHAL_EXTINT0_NUM: u32 = 0;
pub const XCHAL_EXTINT1_NUM: u32 = 1;
pub const XCHAL_EXTINT2_NUM: u32 = 2;
pub const XCHAL_EXTINT3_NUM: u32 = 3;
pub const XCHAL_EXTINT4_NUM: u32 = 4;
pub const XCHAL_EXTINT5_NUM: u32 = 5;
pub const XCHAL_EXTINT6_NUM: u32 = 8;
pub const XCHAL_EXTINT7_NUM: u32 = 9;
pub const XCHAL_EXTINT8_NUM: u32 = 10;
pub const XCHAL_EXTINT9_NUM: u32 = 12;
pub const XCHAL_EXTINT10_NUM: u32 = 13;
pub const XCHAL_EXTINT11_NUM: u32 = 14;
pub const XCHAL_EXTINT12_NUM: u32 = 17;
pub const XCHAL_EXTINT13_NUM: u32 = 18;
pub const XCHAL_EXTINT14_NUM: u32 = 19;
pub const XCHAL_EXTINT15_NUM: u32 = 20;
pub const XCHAL_EXTINT16_NUM: u32 = 21;
pub const XCHAL_EXTINT17_NUM: u32 = 22;
pub const XCHAL_EXTINT18_NUM: u32 = 23;
pub const XCHAL_EXTINT19_NUM: u32 = 24;
pub const XCHAL_EXTINT20_NUM: u32 = 25;
pub const XCHAL_EXTINT21_NUM: u32 = 26;
pub const XCHAL_EXTINT22_NUM: u32 = 27;
pub const XCHAL_EXTINT23_NUM: u32 = 28;
pub const XCHAL_EXTINT24_NUM: u32 = 30;
pub const XCHAL_EXTINT25_NUM: u32 = 31;
pub const XCHAL_INT0_EXTNUM: u32 = 0;
pub const XCHAL_INT1_EXTNUM: u32 = 1;
pub const XCHAL_INT2_EXTNUM: u32 = 2;
pub const XCHAL_INT3_EXTNUM: u32 = 3;
pub const XCHAL_INT4_EXTNUM: u32 = 4;
pub const XCHAL_INT5_EXTNUM: u32 = 5;
pub const XCHAL_INT8_EXTNUM: u32 = 6;
pub const XCHAL_INT9_EXTNUM: u32 = 7;
pub const XCHAL_INT10_EXTNUM: u32 = 8;
pub const XCHAL_INT12_EXTNUM: u32 = 9;
pub const XCHAL_INT13_EXTNUM: u32 = 10;
pub const XCHAL_INT14_EXTNUM: u32 = 11;
pub const XCHAL_INT17_EXTNUM: u32 = 12;
pub const XCHAL_INT18_EXTNUM: u32 = 13;
pub const XCHAL_INT19_EXTNUM: u32 = 14;
pub const XCHAL_INT20_EXTNUM: u32 = 15;
pub const XCHAL_INT21_EXTNUM: u32 = 16;
pub const XCHAL_INT22_EXTNUM: u32 = 17;
pub const XCHAL_INT23_EXTNUM: u32 = 18;
pub const XCHAL_INT24_EXTNUM: u32 = 19;
pub const XCHAL_INT25_EXTNUM: u32 = 20;
pub const XCHAL_INT26_EXTNUM: u32 = 21;
pub const XCHAL_INT27_EXTNUM: u32 = 22;
pub const XCHAL_INT28_EXTNUM: u32 = 23;
pub const XCHAL_INT30_EXTNUM: u32 = 24;
pub const XCHAL_INT31_EXTNUM: u32 = 25;
pub const XCHAL_XEA_VERSION: u32 = 2;
pub const XCHAL_HAVE_XEA1: u32 = 0;
pub const XCHAL_HAVE_XEA2: u32 = 1;
pub const XCHAL_HAVE_XEAX: u32 = 0;
pub const XCHAL_HAVE_EXCEPTIONS: u32 = 1;
pub const XCHAL_HAVE_HALT: u32 = 0;
pub const XCHAL_HAVE_BOOTLOADER: u32 = 0;
pub const XCHAL_HAVE_MEM_ECC_PARITY: u32 = 0;
pub const XCHAL_HAVE_VECTOR_SELECT: u32 = 1;
pub const XCHAL_HAVE_VECBASE: u32 = 1;
pub const XCHAL_VECBASE_RESET_VADDR: u32 = 1073741824;
pub const XCHAL_VECBASE_RESET_PADDR: u32 = 1073741824;
pub const XCHAL_RESET_VECBASE_OVERLAP: u32 = 0;
pub const XCHAL_RESET_VECTOR0_VADDR: u32 = 1342177280;
pub const XCHAL_RESET_VECTOR0_PADDR: u32 = 1342177280;
pub const XCHAL_RESET_VECTOR1_VADDR: u32 = 1073742848;
pub const XCHAL_RESET_VECTOR1_PADDR: u32 = 1073742848;
pub const XCHAL_RESET_VECTOR_VADDR: u32 = 1073742848;
pub const XCHAL_RESET_VECTOR_PADDR: u32 = 1073742848;
pub const XCHAL_USER_VECOFS: u32 = 832;
pub const XCHAL_USER_VECTOR_VADDR: u32 = 1073742656;
pub const XCHAL_USER_VECTOR_PADDR: u32 = 1073742656;
pub const XCHAL_KERNEL_VECOFS: u32 = 768;
pub const XCHAL_KERNEL_VECTOR_VADDR: u32 = 1073742592;
pub const XCHAL_KERNEL_VECTOR_PADDR: u32 = 1073742592;
pub const XCHAL_DOUBLEEXC_VECOFS: u32 = 960;
pub const XCHAL_DOUBLEEXC_VECTOR_VADDR: u32 = 1073742784;
pub const XCHAL_DOUBLEEXC_VECTOR_PADDR: u32 = 1073742784;
pub const XCHAL_WINDOW_OF4_VECOFS: u32 = 0;
pub const XCHAL_WINDOW_UF4_VECOFS: u32 = 64;
pub const XCHAL_WINDOW_OF8_VECOFS: u32 = 128;
pub const XCHAL_WINDOW_UF8_VECOFS: u32 = 192;
pub const XCHAL_WINDOW_OF12_VECOFS: u32 = 256;
pub const XCHAL_WINDOW_UF12_VECOFS: u32 = 320;
pub const XCHAL_WINDOW_VECTORS_VADDR: u32 = 1073741824;
pub const XCHAL_WINDOW_VECTORS_PADDR: u32 = 1073741824;
pub const XCHAL_INTLEVEL2_VECOFS: u32 = 384;
pub const XCHAL_INTLEVEL2_VECTOR_VADDR: u32 = 1073742208;
pub const XCHAL_INTLEVEL2_VECTOR_PADDR: u32 = 1073742208;
pub const XCHAL_INTLEVEL3_VECOFS: u32 = 448;
pub const XCHAL_INTLEVEL3_VECTOR_VADDR: u32 = 1073742272;
pub const XCHAL_INTLEVEL3_VECTOR_PADDR: u32 = 1073742272;
pub const XCHAL_INTLEVEL4_VECOFS: u32 = 512;
pub const XCHAL_INTLEVEL4_VECTOR_VADDR: u32 = 1073742336;
pub const XCHAL_INTLEVEL4_VECTOR_PADDR: u32 = 1073742336;
pub const XCHAL_INTLEVEL5_VECOFS: u32 = 576;
pub const XCHAL_INTLEVEL5_VECTOR_VADDR: u32 = 1073742400;
pub const XCHAL_INTLEVEL5_VECTOR_PADDR: u32 = 1073742400;
pub const XCHAL_INTLEVEL6_VECOFS: u32 = 640;
pub const XCHAL_INTLEVEL6_VECTOR_VADDR: u32 = 1073742464;
pub const XCHAL_INTLEVEL6_VECTOR_PADDR: u32 = 1073742464;
pub const XCHAL_DEBUG_VECOFS: u32 = 640;
pub const XCHAL_DEBUG_VECTOR_VADDR: u32 = 1073742464;
pub const XCHAL_DEBUG_VECTOR_PADDR: u32 = 1073742464;
pub const XCHAL_NMI_VECOFS: u32 = 704;
pub const XCHAL_NMI_VECTOR_VADDR: u32 = 1073742528;
pub const XCHAL_NMI_VECTOR_PADDR: u32 = 1073742528;
pub const XCHAL_INTLEVEL7_VECOFS: u32 = 704;
pub const XCHAL_INTLEVEL7_VECTOR_VADDR: u32 = 1073742528;
pub const XCHAL_INTLEVEL7_VECTOR_PADDR: u32 = 1073742528;
pub const XCHAL_HAVE_DEBUG_ERI: u32 = 1;
pub const XCHAL_HAVE_DEBUG_APB: u32 = 0;
pub const XCHAL_HAVE_DEBUG_JTAG: u32 = 1;
pub const XCHAL_HAVE_OCD: u32 = 1;
pub const XCHAL_NUM_IBREAK: u32 = 2;
pub const XCHAL_NUM_DBREAK: u32 = 2;
pub const XCHAL_HAVE_OCD_DIR_ARRAY: u32 = 0;
pub const XCHAL_HAVE_OCD_LS32DDR: u32 = 1;
pub const XCHAL_HAVE_TRAX: u32 = 1;
pub const XCHAL_TRAX_MEM_SIZE: u32 = 16384;
pub const XCHAL_TRAX_MEM_SHAREABLE: u32 = 1;
pub const XCHAL_TRAX_ATB_WIDTH: u32 = 0;
pub const XCHAL_TRAX_TIME_WIDTH: u32 = 0;
pub const XCHAL_NUM_PERF_COUNTERS: u32 = 2;
pub const XCHAL_HAVE_TLBS: u32 = 1;
pub const XCHAL_HAVE_SPANNING_WAY: u32 = 1;
pub const XCHAL_SPANNING_WAY: u32 = 0;
pub const XCHAL_HAVE_IDENTITY_MAP: u32 = 1;
pub const XCHAL_HAVE_CACHEATTR: u32 = 0;
pub const XCHAL_HAVE_MIMIC_CACHEATTR: u32 = 1;
pub const XCHAL_HAVE_XLT_CACHEATTR: u32 = 0;
pub const XCHAL_HAVE_PTP_MMU: u32 = 0;
pub const XCHAL_MMU_ASID_BITS: u32 = 0;
pub const XCHAL_MMU_RINGS: u32 = 1;
pub const XCHAL_MMU_RING_BITS: u32 = 0;
pub const XCHAL_HAVE_MPU: u32 = 0;
pub const XCHAL_MPU_ENTRIES: u32 = 0;
pub const XCHAL_MPU_ALIGN_REQ: u32 = 1;
pub const XCHAL_MPU_BACKGROUND_ENTRIES: u32 = 0;
pub const XCHAL_MPU_BG_CACHEADRDIS: u32 = 0;
pub const XCHAL_MPU_ALIGN_BITS: u32 = 0;
pub const XCHAL_MPU_ALIGN: u32 = 0;
pub const XCHAL_CA_R: u32 = 1073742016;
pub const XCHAL_CA_RX: u32 = 1073742032;
pub const XCHAL_CA_RW: u32 = 1073742048;
pub const XCHAL_CA_RWX: u32 = 1073742064;
pub const XCHAL_CA_BYPASS: u32 = 2;
pub const XCHAL_CA_BYPASSBUF: u32 = 6;
pub const XCHAL_CA_WRITETHRU: u32 = 1;
pub const XCHAL_CA_WRITEBACK: u32 = 2;
pub const XCHAL_HAVE_CA_WRITEBACK_NOALLOC: u32 = 0;
pub const XCHAL_CA_WRITEBACK_NOALLOC: u32 = 2;
pub const XCHAL_CA_BYPASS_RW: u32 = 0;
pub const XCHAL_CA_WRITETHRU_RW: u32 = 0;
pub const XCHAL_CA_WRITEBACK_RW: u32 = 0;
pub const XCHAL_CA_WRITEBACK_NOALLOC_RW: u32 = 0;
pub const XCHAL_CA_ILLEGAL: u32 = 15;
pub const XCHAL_CA_ISOLATE: u32 = 0;
pub const XCHAL_MMU_ASID_INVALID: u32 = 0;
pub const XCHAL_MMU_ASID_KERNEL: u32 = 0;
pub const XCHAL_MMU_SR_BITS: u32 = 0;
pub const XCHAL_MMU_CA_BITS: u32 = 4;
pub const XCHAL_MMU_MAX_PTE_PAGE_SIZE: u32 = 29;
pub const XCHAL_MMU_MIN_PTE_PAGE_SIZE: u32 = 29;
pub const XCHAL_ITLB_WAY_BITS: u32 = 0;
pub const XCHAL_ITLB_WAYS: u32 = 1;
pub const XCHAL_ITLB_ARF_WAYS: u32 = 0;
pub const XCHAL_ITLB_SETS: u32 = 1;
pub const XCHAL_ITLB_WAY0_SET: u32 = 0;
pub const XCHAL_ITLB_ARF_SETS: u32 = 0;
pub const XCHAL_ITLB_MINWIRED_SETS: u32 = 0;
pub const XCHAL_ITLB_SET0_WAY: u32 = 0;
pub const XCHAL_ITLB_SET0_WAYS: u32 = 1;
pub const XCHAL_ITLB_SET0_ENTRIES_LOG2: u32 = 3;
pub const XCHAL_ITLB_SET0_ENTRIES: u32 = 8;
pub const XCHAL_ITLB_SET0_ARF: u32 = 0;
pub const XCHAL_ITLB_SET0_PAGESIZES: u32 = 1;
pub const XCHAL_ITLB_SET0_PAGESZ_BITS: u32 = 0;
pub const XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN: u32 = 29;
pub const XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX: u32 = 29;
pub const XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST: u32 = 29;
pub const XCHAL_ITLB_SET0_ASID_CONSTMASK: u32 = 0;
pub const XCHAL_ITLB_SET0_VPN_CONSTMASK: u32 = 0;
pub const XCHAL_ITLB_SET0_PPN_CONSTMASK: u32 = 3758096384;
pub const XCHAL_ITLB_SET0_CA_CONSTMASK: u32 = 0;
pub const XCHAL_ITLB_SET0_ASID_RESET: u32 = 0;
pub const XCHAL_ITLB_SET0_VPN_RESET: u32 = 0;
pub const XCHAL_ITLB_SET0_PPN_RESET: u32 = 0;
pub const XCHAL_ITLB_SET0_CA_RESET: u32 = 1;
pub const XCHAL_ITLB_SET0_E0_VPN_CONST: u32 = 0;
pub const XCHAL_ITLB_SET0_E1_VPN_CONST: u32 = 536870912;
pub const XCHAL_ITLB_SET0_E2_VPN_CONST: u32 = 1073741824;
pub const XCHAL_ITLB_SET0_E3_VPN_CONST: u32 = 1610612736;
pub const XCHAL_ITLB_SET0_E4_VPN_CONST: u32 = 2147483648;
pub const XCHAL_ITLB_SET0_E5_VPN_CONST: u32 = 2684354560;
pub const XCHAL_ITLB_SET0_E6_VPN_CONST: u32 = 3221225472;
pub const XCHAL_ITLB_SET0_E7_VPN_CONST: u32 = 3758096384;
pub const XCHAL_ITLB_SET0_E0_PPN_CONST: u32 = 0;
pub const XCHAL_ITLB_SET0_E1_PPN_CONST: u32 = 536870912;
pub const XCHAL_ITLB_SET0_E2_PPN_CONST: u32 = 1073741824;
pub const XCHAL_ITLB_SET0_E3_PPN_CONST: u32 = 1610612736;
pub const XCHAL_ITLB_SET0_E4_PPN_CONST: u32 = 2147483648;
pub const XCHAL_ITLB_SET0_E5_PPN_CONST: u32 = 2684354560;
pub const XCHAL_ITLB_SET0_E6_PPN_CONST: u32 = 3221225472;
pub const XCHAL_ITLB_SET0_E7_PPN_CONST: u32 = 3758096384;
pub const XCHAL_ITLB_SET0_E0_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E1_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E2_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E3_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E4_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E5_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E6_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E7_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_WAY_BITS: u32 = 0;
pub const XCHAL_DTLB_WAYS: u32 = 1;
pub const XCHAL_DTLB_ARF_WAYS: u32 = 0;
pub const XCHAL_DTLB_SETS: u32 = 1;
pub const XCHAL_DTLB_WAY0_SET: u32 = 0;
pub const XCHAL_DTLB_ARF_SETS: u32 = 0;
pub const XCHAL_DTLB_MINWIRED_SETS: u32 = 0;
pub const XCHAL_DTLB_SET0_WAY: u32 = 0;
pub const XCHAL_DTLB_SET0_WAYS: u32 = 1;
pub const XCHAL_DTLB_SET0_ENTRIES_LOG2: u32 = 3;
pub const XCHAL_DTLB_SET0_ENTRIES: u32 = 8;
pub const XCHAL_DTLB_SET0_ARF: u32 = 0;
pub const XCHAL_DTLB_SET0_PAGESIZES: u32 = 1;
pub const XCHAL_DTLB_SET0_PAGESZ_BITS: u32 = 0;
pub const XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN: u32 = 29;
pub const XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX: u32 = 29;
pub const XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST: u32 = 29;
pub const XCHAL_DTLB_SET0_ASID_CONSTMASK: u32 = 0;
pub const XCHAL_DTLB_SET0_VPN_CONSTMASK: u32 = 0;
pub const XCHAL_DTLB_SET0_PPN_CONSTMASK: u32 = 3758096384;
pub const XCHAL_DTLB_SET0_CA_CONSTMASK: u32 = 0;
pub const XCHAL_DTLB_SET0_ASID_RESET: u32 = 0;
pub const XCHAL_DTLB_SET0_VPN_RESET: u32 = 0;
pub const XCHAL_DTLB_SET0_PPN_RESET: u32 = 0;
pub const XCHAL_DTLB_SET0_CA_RESET: u32 = 1;
pub const XCHAL_DTLB_SET0_E0_VPN_CONST: u32 = 0;
pub const XCHAL_DTLB_SET0_E1_VPN_CONST: u32 = 536870912;
pub const XCHAL_DTLB_SET0_E2_VPN_CONST: u32 = 1073741824;
pub const XCHAL_DTLB_SET0_E3_VPN_CONST: u32 = 1610612736;
pub const XCHAL_DTLB_SET0_E4_VPN_CONST: u32 = 2147483648;
pub const XCHAL_DTLB_SET0_E5_VPN_CONST: u32 = 2684354560;
pub const XCHAL_DTLB_SET0_E6_VPN_CONST: u32 = 3221225472;
pub const XCHAL_DTLB_SET0_E7_VPN_CONST: u32 = 3758096384;
pub const XCHAL_DTLB_SET0_E0_PPN_CONST: u32 = 0;
pub const XCHAL_DTLB_SET0_E1_PPN_CONST: u32 = 536870912;
pub const XCHAL_DTLB_SET0_E2_PPN_CONST: u32 = 1073741824;
pub const XCHAL_DTLB_SET0_E3_PPN_CONST: u32 = 1610612736;
pub const XCHAL_DTLB_SET0_E4_PPN_CONST: u32 = 2147483648;
pub const XCHAL_DTLB_SET0_E5_PPN_CONST: u32 = 2684354560;
pub const XCHAL_DTLB_SET0_E6_PPN_CONST: u32 = 3221225472;
pub const XCHAL_DTLB_SET0_E7_PPN_CONST: u32 = 3758096384;
pub const XCHAL_DTLB_SET0_E0_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E1_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E2_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E3_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E4_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E5_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E6_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E7_CA_RESET: u32 = 2;
pub const XCHAL_CP_NUM: u32 = 2;
pub const XCHAL_CP_MAX: u32 = 4;
pub const XCHAL_CP_MASK: u32 = 9;
pub const XCHAL_CP_PORT_MASK: u32 = 0;
pub const XCHAL_CP0_NAME: &[u8; 4usize] = b"FPU\0";
pub const XCHAL_CP0_SA_SIZE: u32 = 72;
pub const XCHAL_CP0_SA_ALIGN: u32 = 4;
pub const XCHAL_CP_ID_FPU: u32 = 0;
pub const XCHAL_CP3_NAME: &[u8; 7usize] = b"cop_ai\0";
pub const XCHAL_CP3_SA_SIZE: u32 = 208;
pub const XCHAL_CP3_SA_ALIGN: u32 = 16;
pub const XCHAL_CP_ID_COP_AI: u32 = 3;
pub const XCHAL_CP1_SA_SIZE: u32 = 0;
pub const XCHAL_CP1_SA_ALIGN: u32 = 1;
pub const XCHAL_CP2_SA_SIZE: u32 = 0;
pub const XCHAL_CP2_SA_ALIGN: u32 = 1;
pub const XCHAL_CP4_SA_SIZE: u32 = 0;
pub const XCHAL_CP4_SA_ALIGN: u32 = 1;
pub const XCHAL_CP5_SA_SIZE: u32 = 0;
pub const XCHAL_CP5_SA_ALIGN: u32 = 1;
pub const XCHAL_CP6_SA_SIZE: u32 = 0;
pub const XCHAL_CP6_SA_ALIGN: u32 = 1;
pub const XCHAL_CP7_SA_SIZE: u32 = 0;
pub const XCHAL_CP7_SA_ALIGN: u32 = 1;
pub const XCHAL_NCP_SA_SIZE: u32 = 36;
pub const XCHAL_NCP_SA_ALIGN: u32 = 4;
pub const XCHAL_TOTAL_SA_SIZE: u32 = 336;
pub const XCHAL_TOTAL_SA_ALIGN: u32 = 16;
pub const XCHAL_NCP_SA_NUM: u32 = 9;
pub const XCHAL_CP0_SA_NUM: u32 = 18;
pub const XCHAL_CP1_SA_NUM: u32 = 0;
pub const XCHAL_CP2_SA_NUM: u32 = 0;
pub const XCHAL_CP3_SA_NUM: u32 = 26;
pub const XCHAL_CP4_SA_NUM: u32 = 0;
pub const XCHAL_CP5_SA_NUM: u32 = 0;
pub const XCHAL_CP6_SA_NUM: u32 = 0;
pub const XCHAL_CP7_SA_NUM: u32 = 0;
pub const XCHAL_ERRATUM_453: u32 = 0;
pub const XCHAL_ERRATUM_497: u32 = 0;
pub const XCHAL_HAVE_LE: u32 = 1;
pub const XCHAL_MEMORY_ORDER: u32 = 0;
pub const XCHAL_HAVE_HIGHLEVEL_INTERRUPTS: u32 = 1;
pub const XCHAL_NUM_LOWPRI_LEVELS: u32 = 1;
pub const XCHAL_FIRST_HIGHPRI_LEVEL: u32 = 2;
pub const XCHAL_INTLEVEL0_MASK: u32 = 0;
pub const XCHAL_INTLEVEL8_MASK: u32 = 0;
pub const XCHAL_INTLEVEL9_MASK: u32 = 0;
pub const XCHAL_INTLEVEL10_MASK: u32 = 0;
pub const XCHAL_INTLEVEL11_MASK: u32 = 0;
pub const XCHAL_INTLEVEL12_MASK: u32 = 0;
pub const XCHAL_INTLEVEL13_MASK: u32 = 0;
pub const XCHAL_INTLEVEL14_MASK: u32 = 0;
pub const XCHAL_INTLEVEL15_MASK: u32 = 0;
pub const XCHAL_INTLEVEL0_ANDBELOW_MASK: u32 = 0;
pub const XCHAL_INTLEVEL8_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL9_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL10_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL11_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL12_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL13_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL14_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL15_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_LOWPRI_MASK: u32 = 407551;
pub const XCHAL_INTCLEARABLE_MASK: u32 = 1883243648;
pub const XCHAL_INTSETTABLE_MASK: u32 = 536871040;
pub const XCHAL_EXTINT0_MASK: u32 = 1;
pub const XCHAL_EXTINT1_MASK: u32 = 2;
pub const XCHAL_EXTINT2_MASK: u32 = 4;
pub const XCHAL_EXTINT3_MASK: u32 = 8;
pub const XCHAL_EXTINT4_MASK: u32 = 16;
pub const XCHAL_EXTINT5_MASK: u32 = 32;
pub const XCHAL_EXTINT6_MASK: u32 = 256;
pub const XCHAL_EXTINT7_MASK: u32 = 512;
pub const XCHAL_EXTINT8_MASK: u32 = 1024;
pub const XCHAL_EXTINT9_MASK: u32 = 4096;
pub const XCHAL_EXTINT10_MASK: u32 = 8192;
pub const XCHAL_EXTINT11_MASK: u32 = 16384;
pub const XCHAL_EXTINT12_MASK: u32 = 131072;
pub const XCHAL_EXTINT13_MASK: u32 = 262144;
pub const XCHAL_EXTINT14_MASK: u32 = 524288;
pub const XCHAL_EXTINT15_MASK: u32 = 1048576;
pub const XCHAL_EXTINT16_MASK: u32 = 2097152;
pub const XCHAL_EXTINT17_MASK: u32 = 4194304;
pub const XCHAL_EXTINT18_MASK: u32 = 8388608;
pub const XCHAL_EXTINT19_MASK: u32 = 16777216;
pub const XCHAL_EXTINT20_MASK: u32 = 33554432;
pub const XCHAL_EXTINT21_MASK: u32 = 67108864;
pub const XCHAL_EXTINT22_MASK: u32 = 134217728;
pub const XCHAL_EXTINT23_MASK: u32 = 268435456;
pub const XCHAL_EXTINT24_MASK: u32 = 1073741824;
pub const XCHAL_EXTINT25_MASK: u32 = 2147483648;
pub const XCHAL_HAVE_OLD_EXC_ARCH: u32 = 0;
pub const XCHAL_HAVE_EXCM: u32 = 1;
pub const XCHAL_PROGRAMEXC_VECTOR_VADDR: u32 = 1073742656;
pub const XCHAL_USEREXC_VECTOR_VADDR: u32 = 1073742656;
pub const XCHAL_PROGRAMEXC_VECTOR_PADDR: u32 = 1073742656;
pub const XCHAL_USEREXC_VECTOR_PADDR: u32 = 1073742656;
pub const XCHAL_STACKEDEXC_VECTOR_VADDR: u32 = 1073742592;
pub const XCHAL_KERNELEXC_VECTOR_VADDR: u32 = 1073742592;
pub const XCHAL_STACKEDEXC_VECTOR_PADDR: u32 = 1073742592;
pub const XCHAL_KERNELEXC_VECTOR_PADDR: u32 = 1073742592;
pub const XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION: u32 = 0;
pub const XCHAL_EXCCAUSE_SYSTEM_CALL: u32 = 1;
pub const XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR: u32 = 2;
pub const XCHAL_EXCCAUSE_LOAD_STORE_ERROR: u32 = 3;
pub const XCHAL_EXCCAUSE_LEVEL1_INTERRUPT: u32 = 4;
pub const XCHAL_EXCCAUSE_ALLOCA: u32 = 5;
pub const XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO: u32 = 6;
pub const XCHAL_EXCCAUSE_SPECULATION: u32 = 7;
pub const XCHAL_EXCCAUSE_PRIVILEGED: u32 = 8;
pub const XCHAL_EXCCAUSE_UNALIGNED: u32 = 9;
pub const XCHAL_EXCCAUSE_ITLB_MISS: u32 = 16;
pub const XCHAL_EXCCAUSE_ITLB_MULTIHIT: u32 = 17;
pub const XCHAL_EXCCAUSE_ITLB_PRIVILEGE: u32 = 18;
pub const XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION: u32 = 19;
pub const XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE: u32 = 20;
pub const XCHAL_EXCCAUSE_DTLB_MISS: u32 = 24;
pub const XCHAL_EXCCAUSE_DTLB_MULTIHIT: u32 = 25;
pub const XCHAL_EXCCAUSE_DTLB_PRIVILEGE: u32 = 26;
pub const XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION: u32 = 27;
pub const XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE: u32 = 28;
pub const XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE: u32 = 29;
pub const XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED: u32 = 32;
pub const XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED: u32 = 33;
pub const XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED: u32 = 34;
pub const XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED: u32 = 35;
pub const XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED: u32 = 36;
pub const XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED: u32 = 37;
pub const XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED: u32 = 38;
pub const XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED: u32 = 39;
pub const XCHAL_DBREAKC_VALIDMASK: u32 = 3221225535;
pub const XCHAL_DBREAKC_MASK_BITS: u32 = 6;
pub const XCHAL_DBREAKC_MASK_NUM: u32 = 64;
pub const XCHAL_DBREAKC_MASK_SHIFT: u32 = 0;
pub const XCHAL_DBREAKC_MASK_MASK: u32 = 63;
pub const XCHAL_DBREAKC_LOADBREAK_BITS: u32 = 1;
pub const XCHAL_DBREAKC_LOADBREAK_NUM: u32 = 2;
pub const XCHAL_DBREAKC_LOADBREAK_SHIFT: u32 = 30;
pub const XCHAL_DBREAKC_LOADBREAK_MASK: u32 = 1073741824;
pub const XCHAL_DBREAKC_STOREBREAK_BITS: u32 = 1;
pub const XCHAL_DBREAKC_STOREBREAK_NUM: u32 = 2;
pub const XCHAL_DBREAKC_STOREBREAK_SHIFT: u32 = 31;
pub const XCHAL_DBREAKC_STOREBREAK_MASK: u32 = 2147483648;
pub const XCHAL_PS_VALIDMASK: u32 = 462655;
pub const XCHAL_PS_INTLEVEL_BITS: u32 = 4;
pub const XCHAL_PS_INTLEVEL_NUM: u32 = 16;
pub const XCHAL_PS_INTLEVEL_SHIFT: u32 = 0;
pub const XCHAL_PS_INTLEVEL_MASK: u32 = 15;
pub const XCHAL_PS_EXCM_BITS: u32 = 1;
pub const XCHAL_PS_EXCM_NUM: u32 = 2;
pub const XCHAL_PS_EXCM_SHIFT: u32 = 4;
pub const XCHAL_PS_EXCM_MASK: u32 = 16;
pub const XCHAL_PS_UM_BITS: u32 = 1;
pub const XCHAL_PS_UM_NUM: u32 = 2;
pub const XCHAL_PS_UM_SHIFT: u32 = 5;
pub const XCHAL_PS_UM_MASK: u32 = 32;
pub const XCHAL_PS_RING_BITS: u32 = 2;
pub const XCHAL_PS_RING_NUM: u32 = 4;
pub const XCHAL_PS_RING_SHIFT: u32 = 6;
pub const XCHAL_PS_RING_MASK: u32 = 192;
pub const XCHAL_PS_OWB_BITS: u32 = 4;
pub const XCHAL_PS_OWB_NUM: u32 = 16;
pub const XCHAL_PS_OWB_SHIFT: u32 = 8;
pub const XCHAL_PS_OWB_MASK: u32 = 3840;
pub const XCHAL_PS_CALLINC_BITS: u32 = 2;
pub const XCHAL_PS_CALLINC_NUM: u32 = 4;
pub const XCHAL_PS_CALLINC_SHIFT: u32 = 16;
pub const XCHAL_PS_CALLINC_MASK: u32 = 196608;
pub const XCHAL_PS_WOE_BITS: u32 = 1;
pub const XCHAL_PS_WOE_NUM: u32 = 2;
pub const XCHAL_PS_WOE_SHIFT: u32 = 18;
pub const XCHAL_PS_WOE_MASK: u32 = 262144;
pub const XCHAL_EXCCAUSE_VALIDMASK: u32 = 63;
pub const XCHAL_EXCCAUSE_BITS: u32 = 6;
pub const XCHAL_EXCCAUSE_NUM: u32 = 64;
pub const XCHAL_EXCCAUSE_SHIFT: u32 = 0;
pub const XCHAL_EXCCAUSE_MASK: u32 = 63;
pub const XCHAL_DEBUGCAUSE_VALIDMASK: u32 = 63;
pub const XCHAL_DEBUGCAUSE_ICOUNT_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_ICOUNT_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_ICOUNT_SHIFT: u32 = 0;
pub const XCHAL_DEBUGCAUSE_ICOUNT_MASK: u32 = 1;
pub const XCHAL_DEBUGCAUSE_IBREAK_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_IBREAK_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_IBREAK_SHIFT: u32 = 1;
pub const XCHAL_DEBUGCAUSE_IBREAK_MASK: u32 = 2;
pub const XCHAL_DEBUGCAUSE_DBREAK_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_DBREAK_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_DBREAK_SHIFT: u32 = 2;
pub const XCHAL_DEBUGCAUSE_DBREAK_MASK: u32 = 4;
pub const XCHAL_DEBUGCAUSE_BREAK_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_BREAK_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_BREAK_SHIFT: u32 = 3;
pub const XCHAL_DEBUGCAUSE_BREAK_MASK: u32 = 8;
pub const XCHAL_DEBUGCAUSE_BREAKN_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_BREAKN_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_BREAKN_SHIFT: u32 = 4;
pub const XCHAL_DEBUGCAUSE_BREAKN_MASK: u32 = 16;
pub const XCHAL_DEBUGCAUSE_DEBUGINT_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_DEBUGINT_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT: u32 = 5;
pub const XCHAL_DEBUGCAUSE_DEBUGINT_MASK: u32 = 32;
pub const XCHAL_NUM_IROM: u32 = 0;
pub const XCHAL_NUM_IRAM: u32 = 1;
pub const XCHAL_NUM_DROM: u32 = 0;
pub const XCHAL_NUM_DRAM: u32 = 1;
pub const XCHAL_IRAM0_VADDR: u32 = 1073741824;
pub const XCHAL_IRAM0_PADDR: u32 = 1073741824;
pub const XCHAL_IRAM0_SIZE: u32 = 67108864;
pub const XCHAL_DRAM0_VADDR: u32 = 1006632960;
pub const XCHAL_DRAM0_PADDR: u32 = 1006632960;
pub const XCHAL_DRAM0_SIZE: u32 = 67108864;
pub const XCHAL_CACHE_PREFCTL_DEFAULT: u32 = 4164;
pub const XCHAL_CACHE_LINEWIDTH_MAX: u32 = 4;
pub const XCHAL_CACHE_LINESIZE_MAX: u32 = 16;
pub const XCHAL_ICACHE_SETSIZE: u32 = 1;
pub const XCHAL_DCACHE_SETSIZE: u32 = 1;
pub const XCHAL_CACHE_SETWIDTH_MAX: u32 = 0;
pub const XCHAL_CACHE_SETSIZE_MAX: u32 = 1;
pub const XCHAL_ICACHE_TAG_V_SHIFT: u32 = 0;
pub const XCHAL_ICACHE_TAG_V: u32 = 1;
pub const XCHAL_ICACHE_TAG_F_SHIFT: u32 = 0;
pub const XCHAL_ICACHE_TAG_F: u32 = 0;
pub const XCHAL_ICACHE_TAG_L_SHIFT: u32 = 0;
pub const XCHAL_ICACHE_TAG_L: u32 = 0;
pub const XCHAL_DCACHE_TAG_V_SHIFT: u32 = 0;
pub const XCHAL_DCACHE_TAG_V: u32 = 1;
pub const XCHAL_DCACHE_TAG_F_SHIFT: u32 = 0;
pub const XCHAL_DCACHE_TAG_F: u32 = 0;
pub const XCHAL_DCACHE_TAG_D_SHIFT: u32 = 0;
pub const XCHAL_DCACHE_TAG_D: u32 = 0;
pub const XCHAL_DCACHE_TAG_L_SHIFT: u32 = 0;
pub const XCHAL_DCACHE_TAG_L: u32 = 0;
pub const _MEMCTL_SNOOP_EN: u32 = 0;
pub const _MEMCTL_L0IBUF_EN: u32 = 1;
pub const XCHAL_CACHE_MEMCTL_DEFAULT: u32 = 1;
pub const XCHAL_SNOOP_LB_MEMCTL_DEFAULT: u32 = 1;
pub const XCHAL_ALIGN_MAX: u32 = 16;
pub const XCHAL_HW_RELEASE_MAJOR: u32 = 2700;
pub const XCHAL_HW_RELEASE_MINOR: u32 = 12;
pub const XCHAL_HW_RELEASE_NAME: &[u8; 9usize] = b"LX7.0.12\0";
pub const XCHAL_EXTRA_SA_SIZE: u32 = 36;
pub const XCHAL_EXTRA_SA_ALIGN: u32 = 4;
pub const XCHAL_CPEXTRA_SA_SIZE: u32 = 336;
pub const XCHAL_CPEXTRA_SA_ALIGN: u32 = 16;
pub const XCHAL_CP1_NAME: u32 = 0;
pub const XCHAL_CP1_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP2_NAME: u32 = 0;
pub const XCHAL_CP2_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP4_NAME: u32 = 0;
pub const XCHAL_CP4_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP5_NAME: u32 = 0;
pub const XCHAL_CP5_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP6_NAME: u32 = 0;
pub const XCHAL_CP6_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP7_NAME: u32 = 0;
pub const XCHAL_CP7_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CPEXTRA_SA_SIZE_TOR2: u32 = 336;
pub const XCHAL_INST_ILLN: u32 = 61549;
pub const XCHAL_INST_ILLN_BYTE0: u32 = 109;
pub const XCHAL_INST_ILLN_BYTE1: u32 = 240;
pub const XTHAL_INST_ILL: u32 = 0;
pub const EXCCAUSE_EXCCAUSE_SHIFT: u32 = 0;
pub const EXCCAUSE_EXCCAUSE_MASK: u32 = 63;
pub const EXCCAUSE_ILLEGAL: u32 = 0;
pub const EXCCAUSE_SYSCALL: u32 = 1;
pub const EXCCAUSE_INSTR_ERROR: u32 = 2;
pub const EXCCAUSE_IFETCHERROR: u32 = 2;
pub const EXCCAUSE_LOAD_STORE_ERROR: u32 = 3;
pub const EXCCAUSE_LOADSTOREERROR: u32 = 3;
pub const EXCCAUSE_LEVEL1_INTERRUPT: u32 = 4;
pub const EXCCAUSE_LEVEL1INTERRUPT: u32 = 4;
pub const EXCCAUSE_ALLOCA: u32 = 5;
pub const EXCCAUSE_DIVIDE_BY_ZERO: u32 = 6;
pub const EXCCAUSE_SPECULATION: u32 = 7;
pub const EXCCAUSE_PC_ERROR: u32 = 7;
pub const EXCCAUSE_PRIVILEGED: u32 = 8;
pub const EXCCAUSE_UNALIGNED: u32 = 9;
pub const EXCCAUSE_EXTREG_PRIVILEGE: u32 = 10;
pub const EXCCAUSE_EXCLUSIVE_ERROR: u32 = 11;
pub const EXCCAUSE_INSTR_DATA_ERROR: u32 = 12;
pub const EXCCAUSE_LOAD_STORE_DATA_ERROR: u32 = 13;
pub const EXCCAUSE_INSTR_ADDR_ERROR: u32 = 14;
pub const EXCCAUSE_LOAD_STORE_ADDR_ERROR: u32 = 15;
pub const EXCCAUSE_ITLB_MISS: u32 = 16;
pub const EXCCAUSE_ITLB_MULTIHIT: u32 = 17;
pub const EXCCAUSE_INSTR_RING: u32 = 18;
pub const EXCCAUSE_INSTR_PROHIBITED: u32 = 20;
pub const EXCCAUSE_DTLB_MISS: u32 = 24;
pub const EXCCAUSE_DTLB_MULTIHIT: u32 = 25;
pub const EXCCAUSE_LOAD_STORE_RING: u32 = 26;
pub const EXCCAUSE_LOAD_PROHIBITED: u32 = 28;
pub const EXCCAUSE_STORE_PROHIBITED: u32 = 29;
pub const EXCCAUSE_CP0_DISABLED: u32 = 32;
pub const EXCCAUSE_CP1_DISABLED: u32 = 33;
pub const EXCCAUSE_CP2_DISABLED: u32 = 34;
pub const EXCCAUSE_CP3_DISABLED: u32 = 35;
pub const EXCCAUSE_CP4_DISABLED: u32 = 36;
pub const EXCCAUSE_CP5_DISABLED: u32 = 37;
pub const EXCCAUSE_CP6_DISABLED: u32 = 38;
pub const EXCCAUSE_CP7_DISABLED: u32 = 39;
pub const PS_WOE_SHIFT: u32 = 18;
pub const PS_WOE_MASK: u32 = 262144;
pub const PS_WOE: u32 = 262144;
pub const PS_CALLINC_SHIFT: u32 = 16;
pub const PS_CALLINC_MASK: u32 = 196608;
pub const PS_OWB_SHIFT: u32 = 8;
pub const PS_OWB_MASK: u32 = 3840;
pub const PS_RING_SHIFT: u32 = 6;
pub const PS_RING_MASK: u32 = 192;
pub const PS_UM_SHIFT: u32 = 5;
pub const PS_UM_MASK: u32 = 32;
pub const PS_UM: u32 = 32;
pub const PS_EXCM_SHIFT: u32 = 4;
pub const PS_EXCM_MASK: u32 = 16;
pub const PS_EXCM: u32 = 16;
pub const PS_INTLEVEL_SHIFT: u32 = 0;
pub const PS_INTLEVEL_MASK: u32 = 15;
pub const PS_WOE_ABI: u32 = 262144;
pub const PS_PROGSTACK_SHIFT: u32 = 5;
pub const PS_PROGSTACK_MASK: u32 = 32;
pub const PS_PROG_SHIFT: u32 = 5;
pub const PS_PROG_MASK: u32 = 32;
pub const PS_PROG: u32 = 32;
pub const DBREAKC_MASK_SHIFT: u32 = 0;
pub const DBREAKC_MASK_MASK: u32 = 63;
pub const DBREAKC_LOADBREAK_SHIFT: u32 = 30;
pub const DBREAKC_LOADBREAK_MASK: u32 = 1073741824;
pub const DBREAKC_STOREBREAK_SHIFT: u32 = 31;
pub const DBREAKC_STOREBREAK_MASK: u32 = 2147483648;
pub const DEBUGCAUSE_DEBUGINT_SHIFT: u32 = 5;
pub const DEBUGCAUSE_DEBUGINT_MASK: u32 = 32;
pub const DEBUGCAUSE_BREAKN_SHIFT: u32 = 4;
pub const DEBUGCAUSE_BREAKN_MASK: u32 = 16;
pub const DEBUGCAUSE_BREAK_SHIFT: u32 = 3;
pub const DEBUGCAUSE_BREAK_MASK: u32 = 8;
pub const DEBUGCAUSE_DBREAK_SHIFT: u32 = 2;
pub const DEBUGCAUSE_DBREAK_MASK: u32 = 4;
pub const DEBUGCAUSE_IBREAK_SHIFT: u32 = 1;
pub const DEBUGCAUSE_IBREAK_MASK: u32 = 2;
pub const DEBUGCAUSE_ICOUNT_SHIFT: u32 = 0;
pub const DEBUGCAUSE_ICOUNT_MASK: u32 = 1;
pub const MESR_MEME: u32 = 1;
pub const MESR_MEME_SHIFT: u32 = 0;
pub const MESR_DME: u32 = 2;
pub const MESR_DME_SHIFT: u32 = 1;
pub const MESR_RCE: u32 = 16;
pub const MESR_RCE_SHIFT: u32 = 4;
pub const MESR_ERRENAB: u32 = 256;
pub const MESR_ERRENAB_SHIFT: u32 = 8;
pub const MESR_ERRTEST: u32 = 512;
pub const MESR_ERRTEST_SHIFT: u32 = 9;
pub const MESR_DATEXC: u32 = 1024;
pub const MESR_DATEXC_SHIFT: u32 = 10;
pub const MESR_INSEXC: u32 = 2048;
pub const MESR_INSEXC_SHIFT: u32 = 11;
pub const MESR_WAYNUM_SHIFT: u32 = 16;
pub const MESR_ACCTYPE_SHIFT: u32 = 20;
pub const MESR_MEMTYPE_SHIFT: u32 = 24;
pub const MESR_ERRTYPE_SHIFT: u32 = 30;
pub const MEMCTL_SNOOP_EN_SHIFT: u32 = 1;
pub const MEMCTL_SNOOP_EN: u32 = 2;
pub const MEMCTL_L0IBUF_EN_SHIFT: u32 = 0;
pub const MEMCTL_L0IBUF_EN: u32 = 1;
pub const MEMCTL_INV_EN_SHIFT: u32 = 23;
pub const MEMCTL_INV_EN: u32 = 8388608;
pub const MEMCTL_DCWU_SHIFT: u32 = 8;
pub const MEMCTL_DCWU_BITS: u32 = 5;
pub const MEMCTL_DCWA_SHIFT: u32 = 13;
pub const MEMCTL_DCWA_BITS: u32 = 5;
pub const MEMCTL_ICWU_SHIFT: u32 = 18;
pub const MEMCTL_ICWU_BITS: u32 = 5;
pub const MEMCTL_DCWU_MASK: u32 = 7936;
pub const MEMCTL_DCWA_MASK: u32 = 253952;
pub const MEMCTL_ICWU_MASK: u32 = 8126464;
pub const MEMCTL_DCWU_CLR_MASK: i32 = -7937;
pub const MEMCTL_DCWA_CLR_MASK: i32 = -253953;
pub const MEMCTL_ICWU_CLR_MASK: i32 = -8126465;
pub const MEMCTL_DCW_CLR_MASK: i32 = -1;
pub const MEMCTL_IDCW_CLR_MASK: i32 = -1;
pub const LBEG: u32 = 0;
pub const LEND: u32 = 1;
pub const LCOUNT: u32 = 2;
pub const SAR: u32 = 3;
pub const BR: u32 = 4;
pub const SCOMPARE1: u32 = 12;
pub const ACCLO: u32 = 16;
pub const ACCHI: u32 = 17;
pub const MR_0: u32 = 32;
pub const MR_1: u32 = 33;
pub const MR_2: u32 = 34;
pub const MR_3: u32 = 35;
pub const WINDOWBASE: u32 = 72;
pub const WINDOWSTART: u32 = 73;
pub const IBREAKENABLE: u32 = 96;
pub const MEMCTL: u32 = 97;
pub const ATOMCTL: u32 = 99;
pub const DDR: u32 = 104;
pub const IBREAKA_0: u32 = 128;
pub const IBREAKA_1: u32 = 129;
pub const DBREAKA_0: u32 = 144;
pub const DBREAKA_1: u32 = 145;
pub const DBREAKC_0: u32 = 160;
pub const DBREAKC_1: u32 = 161;
pub const CONFIGID0: u32 = 176;
pub const EPC_1: u32 = 177;
pub const EPC_2: u32 = 178;
pub const EPC_3: u32 = 179;
pub const EPC_4: u32 = 180;
pub const EPC_5: u32 = 181;
pub const EPC_6: u32 = 182;
pub const EPC_7: u32 = 183;
pub const DEPC: u32 = 192;
pub const EPS_2: u32 = 194;
pub const EPS_3: u32 = 195;
pub const EPS_4: u32 = 196;
pub const EPS_5: u32 = 197;
pub const EPS_6: u32 = 198;
pub const EPS_7: u32 = 199;
pub const CONFIGID1: u32 = 208;
pub const EXCSAVE_1: u32 = 209;
pub const EXCSAVE_2: u32 = 210;
pub const EXCSAVE_3: u32 = 211;
pub const EXCSAVE_4: u32 = 212;
pub const EXCSAVE_5: u32 = 213;
pub const EXCSAVE_6: u32 = 214;
pub const EXCSAVE_7: u32 = 215;
pub const CPENABLE: u32 = 224;
pub const INTERRUPT: u32 = 226;
pub const INTENABLE: u32 = 228;
pub const PS: u32 = 230;
pub const VECBASE: u32 = 231;
pub const EXCCAUSE: u32 = 232;
pub const DEBUGCAUSE: u32 = 233;
pub const CCOUNT: u32 = 234;
pub const PRID: u32 = 235;
pub const ICOUNT: u32 = 236;
pub const ICOUNTLEVEL: u32 = 237;
pub const EXCVADDR: u32 = 238;
pub const CCOMPARE_0: u32 = 240;
pub const CCOMPARE_1: u32 = 241;
pub const CCOMPARE_2: u32 = 242;
pub const MISC_REG_0: u32 = 244;
pub const MISC_REG_1: u32 = 245;
pub const MISC_REG_2: u32 = 246;
pub const MISC_REG_3: u32 = 247;
pub const MR: u32 = 32;
pub const IBREAKA: u32 = 128;
pub const DBREAKA: u32 = 144;
pub const DBREAKC: u32 = 160;
pub const EPC: u32 = 176;
pub const EPS: u32 = 192;
pub const EXCSAVE: u32 = 208;
pub const CCOMPARE: u32 = 240;
pub const INTREAD: u32 = 226;
pub const INTSET: u32 = 226;
pub const INTCLEAR: u32 = 227;
pub const CALL0_ABI: u32 = 0;
pub const ALIGNPAD: u32 = 2;
pub const KERNELSTACKSIZE: u32 = 1024;
pub const CORE_STATE_SIGNATURE: u32 = 2982522861;
pub const XTOS_KEEPON_MEM: u32 = 256;
pub const XTOS_KEEPON_MEM_SHIFT: u32 = 8;
pub const XTOS_KEEPON_DEBUG: u32 = 4096;
pub const XTOS_KEEPON_DEBUG_SHIFT: u32 = 12;
pub const XTOS_IDMA_NO_WAIT: u32 = 65536;
pub const XTOS_IDMA_WAIT_STANDBY: u32 = 131072;
pub const XTOS_COREF_PSO: u32 = 1;
pub const XTOS_COREF_PSO_SHIFT: u32 = 0;
pub const EXTRA_SAVE_AREA_SIZE: u32 = 32;
pub const BASE_SAVE_AREA_SIZE: u32 = 16;
pub const SAVE_AREA_OFFSET: u32 = 48;
pub const BASE_AREA_SP_OFFSET: u32 = 12;
pub const DSRSET: u32 = 1056780;
pub const ESP_WATCHPOINT_LOAD: u32 = 1073741824;
pub const ESP_WATCHPOINT_STORE: u32 = 2147483648;
pub const ESP_WATCHPOINT_ACCESS: u32 = 3221225472;
pub const TOUCH_PAD_BIT_MASK_ALL: u32 = 32767;
pub const TOUCH_PAD_BIT_MASK_MAX: u32 = 32767;
pub const TOUCH_PAD_THRESHOLD_MAX: u32 = 2097151;
pub const TOUCH_PAD_SLEEP_CYCLE_DEFAULT: u32 = 15;
pub const TOUCH_PAD_MEASURE_CYCLE_DEFAULT: u32 = 500;
pub const TOUCH_PROXIMITY_MEAS_NUM_MAX: u32 = 255;
pub const TOUCH_DEBOUNCE_CNT_MAX: u32 = 7;
pub const TOUCH_NOISE_THR_MAX: u32 = 3;
pub const TOUCH_JITTER_STEP_MAX: u32 = 15;
pub const SLP_OE_V: u32 = 1;
pub const SLP_OE_S: u32 = 0;
pub const SLP_SEL_V: u32 = 1;
pub const SLP_SEL_S: u32 = 1;
pub const SLP_PD_V: u32 = 1;
pub const SLP_PD_S: u32 = 2;
pub const SLP_PU_V: u32 = 1;
pub const SLP_PU_S: u32 = 3;
pub const SLP_IE_V: u32 = 1;
pub const SLP_IE_S: u32 = 4;
pub const SLP_DRV: u32 = 3;
pub const SLP_DRV_V: u32 = 3;
pub const SLP_DRV_S: u32 = 5;
pub const FUN_PD_V: u32 = 1;
pub const FUN_PD_S: u32 = 7;
pub const FUN_PU_V: u32 = 1;
pub const FUN_PU_S: u32 = 8;
pub const FUN_IE_V: u32 = 1;
pub const FUN_IE_S: u32 = 9;
pub const FUN_DRV: u32 = 3;
pub const FUN_DRV_V: u32 = 3;
pub const FUN_DRV_S: u32 = 10;
pub const MCU_SEL: u32 = 7;
pub const MCU_SEL_V: u32 = 7;
pub const MCU_SEL_S: u32 = 12;
pub const FUNC_GPIO_GPIO: u32 = 1;
pub const PIN_FUNC_GPIO: u32 = 1;
pub const SPI_CS1_GPIO_NUM: u32 = 26;
pub const SPI_HD_GPIO_NUM: u32 = 27;
pub const SPI_WP_GPIO_NUM: u32 = 28;
pub const SPI_CS0_GPIO_NUM: u32 = 29;
pub const SPI_CLK_GPIO_NUM: u32 = 30;
pub const SPI_Q_GPIO_NUM: u32 = 31;
pub const SPI_D_GPIO_NUM: u32 = 32;
pub const SPI_D4_GPIO_NUM: u32 = 33;
pub const SPI_D5_GPIO_NUM: u32 = 34;
pub const SPI_D6_GPIO_NUM: u32 = 35;
pub const SPI_D7_GPIO_NUM: u32 = 36;
pub const SPI_DQS_GPIO_NUM: u32 = 37;
pub const SD_CLK_GPIO_NUM: u32 = 12;
pub const SD_CMD_GPIO_NUM: u32 = 11;
pub const SD_DATA0_GPIO_NUM: u32 = 13;
pub const SD_DATA1_GPIO_NUM: u32 = 14;
pub const SD_DATA2_GPIO_NUM: u32 = 9;
pub const SD_DATA3_GPIO_NUM: u32 = 10;
pub const MAX_RTC_GPIO_NUM: u32 = 21;
pub const MAX_PAD_GPIO_NUM: u32 = 48;
pub const MAX_GPIO_NUM: u32 = 53;
pub const REG_IO_MUX_BASE: u32 = 1610649600;
pub const PIN_CTRL: u32 = 1610649600;
pub const PAD_POWER_SEL_V: u32 = 1;
pub const PAD_POWER_SEL_S: u32 = 15;
pub const PAD_POWER_SWITCH_DELAY: u32 = 7;
pub const PAD_POWER_SWITCH_DELAY_V: u32 = 7;
pub const PAD_POWER_SWITCH_DELAY_S: u32 = 12;
pub const CLK_OUT3: u32 = 15;
pub const CLK_OUT3_V: u32 = 15;
pub const CLK_OUT3_S: u32 = 8;
pub const CLK_OUT3_M: u32 = 3840;
pub const CLK_OUT2: u32 = 15;
pub const CLK_OUT2_V: u32 = 15;
pub const CLK_OUT2_S: u32 = 4;
pub const CLK_OUT2_M: u32 = 240;
pub const CLK_OUT1: u32 = 15;
pub const CLK_OUT1_V: u32 = 15;
pub const CLK_OUT1_S: u32 = 0;
pub const CLK_OUT1_M: u32 = 15;
pub const PERIPHS_IO_MUX_GPIO0_U: u32 = 1610649604;
pub const FUNC_GPIO0_GPIO0: u32 = 1;
pub const FUNC_GPIO0_GPIO0_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO1_U: u32 = 1610649608;
pub const FUNC_GPIO1_GPIO1: u32 = 1;
pub const FUNC_GPIO1_GPIO1_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO2_U: u32 = 1610649612;
pub const FUNC_GPIO2_GPIO2: u32 = 1;
pub const FUNC_GPIO2_GPIO2_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO3_U: u32 = 1610649616;
pub const FUNC_GPIO3_GPIO3: u32 = 1;
pub const FUNC_GPIO3_GPIO3_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO4_U: u32 = 1610649620;
pub const FUNC_GPIO4_GPIO4: u32 = 1;
pub const FUNC_GPIO4_GPIO4_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO5_U: u32 = 1610649624;
pub const FUNC_GPIO5_GPIO5: u32 = 1;
pub const FUNC_GPIO5_GPIO5_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO6_U: u32 = 1610649628;
pub const FUNC_GPIO6_GPIO6: u32 = 1;
pub const FUNC_GPIO6_GPIO6_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO7_U: u32 = 1610649632;
pub const FUNC_GPIO7_GPIO7: u32 = 1;
pub const FUNC_GPIO7_GPIO7_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO8_U: u32 = 1610649636;
pub const FUNC_GPIO8_SUBSPICS1: u32 = 3;
pub const FUNC_GPIO8_GPIO8: u32 = 1;
pub const FUNC_GPIO8_GPIO8_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO9_U: u32 = 1610649640;
pub const FUNC_GPIO9_FSPIHD: u32 = 4;
pub const FUNC_GPIO9_SUBSPIHD: u32 = 3;
pub const FUNC_GPIO9_GPIO9: u32 = 1;
pub const FUNC_GPIO9_GPIO9_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO10_U: u32 = 1610649644;
pub const FUNC_GPIO10_FSPICS0: u32 = 4;
pub const FUNC_GPIO10_SUBSPICS0: u32 = 3;
pub const FUNC_GPIO10_FSPIIO4: u32 = 2;
pub const FUNC_GPIO10_GPIO10: u32 = 1;
pub const FUNC_GPIO10_GPIO10_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO11_U: u32 = 1610649648;
pub const FUNC_GPIO11_FSPID: u32 = 4;
pub const FUNC_GPIO11_SUBSPID: u32 = 3;
pub const FUNC_GPIO11_FSPIIO5: u32 = 2;
pub const FUNC_GPIO11_GPIO11: u32 = 1;
pub const FUNC_GPIO11_GPIO11_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO12_U: u32 = 1610649652;
pub const FUNC_GPIO12_FSPICLK: u32 = 4;
pub const FUNC_GPIO12_SUBSPICLK: u32 = 3;
pub const FUNC_GPIO12_FSPIIO6: u32 = 2;
pub const FUNC_GPIO12_GPIO12: u32 = 1;
pub const FUNC_GPIO12_GPIO12_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO13_U: u32 = 1610649656;
pub const FUNC_GPIO13_FSPIQ: u32 = 4;
pub const FUNC_GPIO13_SUBSPIQ: u32 = 3;
pub const FUNC_GPIO13_FSPIIO7: u32 = 2;
pub const FUNC_GPIO13_GPIO13: u32 = 1;
pub const FUNC_GPIO13_GPIO13_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO14_U: u32 = 1610649660;
pub const FUNC_GPIO14_FSPIWP: u32 = 4;
pub const FUNC_GPIO14_SUBSPIWP: u32 = 3;
pub const FUNC_GPIO14_FSPIDQS: u32 = 2;
pub const FUNC_GPIO14_GPIO14: u32 = 1;
pub const FUNC_GPIO14_GPIO14_0: u32 = 0;
pub const PERIPHS_IO_MUX_XTAL_32K_P_U: u32 = 1610649664;
pub const FUNC_XTAL_32K_P_U0RTS: u32 = 2;
pub const FUNC_XTAL_32K_P_GPIO15: u32 = 1;
pub const FUNC_XTAL_32K_P_GPIO15_0: u32 = 0;
pub const PERIPHS_IO_MUX_XTAL_32K_N_U: u32 = 1610649668;
pub const FUNC_XTAL_32K_N_U0CTS: u32 = 2;
pub const FUNC_XTAL_32K_N_GPIO16: u32 = 1;
pub const FUNC_XTAL_32K_N_GPIO16_0: u32 = 0;
pub const PERIPHS_IO_MUX_DAC_1_U: u32 = 1610649672;
pub const FUNC_DAC_1_U1TXD: u32 = 2;
pub const FUNC_DAC_1_GPIO17: u32 = 1;
pub const FUNC_DAC_1_GPIO17_0: u32 = 0;
pub const PERIPHS_IO_MUX_DAC_2_U: u32 = 1610649676;
pub const FUNC_DAC_2_CLK_OUT3: u32 = 3;
pub const FUNC_DAC_2_U1RXD: u32 = 2;
pub const FUNC_DAC_2_GPIO18: u32 = 1;
pub const FUNC_DAC_2_GPIO18_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO19_U: u32 = 1610649680;
pub const FUNC_GPIO19_CLK_OUT2: u32 = 3;
pub const FUNC_GPIO19_U1RTS: u32 = 2;
pub const FUNC_GPIO19_GPIO19: u32 = 1;
pub const FUNC_GPIO19_GPIO19_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO20_U: u32 = 1610649684;
pub const FUNC_GPIO20_CLK_OUT1: u32 = 3;
pub const FUNC_GPIO20_U1CTS: u32 = 2;
pub const FUNC_GPIO20_GPIO20: u32 = 1;
pub const FUNC_GPIO20_GPIO20_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO21_U: u32 = 1610649688;
pub const FUNC_GPIO21_GPIO21: u32 = 1;
pub const FUNC_GPIO21_GPIO21_0: u32 = 0;
pub const PERIPHS_IO_MUX_SPICS1_U: u32 = 1610649708;
pub const FUNC_SPICS1_GPIO26: u32 = 1;
pub const FUNC_SPICS1_SPICS1: u32 = 0;
pub const PERIPHS_IO_MUX_SPIHD_U: u32 = 1610649712;
pub const FUNC_SPIHD_GPIO27: u32 = 1;
pub const FUNC_SPIHD_SPIHD: u32 = 0;
pub const PERIPHS_IO_MUX_SPIWP_U: u32 = 1610649716;
pub const FUNC_SPIWP_GPIO28: u32 = 1;
pub const FUNC_SPIWP_SPIWP: u32 = 0;
pub const PERIPHS_IO_MUX_SPICS0_U: u32 = 1610649720;
pub const FUNC_SPICS0_GPIO29: u32 = 1;
pub const FUNC_SPICS0_SPICS0: u32 = 0;
pub const PERIPHS_IO_MUX_SPICLK_U: u32 = 1610649724;
pub const FUNC_SPICLK_GPIO30: u32 = 1;
pub const FUNC_SPICLK_SPICLK: u32 = 0;
pub const PERIPHS_IO_MUX_SPIQ_U: u32 = 1610649728;
pub const FUNC_SPIQ_GPIO31: u32 = 1;
pub const FUNC_SPIQ_SPIQ: u32 = 0;
pub const PERIPHS_IO_MUX_SPID_U: u32 = 1610649732;
pub const FUNC_SPID_GPIO32: u32 = 1;
pub const FUNC_SPID_SPID: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO33_U: u32 = 1610649736;
pub const FUNC_GPIO33_SPIIO4: u32 = 4;
pub const FUNC_GPIO33_SUBSPIHD: u32 = 3;
pub const FUNC_GPIO33_FSPIHD: u32 = 2;
pub const FUNC_GPIO33_GPIO33: u32 = 1;
pub const FUNC_GPIO33_GPIO33_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO34_U: u32 = 1610649740;
pub const FUNC_GPIO34_SPIIO5: u32 = 4;
pub const FUNC_GPIO34_SUBSPICS0: u32 = 3;
pub const FUNC_GPIO34_FSPICS0: u32 = 2;
pub const FUNC_GPIO34_GPIO34: u32 = 1;
pub const FUNC_GPIO34_GPIO34_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO35_U: u32 = 1610649744;
pub const FUNC_GPIO35_SPIIO6: u32 = 4;
pub const FUNC_GPIO35_SUBSPID: u32 = 3;
pub const FUNC_GPIO35_FSPID: u32 = 2;
pub const FUNC_GPIO35_GPIO35: u32 = 1;
pub const FUNC_GPIO35_GPIO35_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO36_U: u32 = 1610649748;
pub const FUNC_GPIO36_SPIIO7: u32 = 4;
pub const FUNC_GPIO36_SUBSPICLK: u32 = 3;
pub const FUNC_GPIO36_FSPICLK: u32 = 2;
pub const FUNC_GPIO36_GPIO36: u32 = 1;
pub const FUNC_GPIO36_GPIO36_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO37_U: u32 = 1610649752;
pub const FUNC_GPIO37_SPIDQS: u32 = 4;
pub const FUNC_GPIO37_SUBSPIQ: u32 = 3;
pub const FUNC_GPIO37_FSPIQ: u32 = 2;
pub const FUNC_GPIO37_GPIO37: u32 = 1;
pub const FUNC_GPIO37_GPIO37_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO38_U: u32 = 1610649756;
pub const FUNC_GPIO38_SUBSPIWP: u32 = 3;
pub const FUNC_GPIO38_FSPIWP: u32 = 2;
pub const FUNC_GPIO38_GPIO38: u32 = 1;
pub const FUNC_GPIO38_GPIO38_0: u32 = 0;
pub const PERIPHS_IO_MUX_MTCK_U: u32 = 1610649760;
pub const FUNC_MTCK_SUBSPICS1: u32 = 3;
pub const FUNC_MTCK_CLK_OUT3: u32 = 2;
pub const FUNC_MTCK_GPIO39: u32 = 1;
pub const FUNC_MTCK_MTCK: u32 = 0;
pub const PERIPHS_IO_MUX_MTDO_U: u32 = 1610649764;
pub const FUNC_MTDO_CLK_OUT2: u32 = 2;
pub const FUNC_MTDO_GPIO40: u32 = 1;
pub const FUNC_MTDO_MTDO: u32 = 0;
pub const PERIPHS_IO_MUX_MTDI_U: u32 = 1610649768;
pub const FUNC_MTDI_CLK_OUT1: u32 = 2;
pub const FUNC_MTDI_GPIO41: u32 = 1;
pub const FUNC_MTDI_MTDI: u32 = 0;
pub const PERIPHS_IO_MUX_MTMS_U: u32 = 1610649772;
pub const FUNC_MTMS_GPIO42: u32 = 1;
pub const FUNC_MTMS_MTMS: u32 = 0;
pub const PERIPHS_IO_MUX_U0TXD_U: u32 = 1610649776;
pub const FUNC_U0TXD_CLK_OUT1: u32 = 2;
pub const FUNC_U0TXD_GPIO43: u32 = 1;
pub const FUNC_U0TXD_U0TXD: u32 = 0;
pub const PERIPHS_IO_MUX_U0RXD_U: u32 = 1610649780;
pub const FUNC_U0RXD_CLK_OUT2: u32 = 2;
pub const FUNC_U0RXD_GPIO44: u32 = 1;
pub const FUNC_U0RXD_U0RXD: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO45_U: u32 = 1610649784;
pub const FUNC_GPIO45_GPIO45: u32 = 1;
pub const FUNC_GPIO45_GPIO45_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO46_U: u32 = 1610649788;
pub const FUNC_GPIO46_GPIO46: u32 = 1;
pub const FUNC_GPIO46_GPIO46_0: u32 = 0;
pub const PERIPHS_IO_MUX_SPICLK_P_U: u32 = 1610649792;
pub const FUNC_SPICLK_P_SUBSPICLK_DIFF: u32 = 2;
pub const FUNC_SPICLK_P_GPIO47: u32 = 1;
pub const FUNC_SPICLK_P_SPICLK_DIFF: u32 = 0;
pub const PERIPHS_IO_MUX_SPICLK_N_U: u32 = 1610649796;
pub const FUNC_SPICLK_N_SUBSPICLK_DIFF: u32 = 2;
pub const FUNC_SPICLK_N_GPIO48: u32 = 1;
pub const FUNC_SPICLK_N_SPICLK_DIFF: u32 = 0;
pub const IO_MUX_DATE_REG: u32 = 1610649852;
pub const IO_MUX_DATE: u32 = 4294967295;
pub const IO_MUX_DATE_S: u32 = 0;
pub const IO_MUX_DATE_VERSION: u32 = 26243424;
pub const GPIO_PIN_CONFIG_MSB: u32 = 12;
pub const GPIO_PIN_CONFIG_LSB: u32 = 11;
pub const GPIO_PIN_CONFIG_MASK: u32 = 6144;
pub const GPIO_WAKEUP_ENABLE: u32 = 1;
pub const GPIO_WAKEUP_DISABLE: i32 = -2;
pub const GPIO_PIN_WAKEUP_ENABLE_MSB: u32 = 10;
pub const GPIO_PIN_WAKEUP_ENABLE_LSB: u32 = 10;
pub const GPIO_PIN_WAKEUP_ENABLE_MASK: u32 = 1024;
pub const GPIO_PIN_INT_TYPE_MASK: u32 = 896;
pub const GPIO_PIN_INT_TYPE_MSB: u32 = 9;
pub const GPIO_PIN_INT_TYPE_LSB: u32 = 7;
pub const GPIO_PAD_DRIVER_ENABLE: u32 = 1;
pub const GPIO_PAD_DRIVER_DISABLE: i32 = -2;
pub const GPIO_PIN_PAD_DRIVER_MSB: u32 = 2;
pub const GPIO_PIN_PAD_DRIVER_LSB: u32 = 2;
pub const GPIO_PIN_PAD_DRIVER_MASK: u32 = 4;
pub const GPIO_BT_SELECT_REG: u32 = 1610629120;
pub const GPIO_BT_SEL: u32 = 4294967295;
pub const GPIO_BT_SEL_V: u32 = 4294967295;
pub const GPIO_BT_SEL_S: u32 = 0;
pub const GPIO_OUT_REG: u32 = 1610629124;
pub const GPIO_OUT_DATA: u32 = 4294967295;
pub const GPIO_OUT_DATA_V: u32 = 4294967295;
pub const GPIO_OUT_DATA_S: u32 = 0;
pub const GPIO_OUT_W1TS_REG: u32 = 1610629128;
pub const GPIO_OUT_W1TS: u32 = 4294967295;
pub const GPIO_OUT_W1TS_V: u32 = 4294967295;
pub const GPIO_OUT_W1TS_S: u32 = 0;
pub const GPIO_OUT_W1TC_REG: u32 = 1610629132;
pub const GPIO_OUT_W1TC: u32 = 4294967295;
pub const GPIO_OUT_W1TC_V: u32 = 4294967295;
pub const GPIO_OUT_W1TC_S: u32 = 0;
pub const GPIO_OUT1_REG: u32 = 1610629136;
pub const GPIO_OUT1_DATA: u32 = 4194303;
pub const GPIO_OUT1_DATA_V: u32 = 4194303;
pub const GPIO_OUT1_DATA_S: u32 = 0;
pub const GPIO_OUT1_W1TS_REG: u32 = 1610629140;
pub const GPIO_OUT1_W1TS: u32 = 4194303;
pub const GPIO_OUT1_W1TS_V: u32 = 4194303;
pub const GPIO_OUT1_W1TS_S: u32 = 0;
pub const GPIO_OUT1_W1TC_REG: u32 = 1610629144;
pub const GPIO_OUT1_W1TC: u32 = 4194303;
pub const GPIO_OUT1_W1TC_V: u32 = 4194303;
pub const GPIO_OUT1_W1TC_S: u32 = 0;
pub const GPIO_SDIO_SELECT_REG: u32 = 1610629148;
pub const GPIO_SDIO_SEL: u32 = 255;
pub const GPIO_SDIO_SEL_V: u32 = 255;
pub const GPIO_SDIO_SEL_S: u32 = 0;
pub const GPIO_ENABLE_REG: u32 = 1610629152;
pub const GPIO_ENABLE_DATA: u32 = 4294967295;
pub const GPIO_ENABLE_DATA_V: u32 = 4294967295;
pub const GPIO_ENABLE_DATA_S: u32 = 0;
pub const GPIO_ENABLE_W1TS_REG: u32 = 1610629156;
pub const GPIO_ENABLE_W1TS: u32 = 4294967295;
pub const GPIO_ENABLE_W1TS_V: u32 = 4294967295;
pub const GPIO_ENABLE_W1TS_S: u32 = 0;
pub const GPIO_ENABLE_W1TC_REG: u32 = 1610629160;
pub const GPIO_ENABLE_W1TC: u32 = 4294967295;
pub const GPIO_ENABLE_W1TC_V: u32 = 4294967295;
pub const GPIO_ENABLE_W1TC_S: u32 = 0;
pub const GPIO_ENABLE1_REG: u32 = 1610629164;
pub const GPIO_ENABLE1_DATA: u32 = 4194303;
pub const GPIO_ENABLE1_DATA_V: u32 = 4194303;
pub const GPIO_ENABLE1_DATA_S: u32 = 0;
pub const GPIO_ENABLE1_W1TS_REG: u32 = 1610629168;
pub const GPIO_ENABLE1_W1TS: u32 = 4194303;
pub const GPIO_ENABLE1_W1TS_V: u32 = 4194303;
pub const GPIO_ENABLE1_W1TS_S: u32 = 0;
pub const GPIO_ENABLE1_W1TC_REG: u32 = 1610629172;
pub const GPIO_ENABLE1_W1TC: u32 = 4194303;
pub const GPIO_ENABLE1_W1TC_V: u32 = 4194303;
pub const GPIO_ENABLE1_W1TC_S: u32 = 0;
pub const GPIO_STRAP_REG: u32 = 1610629176;
pub const GPIO_STRAPPING: u32 = 65535;
pub const GPIO_STRAPPING_V: u32 = 65535;
pub const GPIO_STRAPPING_S: u32 = 0;
pub const GPIO_IN_REG: u32 = 1610629180;
pub const GPIO_IN_DATA: u32 = 4294967295;
pub const GPIO_IN_DATA_V: u32 = 4294967295;
pub const GPIO_IN_DATA_S: u32 = 0;
pub const GPIO_IN1_REG: u32 = 1610629184;
pub const GPIO_IN1_DATA: u32 = 4194303;
pub const GPIO_IN1_DATA_V: u32 = 4194303;
pub const GPIO_IN1_DATA_S: u32 = 0;
pub const GPIO_STATUS_REG: u32 = 1610629188;
pub const GPIO_STATUS_INT: u32 = 4294967295;
pub const GPIO_STATUS_INT_V: u32 = 4294967295;
pub const GPIO_STATUS_INT_S: u32 = 0;
pub const GPIO_STATUS_W1TS_REG: u32 = 1610629192;
pub const GPIO_STATUS_W1TS: u32 = 4294967295;
pub const GPIO_STATUS_W1TS_V: u32 = 4294967295;
pub const GPIO_STATUS_W1TS_S: u32 = 0;
pub const GPIO_STATUS_W1TC_REG: u32 = 1610629196;
pub const GPIO_STATUS_W1TC: u32 = 4294967295;
pub const GPIO_STATUS_W1TC_V: u32 = 4294967295;
pub const GPIO_STATUS_W1TC_S: u32 = 0;
pub const GPIO_STATUS1_REG: u32 = 1610629200;
pub const GPIO_STATUS1_INT: u32 = 4194303;
pub const GPIO_STATUS1_INT_V: u32 = 4194303;
pub const GPIO_STATUS1_INT_S: u32 = 0;
pub const GPIO_STATUS1_W1TS_REG: u32 = 1610629204;
pub const GPIO_STATUS1_W1TS: u32 = 4194303;
pub const GPIO_STATUS1_W1TS_V: u32 = 4194303;
pub const GPIO_STATUS1_W1TS_S: u32 = 0;
pub const GPIO_STATUS1_W1TC_REG: u32 = 1610629208;
pub const GPIO_STATUS1_W1TC: u32 = 4194303;
pub const GPIO_STATUS1_W1TC_V: u32 = 4194303;
pub const GPIO_STATUS1_W1TC_S: u32 = 0;
pub const GPIO_PCPU_INT_REG: u32 = 1610629212;
pub const GPIO_PROCPU_INT: u32 = 4294967295;
pub const GPIO_PROCPU_INT_V: u32 = 4294967295;
pub const GPIO_PROCPU_INT_S: u32 = 0;
pub const GPIO_PCPU_NMI_INT_REG: u32 = 1610629216;
pub const GPIO_PROCPU_NMI_INT: u32 = 4294967295;
pub const GPIO_PROCPU_NMI_INT_V: u32 = 4294967295;
pub const GPIO_PROCPU_NMI_INT_S: u32 = 0;
pub const GPIO_CPUSDIO_INT_REG: u32 = 1610629220;
pub const GPIO_SDIO_INT: u32 = 4294967295;
pub const GPIO_SDIO_INT_V: u32 = 4294967295;
pub const GPIO_SDIO_INT_S: u32 = 0;
pub const GPIO_PCPU_INT1_REG: u32 = 1610629224;
pub const GPIO_PROCPU_INT_H: u32 = 4194303;
pub const GPIO_PROCPU_INT_H_V: u32 = 4194303;
pub const GPIO_PROCPU_INT_H_S: u32 = 0;
pub const GPIO_PCPU_NMI_INT1_REG: u32 = 1610629228;
pub const GPIO_PROCPU_NMI_INT_H: u32 = 4194303;
pub const GPIO_PROCPU_NMI_INT_H_V: u32 = 4194303;
pub const GPIO_PROCPU_NMI_INT_H_S: u32 = 0;
pub const GPIO_CPUSDIO_INT1_REG: u32 = 1610629232;
pub const GPIO_SDIO_INT_H: u32 = 4194303;
pub const GPIO_SDIO_INT_H_V: u32 = 4194303;
pub const GPIO_SDIO_INT_H_S: u32 = 0;
pub const GPIO_PIN0_REG: u32 = 1610629236;
pub const GPIO_PIN0_INT_ENA: u32 = 31;
pub const GPIO_PIN0_INT_ENA_V: u32 = 31;
pub const GPIO_PIN0_INT_ENA_S: u32 = 13;
pub const GPIO_PIN0_CONFIG: u32 = 3;
pub const GPIO_PIN0_CONFIG_V: u32 = 3;
pub const GPIO_PIN0_CONFIG_S: u32 = 11;
pub const GPIO_PIN0_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN0_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN0_INT_TYPE: u32 = 7;
pub const GPIO_PIN0_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN0_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN0_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN0_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN0_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN0_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN0_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN0_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN0_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN0_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN1_REG: u32 = 1610629240;
pub const GPIO_PIN1_INT_ENA: u32 = 31;
pub const GPIO_PIN1_INT_ENA_V: u32 = 31;
pub const GPIO_PIN1_INT_ENA_S: u32 = 13;
pub const GPIO_PIN1_CONFIG: u32 = 3;
pub const GPIO_PIN1_CONFIG_V: u32 = 3;
pub const GPIO_PIN1_CONFIG_S: u32 = 11;
pub const GPIO_PIN1_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN1_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN1_INT_TYPE: u32 = 7;
pub const GPIO_PIN1_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN1_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN1_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN1_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN1_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN1_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN1_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN1_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN1_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN1_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN2_REG: u32 = 1610629244;
pub const GPIO_PIN2_INT_ENA: u32 = 31;
pub const GPIO_PIN2_INT_ENA_V: u32 = 31;
pub const GPIO_PIN2_INT_ENA_S: u32 = 13;
pub const GPIO_PIN2_CONFIG: u32 = 3;
pub const GPIO_PIN2_CONFIG_V: u32 = 3;
pub const GPIO_PIN2_CONFIG_S: u32 = 11;
pub const GPIO_PIN2_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN2_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN2_INT_TYPE: u32 = 7;
pub const GPIO_PIN2_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN2_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN2_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN2_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN2_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN2_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN2_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN2_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN2_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN2_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN3_REG: u32 = 1610629248;
pub const GPIO_PIN3_INT_ENA: u32 = 31;
pub const GPIO_PIN3_INT_ENA_V: u32 = 31;
pub const GPIO_PIN3_INT_ENA_S: u32 = 13;
pub const GPIO_PIN3_CONFIG: u32 = 3;
pub const GPIO_PIN3_CONFIG_V: u32 = 3;
pub const GPIO_PIN3_CONFIG_S: u32 = 11;
pub const GPIO_PIN3_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN3_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN3_INT_TYPE: u32 = 7;
pub const GPIO_PIN3_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN3_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN3_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN3_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN3_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN3_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN3_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN3_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN3_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN3_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN4_REG: u32 = 1610629252;
pub const GPIO_PIN4_INT_ENA: u32 = 31;
pub const GPIO_PIN4_INT_ENA_V: u32 = 31;
pub const GPIO_PIN4_INT_ENA_S: u32 = 13;
pub const GPIO_PIN4_CONFIG: u32 = 3;
pub const GPIO_PIN4_CONFIG_V: u32 = 3;
pub const GPIO_PIN4_CONFIG_S: u32 = 11;
pub const GPIO_PIN4_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN4_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN4_INT_TYPE: u32 = 7;
pub const GPIO_PIN4_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN4_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN4_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN4_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN4_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN4_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN4_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN4_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN4_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN4_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN5_REG: u32 = 1610629256;
pub const GPIO_PIN5_INT_ENA: u32 = 31;
pub const GPIO_PIN5_INT_ENA_V: u32 = 31;
pub const GPIO_PIN5_INT_ENA_S: u32 = 13;
pub const GPIO_PIN5_CONFIG: u32 = 3;
pub const GPIO_PIN5_CONFIG_V: u32 = 3;
pub const GPIO_PIN5_CONFIG_S: u32 = 11;
pub const GPIO_PIN5_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN5_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN5_INT_TYPE: u32 = 7;
pub const GPIO_PIN5_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN5_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN5_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN5_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN5_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN5_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN5_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN5_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN5_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN5_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN6_REG: u32 = 1610629260;
pub const GPIO_PIN6_INT_ENA: u32 = 31;
pub const GPIO_PIN6_INT_ENA_V: u32 = 31;
pub const GPIO_PIN6_INT_ENA_S: u32 = 13;
pub const GPIO_PIN6_CONFIG: u32 = 3;
pub const GPIO_PIN6_CONFIG_V: u32 = 3;
pub const GPIO_PIN6_CONFIG_S: u32 = 11;
pub const GPIO_PIN6_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN6_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN6_INT_TYPE: u32 = 7;
pub const GPIO_PIN6_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN6_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN6_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN6_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN6_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN6_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN6_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN6_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN6_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN6_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN7_REG: u32 = 1610629264;
pub const GPIO_PIN7_INT_ENA: u32 = 31;
pub const GPIO_PIN7_INT_ENA_V: u32 = 31;
pub const GPIO_PIN7_INT_ENA_S: u32 = 13;
pub const GPIO_PIN7_CONFIG: u32 = 3;
pub const GPIO_PIN7_CONFIG_V: u32 = 3;
pub const GPIO_PIN7_CONFIG_S: u32 = 11;
pub const GPIO_PIN7_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN7_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN7_INT_TYPE: u32 = 7;
pub const GPIO_PIN7_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN7_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN7_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN7_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN7_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN7_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN7_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN7_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN7_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN7_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN8_REG: u32 = 1610629268;
pub const GPIO_PIN8_INT_ENA: u32 = 31;
pub const GPIO_PIN8_INT_ENA_V: u32 = 31;
pub const GPIO_PIN8_INT_ENA_S: u32 = 13;
pub const GPIO_PIN8_CONFIG: u32 = 3;
pub const GPIO_PIN8_CONFIG_V: u32 = 3;
pub const GPIO_PIN8_CONFIG_S: u32 = 11;
pub const GPIO_PIN8_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN8_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN8_INT_TYPE: u32 = 7;
pub const GPIO_PIN8_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN8_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN8_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN8_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN8_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN8_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN8_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN8_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN8_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN8_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN9_REG: u32 = 1610629272;
pub const GPIO_PIN9_INT_ENA: u32 = 31;
pub const GPIO_PIN9_INT_ENA_V: u32 = 31;
pub const GPIO_PIN9_INT_ENA_S: u32 = 13;
pub const GPIO_PIN9_CONFIG: u32 = 3;
pub const GPIO_PIN9_CONFIG_V: u32 = 3;
pub const GPIO_PIN9_CONFIG_S: u32 = 11;
pub const GPIO_PIN9_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN9_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN9_INT_TYPE: u32 = 7;
pub const GPIO_PIN9_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN9_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN9_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN9_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN9_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN9_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN9_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN9_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN9_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN9_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN10_REG: u32 = 1610629276;
pub const GPIO_PIN10_INT_ENA: u32 = 31;
pub const GPIO_PIN10_INT_ENA_V: u32 = 31;
pub const GPIO_PIN10_INT_ENA_S: u32 = 13;
pub const GPIO_PIN10_CONFIG: u32 = 3;
pub const GPIO_PIN10_CONFIG_V: u32 = 3;
pub const GPIO_PIN10_CONFIG_S: u32 = 11;
pub const GPIO_PIN10_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN10_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN10_INT_TYPE: u32 = 7;
pub const GPIO_PIN10_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN10_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN10_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN10_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN10_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN10_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN10_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN10_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN10_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN10_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN11_REG: u32 = 1610629280;
pub const GPIO_PIN11_INT_ENA: u32 = 31;
pub const GPIO_PIN11_INT_ENA_V: u32 = 31;
pub const GPIO_PIN11_INT_ENA_S: u32 = 13;
pub const GPIO_PIN11_CONFIG: u32 = 3;
pub const GPIO_PIN11_CONFIG_V: u32 = 3;
pub const GPIO_PIN11_CONFIG_S: u32 = 11;
pub const GPIO_PIN11_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN11_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN11_INT_TYPE: u32 = 7;
pub const GPIO_PIN11_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN11_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN11_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN11_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN11_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN11_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN11_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN11_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN11_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN11_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN12_REG: u32 = 1610629284;
pub const GPIO_PIN12_INT_ENA: u32 = 31;
pub const GPIO_PIN12_INT_ENA_V: u32 = 31;
pub const GPIO_PIN12_INT_ENA_S: u32 = 13;
pub const GPIO_PIN12_CONFIG: u32 = 3;
pub const GPIO_PIN12_CONFIG_V: u32 = 3;
pub const GPIO_PIN12_CONFIG_S: u32 = 11;
pub const GPIO_PIN12_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN12_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN12_INT_TYPE: u32 = 7;
pub const GPIO_PIN12_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN12_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN12_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN12_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN12_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN12_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN12_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN12_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN12_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN12_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN13_REG: u32 = 1610629288;
pub const GPIO_PIN13_INT_ENA: u32 = 31;
pub const GPIO_PIN13_INT_ENA_V: u32 = 31;
pub const GPIO_PIN13_INT_ENA_S: u32 = 13;
pub const GPIO_PIN13_CONFIG: u32 = 3;
pub const GPIO_PIN13_CONFIG_V: u32 = 3;
pub const GPIO_PIN13_CONFIG_S: u32 = 11;
pub const GPIO_PIN13_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN13_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN13_INT_TYPE: u32 = 7;
pub const GPIO_PIN13_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN13_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN13_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN13_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN13_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN13_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN13_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN13_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN13_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN13_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN14_REG: u32 = 1610629292;
pub const GPIO_PIN14_INT_ENA: u32 = 31;
pub const GPIO_PIN14_INT_ENA_V: u32 = 31;
pub const GPIO_PIN14_INT_ENA_S: u32 = 13;
pub const GPIO_PIN14_CONFIG: u32 = 3;
pub const GPIO_PIN14_CONFIG_V: u32 = 3;
pub const GPIO_PIN14_CONFIG_S: u32 = 11;
pub const GPIO_PIN14_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN14_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN14_INT_TYPE: u32 = 7;
pub const GPIO_PIN14_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN14_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN14_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN14_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN14_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN14_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN14_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN14_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN14_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN14_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN15_REG: u32 = 1610629296;
pub const GPIO_PIN15_INT_ENA: u32 = 31;
pub const GPIO_PIN15_INT_ENA_V: u32 = 31;
pub const GPIO_PIN15_INT_ENA_S: u32 = 13;
pub const GPIO_PIN15_CONFIG: u32 = 3;
pub const GPIO_PIN15_CONFIG_V: u32 = 3;
pub const GPIO_PIN15_CONFIG_S: u32 = 11;
pub const GPIO_PIN15_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN15_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN15_INT_TYPE: u32 = 7;
pub const GPIO_PIN15_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN15_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN15_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN15_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN15_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN15_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN15_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN15_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN15_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN15_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN16_REG: u32 = 1610629300;
pub const GPIO_PIN16_INT_ENA: u32 = 31;
pub const GPIO_PIN16_INT_ENA_V: u32 = 31;
pub const GPIO_PIN16_INT_ENA_S: u32 = 13;
pub const GPIO_PIN16_CONFIG: u32 = 3;
pub const GPIO_PIN16_CONFIG_V: u32 = 3;
pub const GPIO_PIN16_CONFIG_S: u32 = 11;
pub const GPIO_PIN16_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN16_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN16_INT_TYPE: u32 = 7;
pub const GPIO_PIN16_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN16_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN16_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN16_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN16_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN16_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN16_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN16_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN16_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN16_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN17_REG: u32 = 1610629304;
pub const GPIO_PIN17_INT_ENA: u32 = 31;
pub const GPIO_PIN17_INT_ENA_V: u32 = 31;
pub const GPIO_PIN17_INT_ENA_S: u32 = 13;
pub const GPIO_PIN17_CONFIG: u32 = 3;
pub const GPIO_PIN17_CONFIG_V: u32 = 3;
pub const GPIO_PIN17_CONFIG_S: u32 = 11;
pub const GPIO_PIN17_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN17_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN17_INT_TYPE: u32 = 7;
pub const GPIO_PIN17_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN17_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN17_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN17_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN17_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN17_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN17_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN17_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN17_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN17_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN18_REG: u32 = 1610629308;
pub const GPIO_PIN18_INT_ENA: u32 = 31;
pub const GPIO_PIN18_INT_ENA_V: u32 = 31;
pub const GPIO_PIN18_INT_ENA_S: u32 = 13;
pub const GPIO_PIN18_CONFIG: u32 = 3;
pub const GPIO_PIN18_CONFIG_V: u32 = 3;
pub const GPIO_PIN18_CONFIG_S: u32 = 11;
pub const GPIO_PIN18_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN18_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN18_INT_TYPE: u32 = 7;
pub const GPIO_PIN18_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN18_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN18_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN18_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN18_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN18_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN18_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN18_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN18_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN18_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN19_REG: u32 = 1610629312;
pub const GPIO_PIN19_INT_ENA: u32 = 31;
pub const GPIO_PIN19_INT_ENA_V: u32 = 31;
pub const GPIO_PIN19_INT_ENA_S: u32 = 13;
pub const GPIO_PIN19_CONFIG: u32 = 3;
pub const GPIO_PIN19_CONFIG_V: u32 = 3;
pub const GPIO_PIN19_CONFIG_S: u32 = 11;
pub const GPIO_PIN19_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN19_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN19_INT_TYPE: u32 = 7;
pub const GPIO_PIN19_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN19_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN19_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN19_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN19_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN19_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN19_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN19_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN19_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN19_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN20_REG: u32 = 1610629316;
pub const GPIO_PIN20_INT_ENA: u32 = 31;
pub const GPIO_PIN20_INT_ENA_V: u32 = 31;
pub const GPIO_PIN20_INT_ENA_S: u32 = 13;
pub const GPIO_PIN20_CONFIG: u32 = 3;
pub const GPIO_PIN20_CONFIG_V: u32 = 3;
pub const GPIO_PIN20_CONFIG_S: u32 = 11;
pub const GPIO_PIN20_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN20_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN20_INT_TYPE: u32 = 7;
pub const GPIO_PIN20_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN20_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN20_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN20_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN20_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN20_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN20_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN20_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN20_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN20_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN21_REG: u32 = 1610629320;
pub const GPIO_PIN21_INT_ENA: u32 = 31;
pub const GPIO_PIN21_INT_ENA_V: u32 = 31;
pub const GPIO_PIN21_INT_ENA_S: u32 = 13;
pub const GPIO_PIN21_CONFIG: u32 = 3;
pub const GPIO_PIN21_CONFIG_V: u32 = 3;
pub const GPIO_PIN21_CONFIG_S: u32 = 11;
pub const GPIO_PIN21_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN21_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN21_INT_TYPE: u32 = 7;
pub const GPIO_PIN21_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN21_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN21_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN21_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN21_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN21_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN21_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN21_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN21_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN21_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN22_REG: u32 = 1610629324;
pub const GPIO_PIN22_INT_ENA: u32 = 31;
pub const GPIO_PIN22_INT_ENA_V: u32 = 31;
pub const GPIO_PIN22_INT_ENA_S: u32 = 13;
pub const GPIO_PIN22_CONFIG: u32 = 3;
pub const GPIO_PIN22_CONFIG_V: u32 = 3;
pub const GPIO_PIN22_CONFIG_S: u32 = 11;
pub const GPIO_PIN22_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN22_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN22_INT_TYPE: u32 = 7;
pub const GPIO_PIN22_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN22_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN22_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN22_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN22_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN22_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN22_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN22_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN22_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN22_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN23_REG: u32 = 1610629328;
pub const GPIO_PIN23_INT_ENA: u32 = 31;
pub const GPIO_PIN23_INT_ENA_V: u32 = 31;
pub const GPIO_PIN23_INT_ENA_S: u32 = 13;
pub const GPIO_PIN23_CONFIG: u32 = 3;
pub const GPIO_PIN23_CONFIG_V: u32 = 3;
pub const GPIO_PIN23_CONFIG_S: u32 = 11;
pub const GPIO_PIN23_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN23_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN23_INT_TYPE: u32 = 7;
pub const GPIO_PIN23_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN23_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN23_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN23_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN23_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN23_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN23_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN23_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN23_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN23_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN24_REG: u32 = 1610629332;
pub const GPIO_PIN24_INT_ENA: u32 = 31;
pub const GPIO_PIN24_INT_ENA_V: u32 = 31;
pub const GPIO_PIN24_INT_ENA_S: u32 = 13;
pub const GPIO_PIN24_CONFIG: u32 = 3;
pub const GPIO_PIN24_CONFIG_V: u32 = 3;
pub const GPIO_PIN24_CONFIG_S: u32 = 11;
pub const GPIO_PIN24_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN24_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN24_INT_TYPE: u32 = 7;
pub const GPIO_PIN24_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN24_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN24_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN24_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN24_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN24_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN24_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN24_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN24_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN24_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN25_REG: u32 = 1610629336;
pub const GPIO_PIN25_INT_ENA: u32 = 31;
pub const GPIO_PIN25_INT_ENA_V: u32 = 31;
pub const GPIO_PIN25_INT_ENA_S: u32 = 13;
pub const GPIO_PIN25_CONFIG: u32 = 3;
pub const GPIO_PIN25_CONFIG_V: u32 = 3;
pub const GPIO_PIN25_CONFIG_S: u32 = 11;
pub const GPIO_PIN25_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN25_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN25_INT_TYPE: u32 = 7;
pub const GPIO_PIN25_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN25_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN25_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN25_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN25_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN25_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN25_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN25_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN25_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN25_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN26_REG: u32 = 1610629340;
pub const GPIO_PIN26_INT_ENA: u32 = 31;
pub const GPIO_PIN26_INT_ENA_V: u32 = 31;
pub const GPIO_PIN26_INT_ENA_S: u32 = 13;
pub const GPIO_PIN26_CONFIG: u32 = 3;
pub const GPIO_PIN26_CONFIG_V: u32 = 3;
pub const GPIO_PIN26_CONFIG_S: u32 = 11;
pub const GPIO_PIN26_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN26_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN26_INT_TYPE: u32 = 7;
pub const GPIO_PIN26_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN26_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN26_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN26_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN26_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN26_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN26_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN26_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN26_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN26_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN27_REG: u32 = 1610629344;
pub const GPIO_PIN27_INT_ENA: u32 = 31;
pub const GPIO_PIN27_INT_ENA_V: u32 = 31;
pub const GPIO_PIN27_INT_ENA_S: u32 = 13;
pub const GPIO_PIN27_CONFIG: u32 = 3;
pub const GPIO_PIN27_CONFIG_V: u32 = 3;
pub const GPIO_PIN27_CONFIG_S: u32 = 11;
pub const GPIO_PIN27_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN27_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN27_INT_TYPE: u32 = 7;
pub const GPIO_PIN27_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN27_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN27_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN27_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN27_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN27_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN27_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN27_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN27_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN27_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN28_REG: u32 = 1610629348;
pub const GPIO_PIN28_INT_ENA: u32 = 31;
pub const GPIO_PIN28_INT_ENA_V: u32 = 31;
pub const GPIO_PIN28_INT_ENA_S: u32 = 13;
pub const GPIO_PIN28_CONFIG: u32 = 3;
pub const GPIO_PIN28_CONFIG_V: u32 = 3;
pub const GPIO_PIN28_CONFIG_S: u32 = 11;
pub const GPIO_PIN28_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN28_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN28_INT_TYPE: u32 = 7;
pub const GPIO_PIN28_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN28_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN28_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN28_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN28_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN28_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN28_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN28_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN28_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN28_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN29_REG: u32 = 1610629352;
pub const GPIO_PIN29_INT_ENA: u32 = 31;
pub const GPIO_PIN29_INT_ENA_V: u32 = 31;
pub const GPIO_PIN29_INT_ENA_S: u32 = 13;
pub const GPIO_PIN29_CONFIG: u32 = 3;
pub const GPIO_PIN29_CONFIG_V: u32 = 3;
pub const GPIO_PIN29_CONFIG_S: u32 = 11;
pub const GPIO_PIN29_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN29_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN29_INT_TYPE: u32 = 7;
pub const GPIO_PIN29_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN29_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN29_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN29_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN29_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN29_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN29_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN29_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN29_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN29_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN30_REG: u32 = 1610629356;
pub const GPIO_PIN30_INT_ENA: u32 = 31;
pub const GPIO_PIN30_INT_ENA_V: u32 = 31;
pub const GPIO_PIN30_INT_ENA_S: u32 = 13;
pub const GPIO_PIN30_CONFIG: u32 = 3;
pub const GPIO_PIN30_CONFIG_V: u32 = 3;
pub const GPIO_PIN30_CONFIG_S: u32 = 11;
pub const GPIO_PIN30_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN30_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN30_INT_TYPE: u32 = 7;
pub const GPIO_PIN30_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN30_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN30_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN30_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN30_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN30_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN30_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN30_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN30_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN30_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN31_REG: u32 = 1610629360;
pub const GPIO_PIN31_INT_ENA: u32 = 31;
pub const GPIO_PIN31_INT_ENA_V: u32 = 31;
pub const GPIO_PIN31_INT_ENA_S: u32 = 13;
pub const GPIO_PIN31_CONFIG: u32 = 3;
pub const GPIO_PIN31_CONFIG_V: u32 = 3;
pub const GPIO_PIN31_CONFIG_S: u32 = 11;
pub const GPIO_PIN31_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN31_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN31_INT_TYPE: u32 = 7;
pub const GPIO_PIN31_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN31_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN31_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN31_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN31_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN31_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN31_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN31_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN31_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN31_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN32_REG: u32 = 1610629364;
pub const GPIO_PIN32_INT_ENA: u32 = 31;
pub const GPIO_PIN32_INT_ENA_V: u32 = 31;
pub const GPIO_PIN32_INT_ENA_S: u32 = 13;
pub const GPIO_PIN32_CONFIG: u32 = 3;
pub const GPIO_PIN32_CONFIG_V: u32 = 3;
pub const GPIO_PIN32_CONFIG_S: u32 = 11;
pub const GPIO_PIN32_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN32_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN32_INT_TYPE: u32 = 7;
pub const GPIO_PIN32_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN32_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN32_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN32_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN32_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN32_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN32_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN32_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN32_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN32_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN33_REG: u32 = 1610629368;
pub const GPIO_PIN33_INT_ENA: u32 = 31;
pub const GPIO_PIN33_INT_ENA_V: u32 = 31;
pub const GPIO_PIN33_INT_ENA_S: u32 = 13;
pub const GPIO_PIN33_CONFIG: u32 = 3;
pub const GPIO_PIN33_CONFIG_V: u32 = 3;
pub const GPIO_PIN33_CONFIG_S: u32 = 11;
pub const GPIO_PIN33_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN33_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN33_INT_TYPE: u32 = 7;
pub const GPIO_PIN33_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN33_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN33_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN33_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN33_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN33_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN33_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN33_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN33_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN33_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN34_REG: u32 = 1610629372;
pub const GPIO_PIN34_INT_ENA: u32 = 31;
pub const GPIO_PIN34_INT_ENA_V: u32 = 31;
pub const GPIO_PIN34_INT_ENA_S: u32 = 13;
pub const GPIO_PIN34_CONFIG: u32 = 3;
pub const GPIO_PIN34_CONFIG_V: u32 = 3;
pub const GPIO_PIN34_CONFIG_S: u32 = 11;
pub const GPIO_PIN34_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN34_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN34_INT_TYPE: u32 = 7;
pub const GPIO_PIN34_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN34_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN34_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN34_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN34_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN34_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN34_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN34_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN34_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN34_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN35_REG: u32 = 1610629376;
pub const GPIO_PIN35_INT_ENA: u32 = 31;
pub const GPIO_PIN35_INT_ENA_V: u32 = 31;
pub const GPIO_PIN35_INT_ENA_S: u32 = 13;
pub const GPIO_PIN35_CONFIG: u32 = 3;
pub const GPIO_PIN35_CONFIG_V: u32 = 3;
pub const GPIO_PIN35_CONFIG_S: u32 = 11;
pub const GPIO_PIN35_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN35_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN35_INT_TYPE: u32 = 7;
pub const GPIO_PIN35_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN35_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN35_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN35_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN35_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN35_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN35_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN35_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN35_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN35_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN36_REG: u32 = 1610629380;
pub const GPIO_PIN36_INT_ENA: u32 = 31;
pub const GPIO_PIN36_INT_ENA_V: u32 = 31;
pub const GPIO_PIN36_INT_ENA_S: u32 = 13;
pub const GPIO_PIN36_CONFIG: u32 = 3;
pub const GPIO_PIN36_CONFIG_V: u32 = 3;
pub const GPIO_PIN36_CONFIG_S: u32 = 11;
pub const GPIO_PIN36_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN36_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN36_INT_TYPE: u32 = 7;
pub const GPIO_PIN36_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN36_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN36_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN36_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN36_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN36_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN36_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN36_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN36_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN36_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN37_REG: u32 = 1610629384;
pub const GPIO_PIN37_INT_ENA: u32 = 31;
pub const GPIO_PIN37_INT_ENA_V: u32 = 31;
pub const GPIO_PIN37_INT_ENA_S: u32 = 13;
pub const GPIO_PIN37_CONFIG: u32 = 3;
pub const GPIO_PIN37_CONFIG_V: u32 = 3;
pub const GPIO_PIN37_CONFIG_S: u32 = 11;
pub const GPIO_PIN37_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN37_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN37_INT_TYPE: u32 = 7;
pub const GPIO_PIN37_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN37_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN37_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN37_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN37_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN37_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN37_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN37_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN37_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN37_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN38_REG: u32 = 1610629388;
pub const GPIO_PIN38_INT_ENA: u32 = 31;
pub const GPIO_PIN38_INT_ENA_V: u32 = 31;
pub const GPIO_PIN38_INT_ENA_S: u32 = 13;
pub const GPIO_PIN38_CONFIG: u32 = 3;
pub const GPIO_PIN38_CONFIG_V: u32 = 3;
pub const GPIO_PIN38_CONFIG_S: u32 = 11;
pub const GPIO_PIN38_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN38_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN38_INT_TYPE: u32 = 7;
pub const GPIO_PIN38_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN38_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN38_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN38_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN38_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN38_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN38_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN38_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN38_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN38_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN39_REG: u32 = 1610629392;
pub const GPIO_PIN39_INT_ENA: u32 = 31;
pub const GPIO_PIN39_INT_ENA_V: u32 = 31;
pub const GPIO_PIN39_INT_ENA_S: u32 = 13;
pub const GPIO_PIN39_CONFIG: u32 = 3;
pub const GPIO_PIN39_CONFIG_V: u32 = 3;
pub const GPIO_PIN39_CONFIG_S: u32 = 11;
pub const GPIO_PIN39_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN39_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN39_INT_TYPE: u32 = 7;
pub const GPIO_PIN39_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN39_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN39_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN39_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN39_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN39_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN39_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN39_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN39_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN39_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN40_REG: u32 = 1610629396;
pub const GPIO_PIN40_INT_ENA: u32 = 31;
pub const GPIO_PIN40_INT_ENA_V: u32 = 31;
pub const GPIO_PIN40_INT_ENA_S: u32 = 13;
pub const GPIO_PIN40_CONFIG: u32 = 3;
pub const GPIO_PIN40_CONFIG_V: u32 = 3;
pub const GPIO_PIN40_CONFIG_S: u32 = 11;
pub const GPIO_PIN40_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN40_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN40_INT_TYPE: u32 = 7;
pub const GPIO_PIN40_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN40_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN40_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN40_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN40_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN40_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN40_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN40_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN40_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN40_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN41_REG: u32 = 1610629400;
pub const GPIO_PIN41_INT_ENA: u32 = 31;
pub const GPIO_PIN41_INT_ENA_V: u32 = 31;
pub const GPIO_PIN41_INT_ENA_S: u32 = 13;
pub const GPIO_PIN41_CONFIG: u32 = 3;
pub const GPIO_PIN41_CONFIG_V: u32 = 3;
pub const GPIO_PIN41_CONFIG_S: u32 = 11;
pub const GPIO_PIN41_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN41_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN41_INT_TYPE: u32 = 7;
pub const GPIO_PIN41_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN41_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN41_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN41_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN41_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN41_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN41_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN41_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN41_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN41_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN42_REG: u32 = 1610629404;
pub const GPIO_PIN42_INT_ENA: u32 = 31;
pub const GPIO_PIN42_INT_ENA_V: u32 = 31;
pub const GPIO_PIN42_INT_ENA_S: u32 = 13;
pub const GPIO_PIN42_CONFIG: u32 = 3;
pub const GPIO_PIN42_CONFIG_V: u32 = 3;
pub const GPIO_PIN42_CONFIG_S: u32 = 11;
pub const GPIO_PIN42_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN42_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN42_INT_TYPE: u32 = 7;
pub const GPIO_PIN42_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN42_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN42_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN42_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN42_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN42_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN42_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN42_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN42_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN42_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN43_REG: u32 = 1610629408;
pub const GPIO_PIN43_INT_ENA: u32 = 31;
pub const GPIO_PIN43_INT_ENA_V: u32 = 31;
pub const GPIO_PIN43_INT_ENA_S: u32 = 13;
pub const GPIO_PIN43_CONFIG: u32 = 3;
pub const GPIO_PIN43_CONFIG_V: u32 = 3;
pub const GPIO_PIN43_CONFIG_S: u32 = 11;
pub const GPIO_PIN43_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN43_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN43_INT_TYPE: u32 = 7;
pub const GPIO_PIN43_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN43_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN43_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN43_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN43_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN43_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN43_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN43_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN43_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN43_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN44_REG: u32 = 1610629412;
pub const GPIO_PIN44_INT_ENA: u32 = 31;
pub const GPIO_PIN44_INT_ENA_V: u32 = 31;
pub const GPIO_PIN44_INT_ENA_S: u32 = 13;
pub const GPIO_PIN44_CONFIG: u32 = 3;
pub const GPIO_PIN44_CONFIG_V: u32 = 3;
pub const GPIO_PIN44_CONFIG_S: u32 = 11;
pub const GPIO_PIN44_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN44_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN44_INT_TYPE: u32 = 7;
pub const GPIO_PIN44_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN44_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN44_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN44_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN44_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN44_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN44_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN44_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN44_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN44_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN45_REG: u32 = 1610629416;
pub const GPIO_PIN45_INT_ENA: u32 = 31;
pub const GPIO_PIN45_INT_ENA_V: u32 = 31;
pub const GPIO_PIN45_INT_ENA_S: u32 = 13;
pub const GPIO_PIN45_CONFIG: u32 = 3;
pub const GPIO_PIN45_CONFIG_V: u32 = 3;
pub const GPIO_PIN45_CONFIG_S: u32 = 11;
pub const GPIO_PIN45_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN45_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN45_INT_TYPE: u32 = 7;
pub const GPIO_PIN45_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN45_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN45_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN45_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN45_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN45_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN45_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN45_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN45_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN45_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN46_REG: u32 = 1610629420;
pub const GPIO_PIN46_INT_ENA: u32 = 31;
pub const GPIO_PIN46_INT_ENA_V: u32 = 31;
pub const GPIO_PIN46_INT_ENA_S: u32 = 13;
pub const GPIO_PIN46_CONFIG: u32 = 3;
pub const GPIO_PIN46_CONFIG_V: u32 = 3;
pub const GPIO_PIN46_CONFIG_S: u32 = 11;
pub const GPIO_PIN46_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN46_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN46_INT_TYPE: u32 = 7;
pub const GPIO_PIN46_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN46_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN46_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN46_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN46_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN46_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN46_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN46_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN46_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN46_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN47_REG: u32 = 1610629424;
pub const GPIO_PIN47_INT_ENA: u32 = 31;
pub const GPIO_PIN47_INT_ENA_V: u32 = 31;
pub const GPIO_PIN47_INT_ENA_S: u32 = 13;
pub const GPIO_PIN47_CONFIG: u32 = 3;
pub const GPIO_PIN47_CONFIG_V: u32 = 3;
pub const GPIO_PIN47_CONFIG_S: u32 = 11;
pub const GPIO_PIN47_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN47_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN47_INT_TYPE: u32 = 7;
pub const GPIO_PIN47_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN47_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN47_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN47_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN47_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN47_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN47_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN47_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN47_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN47_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN48_REG: u32 = 1610629428;
pub const GPIO_PIN48_INT_ENA: u32 = 31;
pub const GPIO_PIN48_INT_ENA_V: u32 = 31;
pub const GPIO_PIN48_INT_ENA_S: u32 = 13;
pub const GPIO_PIN48_CONFIG: u32 = 3;
pub const GPIO_PIN48_CONFIG_V: u32 = 3;
pub const GPIO_PIN48_CONFIG_S: u32 = 11;
pub const GPIO_PIN48_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN48_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN48_INT_TYPE: u32 = 7;
pub const GPIO_PIN48_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN48_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN48_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN48_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN48_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN48_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN48_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN48_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN48_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN48_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN49_REG: u32 = 1610629432;
pub const GPIO_PIN49_INT_ENA: u32 = 31;
pub const GPIO_PIN49_INT_ENA_V: u32 = 31;
pub const GPIO_PIN49_INT_ENA_S: u32 = 13;
pub const GPIO_PIN49_CONFIG: u32 = 3;
pub const GPIO_PIN49_CONFIG_V: u32 = 3;
pub const GPIO_PIN49_CONFIG_S: u32 = 11;
pub const GPIO_PIN49_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN49_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN49_INT_TYPE: u32 = 7;
pub const GPIO_PIN49_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN49_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN49_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN49_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN49_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN49_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN49_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN49_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN49_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN49_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN50_REG: u32 = 1610629436;
pub const GPIO_PIN50_INT_ENA: u32 = 31;
pub const GPIO_PIN50_INT_ENA_V: u32 = 31;
pub const GPIO_PIN50_INT_ENA_S: u32 = 13;
pub const GPIO_PIN50_CONFIG: u32 = 3;
pub const GPIO_PIN50_CONFIG_V: u32 = 3;
pub const GPIO_PIN50_CONFIG_S: u32 = 11;
pub const GPIO_PIN50_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN50_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN50_INT_TYPE: u32 = 7;
pub const GPIO_PIN50_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN50_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN50_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN50_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN50_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN50_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN50_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN50_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN50_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN50_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN51_REG: u32 = 1610629440;
pub const GPIO_PIN51_INT_ENA: u32 = 31;
pub const GPIO_PIN51_INT_ENA_V: u32 = 31;
pub const GPIO_PIN51_INT_ENA_S: u32 = 13;
pub const GPIO_PIN51_CONFIG: u32 = 3;
pub const GPIO_PIN51_CONFIG_V: u32 = 3;
pub const GPIO_PIN51_CONFIG_S: u32 = 11;
pub const GPIO_PIN51_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN51_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN51_INT_TYPE: u32 = 7;
pub const GPIO_PIN51_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN51_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN51_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN51_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN51_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN51_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN51_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN51_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN51_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN51_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN52_REG: u32 = 1610629444;
pub const GPIO_PIN52_INT_ENA: u32 = 31;
pub const GPIO_PIN52_INT_ENA_V: u32 = 31;
pub const GPIO_PIN52_INT_ENA_S: u32 = 13;
pub const GPIO_PIN52_CONFIG: u32 = 3;
pub const GPIO_PIN52_CONFIG_V: u32 = 3;
pub const GPIO_PIN52_CONFIG_S: u32 = 11;
pub const GPIO_PIN52_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN52_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN52_INT_TYPE: u32 = 7;
pub const GPIO_PIN52_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN52_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN52_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN52_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN52_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN52_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN52_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN52_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN52_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN52_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_PIN53_REG: u32 = 1610629448;
pub const GPIO_PIN53_INT_ENA: u32 = 31;
pub const GPIO_PIN53_INT_ENA_V: u32 = 31;
pub const GPIO_PIN53_INT_ENA_S: u32 = 13;
pub const GPIO_PIN53_CONFIG: u32 = 3;
pub const GPIO_PIN53_CONFIG_V: u32 = 3;
pub const GPIO_PIN53_CONFIG_S: u32 = 11;
pub const GPIO_PIN53_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN53_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN53_INT_TYPE: u32 = 7;
pub const GPIO_PIN53_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN53_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN53_SYNC1_BYPASS: u32 = 3;
pub const GPIO_PIN53_SYNC1_BYPASS_V: u32 = 3;
pub const GPIO_PIN53_SYNC1_BYPASS_S: u32 = 3;
pub const GPIO_PIN53_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN53_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN53_SYNC2_BYPASS: u32 = 3;
pub const GPIO_PIN53_SYNC2_BYPASS_V: u32 = 3;
pub const GPIO_PIN53_SYNC2_BYPASS_S: u32 = 0;
pub const GPIO_STATUS_NEXT_REG: u32 = 1610629452;
pub const GPIO_STATUS_INTERRUPT_NEXT: u32 = 4294967295;
pub const GPIO_STATUS_INTERRUPT_NEXT_V: u32 = 4294967295;
pub const GPIO_STATUS_INTERRUPT_NEXT_S: u32 = 0;
pub const GPIO_STATUS_NEXT1_REG: u32 = 1610629456;
pub const GPIO_STATUS_INTERRUPT_NEXT1: u32 = 4194303;
pub const GPIO_STATUS_INTERRUPT_NEXT1_V: u32 = 4194303;
pub const GPIO_STATUS_INTERRUPT_NEXT1_S: u32 = 0;
pub const GPIO_FUNC0_IN_SEL_CFG_REG: u32 = 1610629460;
pub const GPIO_SIG0_IN_SEL_V: u32 = 1;
pub const GPIO_SIG0_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC0_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC0_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC0_IN_SEL: u32 = 63;
pub const GPIO_FUNC0_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC0_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC1_IN_SEL_CFG_REG: u32 = 1610629464;
pub const GPIO_SIG1_IN_SEL_V: u32 = 1;
pub const GPIO_SIG1_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC1_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC1_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC1_IN_SEL: u32 = 63;
pub const GPIO_FUNC1_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC1_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC2_IN_SEL_CFG_REG: u32 = 1610629468;
pub const GPIO_SIG2_IN_SEL_V: u32 = 1;
pub const GPIO_SIG2_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC2_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC2_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC2_IN_SEL: u32 = 63;
pub const GPIO_FUNC2_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC2_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC3_IN_SEL_CFG_REG: u32 = 1610629472;
pub const GPIO_SIG3_IN_SEL_V: u32 = 1;
pub const GPIO_SIG3_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC3_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC3_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC3_IN_SEL: u32 = 63;
pub const GPIO_FUNC3_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC3_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC4_IN_SEL_CFG_REG: u32 = 1610629476;
pub const GPIO_SIG4_IN_SEL_V: u32 = 1;
pub const GPIO_SIG4_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC4_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC4_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC4_IN_SEL: u32 = 63;
pub const GPIO_FUNC4_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC4_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC5_IN_SEL_CFG_REG: u32 = 1610629480;
pub const GPIO_SIG5_IN_SEL_V: u32 = 1;
pub const GPIO_SIG5_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC5_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC5_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC5_IN_SEL: u32 = 63;
pub const GPIO_FUNC5_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC5_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC6_IN_SEL_CFG_REG: u32 = 1610629484;
pub const GPIO_SIG6_IN_SEL_V: u32 = 1;
pub const GPIO_SIG6_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC6_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC6_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC6_IN_SEL: u32 = 63;
pub const GPIO_FUNC6_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC6_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC7_IN_SEL_CFG_REG: u32 = 1610629488;
pub const GPIO_SIG7_IN_SEL_V: u32 = 1;
pub const GPIO_SIG7_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC7_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC7_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC7_IN_SEL: u32 = 63;
pub const GPIO_FUNC7_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC7_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC8_IN_SEL_CFG_REG: u32 = 1610629492;
pub const GPIO_SIG8_IN_SEL_V: u32 = 1;
pub const GPIO_SIG8_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC8_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC8_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC8_IN_SEL: u32 = 63;
pub const GPIO_FUNC8_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC8_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC9_IN_SEL_CFG_REG: u32 = 1610629496;
pub const GPIO_SIG9_IN_SEL_V: u32 = 1;
pub const GPIO_SIG9_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC9_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC9_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC9_IN_SEL: u32 = 63;
pub const GPIO_FUNC9_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC9_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC10_IN_SEL_CFG_REG: u32 = 1610629500;
pub const GPIO_SIG10_IN_SEL_V: u32 = 1;
pub const GPIO_SIG10_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC10_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC10_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC10_IN_SEL: u32 = 63;
pub const GPIO_FUNC10_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC10_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC11_IN_SEL_CFG_REG: u32 = 1610629504;
pub const GPIO_SIG11_IN_SEL_V: u32 = 1;
pub const GPIO_SIG11_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC11_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC11_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC11_IN_SEL: u32 = 63;
pub const GPIO_FUNC11_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC11_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC12_IN_SEL_CFG_REG: u32 = 1610629508;
pub const GPIO_SIG12_IN_SEL_V: u32 = 1;
pub const GPIO_SIG12_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC12_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC12_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC12_IN_SEL: u32 = 63;
pub const GPIO_FUNC12_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC12_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC13_IN_SEL_CFG_REG: u32 = 1610629512;
pub const GPIO_SIG13_IN_SEL_V: u32 = 1;
pub const GPIO_SIG13_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC13_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC13_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC13_IN_SEL: u32 = 63;
pub const GPIO_FUNC13_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC13_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC14_IN_SEL_CFG_REG: u32 = 1610629516;
pub const GPIO_SIG14_IN_SEL_V: u32 = 1;
pub const GPIO_SIG14_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC14_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC14_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC14_IN_SEL: u32 = 63;
pub const GPIO_FUNC14_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC14_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC15_IN_SEL_CFG_REG: u32 = 1610629520;
pub const GPIO_SIG15_IN_SEL_V: u32 = 1;
pub const GPIO_SIG15_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC15_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC15_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC15_IN_SEL: u32 = 63;
pub const GPIO_FUNC15_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC15_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC16_IN_SEL_CFG_REG: u32 = 1610629524;
pub const GPIO_SIG16_IN_SEL_V: u32 = 1;
pub const GPIO_SIG16_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC16_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC16_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC16_IN_SEL: u32 = 63;
pub const GPIO_FUNC16_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC16_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC17_IN_SEL_CFG_REG: u32 = 1610629528;
pub const GPIO_SIG17_IN_SEL_V: u32 = 1;
pub const GPIO_SIG17_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC17_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC17_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC17_IN_SEL: u32 = 63;
pub const GPIO_FUNC17_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC17_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC18_IN_SEL_CFG_REG: u32 = 1610629532;
pub const GPIO_SIG18_IN_SEL_V: u32 = 1;
pub const GPIO_SIG18_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC18_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC18_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC18_IN_SEL: u32 = 63;
pub const GPIO_FUNC18_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC18_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC19_IN_SEL_CFG_REG: u32 = 1610629536;
pub const GPIO_SIG19_IN_SEL_V: u32 = 1;
pub const GPIO_SIG19_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC19_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC19_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC19_IN_SEL: u32 = 63;
pub const GPIO_FUNC19_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC19_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC20_IN_SEL_CFG_REG: u32 = 1610629540;
pub const GPIO_SIG20_IN_SEL_V: u32 = 1;
pub const GPIO_SIG20_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC20_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC20_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC20_IN_SEL: u32 = 63;
pub const GPIO_FUNC20_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC20_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC21_IN_SEL_CFG_REG: u32 = 1610629544;
pub const GPIO_SIG21_IN_SEL_V: u32 = 1;
pub const GPIO_SIG21_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC21_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC21_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC21_IN_SEL: u32 = 63;
pub const GPIO_FUNC21_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC21_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC22_IN_SEL_CFG_REG: u32 = 1610629548;
pub const GPIO_SIG22_IN_SEL_V: u32 = 1;
pub const GPIO_SIG22_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC22_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC22_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC22_IN_SEL: u32 = 63;
pub const GPIO_FUNC22_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC22_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC23_IN_SEL_CFG_REG: u32 = 1610629552;
pub const GPIO_SIG23_IN_SEL_V: u32 = 1;
pub const GPIO_SIG23_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC23_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC23_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC23_IN_SEL: u32 = 63;
pub const GPIO_FUNC23_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC23_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC24_IN_SEL_CFG_REG: u32 = 1610629556;
pub const GPIO_SIG24_IN_SEL_V: u32 = 1;
pub const GPIO_SIG24_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC24_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC24_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC24_IN_SEL: u32 = 63;
pub const GPIO_FUNC24_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC24_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC25_IN_SEL_CFG_REG: u32 = 1610629560;
pub const GPIO_SIG25_IN_SEL_V: u32 = 1;
pub const GPIO_SIG25_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC25_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC25_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC25_IN_SEL: u32 = 63;
pub const GPIO_FUNC25_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC25_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC26_IN_SEL_CFG_REG: u32 = 1610629564;
pub const GPIO_SIG26_IN_SEL_V: u32 = 1;
pub const GPIO_SIG26_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC26_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC26_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC26_IN_SEL: u32 = 63;
pub const GPIO_FUNC26_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC26_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC27_IN_SEL_CFG_REG: u32 = 1610629568;
pub const GPIO_SIG27_IN_SEL_V: u32 = 1;
pub const GPIO_SIG27_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC27_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC27_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC27_IN_SEL: u32 = 63;
pub const GPIO_FUNC27_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC27_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC28_IN_SEL_CFG_REG: u32 = 1610629572;
pub const GPIO_SIG28_IN_SEL_V: u32 = 1;
pub const GPIO_SIG28_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC28_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC28_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC28_IN_SEL: u32 = 63;
pub const GPIO_FUNC28_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC28_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC29_IN_SEL_CFG_REG: u32 = 1610629576;
pub const GPIO_SIG29_IN_SEL_V: u32 = 1;
pub const GPIO_SIG29_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC29_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC29_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC29_IN_SEL: u32 = 63;
pub const GPIO_FUNC29_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC29_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC30_IN_SEL_CFG_REG: u32 = 1610629580;
pub const GPIO_SIG30_IN_SEL_V: u32 = 1;
pub const GPIO_SIG30_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC30_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC30_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC30_IN_SEL: u32 = 63;
pub const GPIO_FUNC30_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC30_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC31_IN_SEL_CFG_REG: u32 = 1610629584;
pub const GPIO_SIG31_IN_SEL_V: u32 = 1;
pub const GPIO_SIG31_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC31_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC31_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC31_IN_SEL: u32 = 63;
pub const GPIO_FUNC31_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC31_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC32_IN_SEL_CFG_REG: u32 = 1610629588;
pub const GPIO_SIG32_IN_SEL_V: u32 = 1;
pub const GPIO_SIG32_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC32_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC32_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC32_IN_SEL: u32 = 63;
pub const GPIO_FUNC32_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC32_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC33_IN_SEL_CFG_REG: u32 = 1610629592;
pub const GPIO_SIG33_IN_SEL_V: u32 = 1;
pub const GPIO_SIG33_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC33_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC33_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC33_IN_SEL: u32 = 63;
pub const GPIO_FUNC33_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC33_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC34_IN_SEL_CFG_REG: u32 = 1610629596;
pub const GPIO_SIG34_IN_SEL_V: u32 = 1;
pub const GPIO_SIG34_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC34_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC34_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC34_IN_SEL: u32 = 63;
pub const GPIO_FUNC34_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC34_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC35_IN_SEL_CFG_REG: u32 = 1610629600;
pub const GPIO_SIG35_IN_SEL_V: u32 = 1;
pub const GPIO_SIG35_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC35_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC35_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC35_IN_SEL: u32 = 63;
pub const GPIO_FUNC35_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC35_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC36_IN_SEL_CFG_REG: u32 = 1610629604;
pub const GPIO_SIG36_IN_SEL_V: u32 = 1;
pub const GPIO_SIG36_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC36_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC36_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC36_IN_SEL: u32 = 63;
pub const GPIO_FUNC36_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC36_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC37_IN_SEL_CFG_REG: u32 = 1610629608;
pub const GPIO_SIG37_IN_SEL_V: u32 = 1;
pub const GPIO_SIG37_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC37_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC37_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC37_IN_SEL: u32 = 63;
pub const GPIO_FUNC37_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC37_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC38_IN_SEL_CFG_REG: u32 = 1610629612;
pub const GPIO_SIG38_IN_SEL_V: u32 = 1;
pub const GPIO_SIG38_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC38_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC38_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC38_IN_SEL: u32 = 63;
pub const GPIO_FUNC38_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC38_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC39_IN_SEL_CFG_REG: u32 = 1610629616;
pub const GPIO_SIG39_IN_SEL_V: u32 = 1;
pub const GPIO_SIG39_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC39_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC39_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC39_IN_SEL: u32 = 63;
pub const GPIO_FUNC39_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC39_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC40_IN_SEL_CFG_REG: u32 = 1610629620;
pub const GPIO_SIG40_IN_SEL_V: u32 = 1;
pub const GPIO_SIG40_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC40_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC40_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC40_IN_SEL: u32 = 63;
pub const GPIO_FUNC40_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC40_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC41_IN_SEL_CFG_REG: u32 = 1610629624;
pub const GPIO_SIG41_IN_SEL_V: u32 = 1;
pub const GPIO_SIG41_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC41_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC41_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC41_IN_SEL: u32 = 63;
pub const GPIO_FUNC41_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC41_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC42_IN_SEL_CFG_REG: u32 = 1610629628;
pub const GPIO_SIG42_IN_SEL_V: u32 = 1;
pub const GPIO_SIG42_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC42_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC42_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC42_IN_SEL: u32 = 63;
pub const GPIO_FUNC42_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC42_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC43_IN_SEL_CFG_REG: u32 = 1610629632;
pub const GPIO_SIG43_IN_SEL_V: u32 = 1;
pub const GPIO_SIG43_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC43_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC43_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC43_IN_SEL: u32 = 63;
pub const GPIO_FUNC43_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC43_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC44_IN_SEL_CFG_REG: u32 = 1610629636;
pub const GPIO_SIG44_IN_SEL_V: u32 = 1;
pub const GPIO_SIG44_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC44_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC44_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC44_IN_SEL: u32 = 63;
pub const GPIO_FUNC44_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC44_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC45_IN_SEL_CFG_REG: u32 = 1610629640;
pub const GPIO_SIG45_IN_SEL_V: u32 = 1;
pub const GPIO_SIG45_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC45_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC45_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC45_IN_SEL: u32 = 63;
pub const GPIO_FUNC45_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC45_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC46_IN_SEL_CFG_REG: u32 = 1610629644;
pub const GPIO_SIG46_IN_SEL_V: u32 = 1;
pub const GPIO_SIG46_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC46_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC46_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC46_IN_SEL: u32 = 63;
pub const GPIO_FUNC46_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC46_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC47_IN_SEL_CFG_REG: u32 = 1610629648;
pub const GPIO_SIG47_IN_SEL_V: u32 = 1;
pub const GPIO_SIG47_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC47_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC47_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC47_IN_SEL: u32 = 63;
pub const GPIO_FUNC47_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC47_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC48_IN_SEL_CFG_REG: u32 = 1610629652;
pub const GPIO_SIG48_IN_SEL_V: u32 = 1;
pub const GPIO_SIG48_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC48_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC48_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC48_IN_SEL: u32 = 63;
pub const GPIO_FUNC48_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC48_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC49_IN_SEL_CFG_REG: u32 = 1610629656;
pub const GPIO_SIG49_IN_SEL_V: u32 = 1;
pub const GPIO_SIG49_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC49_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC49_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC49_IN_SEL: u32 = 63;
pub const GPIO_FUNC49_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC49_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC50_IN_SEL_CFG_REG: u32 = 1610629660;
pub const GPIO_SIG50_IN_SEL_V: u32 = 1;
pub const GPIO_SIG50_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC50_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC50_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC50_IN_SEL: u32 = 63;
pub const GPIO_FUNC50_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC50_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC51_IN_SEL_CFG_REG: u32 = 1610629664;
pub const GPIO_SIG51_IN_SEL_V: u32 = 1;
pub const GPIO_SIG51_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC51_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC51_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC51_IN_SEL: u32 = 63;
pub const GPIO_FUNC51_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC51_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC52_IN_SEL_CFG_REG: u32 = 1610629668;
pub const GPIO_SIG52_IN_SEL_V: u32 = 1;
pub const GPIO_SIG52_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC52_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC52_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC52_IN_SEL: u32 = 63;
pub const GPIO_FUNC52_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC52_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC53_IN_SEL_CFG_REG: u32 = 1610629672;
pub const GPIO_SIG53_IN_SEL_V: u32 = 1;
pub const GPIO_SIG53_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC53_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC53_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC53_IN_SEL: u32 = 63;
pub const GPIO_FUNC53_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC53_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC54_IN_SEL_CFG_REG: u32 = 1610629676;
pub const GPIO_SIG54_IN_SEL_V: u32 = 1;
pub const GPIO_SIG54_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC54_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC54_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC54_IN_SEL: u32 = 63;
pub const GPIO_FUNC54_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC54_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC55_IN_SEL_CFG_REG: u32 = 1610629680;
pub const GPIO_SIG55_IN_SEL_V: u32 = 1;
pub const GPIO_SIG55_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC55_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC55_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC55_IN_SEL: u32 = 63;
pub const GPIO_FUNC55_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC55_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC56_IN_SEL_CFG_REG: u32 = 1610629684;
pub const GPIO_SIG56_IN_SEL_V: u32 = 1;
pub const GPIO_SIG56_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC56_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC56_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC56_IN_SEL: u32 = 63;
pub const GPIO_FUNC56_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC56_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC57_IN_SEL_CFG_REG: u32 = 1610629688;
pub const GPIO_SIG57_IN_SEL_V: u32 = 1;
pub const GPIO_SIG57_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC57_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC57_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC57_IN_SEL: u32 = 63;
pub const GPIO_FUNC57_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC57_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC58_IN_SEL_CFG_REG: u32 = 1610629692;
pub const GPIO_SIG58_IN_SEL_V: u32 = 1;
pub const GPIO_SIG58_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC58_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC58_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC58_IN_SEL: u32 = 63;
pub const GPIO_FUNC58_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC58_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC59_IN_SEL_CFG_REG: u32 = 1610629696;
pub const GPIO_SIG59_IN_SEL_V: u32 = 1;
pub const GPIO_SIG59_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC59_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC59_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC59_IN_SEL: u32 = 63;
pub const GPIO_FUNC59_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC59_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC60_IN_SEL_CFG_REG: u32 = 1610629700;
pub const GPIO_SIG60_IN_SEL_V: u32 = 1;
pub const GPIO_SIG60_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC60_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC60_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC60_IN_SEL: u32 = 63;
pub const GPIO_FUNC60_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC60_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC61_IN_SEL_CFG_REG: u32 = 1610629704;
pub const GPIO_SIG61_IN_SEL_V: u32 = 1;
pub const GPIO_SIG61_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC61_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC61_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC61_IN_SEL: u32 = 63;
pub const GPIO_FUNC61_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC61_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC62_IN_SEL_CFG_REG: u32 = 1610629708;
pub const GPIO_SIG62_IN_SEL_V: u32 = 1;
pub const GPIO_SIG62_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC62_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC62_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC62_IN_SEL: u32 = 63;
pub const GPIO_FUNC62_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC62_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC63_IN_SEL_CFG_REG: u32 = 1610629712;
pub const GPIO_SIG63_IN_SEL_V: u32 = 1;
pub const GPIO_SIG63_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC63_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC63_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC63_IN_SEL: u32 = 63;
pub const GPIO_FUNC63_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC63_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC64_IN_SEL_CFG_REG: u32 = 1610629716;
pub const GPIO_SIG64_IN_SEL_V: u32 = 1;
pub const GPIO_SIG64_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC64_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC64_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC64_IN_SEL: u32 = 63;
pub const GPIO_FUNC64_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC64_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC65_IN_SEL_CFG_REG: u32 = 1610629720;
pub const GPIO_SIG65_IN_SEL_V: u32 = 1;
pub const GPIO_SIG65_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC65_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC65_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC65_IN_SEL: u32 = 63;
pub const GPIO_FUNC65_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC65_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC66_IN_SEL_CFG_REG: u32 = 1610629724;
pub const GPIO_SIG66_IN_SEL_V: u32 = 1;
pub const GPIO_SIG66_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC66_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC66_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC66_IN_SEL: u32 = 63;
pub const GPIO_FUNC66_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC66_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC67_IN_SEL_CFG_REG: u32 = 1610629728;
pub const GPIO_SIG67_IN_SEL_V: u32 = 1;
pub const GPIO_SIG67_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC67_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC67_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC67_IN_SEL: u32 = 63;
pub const GPIO_FUNC67_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC67_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC68_IN_SEL_CFG_REG: u32 = 1610629732;
pub const GPIO_SIG68_IN_SEL_V: u32 = 1;
pub const GPIO_SIG68_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC68_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC68_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC68_IN_SEL: u32 = 63;
pub const GPIO_FUNC68_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC68_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC69_IN_SEL_CFG_REG: u32 = 1610629736;
pub const GPIO_SIG69_IN_SEL_V: u32 = 1;
pub const GPIO_SIG69_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC69_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC69_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC69_IN_SEL: u32 = 63;
pub const GPIO_FUNC69_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC69_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC70_IN_SEL_CFG_REG: u32 = 1610629740;
pub const GPIO_SIG70_IN_SEL_V: u32 = 1;
pub const GPIO_SIG70_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC70_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC70_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC70_IN_SEL: u32 = 63;
pub const GPIO_FUNC70_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC70_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC71_IN_SEL_CFG_REG: u32 = 1610629744;
pub const GPIO_SIG71_IN_SEL_V: u32 = 1;
pub const GPIO_SIG71_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC71_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC71_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC71_IN_SEL: u32 = 63;
pub const GPIO_FUNC71_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC71_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC72_IN_SEL_CFG_REG: u32 = 1610629748;
pub const GPIO_SIG72_IN_SEL_V: u32 = 1;
pub const GPIO_SIG72_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC72_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC72_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC72_IN_SEL: u32 = 63;
pub const GPIO_FUNC72_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC72_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC73_IN_SEL_CFG_REG: u32 = 1610629752;
pub const GPIO_SIG73_IN_SEL_V: u32 = 1;
pub const GPIO_SIG73_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC73_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC73_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC73_IN_SEL: u32 = 63;
pub const GPIO_FUNC73_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC73_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC74_IN_SEL_CFG_REG: u32 = 1610629756;
pub const GPIO_SIG74_IN_SEL_V: u32 = 1;
pub const GPIO_SIG74_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC74_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC74_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC74_IN_SEL: u32 = 63;
pub const GPIO_FUNC74_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC74_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC75_IN_SEL_CFG_REG: u32 = 1610629760;
pub const GPIO_SIG75_IN_SEL_V: u32 = 1;
pub const GPIO_SIG75_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC75_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC75_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC75_IN_SEL: u32 = 63;
pub const GPIO_FUNC75_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC75_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC76_IN_SEL_CFG_REG: u32 = 1610629764;
pub const GPIO_SIG76_IN_SEL_V: u32 = 1;
pub const GPIO_SIG76_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC76_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC76_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC76_IN_SEL: u32 = 63;
pub const GPIO_FUNC76_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC76_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC77_IN_SEL_CFG_REG: u32 = 1610629768;
pub const GPIO_SIG77_IN_SEL_V: u32 = 1;
pub const GPIO_SIG77_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC77_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC77_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC77_IN_SEL: u32 = 63;
pub const GPIO_FUNC77_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC77_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC78_IN_SEL_CFG_REG: u32 = 1610629772;
pub const GPIO_SIG78_IN_SEL_V: u32 = 1;
pub const GPIO_SIG78_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC78_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC78_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC78_IN_SEL: u32 = 63;
pub const GPIO_FUNC78_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC78_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC79_IN_SEL_CFG_REG: u32 = 1610629776;
pub const GPIO_SIG79_IN_SEL_V: u32 = 1;
pub const GPIO_SIG79_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC79_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC79_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC79_IN_SEL: u32 = 63;
pub const GPIO_FUNC79_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC79_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC80_IN_SEL_CFG_REG: u32 = 1610629780;
pub const GPIO_SIG80_IN_SEL_V: u32 = 1;
pub const GPIO_SIG80_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC80_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC80_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC80_IN_SEL: u32 = 63;
pub const GPIO_FUNC80_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC80_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC81_IN_SEL_CFG_REG: u32 = 1610629784;
pub const GPIO_SIG81_IN_SEL_V: u32 = 1;
pub const GPIO_SIG81_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC81_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC81_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC81_IN_SEL: u32 = 63;
pub const GPIO_FUNC81_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC81_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC82_IN_SEL_CFG_REG: u32 = 1610629788;
pub const GPIO_SIG82_IN_SEL_V: u32 = 1;
pub const GPIO_SIG82_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC82_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC82_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC82_IN_SEL: u32 = 63;
pub const GPIO_FUNC82_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC82_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC83_IN_SEL_CFG_REG: u32 = 1610629792;
pub const GPIO_SIG83_IN_SEL_V: u32 = 1;
pub const GPIO_SIG83_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC83_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC83_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC83_IN_SEL: u32 = 63;
pub const GPIO_FUNC83_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC83_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC84_IN_SEL_CFG_REG: u32 = 1610629796;
pub const GPIO_SIG84_IN_SEL_V: u32 = 1;
pub const GPIO_SIG84_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC84_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC84_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC84_IN_SEL: u32 = 63;
pub const GPIO_FUNC84_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC84_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC85_IN_SEL_CFG_REG: u32 = 1610629800;
pub const GPIO_SIG85_IN_SEL_V: u32 = 1;
pub const GPIO_SIG85_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC85_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC85_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC85_IN_SEL: u32 = 63;
pub const GPIO_FUNC85_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC85_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC86_IN_SEL_CFG_REG: u32 = 1610629804;
pub const GPIO_SIG86_IN_SEL_V: u32 = 1;
pub const GPIO_SIG86_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC86_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC86_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC86_IN_SEL: u32 = 63;
pub const GPIO_FUNC86_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC86_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC87_IN_SEL_CFG_REG: u32 = 1610629808;
pub const GPIO_SIG87_IN_SEL_V: u32 = 1;
pub const GPIO_SIG87_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC87_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC87_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC87_IN_SEL: u32 = 63;
pub const GPIO_FUNC87_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC87_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC88_IN_SEL_CFG_REG: u32 = 1610629812;
pub const GPIO_SIG88_IN_SEL_V: u32 = 1;
pub const GPIO_SIG88_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC88_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC88_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC88_IN_SEL: u32 = 63;
pub const GPIO_FUNC88_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC88_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC89_IN_SEL_CFG_REG: u32 = 1610629816;
pub const GPIO_SIG89_IN_SEL_V: u32 = 1;
pub const GPIO_SIG89_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC89_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC89_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC89_IN_SEL: u32 = 63;
pub const GPIO_FUNC89_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC89_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC90_IN_SEL_CFG_REG: u32 = 1610629820;
pub const GPIO_SIG90_IN_SEL_V: u32 = 1;
pub const GPIO_SIG90_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC90_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC90_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC90_IN_SEL: u32 = 63;
pub const GPIO_FUNC90_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC90_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC91_IN_SEL_CFG_REG: u32 = 1610629824;
pub const GPIO_SIG91_IN_SEL_V: u32 = 1;
pub const GPIO_SIG91_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC91_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC91_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC91_IN_SEL: u32 = 63;
pub const GPIO_FUNC91_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC91_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC92_IN_SEL_CFG_REG: u32 = 1610629828;
pub const GPIO_SIG92_IN_SEL_V: u32 = 1;
pub const GPIO_SIG92_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC92_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC92_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC92_IN_SEL: u32 = 63;
pub const GPIO_FUNC92_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC92_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC93_IN_SEL_CFG_REG: u32 = 1610629832;
pub const GPIO_SIG93_IN_SEL_V: u32 = 1;
pub const GPIO_SIG93_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC93_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC93_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC93_IN_SEL: u32 = 63;
pub const GPIO_FUNC93_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC93_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC94_IN_SEL_CFG_REG: u32 = 1610629836;
pub const GPIO_SIG94_IN_SEL_V: u32 = 1;
pub const GPIO_SIG94_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC94_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC94_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC94_IN_SEL: u32 = 63;
pub const GPIO_FUNC94_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC94_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC95_IN_SEL_CFG_REG: u32 = 1610629840;
pub const GPIO_SIG95_IN_SEL_V: u32 = 1;
pub const GPIO_SIG95_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC95_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC95_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC95_IN_SEL: u32 = 63;
pub const GPIO_FUNC95_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC95_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC96_IN_SEL_CFG_REG: u32 = 1610629844;
pub const GPIO_SIG96_IN_SEL_V: u32 = 1;
pub const GPIO_SIG96_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC96_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC96_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC96_IN_SEL: u32 = 63;
pub const GPIO_FUNC96_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC96_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC97_IN_SEL_CFG_REG: u32 = 1610629848;
pub const GPIO_SIG97_IN_SEL_V: u32 = 1;
pub const GPIO_SIG97_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC97_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC97_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC97_IN_SEL: u32 = 63;
pub const GPIO_FUNC97_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC97_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC98_IN_SEL_CFG_REG: u32 = 1610629852;
pub const GPIO_SIG98_IN_SEL_V: u32 = 1;
pub const GPIO_SIG98_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC98_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC98_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC98_IN_SEL: u32 = 63;
pub const GPIO_FUNC98_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC98_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC99_IN_SEL_CFG_REG: u32 = 1610629856;
pub const GPIO_SIG99_IN_SEL_V: u32 = 1;
pub const GPIO_SIG99_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC99_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC99_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC99_IN_SEL: u32 = 63;
pub const GPIO_FUNC99_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC99_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC100_IN_SEL_CFG_REG: u32 = 1610629860;
pub const GPIO_SIG100_IN_SEL_V: u32 = 1;
pub const GPIO_SIG100_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC100_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC100_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC100_IN_SEL: u32 = 63;
pub const GPIO_FUNC100_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC100_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC101_IN_SEL_CFG_REG: u32 = 1610629864;
pub const GPIO_SIG101_IN_SEL_V: u32 = 1;
pub const GPIO_SIG101_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC101_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC101_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC101_IN_SEL: u32 = 63;
pub const GPIO_FUNC101_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC101_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC102_IN_SEL_CFG_REG: u32 = 1610629868;
pub const GPIO_SIG102_IN_SEL_V: u32 = 1;
pub const GPIO_SIG102_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC102_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC102_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC102_IN_SEL: u32 = 63;
pub const GPIO_FUNC102_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC102_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC103_IN_SEL_CFG_REG: u32 = 1610629872;
pub const GPIO_SIG103_IN_SEL_V: u32 = 1;
pub const GPIO_SIG103_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC103_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC103_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC103_IN_SEL: u32 = 63;
pub const GPIO_FUNC103_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC103_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC104_IN_SEL_CFG_REG: u32 = 1610629876;
pub const GPIO_SIG104_IN_SEL_V: u32 = 1;
pub const GPIO_SIG104_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC104_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC104_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC104_IN_SEL: u32 = 63;
pub const GPIO_FUNC104_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC104_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC105_IN_SEL_CFG_REG: u32 = 1610629880;
pub const GPIO_SIG105_IN_SEL_V: u32 = 1;
pub const GPIO_SIG105_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC105_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC105_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC105_IN_SEL: u32 = 63;
pub const GPIO_FUNC105_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC105_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC106_IN_SEL_CFG_REG: u32 = 1610629884;
pub const GPIO_SIG106_IN_SEL_V: u32 = 1;
pub const GPIO_SIG106_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC106_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC106_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC106_IN_SEL: u32 = 63;
pub const GPIO_FUNC106_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC106_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC107_IN_SEL_CFG_REG: u32 = 1610629888;
pub const GPIO_SIG107_IN_SEL_V: u32 = 1;
pub const GPIO_SIG107_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC107_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC107_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC107_IN_SEL: u32 = 63;
pub const GPIO_FUNC107_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC107_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC108_IN_SEL_CFG_REG: u32 = 1610629892;
pub const GPIO_SIG108_IN_SEL_V: u32 = 1;
pub const GPIO_SIG108_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC108_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC108_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC108_IN_SEL: u32 = 63;
pub const GPIO_FUNC108_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC108_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC109_IN_SEL_CFG_REG: u32 = 1610629896;
pub const GPIO_SIG109_IN_SEL_V: u32 = 1;
pub const GPIO_SIG109_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC109_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC109_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC109_IN_SEL: u32 = 63;
pub const GPIO_FUNC109_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC109_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC110_IN_SEL_CFG_REG: u32 = 1610629900;
pub const GPIO_SIG110_IN_SEL_V: u32 = 1;
pub const GPIO_SIG110_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC110_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC110_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC110_IN_SEL: u32 = 63;
pub const GPIO_FUNC110_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC110_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC111_IN_SEL_CFG_REG: u32 = 1610629904;
pub const GPIO_SIG111_IN_SEL_V: u32 = 1;
pub const GPIO_SIG111_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC111_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC111_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC111_IN_SEL: u32 = 63;
pub const GPIO_FUNC111_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC111_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC112_IN_SEL_CFG_REG: u32 = 1610629908;
pub const GPIO_SIG112_IN_SEL_V: u32 = 1;
pub const GPIO_SIG112_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC112_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC112_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC112_IN_SEL: u32 = 63;
pub const GPIO_FUNC112_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC112_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC113_IN_SEL_CFG_REG: u32 = 1610629912;
pub const GPIO_SIG113_IN_SEL_V: u32 = 1;
pub const GPIO_SIG113_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC113_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC113_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC113_IN_SEL: u32 = 63;
pub const GPIO_FUNC113_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC113_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC114_IN_SEL_CFG_REG: u32 = 1610629916;
pub const GPIO_SIG114_IN_SEL_V: u32 = 1;
pub const GPIO_SIG114_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC114_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC114_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC114_IN_SEL: u32 = 63;
pub const GPIO_FUNC114_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC114_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC115_IN_SEL_CFG_REG: u32 = 1610629920;
pub const GPIO_SIG115_IN_SEL_V: u32 = 1;
pub const GPIO_SIG115_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC115_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC115_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC115_IN_SEL: u32 = 63;
pub const GPIO_FUNC115_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC115_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC116_IN_SEL_CFG_REG: u32 = 1610629924;
pub const GPIO_SIG116_IN_SEL_V: u32 = 1;
pub const GPIO_SIG116_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC116_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC116_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC116_IN_SEL: u32 = 63;
pub const GPIO_FUNC116_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC116_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC117_IN_SEL_CFG_REG: u32 = 1610629928;
pub const GPIO_SIG117_IN_SEL_V: u32 = 1;
pub const GPIO_SIG117_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC117_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC117_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC117_IN_SEL: u32 = 63;
pub const GPIO_FUNC117_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC117_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC118_IN_SEL_CFG_REG: u32 = 1610629932;
pub const GPIO_SIG118_IN_SEL_V: u32 = 1;
pub const GPIO_SIG118_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC118_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC118_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC118_IN_SEL: u32 = 63;
pub const GPIO_FUNC118_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC118_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC119_IN_SEL_CFG_REG: u32 = 1610629936;
pub const GPIO_SIG119_IN_SEL_V: u32 = 1;
pub const GPIO_SIG119_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC119_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC119_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC119_IN_SEL: u32 = 63;
pub const GPIO_FUNC119_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC119_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC120_IN_SEL_CFG_REG: u32 = 1610629940;
pub const GPIO_SIG120_IN_SEL_V: u32 = 1;
pub const GPIO_SIG120_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC120_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC120_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC120_IN_SEL: u32 = 63;
pub const GPIO_FUNC120_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC120_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC121_IN_SEL_CFG_REG: u32 = 1610629944;
pub const GPIO_SIG121_IN_SEL_V: u32 = 1;
pub const GPIO_SIG121_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC121_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC121_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC121_IN_SEL: u32 = 63;
pub const GPIO_FUNC121_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC121_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC122_IN_SEL_CFG_REG: u32 = 1610629948;
pub const GPIO_SIG122_IN_SEL_V: u32 = 1;
pub const GPIO_SIG122_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC122_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC122_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC122_IN_SEL: u32 = 63;
pub const GPIO_FUNC122_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC122_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC123_IN_SEL_CFG_REG: u32 = 1610629952;
pub const GPIO_SIG123_IN_SEL_V: u32 = 1;
pub const GPIO_SIG123_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC123_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC123_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC123_IN_SEL: u32 = 63;
pub const GPIO_FUNC123_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC123_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC124_IN_SEL_CFG_REG: u32 = 1610629956;
pub const GPIO_SIG124_IN_SEL_V: u32 = 1;
pub const GPIO_SIG124_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC124_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC124_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC124_IN_SEL: u32 = 63;
pub const GPIO_FUNC124_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC124_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC125_IN_SEL_CFG_REG: u32 = 1610629960;
pub const GPIO_SIG125_IN_SEL_V: u32 = 1;
pub const GPIO_SIG125_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC125_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC125_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC125_IN_SEL: u32 = 63;
pub const GPIO_FUNC125_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC125_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC126_IN_SEL_CFG_REG: u32 = 1610629964;
pub const GPIO_SIG126_IN_SEL_V: u32 = 1;
pub const GPIO_SIG126_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC126_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC126_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC126_IN_SEL: u32 = 63;
pub const GPIO_FUNC126_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC126_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC127_IN_SEL_CFG_REG: u32 = 1610629968;
pub const GPIO_SIG127_IN_SEL_V: u32 = 1;
pub const GPIO_SIG127_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC127_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC127_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC127_IN_SEL: u32 = 63;
pub const GPIO_FUNC127_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC127_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC128_IN_SEL_CFG_REG: u32 = 1610629972;
pub const GPIO_SIG128_IN_SEL_V: u32 = 1;
pub const GPIO_SIG128_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC128_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC128_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC128_IN_SEL: u32 = 63;
pub const GPIO_FUNC128_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC128_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC129_IN_SEL_CFG_REG: u32 = 1610629976;
pub const GPIO_SIG129_IN_SEL_V: u32 = 1;
pub const GPIO_SIG129_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC129_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC129_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC129_IN_SEL: u32 = 63;
pub const GPIO_FUNC129_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC129_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC130_IN_SEL_CFG_REG: u32 = 1610629980;
pub const GPIO_SIG130_IN_SEL_V: u32 = 1;
pub const GPIO_SIG130_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC130_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC130_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC130_IN_SEL: u32 = 63;
pub const GPIO_FUNC130_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC130_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC131_IN_SEL_CFG_REG: u32 = 1610629984;
pub const GPIO_SIG131_IN_SEL_V: u32 = 1;
pub const GPIO_SIG131_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC131_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC131_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC131_IN_SEL: u32 = 63;
pub const GPIO_FUNC131_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC131_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC132_IN_SEL_CFG_REG: u32 = 1610629988;
pub const GPIO_SIG132_IN_SEL_V: u32 = 1;
pub const GPIO_SIG132_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC132_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC132_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC132_IN_SEL: u32 = 63;
pub const GPIO_FUNC132_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC132_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC133_IN_SEL_CFG_REG: u32 = 1610629992;
pub const GPIO_SIG133_IN_SEL_V: u32 = 1;
pub const GPIO_SIG133_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC133_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC133_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC133_IN_SEL: u32 = 63;
pub const GPIO_FUNC133_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC133_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC134_IN_SEL_CFG_REG: u32 = 1610629996;
pub const GPIO_SIG134_IN_SEL_V: u32 = 1;
pub const GPIO_SIG134_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC134_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC134_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC134_IN_SEL: u32 = 63;
pub const GPIO_FUNC134_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC134_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC135_IN_SEL_CFG_REG: u32 = 1610630000;
pub const GPIO_SIG135_IN_SEL_V: u32 = 1;
pub const GPIO_SIG135_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC135_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC135_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC135_IN_SEL: u32 = 63;
pub const GPIO_FUNC135_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC135_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC136_IN_SEL_CFG_REG: u32 = 1610630004;
pub const GPIO_SIG136_IN_SEL_V: u32 = 1;
pub const GPIO_SIG136_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC136_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC136_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC136_IN_SEL: u32 = 63;
pub const GPIO_FUNC136_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC136_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC137_IN_SEL_CFG_REG: u32 = 1610630008;
pub const GPIO_SIG137_IN_SEL_V: u32 = 1;
pub const GPIO_SIG137_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC137_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC137_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC137_IN_SEL: u32 = 63;
pub const GPIO_FUNC137_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC137_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC138_IN_SEL_CFG_REG: u32 = 1610630012;
pub const GPIO_SIG138_IN_SEL_V: u32 = 1;
pub const GPIO_SIG138_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC138_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC138_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC138_IN_SEL: u32 = 63;
pub const GPIO_FUNC138_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC138_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC139_IN_SEL_CFG_REG: u32 = 1610630016;
pub const GPIO_SIG139_IN_SEL_V: u32 = 1;
pub const GPIO_SIG139_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC139_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC139_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC139_IN_SEL: u32 = 63;
pub const GPIO_FUNC139_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC139_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC140_IN_SEL_CFG_REG: u32 = 1610630020;
pub const GPIO_SIG140_IN_SEL_V: u32 = 1;
pub const GPIO_SIG140_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC140_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC140_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC140_IN_SEL: u32 = 63;
pub const GPIO_FUNC140_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC140_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC141_IN_SEL_CFG_REG: u32 = 1610630024;
pub const GPIO_SIG141_IN_SEL_V: u32 = 1;
pub const GPIO_SIG141_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC141_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC141_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC141_IN_SEL: u32 = 63;
pub const GPIO_FUNC141_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC141_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC142_IN_SEL_CFG_REG: u32 = 1610630028;
pub const GPIO_SIG142_IN_SEL_V: u32 = 1;
pub const GPIO_SIG142_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC142_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC142_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC142_IN_SEL: u32 = 63;
pub const GPIO_FUNC142_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC142_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC143_IN_SEL_CFG_REG: u32 = 1610630032;
pub const GPIO_SIG143_IN_SEL_V: u32 = 1;
pub const GPIO_SIG143_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC143_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC143_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC143_IN_SEL: u32 = 63;
pub const GPIO_FUNC143_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC143_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC144_IN_SEL_CFG_REG: u32 = 1610630036;
pub const GPIO_SIG144_IN_SEL_V: u32 = 1;
pub const GPIO_SIG144_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC144_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC144_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC144_IN_SEL: u32 = 63;
pub const GPIO_FUNC144_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC144_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC145_IN_SEL_CFG_REG: u32 = 1610630040;
pub const GPIO_SIG145_IN_SEL_V: u32 = 1;
pub const GPIO_SIG145_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC145_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC145_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC145_IN_SEL: u32 = 63;
pub const GPIO_FUNC145_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC145_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC146_IN_SEL_CFG_REG: u32 = 1610630044;
pub const GPIO_SIG146_IN_SEL_V: u32 = 1;
pub const GPIO_SIG146_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC146_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC146_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC146_IN_SEL: u32 = 63;
pub const GPIO_FUNC146_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC146_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC147_IN_SEL_CFG_REG: u32 = 1610630048;
pub const GPIO_SIG147_IN_SEL_V: u32 = 1;
pub const GPIO_SIG147_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC147_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC147_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC147_IN_SEL: u32 = 63;
pub const GPIO_FUNC147_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC147_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC148_IN_SEL_CFG_REG: u32 = 1610630052;
pub const GPIO_SIG148_IN_SEL_V: u32 = 1;
pub const GPIO_SIG148_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC148_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC148_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC148_IN_SEL: u32 = 63;
pub const GPIO_FUNC148_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC148_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC149_IN_SEL_CFG_REG: u32 = 1610630056;
pub const GPIO_SIG149_IN_SEL_V: u32 = 1;
pub const GPIO_SIG149_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC149_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC149_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC149_IN_SEL: u32 = 63;
pub const GPIO_FUNC149_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC149_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC150_IN_SEL_CFG_REG: u32 = 1610630060;
pub const GPIO_SIG150_IN_SEL_V: u32 = 1;
pub const GPIO_SIG150_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC150_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC150_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC150_IN_SEL: u32 = 63;
pub const GPIO_FUNC150_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC150_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC151_IN_SEL_CFG_REG: u32 = 1610630064;
pub const GPIO_SIG151_IN_SEL_V: u32 = 1;
pub const GPIO_SIG151_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC151_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC151_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC151_IN_SEL: u32 = 63;
pub const GPIO_FUNC151_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC151_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC152_IN_SEL_CFG_REG: u32 = 1610630068;
pub const GPIO_SIG152_IN_SEL_V: u32 = 1;
pub const GPIO_SIG152_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC152_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC152_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC152_IN_SEL: u32 = 63;
pub const GPIO_FUNC152_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC152_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC153_IN_SEL_CFG_REG: u32 = 1610630072;
pub const GPIO_SIG153_IN_SEL_V: u32 = 1;
pub const GPIO_SIG153_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC153_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC153_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC153_IN_SEL: u32 = 63;
pub const GPIO_FUNC153_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC153_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC154_IN_SEL_CFG_REG: u32 = 1610630076;
pub const GPIO_SIG154_IN_SEL_V: u32 = 1;
pub const GPIO_SIG154_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC154_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC154_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC154_IN_SEL: u32 = 63;
pub const GPIO_FUNC154_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC154_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC155_IN_SEL_CFG_REG: u32 = 1610630080;
pub const GPIO_SIG155_IN_SEL_V: u32 = 1;
pub const GPIO_SIG155_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC155_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC155_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC155_IN_SEL: u32 = 63;
pub const GPIO_FUNC155_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC155_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC156_IN_SEL_CFG_REG: u32 = 1610630084;
pub const GPIO_SIG156_IN_SEL_V: u32 = 1;
pub const GPIO_SIG156_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC156_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC156_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC156_IN_SEL: u32 = 63;
pub const GPIO_FUNC156_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC156_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC157_IN_SEL_CFG_REG: u32 = 1610630088;
pub const GPIO_SIG157_IN_SEL_V: u32 = 1;
pub const GPIO_SIG157_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC157_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC157_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC157_IN_SEL: u32 = 63;
pub const GPIO_FUNC157_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC157_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC158_IN_SEL_CFG_REG: u32 = 1610630092;
pub const GPIO_SIG158_IN_SEL_V: u32 = 1;
pub const GPIO_SIG158_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC158_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC158_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC158_IN_SEL: u32 = 63;
pub const GPIO_FUNC158_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC158_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC159_IN_SEL_CFG_REG: u32 = 1610630096;
pub const GPIO_SIG159_IN_SEL_V: u32 = 1;
pub const GPIO_SIG159_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC159_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC159_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC159_IN_SEL: u32 = 63;
pub const GPIO_FUNC159_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC159_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC160_IN_SEL_CFG_REG: u32 = 1610630100;
pub const GPIO_SIG160_IN_SEL_V: u32 = 1;
pub const GPIO_SIG160_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC160_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC160_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC160_IN_SEL: u32 = 63;
pub const GPIO_FUNC160_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC160_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC161_IN_SEL_CFG_REG: u32 = 1610630104;
pub const GPIO_SIG161_IN_SEL_V: u32 = 1;
pub const GPIO_SIG161_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC161_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC161_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC161_IN_SEL: u32 = 63;
pub const GPIO_FUNC161_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC161_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC162_IN_SEL_CFG_REG: u32 = 1610630108;
pub const GPIO_SIG162_IN_SEL_V: u32 = 1;
pub const GPIO_SIG162_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC162_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC162_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC162_IN_SEL: u32 = 63;
pub const GPIO_FUNC162_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC162_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC163_IN_SEL_CFG_REG: u32 = 1610630112;
pub const GPIO_SIG163_IN_SEL_V: u32 = 1;
pub const GPIO_SIG163_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC163_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC163_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC163_IN_SEL: u32 = 63;
pub const GPIO_FUNC163_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC163_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC164_IN_SEL_CFG_REG: u32 = 1610630116;
pub const GPIO_SIG164_IN_SEL_V: u32 = 1;
pub const GPIO_SIG164_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC164_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC164_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC164_IN_SEL: u32 = 63;
pub const GPIO_FUNC164_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC164_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC165_IN_SEL_CFG_REG: u32 = 1610630120;
pub const GPIO_SIG165_IN_SEL_V: u32 = 1;
pub const GPIO_SIG165_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC165_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC165_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC165_IN_SEL: u32 = 63;
pub const GPIO_FUNC165_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC165_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC166_IN_SEL_CFG_REG: u32 = 1610630124;
pub const GPIO_SIG166_IN_SEL_V: u32 = 1;
pub const GPIO_SIG166_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC166_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC166_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC166_IN_SEL: u32 = 63;
pub const GPIO_FUNC166_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC166_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC167_IN_SEL_CFG_REG: u32 = 1610630128;
pub const GPIO_SIG167_IN_SEL_V: u32 = 1;
pub const GPIO_SIG167_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC167_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC167_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC167_IN_SEL: u32 = 63;
pub const GPIO_FUNC167_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC167_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC168_IN_SEL_CFG_REG: u32 = 1610630132;
pub const GPIO_SIG168_IN_SEL_V: u32 = 1;
pub const GPIO_SIG168_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC168_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC168_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC168_IN_SEL: u32 = 63;
pub const GPIO_FUNC168_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC168_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC169_IN_SEL_CFG_REG: u32 = 1610630136;
pub const GPIO_SIG169_IN_SEL_V: u32 = 1;
pub const GPIO_SIG169_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC169_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC169_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC169_IN_SEL: u32 = 63;
pub const GPIO_FUNC169_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC169_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC170_IN_SEL_CFG_REG: u32 = 1610630140;
pub const GPIO_SIG170_IN_SEL_V: u32 = 1;
pub const GPIO_SIG170_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC170_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC170_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC170_IN_SEL: u32 = 63;
pub const GPIO_FUNC170_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC170_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC171_IN_SEL_CFG_REG: u32 = 1610630144;
pub const GPIO_SIG171_IN_SEL_V: u32 = 1;
pub const GPIO_SIG171_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC171_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC171_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC171_IN_SEL: u32 = 63;
pub const GPIO_FUNC171_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC171_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC172_IN_SEL_CFG_REG: u32 = 1610630148;
pub const GPIO_SIG172_IN_SEL_V: u32 = 1;
pub const GPIO_SIG172_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC172_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC172_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC172_IN_SEL: u32 = 63;
pub const GPIO_FUNC172_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC172_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC173_IN_SEL_CFG_REG: u32 = 1610630152;
pub const GPIO_SIG173_IN_SEL_V: u32 = 1;
pub const GPIO_SIG173_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC173_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC173_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC173_IN_SEL: u32 = 63;
pub const GPIO_FUNC173_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC173_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC174_IN_SEL_CFG_REG: u32 = 1610630156;
pub const GPIO_SIG174_IN_SEL_V: u32 = 1;
pub const GPIO_SIG174_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC174_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC174_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC174_IN_SEL: u32 = 63;
pub const GPIO_FUNC174_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC174_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC175_IN_SEL_CFG_REG: u32 = 1610630160;
pub const GPIO_SIG175_IN_SEL_V: u32 = 1;
pub const GPIO_SIG175_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC175_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC175_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC175_IN_SEL: u32 = 63;
pub const GPIO_FUNC175_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC175_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC176_IN_SEL_CFG_REG: u32 = 1610630164;
pub const GPIO_SIG176_IN_SEL_V: u32 = 1;
pub const GPIO_SIG176_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC176_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC176_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC176_IN_SEL: u32 = 63;
pub const GPIO_FUNC176_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC176_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC177_IN_SEL_CFG_REG: u32 = 1610630168;
pub const GPIO_SIG177_IN_SEL_V: u32 = 1;
pub const GPIO_SIG177_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC177_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC177_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC177_IN_SEL: u32 = 63;
pub const GPIO_FUNC177_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC177_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC178_IN_SEL_CFG_REG: u32 = 1610630172;
pub const GPIO_SIG178_IN_SEL_V: u32 = 1;
pub const GPIO_SIG178_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC178_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC178_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC178_IN_SEL: u32 = 63;
pub const GPIO_FUNC178_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC178_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC179_IN_SEL_CFG_REG: u32 = 1610630176;
pub const GPIO_SIG179_IN_SEL_V: u32 = 1;
pub const GPIO_SIG179_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC179_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC179_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC179_IN_SEL: u32 = 63;
pub const GPIO_FUNC179_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC179_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC180_IN_SEL_CFG_REG: u32 = 1610630180;
pub const GPIO_SIG180_IN_SEL_V: u32 = 1;
pub const GPIO_SIG180_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC180_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC180_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC180_IN_SEL: u32 = 63;
pub const GPIO_FUNC180_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC180_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC181_IN_SEL_CFG_REG: u32 = 1610630184;
pub const GPIO_SIG181_IN_SEL_V: u32 = 1;
pub const GPIO_SIG181_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC181_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC181_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC181_IN_SEL: u32 = 63;
pub const GPIO_FUNC181_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC181_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC182_IN_SEL_CFG_REG: u32 = 1610630188;
pub const GPIO_SIG182_IN_SEL_V: u32 = 1;
pub const GPIO_SIG182_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC182_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC182_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC182_IN_SEL: u32 = 63;
pub const GPIO_FUNC182_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC182_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC183_IN_SEL_CFG_REG: u32 = 1610630192;
pub const GPIO_SIG183_IN_SEL_V: u32 = 1;
pub const GPIO_SIG183_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC183_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC183_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC183_IN_SEL: u32 = 63;
pub const GPIO_FUNC183_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC183_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC184_IN_SEL_CFG_REG: u32 = 1610630196;
pub const GPIO_SIG184_IN_SEL_V: u32 = 1;
pub const GPIO_SIG184_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC184_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC184_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC184_IN_SEL: u32 = 63;
pub const GPIO_FUNC184_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC184_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC185_IN_SEL_CFG_REG: u32 = 1610630200;
pub const GPIO_SIG185_IN_SEL_V: u32 = 1;
pub const GPIO_SIG185_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC185_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC185_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC185_IN_SEL: u32 = 63;
pub const GPIO_FUNC185_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC185_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC186_IN_SEL_CFG_REG: u32 = 1610630204;
pub const GPIO_SIG186_IN_SEL_V: u32 = 1;
pub const GPIO_SIG186_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC186_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC186_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC186_IN_SEL: u32 = 63;
pub const GPIO_FUNC186_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC186_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC187_IN_SEL_CFG_REG: u32 = 1610630208;
pub const GPIO_SIG187_IN_SEL_V: u32 = 1;
pub const GPIO_SIG187_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC187_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC187_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC187_IN_SEL: u32 = 63;
pub const GPIO_FUNC187_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC187_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC188_IN_SEL_CFG_REG: u32 = 1610630212;
pub const GPIO_SIG188_IN_SEL_V: u32 = 1;
pub const GPIO_SIG188_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC188_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC188_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC188_IN_SEL: u32 = 63;
pub const GPIO_FUNC188_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC188_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC189_IN_SEL_CFG_REG: u32 = 1610630216;
pub const GPIO_SIG189_IN_SEL_V: u32 = 1;
pub const GPIO_SIG189_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC189_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC189_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC189_IN_SEL: u32 = 63;
pub const GPIO_FUNC189_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC189_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC190_IN_SEL_CFG_REG: u32 = 1610630220;
pub const GPIO_SIG190_IN_SEL_V: u32 = 1;
pub const GPIO_SIG190_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC190_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC190_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC190_IN_SEL: u32 = 63;
pub const GPIO_FUNC190_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC190_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC191_IN_SEL_CFG_REG: u32 = 1610630224;
pub const GPIO_SIG191_IN_SEL_V: u32 = 1;
pub const GPIO_SIG191_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC191_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC191_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC191_IN_SEL: u32 = 63;
pub const GPIO_FUNC191_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC191_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC192_IN_SEL_CFG_REG: u32 = 1610630228;
pub const GPIO_SIG192_IN_SEL_V: u32 = 1;
pub const GPIO_SIG192_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC192_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC192_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC192_IN_SEL: u32 = 63;
pub const GPIO_FUNC192_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC192_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC193_IN_SEL_CFG_REG: u32 = 1610630232;
pub const GPIO_SIG193_IN_SEL_V: u32 = 1;
pub const GPIO_SIG193_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC193_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC193_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC193_IN_SEL: u32 = 63;
pub const GPIO_FUNC193_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC193_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC194_IN_SEL_CFG_REG: u32 = 1610630236;
pub const GPIO_SIG194_IN_SEL_V: u32 = 1;
pub const GPIO_SIG194_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC194_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC194_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC194_IN_SEL: u32 = 63;
pub const GPIO_FUNC194_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC194_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC195_IN_SEL_CFG_REG: u32 = 1610630240;
pub const GPIO_SIG195_IN_SEL_V: u32 = 1;
pub const GPIO_SIG195_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC195_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC195_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC195_IN_SEL: u32 = 63;
pub const GPIO_FUNC195_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC195_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC196_IN_SEL_CFG_REG: u32 = 1610630244;
pub const GPIO_SIG196_IN_SEL_V: u32 = 1;
pub const GPIO_SIG196_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC196_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC196_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC196_IN_SEL: u32 = 63;
pub const GPIO_FUNC196_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC196_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC197_IN_SEL_CFG_REG: u32 = 1610630248;
pub const GPIO_SIG197_IN_SEL_V: u32 = 1;
pub const GPIO_SIG197_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC197_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC197_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC197_IN_SEL: u32 = 63;
pub const GPIO_FUNC197_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC197_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC198_IN_SEL_CFG_REG: u32 = 1610630252;
pub const GPIO_SIG198_IN_SEL_V: u32 = 1;
pub const GPIO_SIG198_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC198_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC198_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC198_IN_SEL: u32 = 63;
pub const GPIO_FUNC198_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC198_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC199_IN_SEL_CFG_REG: u32 = 1610630256;
pub const GPIO_SIG199_IN_SEL_V: u32 = 1;
pub const GPIO_SIG199_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC199_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC199_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC199_IN_SEL: u32 = 63;
pub const GPIO_FUNC199_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC199_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC200_IN_SEL_CFG_REG: u32 = 1610630260;
pub const GPIO_SIG200_IN_SEL_V: u32 = 1;
pub const GPIO_SIG200_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC200_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC200_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC200_IN_SEL: u32 = 63;
pub const GPIO_FUNC200_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC200_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC201_IN_SEL_CFG_REG: u32 = 1610630264;
pub const GPIO_SIG201_IN_SEL_V: u32 = 1;
pub const GPIO_SIG201_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC201_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC201_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC201_IN_SEL: u32 = 63;
pub const GPIO_FUNC201_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC201_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC202_IN_SEL_CFG_REG: u32 = 1610630268;
pub const GPIO_SIG202_IN_SEL_V: u32 = 1;
pub const GPIO_SIG202_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC202_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC202_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC202_IN_SEL: u32 = 63;
pub const GPIO_FUNC202_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC202_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC203_IN_SEL_CFG_REG: u32 = 1610630272;
pub const GPIO_SIG203_IN_SEL_V: u32 = 1;
pub const GPIO_SIG203_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC203_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC203_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC203_IN_SEL: u32 = 63;
pub const GPIO_FUNC203_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC203_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC204_IN_SEL_CFG_REG: u32 = 1610630276;
pub const GPIO_SIG204_IN_SEL_V: u32 = 1;
pub const GPIO_SIG204_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC204_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC204_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC204_IN_SEL: u32 = 63;
pub const GPIO_FUNC204_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC204_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC205_IN_SEL_CFG_REG: u32 = 1610630280;
pub const GPIO_SIG205_IN_SEL_V: u32 = 1;
pub const GPIO_SIG205_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC205_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC205_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC205_IN_SEL: u32 = 63;
pub const GPIO_FUNC205_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC205_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC206_IN_SEL_CFG_REG: u32 = 1610630284;
pub const GPIO_SIG206_IN_SEL_V: u32 = 1;
pub const GPIO_SIG206_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC206_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC206_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC206_IN_SEL: u32 = 63;
pub const GPIO_FUNC206_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC206_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC207_IN_SEL_CFG_REG: u32 = 1610630288;
pub const GPIO_SIG207_IN_SEL_V: u32 = 1;
pub const GPIO_SIG207_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC207_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC207_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC207_IN_SEL: u32 = 63;
pub const GPIO_FUNC207_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC207_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC208_IN_SEL_CFG_REG: u32 = 1610630292;
pub const GPIO_SIG208_IN_SEL_V: u32 = 1;
pub const GPIO_SIG208_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC208_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC208_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC208_IN_SEL: u32 = 63;
pub const GPIO_FUNC208_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC208_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC209_IN_SEL_CFG_REG: u32 = 1610630296;
pub const GPIO_SIG209_IN_SEL_V: u32 = 1;
pub const GPIO_SIG209_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC209_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC209_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC209_IN_SEL: u32 = 63;
pub const GPIO_FUNC209_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC209_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC210_IN_SEL_CFG_REG: u32 = 1610630300;
pub const GPIO_SIG210_IN_SEL_V: u32 = 1;
pub const GPIO_SIG210_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC210_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC210_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC210_IN_SEL: u32 = 63;
pub const GPIO_FUNC210_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC210_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC211_IN_SEL_CFG_REG: u32 = 1610630304;
pub const GPIO_SIG211_IN_SEL_V: u32 = 1;
pub const GPIO_SIG211_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC211_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC211_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC211_IN_SEL: u32 = 63;
pub const GPIO_FUNC211_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC211_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC212_IN_SEL_CFG_REG: u32 = 1610630308;
pub const GPIO_SIG212_IN_SEL_V: u32 = 1;
pub const GPIO_SIG212_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC212_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC212_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC212_IN_SEL: u32 = 63;
pub const GPIO_FUNC212_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC212_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC213_IN_SEL_CFG_REG: u32 = 1610630312;
pub const GPIO_SIG213_IN_SEL_V: u32 = 1;
pub const GPIO_SIG213_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC213_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC213_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC213_IN_SEL: u32 = 63;
pub const GPIO_FUNC213_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC213_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC214_IN_SEL_CFG_REG: u32 = 1610630316;
pub const GPIO_SIG214_IN_SEL_V: u32 = 1;
pub const GPIO_SIG214_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC214_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC214_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC214_IN_SEL: u32 = 63;
pub const GPIO_FUNC214_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC214_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC215_IN_SEL_CFG_REG: u32 = 1610630320;
pub const GPIO_SIG215_IN_SEL_V: u32 = 1;
pub const GPIO_SIG215_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC215_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC215_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC215_IN_SEL: u32 = 63;
pub const GPIO_FUNC215_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC215_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC216_IN_SEL_CFG_REG: u32 = 1610630324;
pub const GPIO_SIG216_IN_SEL_V: u32 = 1;
pub const GPIO_SIG216_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC216_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC216_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC216_IN_SEL: u32 = 63;
pub const GPIO_FUNC216_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC216_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC217_IN_SEL_CFG_REG: u32 = 1610630328;
pub const GPIO_SIG217_IN_SEL_V: u32 = 1;
pub const GPIO_SIG217_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC217_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC217_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC217_IN_SEL: u32 = 63;
pub const GPIO_FUNC217_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC217_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC218_IN_SEL_CFG_REG: u32 = 1610630332;
pub const GPIO_SIG218_IN_SEL_V: u32 = 1;
pub const GPIO_SIG218_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC218_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC218_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC218_IN_SEL: u32 = 63;
pub const GPIO_FUNC218_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC218_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC219_IN_SEL_CFG_REG: u32 = 1610630336;
pub const GPIO_SIG219_IN_SEL_V: u32 = 1;
pub const GPIO_SIG219_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC219_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC219_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC219_IN_SEL: u32 = 63;
pub const GPIO_FUNC219_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC219_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC220_IN_SEL_CFG_REG: u32 = 1610630340;
pub const GPIO_SIG220_IN_SEL_V: u32 = 1;
pub const GPIO_SIG220_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC220_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC220_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC220_IN_SEL: u32 = 63;
pub const GPIO_FUNC220_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC220_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC221_IN_SEL_CFG_REG: u32 = 1610630344;
pub const GPIO_SIG221_IN_SEL_V: u32 = 1;
pub const GPIO_SIG221_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC221_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC221_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC221_IN_SEL: u32 = 63;
pub const GPIO_FUNC221_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC221_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC222_IN_SEL_CFG_REG: u32 = 1610630348;
pub const GPIO_SIG222_IN_SEL_V: u32 = 1;
pub const GPIO_SIG222_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC222_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC222_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC222_IN_SEL: u32 = 63;
pub const GPIO_FUNC222_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC222_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC223_IN_SEL_CFG_REG: u32 = 1610630352;
pub const GPIO_SIG223_IN_SEL_V: u32 = 1;
pub const GPIO_SIG223_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC223_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC223_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC223_IN_SEL: u32 = 63;
pub const GPIO_FUNC223_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC223_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC224_IN_SEL_CFG_REG: u32 = 1610630356;
pub const GPIO_SIG224_IN_SEL_V: u32 = 1;
pub const GPIO_SIG224_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC224_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC224_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC224_IN_SEL: u32 = 63;
pub const GPIO_FUNC224_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC224_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC225_IN_SEL_CFG_REG: u32 = 1610630360;
pub const GPIO_SIG225_IN_SEL_V: u32 = 1;
pub const GPIO_SIG225_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC225_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC225_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC225_IN_SEL: u32 = 63;
pub const GPIO_FUNC225_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC225_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC226_IN_SEL_CFG_REG: u32 = 1610630364;
pub const GPIO_SIG226_IN_SEL_V: u32 = 1;
pub const GPIO_SIG226_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC226_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC226_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC226_IN_SEL: u32 = 63;
pub const GPIO_FUNC226_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC226_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC227_IN_SEL_CFG_REG: u32 = 1610630368;
pub const GPIO_SIG227_IN_SEL_V: u32 = 1;
pub const GPIO_SIG227_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC227_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC227_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC227_IN_SEL: u32 = 63;
pub const GPIO_FUNC227_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC227_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC228_IN_SEL_CFG_REG: u32 = 1610630372;
pub const GPIO_SIG228_IN_SEL_V: u32 = 1;
pub const GPIO_SIG228_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC228_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC228_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC228_IN_SEL: u32 = 63;
pub const GPIO_FUNC228_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC228_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC229_IN_SEL_CFG_REG: u32 = 1610630376;
pub const GPIO_SIG229_IN_SEL_V: u32 = 1;
pub const GPIO_SIG229_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC229_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC229_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC229_IN_SEL: u32 = 63;
pub const GPIO_FUNC229_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC229_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC230_IN_SEL_CFG_REG: u32 = 1610630380;
pub const GPIO_SIG230_IN_SEL_V: u32 = 1;
pub const GPIO_SIG230_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC230_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC230_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC230_IN_SEL: u32 = 63;
pub const GPIO_FUNC230_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC230_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC231_IN_SEL_CFG_REG: u32 = 1610630384;
pub const GPIO_SIG231_IN_SEL_V: u32 = 1;
pub const GPIO_SIG231_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC231_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC231_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC231_IN_SEL: u32 = 63;
pub const GPIO_FUNC231_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC231_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC232_IN_SEL_CFG_REG: u32 = 1610630388;
pub const GPIO_SIG232_IN_SEL_V: u32 = 1;
pub const GPIO_SIG232_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC232_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC232_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC232_IN_SEL: u32 = 63;
pub const GPIO_FUNC232_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC232_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC233_IN_SEL_CFG_REG: u32 = 1610630392;
pub const GPIO_SIG233_IN_SEL_V: u32 = 1;
pub const GPIO_SIG233_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC233_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC233_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC233_IN_SEL: u32 = 63;
pub const GPIO_FUNC233_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC233_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC234_IN_SEL_CFG_REG: u32 = 1610630396;
pub const GPIO_SIG234_IN_SEL_V: u32 = 1;
pub const GPIO_SIG234_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC234_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC234_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC234_IN_SEL: u32 = 63;
pub const GPIO_FUNC234_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC234_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC235_IN_SEL_CFG_REG: u32 = 1610630400;
pub const GPIO_SIG235_IN_SEL_V: u32 = 1;
pub const GPIO_SIG235_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC235_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC235_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC235_IN_SEL: u32 = 63;
pub const GPIO_FUNC235_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC235_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC236_IN_SEL_CFG_REG: u32 = 1610630404;
pub const GPIO_SIG236_IN_SEL_V: u32 = 1;
pub const GPIO_SIG236_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC236_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC236_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC236_IN_SEL: u32 = 63;
pub const GPIO_FUNC236_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC236_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC237_IN_SEL_CFG_REG: u32 = 1610630408;
pub const GPIO_SIG237_IN_SEL_V: u32 = 1;
pub const GPIO_SIG237_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC237_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC237_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC237_IN_SEL: u32 = 63;
pub const GPIO_FUNC237_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC237_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC238_IN_SEL_CFG_REG: u32 = 1610630412;
pub const GPIO_SIG238_IN_SEL_V: u32 = 1;
pub const GPIO_SIG238_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC238_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC238_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC238_IN_SEL: u32 = 63;
pub const GPIO_FUNC238_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC238_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC239_IN_SEL_CFG_REG: u32 = 1610630416;
pub const GPIO_SIG239_IN_SEL_V: u32 = 1;
pub const GPIO_SIG239_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC239_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC239_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC239_IN_SEL: u32 = 63;
pub const GPIO_FUNC239_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC239_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC240_IN_SEL_CFG_REG: u32 = 1610630420;
pub const GPIO_SIG240_IN_SEL_V: u32 = 1;
pub const GPIO_SIG240_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC240_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC240_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC240_IN_SEL: u32 = 63;
pub const GPIO_FUNC240_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC240_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC241_IN_SEL_CFG_REG: u32 = 1610630424;
pub const GPIO_SIG241_IN_SEL_V: u32 = 1;
pub const GPIO_SIG241_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC241_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC241_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC241_IN_SEL: u32 = 63;
pub const GPIO_FUNC241_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC241_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC242_IN_SEL_CFG_REG: u32 = 1610630428;
pub const GPIO_SIG242_IN_SEL_V: u32 = 1;
pub const GPIO_SIG242_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC242_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC242_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC242_IN_SEL: u32 = 63;
pub const GPIO_FUNC242_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC242_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC243_IN_SEL_CFG_REG: u32 = 1610630432;
pub const GPIO_SIG243_IN_SEL_V: u32 = 1;
pub const GPIO_SIG243_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC243_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC243_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC243_IN_SEL: u32 = 63;
pub const GPIO_FUNC243_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC243_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC244_IN_SEL_CFG_REG: u32 = 1610630436;
pub const GPIO_SIG244_IN_SEL_V: u32 = 1;
pub const GPIO_SIG244_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC244_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC244_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC244_IN_SEL: u32 = 63;
pub const GPIO_FUNC244_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC244_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC245_IN_SEL_CFG_REG: u32 = 1610630440;
pub const GPIO_SIG245_IN_SEL_V: u32 = 1;
pub const GPIO_SIG245_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC245_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC245_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC245_IN_SEL: u32 = 63;
pub const GPIO_FUNC245_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC245_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC246_IN_SEL_CFG_REG: u32 = 1610630444;
pub const GPIO_SIG246_IN_SEL_V: u32 = 1;
pub const GPIO_SIG246_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC246_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC246_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC246_IN_SEL: u32 = 63;
pub const GPIO_FUNC246_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC246_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC247_IN_SEL_CFG_REG: u32 = 1610630448;
pub const GPIO_SIG247_IN_SEL_V: u32 = 1;
pub const GPIO_SIG247_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC247_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC247_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC247_IN_SEL: u32 = 63;
pub const GPIO_FUNC247_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC247_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC248_IN_SEL_CFG_REG: u32 = 1610630452;
pub const GPIO_SIG248_IN_SEL_V: u32 = 1;
pub const GPIO_SIG248_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC248_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC248_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC248_IN_SEL: u32 = 63;
pub const GPIO_FUNC248_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC248_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC249_IN_SEL_CFG_REG: u32 = 1610630456;
pub const GPIO_SIG249_IN_SEL_V: u32 = 1;
pub const GPIO_SIG249_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC249_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC249_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC249_IN_SEL: u32 = 63;
pub const GPIO_FUNC249_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC249_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC250_IN_SEL_CFG_REG: u32 = 1610630460;
pub const GPIO_SIG250_IN_SEL_V: u32 = 1;
pub const GPIO_SIG250_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC250_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC250_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC250_IN_SEL: u32 = 63;
pub const GPIO_FUNC250_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC250_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC251_IN_SEL_CFG_REG: u32 = 1610630464;
pub const GPIO_SIG251_IN_SEL_V: u32 = 1;
pub const GPIO_SIG251_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC251_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC251_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC251_IN_SEL: u32 = 63;
pub const GPIO_FUNC251_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC251_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC252_IN_SEL_CFG_REG: u32 = 1610630468;
pub const GPIO_SIG252_IN_SEL_V: u32 = 1;
pub const GPIO_SIG252_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC252_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC252_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC252_IN_SEL: u32 = 63;
pub const GPIO_FUNC252_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC252_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC253_IN_SEL_CFG_REG: u32 = 1610630472;
pub const GPIO_SIG253_IN_SEL_V: u32 = 1;
pub const GPIO_SIG253_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC253_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC253_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC253_IN_SEL: u32 = 63;
pub const GPIO_FUNC253_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC253_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC254_IN_SEL_CFG_REG: u32 = 1610630476;
pub const GPIO_SIG254_IN_SEL_V: u32 = 1;
pub const GPIO_SIG254_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC254_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC254_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC254_IN_SEL: u32 = 63;
pub const GPIO_FUNC254_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC254_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC255_IN_SEL_CFG_REG: u32 = 1610630480;
pub const GPIO_SIG255_IN_SEL_V: u32 = 1;
pub const GPIO_SIG255_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC255_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC255_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC255_IN_SEL: u32 = 63;
pub const GPIO_FUNC255_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC255_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC0_OUT_SEL_CFG_REG: u32 = 1610630484;
pub const GPIO_FUNC0_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC0_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC0_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC0_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC0_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC0_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC0_OUT_SEL: u32 = 511;
pub const GPIO_FUNC0_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC0_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC1_OUT_SEL_CFG_REG: u32 = 1610630488;
pub const GPIO_FUNC1_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC1_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC1_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC1_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC1_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC1_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC1_OUT_SEL: u32 = 511;
pub const GPIO_FUNC1_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC1_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC2_OUT_SEL_CFG_REG: u32 = 1610630492;
pub const GPIO_FUNC2_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC2_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC2_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC2_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC2_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC2_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC2_OUT_SEL: u32 = 511;
pub const GPIO_FUNC2_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC2_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC3_OUT_SEL_CFG_REG: u32 = 1610630496;
pub const GPIO_FUNC3_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC3_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC3_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC3_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC3_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC3_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC3_OUT_SEL: u32 = 511;
pub const GPIO_FUNC3_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC3_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC4_OUT_SEL_CFG_REG: u32 = 1610630500;
pub const GPIO_FUNC4_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC4_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC4_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC4_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC4_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC4_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC4_OUT_SEL: u32 = 511;
pub const GPIO_FUNC4_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC4_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC5_OUT_SEL_CFG_REG: u32 = 1610630504;
pub const GPIO_FUNC5_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC5_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC5_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC5_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC5_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC5_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC5_OUT_SEL: u32 = 511;
pub const GPIO_FUNC5_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC5_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC6_OUT_SEL_CFG_REG: u32 = 1610630508;
pub const GPIO_FUNC6_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC6_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC6_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC6_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC6_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC6_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC6_OUT_SEL: u32 = 511;
pub const GPIO_FUNC6_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC6_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC7_OUT_SEL_CFG_REG: u32 = 1610630512;
pub const GPIO_FUNC7_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC7_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC7_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC7_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC7_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC7_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC7_OUT_SEL: u32 = 511;
pub const GPIO_FUNC7_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC7_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC8_OUT_SEL_CFG_REG: u32 = 1610630516;
pub const GPIO_FUNC8_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC8_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC8_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC8_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC8_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC8_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC8_OUT_SEL: u32 = 511;
pub const GPIO_FUNC8_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC8_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC9_OUT_SEL_CFG_REG: u32 = 1610630520;
pub const GPIO_FUNC9_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC9_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC9_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC9_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC9_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC9_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC9_OUT_SEL: u32 = 511;
pub const GPIO_FUNC9_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC9_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC10_OUT_SEL_CFG_REG: u32 = 1610630524;
pub const GPIO_FUNC10_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC10_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC10_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC10_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC10_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC10_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC10_OUT_SEL: u32 = 511;
pub const GPIO_FUNC10_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC10_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC11_OUT_SEL_CFG_REG: u32 = 1610630528;
pub const GPIO_FUNC11_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC11_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC11_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC11_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC11_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC11_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC11_OUT_SEL: u32 = 511;
pub const GPIO_FUNC11_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC11_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC12_OUT_SEL_CFG_REG: u32 = 1610630532;
pub const GPIO_FUNC12_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC12_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC12_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC12_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC12_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC12_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC12_OUT_SEL: u32 = 511;
pub const GPIO_FUNC12_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC12_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC13_OUT_SEL_CFG_REG: u32 = 1610630536;
pub const GPIO_FUNC13_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC13_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC13_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC13_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC13_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC13_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC13_OUT_SEL: u32 = 511;
pub const GPIO_FUNC13_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC13_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC14_OUT_SEL_CFG_REG: u32 = 1610630540;
pub const GPIO_FUNC14_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC14_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC14_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC14_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC14_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC14_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC14_OUT_SEL: u32 = 511;
pub const GPIO_FUNC14_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC14_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC15_OUT_SEL_CFG_REG: u32 = 1610630544;
pub const GPIO_FUNC15_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC15_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC15_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC15_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC15_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC15_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC15_OUT_SEL: u32 = 511;
pub const GPIO_FUNC15_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC15_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC16_OUT_SEL_CFG_REG: u32 = 1610630548;
pub const GPIO_FUNC16_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC16_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC16_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC16_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC16_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC16_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC16_OUT_SEL: u32 = 511;
pub const GPIO_FUNC16_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC16_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC17_OUT_SEL_CFG_REG: u32 = 1610630552;
pub const GPIO_FUNC17_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC17_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC17_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC17_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC17_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC17_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC17_OUT_SEL: u32 = 511;
pub const GPIO_FUNC17_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC17_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC18_OUT_SEL_CFG_REG: u32 = 1610630556;
pub const GPIO_FUNC18_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC18_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC18_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC18_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC18_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC18_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC18_OUT_SEL: u32 = 511;
pub const GPIO_FUNC18_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC18_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC19_OUT_SEL_CFG_REG: u32 = 1610630560;
pub const GPIO_FUNC19_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC19_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC19_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC19_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC19_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC19_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC19_OUT_SEL: u32 = 511;
pub const GPIO_FUNC19_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC19_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC20_OUT_SEL_CFG_REG: u32 = 1610630564;
pub const GPIO_FUNC20_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC20_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC20_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC20_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC20_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC20_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC20_OUT_SEL: u32 = 511;
pub const GPIO_FUNC20_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC20_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC21_OUT_SEL_CFG_REG: u32 = 1610630568;
pub const GPIO_FUNC21_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC21_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC21_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC21_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC21_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC21_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC21_OUT_SEL: u32 = 511;
pub const GPIO_FUNC21_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC21_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC22_OUT_SEL_CFG_REG: u32 = 1610630572;
pub const GPIO_FUNC22_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC22_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC22_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC22_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC22_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC22_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC22_OUT_SEL: u32 = 511;
pub const GPIO_FUNC22_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC22_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC23_OUT_SEL_CFG_REG: u32 = 1610630576;
pub const GPIO_FUNC23_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC23_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC23_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC23_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC23_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC23_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC23_OUT_SEL: u32 = 511;
pub const GPIO_FUNC23_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC23_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC24_OUT_SEL_CFG_REG: u32 = 1610630580;
pub const GPIO_FUNC24_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC24_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC24_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC24_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC24_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC24_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC24_OUT_SEL: u32 = 511;
pub const GPIO_FUNC24_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC24_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC25_OUT_SEL_CFG_REG: u32 = 1610630584;
pub const GPIO_FUNC25_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC25_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC25_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC25_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC25_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC25_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC25_OUT_SEL: u32 = 511;
pub const GPIO_FUNC25_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC25_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC26_OUT_SEL_CFG_REG: u32 = 1610630588;
pub const GPIO_FUNC26_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC26_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC26_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC26_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC26_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC26_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC26_OUT_SEL: u32 = 511;
pub const GPIO_FUNC26_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC26_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC27_OUT_SEL_CFG_REG: u32 = 1610630592;
pub const GPIO_FUNC27_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC27_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC27_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC27_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC27_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC27_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC27_OUT_SEL: u32 = 511;
pub const GPIO_FUNC27_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC27_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC28_OUT_SEL_CFG_REG: u32 = 1610630596;
pub const GPIO_FUNC28_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC28_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC28_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC28_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC28_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC28_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC28_OUT_SEL: u32 = 511;
pub const GPIO_FUNC28_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC28_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC29_OUT_SEL_CFG_REG: u32 = 1610630600;
pub const GPIO_FUNC29_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC29_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC29_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC29_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC29_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC29_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC29_OUT_SEL: u32 = 511;
pub const GPIO_FUNC29_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC29_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC30_OUT_SEL_CFG_REG: u32 = 1610630604;
pub const GPIO_FUNC30_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC30_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC30_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC30_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC30_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC30_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC30_OUT_SEL: u32 = 511;
pub const GPIO_FUNC30_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC30_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC31_OUT_SEL_CFG_REG: u32 = 1610630608;
pub const GPIO_FUNC31_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC31_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC31_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC31_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC31_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC31_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC31_OUT_SEL: u32 = 511;
pub const GPIO_FUNC31_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC31_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC32_OUT_SEL_CFG_REG: u32 = 1610630612;
pub const GPIO_FUNC32_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC32_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC32_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC32_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC32_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC32_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC32_OUT_SEL: u32 = 511;
pub const GPIO_FUNC32_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC32_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC33_OUT_SEL_CFG_REG: u32 = 1610630616;
pub const GPIO_FUNC33_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC33_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC33_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC33_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC33_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC33_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC33_OUT_SEL: u32 = 511;
pub const GPIO_FUNC33_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC33_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC34_OUT_SEL_CFG_REG: u32 = 1610630620;
pub const GPIO_FUNC34_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC34_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC34_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC34_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC34_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC34_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC34_OUT_SEL: u32 = 511;
pub const GPIO_FUNC34_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC34_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC35_OUT_SEL_CFG_REG: u32 = 1610630624;
pub const GPIO_FUNC35_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC35_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC35_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC35_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC35_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC35_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC35_OUT_SEL: u32 = 511;
pub const GPIO_FUNC35_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC35_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC36_OUT_SEL_CFG_REG: u32 = 1610630628;
pub const GPIO_FUNC36_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC36_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC36_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC36_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC36_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC36_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC36_OUT_SEL: u32 = 511;
pub const GPIO_FUNC36_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC36_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC37_OUT_SEL_CFG_REG: u32 = 1610630632;
pub const GPIO_FUNC37_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC37_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC37_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC37_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC37_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC37_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC37_OUT_SEL: u32 = 511;
pub const GPIO_FUNC37_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC37_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC38_OUT_SEL_CFG_REG: u32 = 1610630636;
pub const GPIO_FUNC38_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC38_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC38_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC38_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC38_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC38_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC38_OUT_SEL: u32 = 511;
pub const GPIO_FUNC38_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC38_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC39_OUT_SEL_CFG_REG: u32 = 1610630640;
pub const GPIO_FUNC39_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC39_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC39_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC39_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC39_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC39_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC39_OUT_SEL: u32 = 511;
pub const GPIO_FUNC39_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC39_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC40_OUT_SEL_CFG_REG: u32 = 1610630644;
pub const GPIO_FUNC40_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC40_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC40_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC40_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC40_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC40_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC40_OUT_SEL: u32 = 511;
pub const GPIO_FUNC40_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC40_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC41_OUT_SEL_CFG_REG: u32 = 1610630648;
pub const GPIO_FUNC41_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC41_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC41_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC41_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC41_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC41_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC41_OUT_SEL: u32 = 511;
pub const GPIO_FUNC41_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC41_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC42_OUT_SEL_CFG_REG: u32 = 1610630652;
pub const GPIO_FUNC42_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC42_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC42_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC42_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC42_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC42_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC42_OUT_SEL: u32 = 511;
pub const GPIO_FUNC42_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC42_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC43_OUT_SEL_CFG_REG: u32 = 1610630656;
pub const GPIO_FUNC43_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC43_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC43_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC43_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC43_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC43_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC43_OUT_SEL: u32 = 511;
pub const GPIO_FUNC43_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC43_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC44_OUT_SEL_CFG_REG: u32 = 1610630660;
pub const GPIO_FUNC44_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC44_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC44_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC44_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC44_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC44_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC44_OUT_SEL: u32 = 511;
pub const GPIO_FUNC44_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC44_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC45_OUT_SEL_CFG_REG: u32 = 1610630664;
pub const GPIO_FUNC45_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC45_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC45_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC45_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC45_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC45_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC45_OUT_SEL: u32 = 511;
pub const GPIO_FUNC45_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC45_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC46_OUT_SEL_CFG_REG: u32 = 1610630668;
pub const GPIO_FUNC46_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC46_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC46_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC46_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC46_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC46_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC46_OUT_SEL: u32 = 511;
pub const GPIO_FUNC46_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC46_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC47_OUT_SEL_CFG_REG: u32 = 1610630672;
pub const GPIO_FUNC47_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC47_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC47_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC47_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC47_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC47_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC47_OUT_SEL: u32 = 511;
pub const GPIO_FUNC47_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC47_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC48_OUT_SEL_CFG_REG: u32 = 1610630676;
pub const GPIO_FUNC48_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC48_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC48_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC48_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC48_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC48_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC48_OUT_SEL: u32 = 511;
pub const GPIO_FUNC48_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC48_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC49_OUT_SEL_CFG_REG: u32 = 1610630680;
pub const GPIO_FUNC49_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC49_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC49_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC49_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC49_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC49_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC49_OUT_SEL: u32 = 511;
pub const GPIO_FUNC49_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC49_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC50_OUT_SEL_CFG_REG: u32 = 1610630684;
pub const GPIO_FUNC50_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC50_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC50_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC50_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC50_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC50_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC50_OUT_SEL: u32 = 511;
pub const GPIO_FUNC50_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC50_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC51_OUT_SEL_CFG_REG: u32 = 1610630688;
pub const GPIO_FUNC51_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC51_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC51_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC51_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC51_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC51_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC51_OUT_SEL: u32 = 511;
pub const GPIO_FUNC51_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC51_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC52_OUT_SEL_CFG_REG: u32 = 1610630692;
pub const GPIO_FUNC52_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC52_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC52_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC52_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC52_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC52_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC52_OUT_SEL: u32 = 511;
pub const GPIO_FUNC52_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC52_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC53_OUT_SEL_CFG_REG: u32 = 1610630696;
pub const GPIO_FUNC53_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC53_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC53_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC53_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC53_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC53_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC53_OUT_SEL: u32 = 511;
pub const GPIO_FUNC53_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC53_OUT_SEL_S: u32 = 0;
pub const GPIO_CLOCK_GATE_REG: u32 = 1610630700;
pub const GPIO_CLK_EN_V: u32 = 1;
pub const GPIO_CLK_EN_S: u32 = 0;
pub const GPIO_DATE_REG: u32 = 1610630908;
pub const GPIO_DATE: u32 = 268435455;
pub const GPIO_DATE_V: u32 = 268435455;
pub const GPIO_DATE_S: u32 = 0;
pub const SPIQ_IN_IDX: u32 = 0;
pub const SPIQ_OUT_IDX: u32 = 0;
pub const SPID_IN_IDX: u32 = 1;
pub const SPID_OUT_IDX: u32 = 1;
pub const SPIHD_IN_IDX: u32 = 2;
pub const SPIHD_OUT_IDX: u32 = 2;
pub const SPIWP_IN_IDX: u32 = 3;
pub const SPIWP_OUT_IDX: u32 = 3;
pub const SPICLK_OUT_IDX: u32 = 4;
pub const SPICS0_OUT_IDX: u32 = 5;
pub const SPICS1_OUT_IDX: u32 = 6;
pub const SPID4_IN_IDX: u32 = 7;
pub const SPID4_OUT_IDX: u32 = 7;
pub const SPID5_IN_IDX: u32 = 8;
pub const SPID5_OUT_IDX: u32 = 8;
pub const SPID6_IN_IDX: u32 = 9;
pub const SPID6_OUT_IDX: u32 = 9;
pub const SPID7_IN_IDX: u32 = 10;
pub const SPID7_OUT_IDX: u32 = 10;
pub const SPIDQS_IN_IDX: u32 = 11;
pub const SPIDQS_OUT_IDX: u32 = 11;
pub const U0RXD_IN_IDX: u32 = 12;
pub const U0TXD_OUT_IDX: u32 = 12;
pub const U0CTS_IN_IDX: u32 = 13;
pub const U0RTS_OUT_IDX: u32 = 13;
pub const U0DSR_IN_IDX: u32 = 14;
pub const U0DTR_OUT_IDX: u32 = 14;
pub const U1RXD_IN_IDX: u32 = 15;
pub const U1TXD_OUT_IDX: u32 = 15;
pub const U1CTS_IN_IDX: u32 = 16;
pub const U1RTS_OUT_IDX: u32 = 16;
pub const U1DSR_IN_IDX: u32 = 17;
pub const U1DTR_OUT_IDX: u32 = 17;
pub const U2RXD_IN_IDX: u32 = 18;
pub const U2TXD_OUT_IDX: u32 = 18;
pub const U2CTS_IN_IDX: u32 = 19;
pub const U2RTS_OUT_IDX: u32 = 19;
pub const U2DSR_IN_IDX: u32 = 20;
pub const U2DTR_OUT_IDX: u32 = 20;
pub const I2S1_MCLK_IN_IDX: u32 = 21;
pub const I2S1_MCLK_OUT_IDX: u32 = 21;
pub const I2S0O_BCK_IN_IDX: u32 = 22;
pub const I2S0O_BCK_OUT_IDX: u32 = 22;
pub const I2S0_MCLK_IN_IDX: u32 = 23;
pub const I2S0_MCLK_OUT_IDX: u32 = 23;
pub const I2S0O_WS_IN_IDX: u32 = 24;
pub const I2S0O_WS_OUT_IDX: u32 = 24;
pub const I2S0I_SD_IN_IDX: u32 = 25;
pub const I2S0O_SD_OUT_IDX: u32 = 25;
pub const I2S0I_BCK_IN_IDX: u32 = 26;
pub const I2S0I_BCK_OUT_IDX: u32 = 26;
pub const I2S0I_WS_IN_IDX: u32 = 27;
pub const I2S0I_WS_OUT_IDX: u32 = 27;
pub const I2S1O_BCK_IN_IDX: u32 = 28;
pub const I2S1O_BCK_OUT_IDX: u32 = 28;
pub const I2S1O_WS_IN_IDX: u32 = 29;
pub const I2S1O_WS_OUT_IDX: u32 = 29;
pub const I2S1I_SD_IN_IDX: u32 = 30;
pub const I2S1O_SD_OUT_IDX: u32 = 30;
pub const I2S1I_BCK_IN_IDX: u32 = 31;
pub const I2S1I_BCK_OUT_IDX: u32 = 31;
pub const I2S1I_WS_IN_IDX: u32 = 32;
pub const I2S1I_WS_OUT_IDX: u32 = 32;
pub const PCNT_SIG_CH0_IN0_IDX: u32 = 33;
pub const GPIO_WLAN_PRIO_IDX: u32 = 33;
pub const PCNT_SIG_CH1_IN0_IDX: u32 = 34;
pub const GPIO_WLAN_ACTIVE_IDX: u32 = 34;
pub const PCNT_CTRL_CH0_IN0_IDX: u32 = 35;
pub const BB_DIAG0_IDX: u32 = 35;
pub const PCNT_CTRL_CH1_IN0_IDX: u32 = 36;
pub const BB_DIAG1_IDX: u32 = 36;
pub const PCNT_SIG_CH0_IN1_IDX: u32 = 37;
pub const BB_DIAG2_IDX: u32 = 37;
pub const PCNT_SIG_CH1_IN1_IDX: u32 = 38;
pub const BB_DIAG3_IDX: u32 = 38;
pub const PCNT_CTRL_CH0_IN1_IDX: u32 = 39;
pub const BB_DIAG4_IDX: u32 = 39;
pub const PCNT_CTRL_CH1_IN1_IDX: u32 = 40;
pub const BB_DIAG5_IDX: u32 = 40;
pub const PCNT_SIG_CH0_IN2_IDX: u32 = 41;
pub const BB_DIAG6_IDX: u32 = 41;
pub const PCNT_SIG_CH1_IN2_IDX: u32 = 42;
pub const BB_DIAG7_IDX: u32 = 42;
pub const PCNT_CTRL_CH0_IN2_IDX: u32 = 43;
pub const BB_DIAG8_IDX: u32 = 43;
pub const PCNT_CTRL_CH1_IN2_IDX: u32 = 44;
pub const BB_DIAG9_IDX: u32 = 44;
pub const PCNT_SIG_CH0_IN3_IDX: u32 = 45;
pub const BB_DIAG10_IDX: u32 = 45;
pub const PCNT_SIG_CH1_IN3_IDX: u32 = 46;
pub const BB_DIAG11_IDX: u32 = 46;
pub const PCNT_CTRL_CH0_IN3_IDX: u32 = 47;
pub const BB_DIAG12_IDX: u32 = 47;
pub const PCNT_CTRL_CH1_IN3_IDX: u32 = 48;
pub const BB_DIAG13_IDX: u32 = 48;
pub const GPIO_BT_ACTIVE_IDX: u32 = 49;
pub const BB_DIAG14_IDX: u32 = 49;
pub const GPIO_BT_PRIORITY_IDX: u32 = 50;
pub const BB_DIAG15_IDX: u32 = 50;
pub const I2S0I_SD1_IN_IDX: u32 = 51;
pub const BB_DIAG16_IDX: u32 = 51;
pub const I2S0I_SD2_IN_IDX: u32 = 52;
pub const BB_DIAG17_IDX: u32 = 52;
pub const I2S0I_SD3_IN_IDX: u32 = 53;
pub const BB_DIAG18_IDX: u32 = 53;
pub const CORE1_GPIO_IN7_IDX: u32 = 54;
pub const CORE1_GPIO_OUT7_IDX: u32 = 54;
pub const USB_EXTPHY_VP_IDX: u32 = 55;
pub const USB_EXTPHY_OEN_IDX: u32 = 55;
pub const USB_EXTPHY_VM_IDX: u32 = 56;
pub const USB_EXTPHY_SPEED_IDX: u32 = 56;
pub const USB_EXTPHY_RCV_IDX: u32 = 57;
pub const USB_EXTPHY_VPO_IDX: u32 = 57;
pub const USB_OTG_IDDIG_IN_IDX: u32 = 58;
pub const USB_EXTPHY_VMO_IDX: u32 = 58;
pub const USB_OTG_AVALID_IN_IDX: u32 = 59;
pub const USB_EXTPHY_SUSPND_IDX: u32 = 59;
pub const USB_SRP_BVALID_IN_IDX: u32 = 60;
pub const USB_OTG_IDPULLUP_IDX: u32 = 60;
pub const USB_OTG_VBUSVALID_IN_IDX: u32 = 61;
pub const USB_OTG_DPPULLDOWN_IDX: u32 = 61;
pub const USB_SRP_SESSEND_IN_IDX: u32 = 62;
pub const USB_OTG_DMPULLDOWN_IDX: u32 = 62;
pub const USB_OTG_DRVVBUS_IDX: u32 = 63;
pub const USB_SRP_CHRGVBUS_IDX: u32 = 64;
pub const USB_SRP_DISCHRGVBUS_IDX: u32 = 65;
pub const SPI3_CLK_IN_IDX: u32 = 66;
pub const SPI3_CLK_OUT_IDX: u32 = 66;
pub const SPI3_Q_IN_IDX: u32 = 67;
pub const SPI3_Q_OUT_IDX: u32 = 67;
pub const SPI3_D_IN_IDX: u32 = 68;
pub const SPI3_D_OUT_IDX: u32 = 68;
pub const SPI3_HD_IN_IDX: u32 = 69;
pub const SPI3_HD_OUT_IDX: u32 = 69;
pub const SPI3_WP_IN_IDX: u32 = 70;
pub const SPI3_WP_OUT_IDX: u32 = 70;
pub const SPI3_CS0_IN_IDX: u32 = 71;
pub const SPI3_CS0_OUT_IDX: u32 = 71;
pub const SPI3_CS1_OUT_IDX: u32 = 72;
pub const EXT_ADC_START_IDX: u32 = 73;
pub const LEDC_LS_SIG_OUT0_IDX: u32 = 73;
pub const LEDC_LS_SIG_OUT1_IDX: u32 = 74;
pub const LEDC_LS_SIG_OUT2_IDX: u32 = 75;
pub const LEDC_LS_SIG_OUT3_IDX: u32 = 76;
pub const LEDC_LS_SIG_OUT4_IDX: u32 = 77;
pub const LEDC_LS_SIG_OUT5_IDX: u32 = 78;
pub const LEDC_LS_SIG_OUT6_IDX: u32 = 79;
pub const LEDC_LS_SIG_OUT7_IDX: u32 = 80;
pub const RMT_SIG_IN0_IDX: u32 = 81;
pub const RMT_SIG_OUT0_IDX: u32 = 81;
pub const RMT_SIG_IN1_IDX: u32 = 82;
pub const RMT_SIG_OUT1_IDX: u32 = 82;
pub const RMT_SIG_IN2_IDX: u32 = 83;
pub const RMT_SIG_OUT2_IDX: u32 = 83;
pub const RMT_SIG_IN3_IDX: u32 = 84;
pub const RMT_SIG_OUT3_IDX: u32 = 84;
pub const USB_JTAG_TCK_IDX: u32 = 85;
pub const USB_JTAG_TMS_IDX: u32 = 86;
pub const USB_JTAG_TDI_IDX: u32 = 87;
pub const USB_JTAG_TDO_IDX: u32 = 88;
pub const I2CEXT0_SCL_IN_IDX: u32 = 89;
pub const I2CEXT0_SCL_OUT_IDX: u32 = 89;
pub const I2CEXT0_SDA_IN_IDX: u32 = 90;
pub const I2CEXT0_SDA_OUT_IDX: u32 = 90;
pub const I2CEXT1_SCL_IN_IDX: u32 = 91;
pub const I2CEXT1_SCL_OUT_IDX: u32 = 91;
pub const I2CEXT1_SDA_IN_IDX: u32 = 92;
pub const I2CEXT1_SDA_OUT_IDX: u32 = 92;
pub const GPIO_SD0_OUT_IDX: u32 = 93;
pub const GPIO_SD1_OUT_IDX: u32 = 94;
pub const GPIO_SD2_OUT_IDX: u32 = 95;
pub const GPIO_SD3_OUT_IDX: u32 = 96;
pub const GPIO_SD4_OUT_IDX: u32 = 97;
pub const GPIO_SD5_OUT_IDX: u32 = 98;
pub const GPIO_SD6_OUT_IDX: u32 = 99;
pub const GPIO_SD7_OUT_IDX: u32 = 100;
pub const FSPICLK_IN_IDX: u32 = 101;
pub const FSPICLK_OUT_IDX: u32 = 101;
pub const FSPIQ_IN_IDX: u32 = 102;
pub const FSPIQ_OUT_IDX: u32 = 102;
pub const FSPID_IN_IDX: u32 = 103;
pub const FSPID_OUT_IDX: u32 = 103;
pub const FSPIHD_IN_IDX: u32 = 104;
pub const FSPIHD_OUT_IDX: u32 = 104;
pub const FSPIWP_IN_IDX: u32 = 105;
pub const FSPIWP_OUT_IDX: u32 = 105;
pub const FSPIIO4_IN_IDX: u32 = 106;
pub const FSPIIO4_OUT_IDX: u32 = 106;
pub const FSPIIO5_IN_IDX: u32 = 107;
pub const FSPIIO5_OUT_IDX: u32 = 107;
pub const FSPIIO6_IN_IDX: u32 = 108;
pub const FSPIIO6_OUT_IDX: u32 = 108;
pub const FSPIIO7_IN_IDX: u32 = 109;
pub const FSPIIO7_OUT_IDX: u32 = 109;
pub const FSPICS0_IN_IDX: u32 = 110;
pub const FSPICS0_OUT_IDX: u32 = 110;
pub const FSPICS1_OUT_IDX: u32 = 111;
pub const FSPICS2_OUT_IDX: u32 = 112;
pub const FSPICS3_OUT_IDX: u32 = 113;
pub const FSPICS4_OUT_IDX: u32 = 114;
pub const FSPICS5_OUT_IDX: u32 = 115;
pub const TWAI_RX_IDX: u32 = 116;
pub const TWAI_TX_IDX: u32 = 116;
pub const TWAI_BUS_OFF_ON_IDX: u32 = 117;
pub const TWAI_CLKOUT_IDX: u32 = 118;
pub const SUBSPICLK_OUT_IDX: u32 = 119;
pub const SUBSPIQ_IN_IDX: u32 = 120;
pub const SUBSPIQ_OUT_IDX: u32 = 120;
pub const SUBSPID_IN_IDX: u32 = 121;
pub const SUBSPID_OUT_IDX: u32 = 121;
pub const SUBSPIHD_IN_IDX: u32 = 122;
pub const SUBSPIHD_OUT_IDX: u32 = 122;
pub const SUBSPIWP_IN_IDX: u32 = 123;
pub const SUBSPIWP_OUT_IDX: u32 = 123;
pub const SUBSPICS0_OUT_IDX: u32 = 124;
pub const SUBSPICS1_OUT_IDX: u32 = 125;
pub const FSPIDQS_OUT_IDX: u32 = 126;
pub const SPI3_CS2_OUT_IDX: u32 = 127;
pub const I2S0O_SD1_OUT_IDX: u32 = 128;
pub const CORE1_GPIO_IN0_IDX: u32 = 129;
pub const CORE1_GPIO_OUT0_IDX: u32 = 129;
pub const CORE1_GPIO_IN1_IDX: u32 = 130;
pub const CORE1_GPIO_OUT1_IDX: u32 = 130;
pub const CORE1_GPIO_IN2_IDX: u32 = 131;
pub const CORE1_GPIO_OUT2_IDX: u32 = 131;
pub const LCD_CS_IDX: u32 = 132;
pub const CAM_DATA_IN0_IDX: u32 = 133;
pub const LCD_DATA_OUT0_IDX: u32 = 133;
pub const CAM_DATA_IN1_IDX: u32 = 134;
pub const LCD_DATA_OUT1_IDX: u32 = 134;
pub const CAM_DATA_IN2_IDX: u32 = 135;
pub const LCD_DATA_OUT2_IDX: u32 = 135;
pub const CAM_DATA_IN3_IDX: u32 = 136;
pub const LCD_DATA_OUT3_IDX: u32 = 136;
pub const CAM_DATA_IN4_IDX: u32 = 137;
pub const LCD_DATA_OUT4_IDX: u32 = 137;
pub const CAM_DATA_IN5_IDX: u32 = 138;
pub const LCD_DATA_OUT5_IDX: u32 = 138;
pub const CAM_DATA_IN6_IDX: u32 = 139;
pub const LCD_DATA_OUT6_IDX: u32 = 139;
pub const CAM_DATA_IN7_IDX: u32 = 140;
pub const LCD_DATA_OUT7_IDX: u32 = 140;
pub const CAM_DATA_IN8_IDX: u32 = 141;
pub const LCD_DATA_OUT8_IDX: u32 = 141;
pub const CAM_DATA_IN9_IDX: u32 = 142;
pub const LCD_DATA_OUT9_IDX: u32 = 142;
pub const CAM_DATA_IN10_IDX: u32 = 143;
pub const LCD_DATA_OUT10_IDX: u32 = 143;
pub const CAM_DATA_IN11_IDX: u32 = 144;
pub const LCD_DATA_OUT11_IDX: u32 = 144;
pub const CAM_DATA_IN12_IDX: u32 = 145;
pub const LCD_DATA_OUT12_IDX: u32 = 145;
pub const CAM_DATA_IN13_IDX: u32 = 146;
pub const LCD_DATA_OUT13_IDX: u32 = 146;
pub const CAM_DATA_IN14_IDX: u32 = 147;
pub const LCD_DATA_OUT14_IDX: u32 = 147;
pub const CAM_DATA_IN15_IDX: u32 = 148;
pub const LCD_DATA_OUT15_IDX: u32 = 148;
pub const CAM_PCLK_IDX: u32 = 149;
pub const CAM_CLK_IDX: u32 = 149;
pub const CAM_H_ENABLE_IDX: u32 = 150;
pub const LCD_H_ENABLE_IDX: u32 = 150;
pub const CAM_H_SYNC_IDX: u32 = 151;
pub const LCD_H_SYNC_IDX: u32 = 151;
pub const CAM_V_SYNC_IDX: u32 = 152;
pub const LCD_V_SYNC_IDX: u32 = 152;
pub const LCD_DC_IDX: u32 = 153;
pub const LCD_PCLK_IDX: u32 = 154;
pub const SUBSPID4_IN_IDX: u32 = 155;
pub const SUBSPID4_OUT_IDX: u32 = 155;
pub const SUBSPID5_IN_IDX: u32 = 156;
pub const SUBSPID5_OUT_IDX: u32 = 156;
pub const SUBSPID6_IN_IDX: u32 = 157;
pub const SUBSPID6_OUT_IDX: u32 = 157;
pub const SUBSPID7_IN_IDX: u32 = 158;
pub const SUBSPID7_OUT_IDX: u32 = 158;
pub const SUBSPIDQS_IN_IDX: u32 = 159;
pub const SUBSPIDQS_OUT_IDX: u32 = 159;
pub const PWM0_SYNC0_IN_IDX: u32 = 160;
pub const PWM0_OUT0A_IDX: u32 = 160;
pub const PWM0_SYNC1_IN_IDX: u32 = 161;
pub const PWM0_OUT0B_IDX: u32 = 161;
pub const PWM0_SYNC2_IN_IDX: u32 = 162;
pub const PWM0_OUT1A_IDX: u32 = 162;
pub const PWM0_F0_IN_IDX: u32 = 163;
pub const PWM0_OUT1B_IDX: u32 = 163;
pub const PWM0_F1_IN_IDX: u32 = 164;
pub const PWM0_OUT2A_IDX: u32 = 164;
pub const PWM0_F2_IN_IDX: u32 = 165;
pub const PWM0_OUT2B_IDX: u32 = 165;
pub const PWM0_CAP0_IN_IDX: u32 = 166;
pub const PWM1_OUT0A_IDX: u32 = 166;
pub const PWM0_CAP1_IN_IDX: u32 = 167;
pub const PWM1_OUT0B_IDX: u32 = 167;
pub const PWM0_CAP2_IN_IDX: u32 = 168;
pub const PWM1_OUT1A_IDX: u32 = 168;
pub const PWM1_SYNC0_IN_IDX: u32 = 169;
pub const PWM1_OUT1B_IDX: u32 = 169;
pub const PWM1_SYNC1_IN_IDX: u32 = 170;
pub const PWM1_OUT2A_IDX: u32 = 170;
pub const PWM1_SYNC2_IN_IDX: u32 = 171;
pub const PWM1_OUT2B_IDX: u32 = 171;
pub const PWM1_F0_IN_IDX: u32 = 172;
pub const SDHOST_CCLK_OUT_1_IDX: u32 = 172;
pub const PWM1_F1_IN_IDX: u32 = 173;
pub const SDHOST_CCLK_OUT_2_IDX: u32 = 173;
pub const PWM1_F2_IN_IDX: u32 = 174;
pub const SDHOST_RST_N_1_IDX: u32 = 174;
pub const PWM1_CAP0_IN_IDX: u32 = 175;
pub const SDHOST_RST_N_2_IDX: u32 = 175;
pub const PWM1_CAP1_IN_IDX: u32 = 176;
pub const PWM1_CAP2_IN_IDX: u32 = 177;
pub const SDIO_TOHOST_INT_OUT_IDX: u32 = 177;
pub const SDHOST_CCMD_IN_1_IDX: u32 = 178;
pub const SDHOST_CCMD_OUT_1_IDX: u32 = 178;
pub const SDHOST_CCMD_IN_2_IDX: u32 = 179;
pub const SDHOST_CCMD_OUT_2_IDX: u32 = 179;
pub const SDHOST_CDATA_IN_10_IDX: u32 = 180;
pub const SDHOST_CDATA_OUT_10_IDX: u32 = 180;
pub const SDHOST_CDATA_IN_11_IDX: u32 = 181;
pub const SDHOST_CDATA_OUT_11_IDX: u32 = 181;
pub const SDHOST_CDATA_IN_12_IDX: u32 = 182;
pub const SDHOST_CDATA_OUT_12_IDX: u32 = 182;
pub const SDHOST_CDATA_IN_13_IDX: u32 = 183;
pub const SDHOST_CDATA_OUT_13_IDX: u32 = 183;
pub const SDHOST_CDATA_IN_14_IDX: u32 = 184;
pub const SDHOST_CDATA_OUT_14_IDX: u32 = 184;
pub const SDHOST_CDATA_IN_15_IDX: u32 = 185;
pub const SDHOST_CDATA_OUT_15_IDX: u32 = 185;
pub const SDHOST_CDATA_IN_16_IDX: u32 = 186;
pub const SDHOST_CDATA_OUT_16_IDX: u32 = 186;
pub const SDHOST_CDATA_IN_17_IDX: u32 = 187;
pub const SDHOST_CDATA_OUT_17_IDX: u32 = 187;
pub const PCMFSYNC_IN_IDX: u32 = 188;
pub const BT_AUDIO0_IRQ_IDX: u32 = 188;
pub const PCMCLK_IN_IDX: u32 = 189;
pub const BT_AUDIO1_IRQ_IDX: u32 = 189;
pub const PCMDIN_IDX: u32 = 190;
pub const BT_AUDIO2_IRQ_IDX: u32 = 190;
pub const RW_WAKEUP_REQ_IDX: u32 = 191;
pub const BLE_AUDIO0_IRQ_IDX: u32 = 191;
pub const SDHOST_DATA_STROBE_1_IDX: u32 = 192;
pub const BLE_AUDIO1_IRQ_IDX: u32 = 192;
pub const SDHOST_DATA_STROBE_2_IDX: u32 = 193;
pub const BLE_AUDIO2_IRQ_IDX: u32 = 193;
pub const SDHOST_CARD_DETECT_N_1_IDX: u32 = 194;
pub const PCMFSYNC_OUT_IDX: u32 = 194;
pub const SDHOST_CARD_DETECT_N_2_IDX: u32 = 195;
pub const PCMCLK_OUT_IDX: u32 = 195;
pub const SDHOST_CARD_WRITE_PRT_1_IDX: u32 = 196;
pub const PCMDOUT_IDX: u32 = 196;
pub const SDHOST_CARD_WRITE_PRT_2_IDX: u32 = 197;
pub const BLE_AUDIO_SYNC0_P_IDX: u32 = 197;
pub const SDHOST_CARD_INT_N_1_IDX: u32 = 198;
pub const BLE_AUDIO_SYNC1_P_IDX: u32 = 198;
pub const SDHOST_CARD_INT_N_2_IDX: u32 = 199;
pub const BLE_AUDIO_SYNC2_P_IDX: u32 = 199;
pub const ANT_SEL0_IDX: u32 = 200;
pub const ANT_SEL1_IDX: u32 = 201;
pub const ANT_SEL2_IDX: u32 = 202;
pub const ANT_SEL3_IDX: u32 = 203;
pub const ANT_SEL4_IDX: u32 = 204;
pub const ANT_SEL5_IDX: u32 = 205;
pub const ANT_SEL6_IDX: u32 = 206;
pub const ANT_SEL7_IDX: u32 = 207;
pub const SIG_IN_FUNC_208_IDX: u32 = 208;
pub const SIG_IN_FUNC208_IDX: u32 = 208;
pub const SIG_IN_FUNC_209_IDX: u32 = 209;
pub const SIG_IN_FUNC209_IDX: u32 = 209;
pub const SIG_IN_FUNC_210_IDX: u32 = 210;
pub const SIG_IN_FUNC210_IDX: u32 = 210;
pub const SIG_IN_FUNC_211_IDX: u32 = 211;
pub const SIG_IN_FUNC211_IDX: u32 = 211;
pub const SIG_IN_FUNC_212_IDX: u32 = 212;
pub const SIG_IN_FUNC212_IDX: u32 = 212;
pub const SDHOST_CDATA_IN_20_IDX: u32 = 213;
pub const SDHOST_CDATA_OUT_20_IDX: u32 = 213;
pub const SDHOST_CDATA_IN_21_IDX: u32 = 214;
pub const SDHOST_CDATA_OUT_21_IDX: u32 = 214;
pub const SDHOST_CDATA_IN_22_IDX: u32 = 215;
pub const SDHOST_CDATA_OUT_22_IDX: u32 = 215;
pub const SDHOST_CDATA_IN_23_IDX: u32 = 216;
pub const SDHOST_CDATA_OUT_23_IDX: u32 = 216;
pub const SDHOST_CDATA_IN_24_IDX: u32 = 217;
pub const SDHOST_CDATA_OUT_24_IDX: u32 = 217;
pub const SDHOST_CDATA_IN_25_IDX: u32 = 218;
pub const SDHOST_CDATA_OUT_25_IDX: u32 = 218;
pub const SDHOST_CDATA_IN_26_IDX: u32 = 219;
pub const SDHOST_CDATA_OUT_26_IDX: u32 = 219;
pub const SDHOST_CDATA_IN_27_IDX: u32 = 220;
pub const SDHOST_CDATA_OUT_27_IDX: u32 = 220;
pub const PRO_ALONEGPIO_IN0_IDX: u32 = 221;
pub const PRO_ALONEGPIO_OUT0_IDX: u32 = 221;
pub const PRO_ALONEGPIO_IN1_IDX: u32 = 222;
pub const PRO_ALONEGPIO_OUT1_IDX: u32 = 222;
pub const PRO_ALONEGPIO_IN2_IDX: u32 = 223;
pub const PRO_ALONEGPIO_OUT2_IDX: u32 = 223;
pub const PRO_ALONEGPIO_IN3_IDX: u32 = 224;
pub const PRO_ALONEGPIO_OUT3_IDX: u32 = 224;
pub const PRO_ALONEGPIO_IN4_IDX: u32 = 225;
pub const PRO_ALONEGPIO_OUT4_IDX: u32 = 225;
pub const PRO_ALONEGPIO_IN5_IDX: u32 = 226;
pub const PRO_ALONEGPIO_OUT5_IDX: u32 = 226;
pub const PRO_ALONEGPIO_IN6_IDX: u32 = 227;
pub const PRO_ALONEGPIO_OUT6_IDX: u32 = 227;
pub const PRO_ALONEGPIO_IN7_IDX: u32 = 228;
pub const PRO_ALONEGPIO_OUT7_IDX: u32 = 228;
pub const SYNCERR_IDX: u32 = 229;
pub const SYNCFOUND_FLAG_IDX: u32 = 230;
pub const EVT_CNTL_IMMEDIATE_ABORT_IDX: u32 = 231;
pub const LINKLBL_IDX: u32 = 232;
pub const DATA_EN_IDX: u32 = 233;
pub const DATA_IDX: u32 = 234;
pub const PKT_TX_ON_IDX: u32 = 235;
pub const PKT_RX_ON_IDX: u32 = 236;
pub const RW_TX_ON_IDX: u32 = 237;
pub const RW_RX_ON_IDX: u32 = 238;
pub const EVT_REQ_P_IDX: u32 = 239;
pub const EVT_STOP_P_IDX: u32 = 240;
pub const BT_MODE_ON_IDX: u32 = 241;
pub const GPIO_LC_DIAG0_IDX: u32 = 242;
pub const GPIO_LC_DIAG1_IDX: u32 = 243;
pub const GPIO_LC_DIAG2_IDX: u32 = 244;
pub const CH_IDX_IDX: u32 = 245;
pub const RX_WINDOW_IDX: u32 = 246;
pub const UPDATE_RX_IDX: u32 = 247;
pub const RX_STATUS_IDX: u32 = 248;
pub const CLK_GPIO_IDX: u32 = 249;
pub const NBT_BLE_IDX: u32 = 250;
pub const USB_JTAG_TDO_BRIDGE_IDX: u32 = 251;
pub const USB_JTAG_TRST_IDX: u32 = 251;
pub const CORE1_GPIO_IN3_IDX: u32 = 252;
pub const CORE1_GPIO_OUT3_IDX: u32 = 252;
pub const CORE1_GPIO_IN4_IDX: u32 = 253;
pub const CORE1_GPIO_OUT4_IDX: u32 = 253;
pub const CORE1_GPIO_IN5_IDX: u32 = 254;
pub const CORE1_GPIO_OUT5_IDX: u32 = 254;
pub const CORE1_GPIO_IN6_IDX: u32 = 255;
pub const CORE1_GPIO_OUT6_IDX: u32 = 255;
pub const SIG_GPIO_OUT_IDX: u32 = 256;
pub const GPIO_MAP_DATE_IDX: u32 = 26243136;
pub const GPIO_MODE_DEF_DISABLE: u32 = 0;
pub const GPIO_MODE_DEF_INPUT: u32 = 1;
pub const GPIO_MODE_DEF_OUTPUT: u32 = 2;
pub const GPIO_MODE_DEF_OD: u32 = 4;
pub const XT_USE_THREAD_SAFE_CLIB: u32 = 0;
pub const XSHAL_USE_ABSOLUTE_LITERALS: u32 = 0;
pub const XSHAL_HAVE_TEXT_SECTION_LITERALS: u32 = 1;
pub const XTHAL_ABI_WINDOWED: u32 = 0;
pub const XTHAL_ABI_CALL0: u32 = 1;
pub const XTHAL_CLIB_NEWLIB: u32 = 0;
pub const XTHAL_CLIB_UCLIBC: u32 = 1;
pub const XTHAL_CLIB_XCLIB: u32 = 2;
pub const XSHAL_USE_FLOATING_POINT: u32 = 1;
pub const XSHAL_FLOATING_POINT_ABI: u32 = 0;
pub const XSHAL_FUNC_SAFETY_ENABLED: u32 = 0;
pub const XSHAL_IOBLOCK_CACHED_VADDR: u32 = 1879048192;
pub const XSHAL_IOBLOCK_CACHED_PADDR: u32 = 1879048192;
pub const XSHAL_IOBLOCK_CACHED_SIZE: u32 = 234881024;
pub const XSHAL_IOBLOCK_BYPASS_VADDR: u32 = 2415919104;
pub const XSHAL_IOBLOCK_BYPASS_PADDR: u32 = 2415919104;
pub const XSHAL_IOBLOCK_BYPASS_SIZE: u32 = 234881024;
pub const XSHAL_ROM_VADDR: u32 = 1342177280;
pub const XSHAL_ROM_PADDR: u32 = 1342177280;
pub const XSHAL_ROM_SIZE: u32 = 16777216;
pub const XSHAL_ROM_AVAIL_VADDR: u32 = 1342177280;
pub const XSHAL_ROM_AVAIL_VSIZE: u32 = 16777216;
pub const XSHAL_RAM_VADDR: u32 = 1610612736;
pub const XSHAL_RAM_PADDR: u32 = 1610612736;
pub const XSHAL_RAM_VSIZE: u32 = 536870912;
pub const XSHAL_RAM_PSIZE: u32 = 536870912;
pub const XSHAL_RAM_SIZE: u32 = 536870912;
pub const XSHAL_RAM_AVAIL_VADDR: u32 = 1610612736;
pub const XSHAL_RAM_AVAIL_VSIZE: u32 = 536870912;
pub const XSHAL_RAM_BYPASS_VADDR: u32 = 2684354560;
pub const XSHAL_RAM_BYPASS_PADDR: u32 = 2684354560;
pub const XSHAL_RAM_BYPASS_PSIZE: u32 = 536870912;
pub const XSHAL_SIMIO_CACHED_VADDR: u32 = 3221225472;
pub const XSHAL_SIMIO_BYPASS_VADDR: u32 = 3221225472;
pub const XSHAL_SIMIO_PADDR: u32 = 3221225472;
pub const XSHAL_SIMIO_SIZE: u32 = 536870912;
pub const XSHAL_MAGIC_EXIT: u32 = 0;
pub const XSHAL_ALLVALID_CACHEATTR_WRITEBACK: u32 = 572657938;
pub const XSHAL_ALLVALID_CACHEATTR_WRITEALLOC: u32 = 572657938;
pub const XSHAL_ALLVALID_CACHEATTR_WRITETHRU: u32 = 572657938;
pub const XSHAL_ALLVALID_CACHEATTR_BYPASS: u32 = 572662306;
pub const XSHAL_ALLVALID_CACHEATTR_DEFAULT: u32 = 572657938;
pub const XSHAL_STRICT_CACHEATTR_WRITEBACK: u32 = 4294906143;
pub const XSHAL_STRICT_CACHEATTR_WRITEALLOC: u32 = 4294906143;
pub const XSHAL_STRICT_CACHEATTR_WRITETHRU: u32 = 4294906143;
pub const XSHAL_STRICT_CACHEATTR_BYPASS: u32 = 4294910511;
pub const XSHAL_STRICT_CACHEATTR_DEFAULT: u32 = 4294906143;
pub const XSHAL_TRAPNULL_CACHEATTR_WRITEBACK: u32 = 572657951;
pub const XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC: u32 = 572657951;
pub const XSHAL_TRAPNULL_CACHEATTR_WRITETHRU: u32 = 572657951;
pub const XSHAL_TRAPNULL_CACHEATTR_BYPASS: u32 = 572662319;
pub const XSHAL_TRAPNULL_CACHEATTR_DEFAULT: u32 = 572657951;
pub const XSHAL_ISS_CACHEATTR_WRITEBACK: u32 = 572657951;
pub const XSHAL_ISS_CACHEATTR_WRITEALLOC: u32 = 572657951;
pub const XSHAL_ISS_CACHEATTR_WRITETHRU: u32 = 572657951;
pub const XSHAL_ISS_CACHEATTR_BYPASS: u32 = 572662319;
pub const XSHAL_ISS_CACHEATTR_DEFAULT: u32 = 572657951;
pub const XSHAL_ISS_PIPE_REGIONS: u32 = 0;
pub const XSHAL_ISS_SDRAM_REGIONS: u32 = 0;
pub const XSHAL_XT2000_CACHEATTR_WRITEBACK: u32 = 4280422687;
pub const XSHAL_XT2000_CACHEATTR_WRITEALLOC: u32 = 4280422687;
pub const XSHAL_XT2000_CACHEATTR_WRITETHRU: u32 = 4280422687;
pub const XSHAL_XT2000_CACHEATTR_BYPASS: u32 = 4280427055;
pub const XSHAL_XT2000_CACHEATTR_DEFAULT: u32 = 4280422687;
pub const XSHAL_XT2000_PIPE_REGIONS: u32 = 0;
pub const XSHAL_XT2000_SDRAM_REGIONS: u32 = 1088;
pub const XSHAL_VECTORS_PACKED: u32 = 0;
pub const XSHAL_STATIC_VECTOR_SELECT: u32 = 1;
pub const XSHAL_RESET_VECTOR_VADDR: u32 = 1073742848;
pub const XSHAL_RESET_VECTOR_PADDR: u32 = 1073742848;
pub const XSHAL_RESET_VECTOR_SIZE: u32 = 768;
pub const XSHAL_RESET_VECTOR_ISROM: u32 = 0;
pub const XSHAL_USER_VECTOR_SIZE: u32 = 56;
pub const XSHAL_USER_VECTOR_ISROM: u32 = 0;
pub const XSHAL_PROGRAMEXC_VECTOR_SIZE: u32 = 56;
pub const XSHAL_USEREXC_VECTOR_SIZE: u32 = 56;
pub const XSHAL_KERNEL_VECTOR_SIZE: u32 = 56;
pub const XSHAL_KERNEL_VECTOR_ISROM: u32 = 0;
pub const XSHAL_STACKEDEXC_VECTOR_SIZE: u32 = 56;
pub const XSHAL_KERNELEXC_VECTOR_SIZE: u32 = 56;
pub const XSHAL_DOUBLEEXC_VECTOR_SIZE: u32 = 64;
pub const XSHAL_DOUBLEEXC_VECTOR_ISROM: u32 = 0;
pub const XSHAL_WINDOW_VECTORS_SIZE: u32 = 376;
pub const XSHAL_WINDOW_VECTORS_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL2_VECTOR_SIZE: u32 = 56;
pub const XSHAL_INTLEVEL2_VECTOR_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL3_VECTOR_SIZE: u32 = 56;
pub const XSHAL_INTLEVEL3_VECTOR_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL4_VECTOR_SIZE: u32 = 56;
pub const XSHAL_INTLEVEL4_VECTOR_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL5_VECTOR_SIZE: u32 = 56;
pub const XSHAL_INTLEVEL5_VECTOR_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL6_VECTOR_SIZE: u32 = 56;
pub const XSHAL_INTLEVEL6_VECTOR_ISROM: u32 = 0;
pub const XSHAL_DEBUG_VECTOR_SIZE: u32 = 56;
pub const XSHAL_DEBUG_VECTOR_ISROM: u32 = 0;
pub const XSHAL_NMI_VECTOR_SIZE: u32 = 56;
pub const XSHAL_NMI_VECTOR_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL7_VECTOR_SIZE: u32 = 56;
pub const XT_CP0_SA: u32 = 0;
pub const XT_CPENABLE: u32 = 0;
pub const XT_CPSTORED: u32 = 2;
pub const XT_CP_CS_ST: u32 = 4;
pub const XT_CP_ASA: u32 = 8;
pub const CORE_ID_REGVAL_PRO: u32 = 52685;
pub const CORE_ID_REGVAL_APP: u32 = 43947;
pub const CORE_ID_PRO: u32 = 52685;
pub const CORE_ID_APP: u32 = 43947;
pub const STK_INTEXC_EXTRA: u32 = 0;
pub const XT_CLIB_CONTEXT_AREA_SIZE: u32 = 0;
pub const XT_USER_SIZE: u32 = 1024;
pub const configXT_BOARD: u32 = 1;
pub const configXT_SIMULATOR: u32 = 0;
pub const configMAX_SYSCALL_INTERRUPT_PRIORITY: u32 = 3;
pub const configSTACK_ALIGNMENT: u32 = 16;
pub const configISR_STACK_SIZE: u32 = 1536;
pub const portNUM_PROCESSORS: u32 = 2;
pub const portUSING_MPU_WRAPPERS: u32 = 0;
pub const configUSE_MUTEX: u32 = 1;
pub const configNUM_THREAD_LOCAL_STORAGE_POINTERS: u32 = 1;
pub const configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS: u32 = 1;
pub const configUSE_PREEMPTION: u32 = 1;
pub const configUSE_IDLE_HOOK: u32 = 1;
pub const configUSE_TICK_HOOK: u32 = 1;
pub const configRECORD_STACK_HIGH_ADDRESS: u32 = 1;
pub const configTICK_RATE_HZ: u32 = 100;
pub const configMAX_PRIORITIES: u32 = 25;
pub const configSTACK_OVERHEAD_CHECKER: u32 = 0;
pub const configSTACK_OVERHEAD_OPTIMIZATION: u32 = 0;
pub const configSTACK_OVERHEAD_APPTRACE: u32 = 0;
pub const configSTACK_OVERHEAD_WATCHPOINT: u32 = 0;
pub const configSTACK_OVERHEAD_TOTAL: u32 = 0;
pub const configMINIMAL_STACK_SIZE: u32 = 768;
pub const configIDLE_TASK_STACK_SIZE: u32 = 1536;
pub const configAPPLICATION_ALLOCATED_HEAP: u32 = 1;
pub const configMAX_TASK_NAME_LEN: u32 = 16;
pub const configBENCHMARK: u32 = 0;
pub const configUSE_16_BIT_TICKS: u32 = 0;
pub const configIDLE_SHOULD_YIELD: u32 = 0;
pub const configQUEUE_REGISTRY_SIZE: u32 = 0;
pub const configUSE_MUTEXES: u32 = 1;
pub const configUSE_RECURSIVE_MUTEXES: u32 = 1;
pub const configUSE_COUNTING_SEMAPHORES: u32 = 1;
pub const configCHECK_FOR_STACK_OVERFLOW: u32 = 2;
pub const configUSE_CO_ROUTINES: u32 = 0;
pub const configMAX_CO_ROUTINE_PRIORITIES: u32 = 2;
pub const INCLUDE_vTaskPrioritySet: u32 = 1;
pub const INCLUDE_uxTaskPriorityGet: u32 = 1;
pub const INCLUDE_vTaskDelete: u32 = 1;
pub const INCLUDE_vTaskCleanUpResources: u32 = 0;
pub const INCLUDE_vTaskSuspend: u32 = 1;
pub const INCLUDE_vTaskDelayUntil: u32 = 1;
pub const INCLUDE_vTaskDelay: u32 = 1;
pub const INCLUDE_uxTaskGetStackHighWaterMark: u32 = 1;
pub const INCLUDE_pcTaskGetTaskName: u32 = 1;
pub const INCLUDE_xTaskGetIdleTaskHandle: u32 = 1;
pub const INCLUDE_pxTaskGetStackStart: u32 = 1;
pub const INCLUDE_eTaskGetState: u32 = 1;
pub const INCLUDE_xTaskAbortDelay: u32 = 1;
pub const INCLUDE_xTaskGetHandle: u32 = 1;
pub const INCLUDE_xSemaphoreGetMutexHolder: u32 = 1;
pub const INCLUDE_xTimerPendFunctionCall: u32 = 1;
pub const INCLUDE_xTimerGetTimerDaemonTaskHandle: u32 = 0;
pub const configKERNEL_INTERRUPT_PRIORITY: u32 = 1;
pub const configUSE_NEWLIB_REENTRANT: u32 = 1;
pub const configSUPPORT_DYNAMIC_ALLOCATION: u32 = 1;
pub const configSUPPORT_STATIC_ALLOCATION: u32 = 1;
pub const configUSE_TIMERS: u32 = 1;
pub const configTIMER_TASK_PRIORITY: u32 = 1;
pub const configTIMER_QUEUE_LENGTH: u32 = 10;
pub const configTIMER_TASK_STACK_DEPTH: u32 = 2048;
pub const configUSE_QUEUE_SETS: u32 = 1;
pub const configENABLE_TASK_SNAPSHOT: u32 = 1;
pub const configCHECK_MUTEX_GIVEN_BY_OWNER: u32 = 1;
pub const configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H: u32 = 1;
pub const configTASK_NOTIFICATION_ARRAY_ENTRIES: u32 = 1;
pub const configNUM_CORES: u32 = 2;
pub const errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY: i32 = -1;
pub const errQUEUE_BLOCKED: i32 = -4;
pub const errQUEUE_YIELD: i32 = -5;
pub const configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES: u32 = 0;
pub const pdINTEGRITY_CHECK_VALUE: u32 = 1515870810;
pub const pdFREERTOS_ERRNO_NONE: u32 = 0;
pub const pdFREERTOS_ERRNO_ENOENT: u32 = 2;
pub const pdFREERTOS_ERRNO_EINTR: u32 = 4;
pub const pdFREERTOS_ERRNO_EIO: u32 = 5;
pub const pdFREERTOS_ERRNO_ENXIO: u32 = 6;
pub const pdFREERTOS_ERRNO_EBADF: u32 = 9;
pub const pdFREERTOS_ERRNO_EAGAIN: u32 = 11;
pub const pdFREERTOS_ERRNO_EWOULDBLOCK: u32 = 11;
pub const pdFREERTOS_ERRNO_ENOMEM: u32 = 12;
pub const pdFREERTOS_ERRNO_EACCES: u32 = 13;
pub const pdFREERTOS_ERRNO_EFAULT: u32 = 14;
pub const pdFREERTOS_ERRNO_EBUSY: u32 = 16;
pub const pdFREERTOS_ERRNO_EEXIST: u32 = 17;
pub const pdFREERTOS_ERRNO_EXDEV: u32 = 18;
pub const pdFREERTOS_ERRNO_ENODEV: u32 = 19;
pub const pdFREERTOS_ERRNO_ENOTDIR: u32 = 20;
pub const pdFREERTOS_ERRNO_EISDIR: u32 = 21;
pub const pdFREERTOS_ERRNO_EINVAL: u32 = 22;
pub const pdFREERTOS_ERRNO_ENOSPC: u32 = 28;
pub const pdFREERTOS_ERRNO_ESPIPE: u32 = 29;
pub const pdFREERTOS_ERRNO_EROFS: u32 = 30;
pub const pdFREERTOS_ERRNO_EUNATCH: u32 = 42;
pub const pdFREERTOS_ERRNO_EBADE: u32 = 50;
pub const pdFREERTOS_ERRNO_EFTYPE: u32 = 79;
pub const pdFREERTOS_ERRNO_ENMFILE: u32 = 89;
pub const pdFREERTOS_ERRNO_ENOTEMPTY: u32 = 90;
pub const pdFREERTOS_ERRNO_ENAMETOOLONG: u32 = 91;
pub const pdFREERTOS_ERRNO_EOPNOTSUPP: u32 = 95;
pub const pdFREERTOS_ERRNO_ENOBUFS: u32 = 105;
pub const pdFREERTOS_ERRNO_ENOPROTOOPT: u32 = 109;
pub const pdFREERTOS_ERRNO_EADDRINUSE: u32 = 112;
pub const pdFREERTOS_ERRNO_ETIMEDOUT: u32 = 116;
pub const pdFREERTOS_ERRNO_EINPROGRESS: u32 = 119;
pub const pdFREERTOS_ERRNO_EALREADY: u32 = 120;
pub const pdFREERTOS_ERRNO_EADDRNOTAVAIL: u32 = 125;
pub const pdFREERTOS_ERRNO_EISCONN: u32 = 127;
pub const pdFREERTOS_ERRNO_ENOTCONN: u32 = 128;
pub const pdFREERTOS_ERRNO_ENOMEDIUM: u32 = 135;
pub const pdFREERTOS_ERRNO_EILSEQ: u32 = 138;
pub const pdFREERTOS_ERRNO_ECANCELED: u32 = 140;
pub const pdFREERTOS_LITTLE_ENDIAN: u32 = 0;
pub const pdFREERTOS_BIG_ENDIAN: u32 = 1;
pub const pdLITTLE_ENDIAN: u32 = 0;
pub const pdBIG_ENDIAN: u32 = 1;
pub const SPINLOCK_FREE: u32 = 3007315967;
pub const SPINLOCK_WAIT_FOREVER: i32 = -1;
pub const SPINLOCK_NO_WAIT: u32 = 0;
pub const CORE_ID_REGVAL_XOR_SWAP: u32 = 26214;
pub const MALLOC_CAP_EXEC: u32 = 1;
pub const MALLOC_CAP_32BIT: u32 = 2;
pub const MALLOC_CAP_8BIT: u32 = 4;
pub const MALLOC_CAP_DMA: u32 = 8;
pub const MALLOC_CAP_PID2: u32 = 16;
pub const MALLOC_CAP_PID3: u32 = 32;
pub const MALLOC_CAP_PID4: u32 = 64;
pub const MALLOC_CAP_PID5: u32 = 128;
pub const MALLOC_CAP_PID6: u32 = 256;
pub const MALLOC_CAP_PID7: u32 = 512;
pub const MALLOC_CAP_SPIRAM: u32 = 1024;
pub const MALLOC_CAP_INTERNAL: u32 = 2048;
pub const MALLOC_CAP_DEFAULT: u32 = 4096;
pub const MALLOC_CAP_IRAM_8BIT: u32 = 8192;
pub const MALLOC_CAP_RETENTION: u32 = 16384;
pub const MALLOC_CAP_RTCRAM: u32 = 32768;
pub const MALLOC_CAP_INVALID: u32 = 2147483648;
pub const _LIBC_LIMITS_H_: u32 = 1;
pub const ARG_MAX: u32 = 4096;
pub const CHILD_MAX: u32 = 40;
pub const LINK_MAX: u32 = 32767;
pub const MAX_CANON: u32 = 255;
pub const MAX_INPUT: u32 = 255;
pub const NAME_MAX: u32 = 255;
pub const NGROUPS_MAX: u32 = 16;
pub const OPEN_MAX: u32 = 64;
pub const PATH_MAX: u32 = 1024;
pub const PIPE_BUF: u32 = 512;
pub const IOV_MAX: u32 = 1024;
pub const BC_BASE_MAX: u32 = 99;
pub const BC_DIM_MAX: u32 = 2048;
pub const BC_SCALE_MAX: u32 = 99;
pub const BC_STRING_MAX: u32 = 1000;
pub const COLL_WEIGHTS_MAX: u32 = 0;
pub const EXPR_NEST_MAX: u32 = 32;
pub const LINE_MAX: u32 = 2048;
pub const RE_DUP_MAX: u32 = 255;
pub const MB_LEN_MAX: u32 = 1;
pub const NL_ARGMAX: u32 = 32;
pub const _POSIX2_RE_DUP_MAX: u32 = 255;
pub const portCRITICAL_NESTING_IN_TCB: u32 = 0;
pub const portSTACK_GROWTH: i32 = -1;
pub const portBYTE_ALIGNMENT: u32 = 4;
pub const portMUX_FREE_VAL: u32 = 3007315967;
pub const portMUX_NO_TIMEOUT: i32 = -1;
pub const portMUX_TRY_LOCK: u32 = 0;
pub const portTcbMemoryCaps: u32 = 2052;
pub const portStackMemoryCaps: u32 = 2052;
pub const portBYTE_ALIGNMENT_MASK: u32 = 3;
pub const portNUM_CONFIGURABLE_REGIONS: u32 = 1;
pub const portHAS_STACK_OVERFLOW_CHECKING: u32 = 0;
pub const INCLUDE_xTaskDelayUntil: u32 = 1;
pub const INCLUDE_xQueueGetMutexHolder: u32 = 0;
pub const INCLUDE_uxTaskGetStackHighWaterMark2: u32 = 0;
pub const INCLUDE_xTaskResumeFromISR: u32 = 1;
pub const INCLUDE_xTaskGetSchedulerState: u32 = 0;
pub const INCLUDE_xTaskGetCurrentTaskHandle: u32 = 0;
pub const configUSE_DAEMON_TASK_STARTUP_HOOK: u32 = 0;
pub const configUSE_APPLICATION_TASK_TAG: u32 = 0;
pub const configUSE_ALTERNATIVE_API: u32 = 0;
pub const configASSERT_DEFINED: u32 = 1;
pub const configPRECONDITION_DEFINED: u32 = 0;
pub const configGENERATE_RUN_TIME_STATS: u32 = 0;
pub const configUSE_MALLOC_FAILED_HOOK: u32 = 0;
pub const configEXPECTED_IDLE_TIME_BEFORE_SLEEP: u32 = 2;
pub const configUSE_TIME_SLICING: u32 = 1;
pub const configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS: u32 = 0;
pub const configUSE_STATS_FORMATTING_FUNCTIONS: u32 = 0;
pub const configUSE_TRACE_FACILITY: u32 = 0;
pub const configUSE_PORT_OPTIMISED_TASK_SELECTION: u32 = 0;
pub const configUSE_TASK_NOTIFICATIONS: u32 = 1;
pub const configUSE_POSIX_ERRNO: u32 = 0;
pub const portTICK_TYPE_IS_ATOMIC: u32 = 0;
pub const configSTACK_ALLOCATION_FROM_SEPARATE_HEAP: u32 = 0;
pub const configINITIAL_TICK_COUNT: u32 = 0;
pub const configENABLE_BACKWARD_COMPATIBILITY: u32 = 1;
pub const configUSE_TASK_FPU_SUPPORT: u32 = 1;
pub const configENABLE_MPU: u32 = 0;
pub const configENABLE_FPU: u32 = 1;
pub const configENABLE_TRUSTZONE: u32 = 1;
pub const configRUN_FREERTOS_SECURE_ONLY: u32 = 0;
pub const ESP_TASK_PRIO_MAX: u32 = 25;
pub const ESP_TASK_PRIO_MIN: u32 = 0;
pub const ESP_TASK_BT_CONTROLLER_PRIO: u32 = 23;
pub const TASK_EXTRA_STACK_SIZE: u32 = 512;
pub const BT_TASK_EXTRA_STACK_SIZE: u32 = 512;
pub const ESP_TASK_BT_CONTROLLER_STACK: u32 = 4096;
pub const ESP_TASK_TIMER_PRIO: u32 = 22;
pub const ESP_TASK_TIMER_STACK: u32 = 4096;
pub const ESP_TASKD_EVENT_PRIO: u32 = 20;
pub const ESP_TASKD_EVENT_STACK: u32 = 5120;
pub const ESP_TASK_TCPIP_PRIO: u32 = 18;
pub const ESP_TASK_TCPIP_STACK: u32 = 3584;
pub const ESP_TASK_MAIN_PRIO: u32 = 1;
pub const ESP_TASK_MAIN_STACK: u32 = 16512;
pub const ESP_TASK_MAIN_CORE: u32 = 0;
pub const tskKERNEL_VERSION_NUMBER: &[u8; 8usize] = b"V10.4.3\0";
pub const tskKERNEL_VERSION_MAJOR: u32 = 10;
pub const tskKERNEL_VERSION_MINOR: u32 = 4;
pub const tskKERNEL_VERSION_BUILD: u32 = 3;
pub const tskMPU_REGION_READ_ONLY: u32 = 1;
pub const tskMPU_REGION_READ_WRITE: u32 = 2;
pub const tskMPU_REGION_EXECUTE_NEVER: u32 = 4;
pub const tskMPU_REGION_NORMAL_MEMORY: u32 = 8;
pub const tskMPU_REGION_DEVICE_MEMORY: u32 = 16;
pub const tskDEFAULT_INDEX_TO_NOTIFY: u32 = 0;
pub const tskNO_AFFINITY: u32 = 2147483647;
pub const _CLOCKS_PER_SEC_: u32 = 1000;
pub const CLOCKS_PER_SEC: u32 = 1000;
pub const CLK_TCK: u32 = 1000;
pub const SIGEV_NONE: u32 = 1;
pub const SIGEV_SIGNAL: u32 = 2;
pub const SIGEV_THREAD: u32 = 3;
pub const SI_USER: u32 = 1;
pub const SI_QUEUE: u32 = 2;
pub const SI_TIMER: u32 = 3;
pub const SI_ASYNCIO: u32 = 4;
pub const SI_MESGQ: u32 = 5;
pub const SA_NOCLDSTOP: u32 = 1;
pub const MINSIGSTKSZ: u32 = 2048;
pub const SIGSTKSZ: u32 = 8192;
pub const SS_ONSTACK: u32 = 1;
pub const SS_DISABLE: u32 = 2;
pub const SIG_SETMASK: u32 = 0;
pub const SIG_BLOCK: u32 = 1;
pub const SIG_UNBLOCK: u32 = 2;
pub const SIGHUP: u32 = 1;
pub const SIGINT: u32 = 2;
pub const SIGQUIT: u32 = 3;
pub const SIGILL: u32 = 4;
pub const SIGTRAP: u32 = 5;
pub const SIGIOT: u32 = 6;
pub const SIGABRT: u32 = 6;
pub const SIGEMT: u32 = 7;
pub const SIGFPE: u32 = 8;
pub const SIGKILL: u32 = 9;
pub const SIGBUS: u32 = 10;
pub const SIGSEGV: u32 = 11;
pub const SIGSYS: u32 = 12;
pub const SIGPIPE: u32 = 13;
pub const SIGALRM: u32 = 14;
pub const SIGTERM: u32 = 15;
pub const SIGURG: u32 = 16;
pub const SIGSTOP: u32 = 17;
pub const SIGTSTP: u32 = 18;
pub const SIGCONT: u32 = 19;
pub const SIGCHLD: u32 = 20;
pub const SIGCLD: u32 = 20;
pub const SIGTTIN: u32 = 21;
pub const SIGTTOU: u32 = 22;
pub const SIGIO: u32 = 23;
pub const SIGPOLL: u32 = 23;
pub const SIGXCPU: u32 = 24;
pub const SIGXFSZ: u32 = 25;
pub const SIGVTALRM: u32 = 26;
pub const SIGPROF: u32 = 27;
pub const SIGWINCH: u32 = 28;
pub const SIGLOST: u32 = 29;
pub const SIGUSR1: u32 = 30;
pub const SIGUSR2: u32 = 31;
pub const NSIG: u32 = 32;
pub const CLOCK_ENABLED: u32 = 1;
pub const CLOCK_DISABLED: u32 = 0;
pub const CLOCK_ALLOWED: u32 = 1;
pub const CLOCK_DISALLOWED: u32 = 0;
pub const TIMER_ABSTIME: u32 = 4;
pub const ARG_REX_ICASE: u32 = 1;
pub const ETS_SIG_LEN: u32 = 384;
pub const ETS_DIGEST_LEN: u32 = 32;
pub const CRC_SIGN_BLOCK_LEN: u32 = 1196;
pub const SIG_BLOCK_PADDING: u32 = 4096;
pub const ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC: u32 = 231;
pub const SECURE_BOOT_NUM_BLOCKS: u32 = 3;
pub const MAX_KEY_DIGESTS: u32 = 3;
pub const ESP_ERR_EFUSE: i32 = 5632;
pub const ESP_OK_EFUSE_CNT: u32 = 5633;
pub const ESP_ERR_EFUSE_CNT_IS_FULL: i32 = 5634;
pub const ESP_ERR_EFUSE_REPEATED_PROG: i32 = 5635;
pub const ESP_ERR_CODING: i32 = 5636;
pub const ESP_ERR_NOT_ENOUGH_UNUSED_KEY_BLOCKS: i32 = 5637;
pub const ESP_ERR_DAMAGED_READING: i32 = 5638;
pub const MHZ: u32 = 1000000;
pub const SOC_CLK_RC_SLOW_FREQ_APPROX: u32 = 136000;
pub const RTC_SLOW_CLK_FREQ_150K: u32 = 136000;
pub const RTC_SLOW_CLK_FREQ_32K: u32 = 32768;
pub const OTHER_BLOCKS_POWERUP: u32 = 1;
pub const OTHER_BLOCKS_WAIT: u32 = 1;
pub const RTC_CNTL_DBIAS_SLP: u32 = 5;
pub const RTC_CNTL_DBIAS_0V90: u32 = 13;
pub const RTC_CNTL_DBIAS_0V95: u32 = 16;
pub const RTC_CNTL_DBIAS_1V00: u32 = 18;
pub const RTC_CNTL_DBIAS_1V05: u32 = 20;
pub const RTC_CNTL_DBIAS_1V10: u32 = 23;
pub const RTC_CNTL_DBIAS_1V15: u32 = 25;
pub const RTC_CNTL_DBIAS_1V20: u32 = 28;
pub const RTC_CNTL_DBIAS_1V25: u32 = 30;
pub const RTC_CNTL_DBIAS_1V30: u32 = 31;
pub const DELAY_FAST_CLK_SWITCH: u32 = 3;
pub const DELAY_SLOW_CLK_SWITCH: u32 = 300;
pub const DELAY_8M_ENABLE: u32 = 50;
pub const XTAL_FREQ_EST_CYCLES: u32 = 10;
pub const DIG_DBIAS_80M_160M: u32 = 30;
pub const DIG_DBIAS_240M: u32 = 30;
pub const DIG_DBIAS_XTAL: u32 = 23;
pub const DIG_DBIAS_2M: u32 = 18;
pub const RTC_CNTL_PLL_BUF_WAIT_DEFAULT: u32 = 20;
pub const RTC_CNTL_XTL_BUF_WAIT_DEFAULT: u32 = 100;
pub const RTC_CNTL_CK8M_WAIT_DEFAULT: u32 = 20;
pub const RTC_CK8M_ENABLE_WAIT_DEFAULT: u32 = 5;
pub const RTC_CNTL_XTL_BUF_WAIT_SLP_US: u32 = 250;
pub const RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES: u32 = 1;
pub const RTC_CNTL_CK8M_WAIT_SLP_CYCLES: u32 = 4;
pub const RTC_CNTL_WAKEUP_DELAY_CYCLES: u32 = 4;
pub const RTC_CNTL_CK8M_DFREQ_DEFAULT: u32 = 100;
pub const RTC_CNTL_SCK_DCAP_DEFAULT: u32 = 255;
pub const RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP: u32 = 255;
pub const RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT: u32 = 16;
pub const RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT: u32 = 5;
pub const RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP: u32 = 0;
pub const RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP: u32 = 0;
pub const RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT: u32 = 14;
pub const RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW: u32 = 15;
pub const RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT: u32 = 0;
pub const RTC_CNTL_BIASSLP_MONITOR_ON: u32 = 0;
pub const RTC_CNTL_BIASSLP_MONITOR_DEFAULT: u32 = 1;
pub const RTC_CNTL_BIASSLP_SLEEP_ON: u32 = 0;
pub const RTC_CNTL_BIASSLP_SLEEP_DEFAULT: u32 = 1;
pub const RTC_CNTL_PD_CUR_MONITOR_ON: u32 = 0;
pub const RTC_CNTL_PD_CUR_MONITOR_DEFAULT: u32 = 1;
pub const RTC_CNTL_PD_CUR_SLEEP_ON: u32 = 0;
pub const RTC_CNTL_PD_CUR_SLEEP_DEFAULT: u32 = 1;
pub const RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT: u32 = 15;
pub const RTC_FAST_CLK_FREQ_APPROX: u32 = 17500000;
pub const RTC_CLK_CAL_FRACT: u32 = 19;
pub const RTC_VDDSDIO_TIEH_1_8V: u32 = 0;
pub const RTC_VDDSDIO_TIEH_3_3V: u32 = 1;
pub const ESP_ERR_FLASH_OP_FAIL: i32 = 24577;
pub const ESP_ERR_FLASH_OP_TIMEOUT: i32 = 24578;
pub const SPI_FLASH_SEC_SIZE: u32 = 4096;
pub const SPI_FLASH_MMU_PAGE_SIZE: u32 = 65536;
pub const ESP_ERR_FLASH_NOT_INITIALISED: i32 = 24579;
pub const ESP_ERR_FLASH_UNSUPPORTED_HOST: i32 = 24580;
pub const ESP_ERR_FLASH_UNSUPPORTED_CHIP: i32 = 24581;
pub const ESP_ERR_FLASH_PROTECTED: i32 = 24582;
pub const SPI_FLASH_OPI_FLAG: u32 = 16;
pub const ESP_INTR_FLAG_LEVEL1: u32 = 2;
pub const ESP_INTR_FLAG_LEVEL2: u32 = 4;
pub const ESP_INTR_FLAG_LEVEL3: u32 = 8;
pub const ESP_INTR_FLAG_LEVEL4: u32 = 16;
pub const ESP_INTR_FLAG_LEVEL5: u32 = 32;
pub const ESP_INTR_FLAG_LEVEL6: u32 = 64;
pub const ESP_INTR_FLAG_NMI: u32 = 128;
pub const ESP_INTR_FLAG_SHARED: u32 = 256;
pub const ESP_INTR_FLAG_EDGE: u32 = 512;
pub const ESP_INTR_FLAG_IRAM: u32 = 1024;
pub const ESP_INTR_FLAG_INTRDISABLED: u32 = 2048;
pub const ESP_INTR_FLAG_LOWMED: u32 = 14;
pub const ESP_INTR_FLAG_HIGH: u32 = 240;
pub const ESP_INTR_FLAG_LEVELMASK: u32 = 254;
pub const ETS_INTERNAL_TIMER0_INTR_SOURCE: i32 = -1;
pub const ETS_INTERNAL_TIMER1_INTR_SOURCE: i32 = -2;
pub const ETS_INTERNAL_TIMER2_INTR_SOURCE: i32 = -3;
pub const ETS_INTERNAL_SW0_INTR_SOURCE: i32 = -4;
pub const ETS_INTERNAL_SW1_INTR_SOURCE: i32 = -5;
pub const ETS_INTERNAL_PROFILING_INTR_SOURCE: i32 = -6;
pub const ETS_INTERNAL_INTR_SOURCE_OFF: u32 = 6;
pub const GPIO_ID_PIN0: u32 = 0;
pub const GPIO_FUNC_IN_HIGH: u32 = 56;
pub const GPIO_FUNC_IN_LOW: u32 = 60;
pub const GPIO_PIN_COUNT: u32 = 49;
pub const ESP_EVENT_ANY_ID: i32 = -1;
pub const WIFI_OFFCHAN_TX_REQ: u32 = 1;
pub const WIFI_OFFCHAN_TX_CANCEL: u32 = 0;
pub const WIFI_ROC_REQ: u32 = 1;
pub const WIFI_ROC_CANCEL: u32 = 0;
pub const WIFI_PROTOCOL_11B: u32 = 1;
pub const WIFI_PROTOCOL_11G: u32 = 2;
pub const WIFI_PROTOCOL_11N: u32 = 4;
pub const WIFI_PROTOCOL_LR: u32 = 8;
pub const ESP_WIFI_MAX_CONN_NUM: u32 = 10;
pub const WIFI_VENDOR_IE_ELEMENT_ID: u32 = 221;
pub const WIFI_PROMIS_FILTER_MASK_ALL: u32 = 4294967295;
pub const WIFI_PROMIS_FILTER_MASK_MGMT: u32 = 1;
pub const WIFI_PROMIS_FILTER_MASK_CTRL: u32 = 2;
pub const WIFI_PROMIS_FILTER_MASK_DATA: u32 = 4;
pub const WIFI_PROMIS_FILTER_MASK_MISC: u32 = 8;
pub const WIFI_PROMIS_FILTER_MASK_DATA_MPDU: u32 = 16;
pub const WIFI_PROMIS_FILTER_MASK_DATA_AMPDU: u32 = 32;
pub const WIFI_PROMIS_FILTER_MASK_FCSFAIL: u32 = 64;
pub const WIFI_PROMIS_CTRL_FILTER_MASK_ALL: u32 = 4286578688;
pub const WIFI_PROMIS_CTRL_FILTER_MASK_WRAPPER: u32 = 8388608;
pub const WIFI_PROMIS_CTRL_FILTER_MASK_BAR: u32 = 16777216;
pub const WIFI_PROMIS_CTRL_FILTER_MASK_BA: u32 = 33554432;
pub const WIFI_PROMIS_CTRL_FILTER_MASK_PSPOLL: u32 = 67108864;
pub const WIFI_PROMIS_CTRL_FILTER_MASK_RTS: u32 = 134217728;
pub const WIFI_PROMIS_CTRL_FILTER_MASK_CTS: u32 = 268435456;
pub const WIFI_PROMIS_CTRL_FILTER_MASK_ACK: u32 = 536870912;
pub const WIFI_PROMIS_CTRL_FILTER_MASK_CFEND: u32 = 1073741824;
pub const WIFI_PROMIS_CTRL_FILTER_MASK_CFENDACK: u32 = 2147483648;
pub const WIFI_EVENT_MASK_ALL: u32 = 4294967295;
pub const WIFI_EVENT_MASK_NONE: u32 = 0;
pub const MAX_SSID_LEN: u32 = 32;
pub const MAX_PASSPHRASE_LEN: u32 = 64;
pub const MAX_WPS_AP_CRED: u32 = 3;
pub const WIFI_STATIS_BUFFER: u32 = 1;
pub const WIFI_STATIS_RXTX: u32 = 2;
pub const WIFI_STATIS_HW: u32 = 4;
pub const WIFI_STATIS_DIAG: u32 = 8;
pub const WIFI_STATIS_PS: u32 = 16;
pub const WIFI_STATIS_ALL: i32 = -1;
pub const IPSTR: &[u8; 12usize] = b"%d.%d.%d.%d\0";
pub const IPV6STR: &[u8; 40usize] = b"%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\0";
pub const ESP_IPADDR_TYPE_V4: u32 = 0;
pub const ESP_IPADDR_TYPE_V6: u32 = 6;
pub const ESP_IPADDR_TYPE_ANY: u32 = 46;
pub const ESP_ERR_ESP_NETIF_BASE: i32 = 20480;
pub const ESP_ERR_ESP_NETIF_INVALID_PARAMS: i32 = 20481;
pub const ESP_ERR_ESP_NETIF_IF_NOT_READY: i32 = 20482;
pub const ESP_ERR_ESP_NETIF_DHCPC_START_FAILED: i32 = 20483;
pub const ESP_ERR_ESP_NETIF_DHCP_ALREADY_STARTED: i32 = 20484;
pub const ESP_ERR_ESP_NETIF_DHCP_ALREADY_STOPPED: i32 = 20485;
pub const ESP_ERR_ESP_NETIF_NO_MEM: i32 = 20486;
pub const ESP_ERR_ESP_NETIF_DHCP_NOT_STOPPED: i32 = 20487;
pub const ESP_ERR_ESP_NETIF_DRIVER_ATTACH_FAILED: i32 = 20488;
pub const ESP_ERR_ESP_NETIF_INIT_FAILED: i32 = 20489;
pub const ESP_ERR_ESP_NETIF_DNS_NOT_CONFIGURED: i32 = 20490;
pub const ESP_ERR_ESP_NETIF_MLD6_FAILED: i32 = 20491;
pub const ESP_ERR_ESP_NETIF_IP6_ADDR_FAILED: i32 = 20492;
pub const ETH_CRC_LEN: u32 = 4;
pub const ETH_MAX_PAYLOAD_LEN: u32 = 1500;
pub const ETH_MIN_PAYLOAD_LEN: u32 = 46;
pub const ETH_HEADER_LEN: u32 = 14;
pub const ETH_VLAN_TAG_LEN: u32 = 4;
pub const ETH_JUMBO_FRAME_PAYLOAD_LEN: u32 = 9000;
pub const ETH_MAX_PACKET_SIZE: u32 = 1522;
pub const ETH_MIN_PACKET_SIZE: u32 = 64;
pub const ETH_MAC_FLAG_WORK_WITH_CACHE_DISABLE: u32 = 1;
pub const ETH_MAC_FLAG_PIN_TO_CORE: u32 = 2;
pub const ESP_ETH_PHY_ADDR_AUTO: i32 = -1;
pub const F_ULOCK: u32 = 0;
pub const F_LOCK: u32 = 1;
pub const F_TLOCK: u32 = 2;
pub const F_TEST: u32 = 3;
pub const F_OK: u32 = 0;
pub const R_OK: u32 = 4;
pub const W_OK: u32 = 2;
pub const X_OK: u32 = 1;
pub const STDIN_FILENO: u32 = 0;
pub const STDOUT_FILENO: u32 = 1;
pub const STDERR_FILENO: u32 = 2;
pub const _SC_ARG_MAX: u32 = 0;
pub const _SC_CHILD_MAX: u32 = 1;
pub const _SC_CLK_TCK: u32 = 2;
pub const _SC_NGROUPS_MAX: u32 = 3;
pub const _SC_OPEN_MAX: u32 = 4;
pub const _SC_JOB_CONTROL: u32 = 5;
pub const _SC_SAVED_IDS: u32 = 6;
pub const _SC_VERSION: u32 = 7;
pub const _SC_PAGESIZE: u32 = 8;
pub const _SC_PAGE_SIZE: u32 = 8;
pub const _SC_NPROCESSORS_CONF: u32 = 9;
pub const _SC_NPROCESSORS_ONLN: u32 = 10;
pub const _SC_PHYS_PAGES: u32 = 11;
pub const _SC_AVPHYS_PAGES: u32 = 12;
pub const _SC_MQ_OPEN_MAX: u32 = 13;
pub const _SC_MQ_PRIO_MAX: u32 = 14;
pub const _SC_RTSIG_MAX: u32 = 15;
pub const _SC_SEM_NSEMS_MAX: u32 = 16;
pub const _SC_SEM_VALUE_MAX: u32 = 17;
pub const _SC_SIGQUEUE_MAX: u32 = 18;
pub const _SC_TIMER_MAX: u32 = 19;
pub const _SC_TZNAME_MAX: u32 = 20;
pub const _SC_ASYNCHRONOUS_IO: u32 = 21;
pub const _SC_FSYNC: u32 = 22;
pub const _SC_MAPPED_FILES: u32 = 23;
pub const _SC_MEMLOCK: u32 = 24;
pub const _SC_MEMLOCK_RANGE: u32 = 25;
pub const _SC_MEMORY_PROTECTION: u32 = 26;
pub const _SC_MESSAGE_PASSING: u32 = 27;
pub const _SC_PRIORITIZED_IO: u32 = 28;
pub const _SC_REALTIME_SIGNALS: u32 = 29;
pub const _SC_SEMAPHORES: u32 = 30;
pub const _SC_SHARED_MEMORY_OBJECTS: u32 = 31;
pub const _SC_SYNCHRONIZED_IO: u32 = 32;
pub const _SC_TIMERS: u32 = 33;
pub const _SC_AIO_LISTIO_MAX: u32 = 34;
pub const _SC_AIO_MAX: u32 = 35;
pub const _SC_AIO_PRIO_DELTA_MAX: u32 = 36;
pub const _SC_DELAYTIMER_MAX: u32 = 37;
pub const _SC_THREAD_KEYS_MAX: u32 = 38;
pub const _SC_THREAD_STACK_MIN: u32 = 39;
pub const _SC_THREAD_THREADS_MAX: u32 = 40;
pub const _SC_TTY_NAME_MAX: u32 = 41;
pub const _SC_THREADS: u32 = 42;
pub const _SC_THREAD_ATTR_STACKADDR: u32 = 43;
pub const _SC_THREAD_ATTR_STACKSIZE: u32 = 44;
pub const _SC_THREAD_PRIORITY_SCHEDULING: u32 = 45;
pub const _SC_THREAD_PRIO_INHERIT: u32 = 46;
pub const _SC_THREAD_PRIO_PROTECT: u32 = 47;
pub const _SC_THREAD_PRIO_CEILING: u32 = 47;
pub const _SC_THREAD_PROCESS_SHARED: u32 = 48;
pub const _SC_THREAD_SAFE_FUNCTIONS: u32 = 49;
pub const _SC_GETGR_R_SIZE_MAX: u32 = 50;
pub const _SC_GETPW_R_SIZE_MAX: u32 = 51;
pub const _SC_LOGIN_NAME_MAX: u32 = 52;
pub const _SC_THREAD_DESTRUCTOR_ITERATIONS: u32 = 53;
pub const _SC_ADVISORY_INFO: u32 = 54;
pub const _SC_ATEXIT_MAX: u32 = 55;
pub const _SC_BARRIERS: u32 = 56;
pub const _SC_BC_BASE_MAX: u32 = 57;
pub const _SC_BC_DIM_MAX: u32 = 58;
pub const _SC_BC_SCALE_MAX: u32 = 59;
pub const _SC_BC_STRING_MAX: u32 = 60;
pub const _SC_CLOCK_SELECTION: u32 = 61;
pub const _SC_COLL_WEIGHTS_MAX: u32 = 62;
pub const _SC_CPUTIME: u32 = 63;
pub const _SC_EXPR_NEST_MAX: u32 = 64;
pub const _SC_HOST_NAME_MAX: u32 = 65;
pub const _SC_IOV_MAX: u32 = 66;
pub const _SC_IPV6: u32 = 67;
pub const _SC_LINE_MAX: u32 = 68;
pub const _SC_MONOTONIC_CLOCK: u32 = 69;
pub const _SC_RAW_SOCKETS: u32 = 70;
pub const _SC_READER_WRITER_LOCKS: u32 = 71;
pub const _SC_REGEXP: u32 = 72;
pub const _SC_RE_DUP_MAX: u32 = 73;
pub const _SC_SHELL: u32 = 74;
pub const _SC_SPAWN: u32 = 75;
pub const _SC_SPIN_LOCKS: u32 = 76;
pub const _SC_SPORADIC_SERVER: u32 = 77;
pub const _SC_SS_REPL_MAX: u32 = 78;
pub const _SC_SYMLOOP_MAX: u32 = 79;
pub const _SC_THREAD_CPUTIME: u32 = 80;
pub const _SC_THREAD_SPORADIC_SERVER: u32 = 81;
pub const _SC_TIMEOUTS: u32 = 82;
pub const _SC_TRACE: u32 = 83;
pub const _SC_TRACE_EVENT_FILTER: u32 = 84;
pub const _SC_TRACE_EVENT_NAME_MAX: u32 = 85;
pub const _SC_TRACE_INHERIT: u32 = 86;
pub const _SC_TRACE_LOG: u32 = 87;
pub const _SC_TRACE_NAME_MAX: u32 = 88;
pub const _SC_TRACE_SYS_MAX: u32 = 89;
pub const _SC_TRACE_USER_EVENT_MAX: u32 = 90;
pub const _SC_TYPED_MEMORY_OBJECTS: u32 = 91;
pub const _SC_V7_ILP32_OFF32: u32 = 92;
pub const _SC_V6_ILP32_OFF32: u32 = 92;
pub const _SC_XBS5_ILP32_OFF32: u32 = 92;
pub const _SC_V7_ILP32_OFFBIG: u32 = 93;
pub const _SC_V6_ILP32_OFFBIG: u32 = 93;
pub const _SC_XBS5_ILP32_OFFBIG: u32 = 93;
pub const _SC_V7_LP64_OFF64: u32 = 94;
pub const _SC_V6_LP64_OFF64: u32 = 94;
pub const _SC_XBS5_LP64_OFF64: u32 = 94;
pub const _SC_V7_LPBIG_OFFBIG: u32 = 95;
pub const _SC_V6_LPBIG_OFFBIG: u32 = 95;
pub const _SC_XBS5_LPBIG_OFFBIG: u32 = 95;
pub const _SC_XOPEN_CRYPT: u32 = 96;
pub const _SC_XOPEN_ENH_I18N: u32 = 97;
pub const _SC_XOPEN_LEGACY: u32 = 98;
pub const _SC_XOPEN_REALTIME: u32 = 99;
pub const _SC_STREAM_MAX: u32 = 100;
pub const _SC_PRIORITY_SCHEDULING: u32 = 101;
pub const _SC_XOPEN_REALTIME_THREADS: u32 = 102;
pub const _SC_XOPEN_SHM: u32 = 103;
pub const _SC_XOPEN_STREAMS: u32 = 104;
pub const _SC_XOPEN_UNIX: u32 = 105;
pub const _SC_XOPEN_VERSION: u32 = 106;
pub const _SC_2_CHAR_TERM: u32 = 107;
pub const _SC_2_C_BIND: u32 = 108;
pub const _SC_2_C_DEV: u32 = 109;
pub const _SC_2_FORT_DEV: u32 = 110;
pub const _SC_2_FORT_RUN: u32 = 111;
pub const _SC_2_LOCALEDEF: u32 = 112;
pub const _SC_2_PBS: u32 = 113;
pub const _SC_2_PBS_ACCOUNTING: u32 = 114;
pub const _SC_2_PBS_CHECKPOINT: u32 = 115;
pub const _SC_2_PBS_LOCATE: u32 = 116;
pub const _SC_2_PBS_MESSAGE: u32 = 117;
pub const _SC_2_PBS_TRACK: u32 = 118;
pub const _SC_2_SW_DEV: u32 = 119;
pub const _SC_2_UPE: u32 = 120;
pub const _SC_2_VERSION: u32 = 121;
pub const _SC_THREAD_ROBUST_PRIO_INHERIT: u32 = 122;
pub const _SC_THREAD_ROBUST_PRIO_PROTECT: u32 = 123;
pub const _SC_XOPEN_UUCP: u32 = 124;
pub const _SC_LEVEL1_ICACHE_SIZE: u32 = 125;
pub const _SC_LEVEL1_ICACHE_ASSOC: u32 = 126;
pub const _SC_LEVEL1_ICACHE_LINESIZE: u32 = 127;
pub const _SC_LEVEL1_DCACHE_SIZE: u32 = 128;
pub const _SC_LEVEL1_DCACHE_ASSOC: u32 = 129;
pub const _SC_LEVEL1_DCACHE_LINESIZE: u32 = 130;
pub const _SC_LEVEL2_CACHE_SIZE: u32 = 131;
pub const _SC_LEVEL2_CACHE_ASSOC: u32 = 132;
pub const _SC_LEVEL2_CACHE_LINESIZE: u32 = 133;
pub const _SC_LEVEL3_CACHE_SIZE: u32 = 134;
pub const _SC_LEVEL3_CACHE_ASSOC: u32 = 135;
pub const _SC_LEVEL3_CACHE_LINESIZE: u32 = 136;
pub const _SC_LEVEL4_CACHE_SIZE: u32 = 137;
pub const _SC_LEVEL4_CACHE_ASSOC: u32 = 138;
pub const _SC_LEVEL4_CACHE_LINESIZE: u32 = 139;
pub const _SC_POSIX_26_VERSION: u32 = 140;
pub const _PC_LINK_MAX: u32 = 0;
pub const _PC_MAX_CANON: u32 = 1;
pub const _PC_MAX_INPUT: u32 = 2;
pub const _PC_NAME_MAX: u32 = 3;
pub const _PC_PATH_MAX: u32 = 4;
pub const _PC_PIPE_BUF: u32 = 5;
pub const _PC_CHOWN_RESTRICTED: u32 = 6;
pub const _PC_NO_TRUNC: u32 = 7;
pub const _PC_VDISABLE: u32 = 8;
pub const _PC_ASYNC_IO: u32 = 9;
pub const _PC_PRIO_IO: u32 = 10;
pub const _PC_SYNC_IO: u32 = 11;
pub const _PC_FILESIZEBITS: u32 = 12;
pub const _PC_2_SYMLINKS: u32 = 13;
pub const _PC_SYMLINK_MAX: u32 = 14;
pub const _PC_ALLOC_SIZE_MIN: u32 = 15;
pub const _PC_REC_INCR_XFER_SIZE: u32 = 16;
pub const _PC_REC_MAX_XFER_SIZE: u32 = 17;
pub const _PC_REC_MIN_XFER_SIZE: u32 = 18;
pub const _PC_REC_XFER_ALIGN: u32 = 19;
pub const _PC_TIMESTAMP_RESOLUTION: u32 = 20;
pub const L_SET: u32 = 0;
pub const L_INCR: u32 = 1;
pub const L_XTND: u32 = 2;
pub const _FOPEN: i32 = -1;
pub const _FREAD: u32 = 1;
pub const _FWRITE: u32 = 2;
pub const _FAPPEND: u32 = 8;
pub const _FMARK: u32 = 16;
pub const _FDEFER: u32 = 32;
pub const _FASYNC: u32 = 64;
pub const _FSHLOCK: u32 = 128;
pub const _FEXLOCK: u32 = 256;
pub const _FCREAT: u32 = 512;
pub const _FTRUNC: u32 = 1024;
pub const _FEXCL: u32 = 2048;
pub const _FNBIO: u32 = 4096;
pub const _FSYNC: u32 = 8192;
pub const _FNONBLOCK: u32 = 16384;
pub const _FNDELAY: u32 = 16384;
pub const _FNOCTTY: u32 = 32768;
pub const _FNOINHERIT: u32 = 262144;
pub const _FDIRECT: u32 = 524288;
pub const _FNOFOLLOW: u32 = 1048576;
pub const _FDIRECTORY: u32 = 2097152;
pub const _FEXECSRCH: u32 = 4194304;
pub const O_RDONLY: u32 = 0;
pub const O_WRONLY: u32 = 1;
pub const O_RDWR: u32 = 2;
pub const O_APPEND: u32 = 8;
pub const O_CREAT: u32 = 512;
pub const O_TRUNC: u32 = 1024;
pub const O_EXCL: u32 = 2048;
pub const O_SYNC: u32 = 8192;
pub const O_NONBLOCK: u32 = 16384;
pub const O_NOCTTY: u32 = 32768;
pub const O_CLOEXEC: u32 = 262144;
pub const O_NOFOLLOW: u32 = 1048576;
pub const O_DIRECTORY: u32 = 2097152;
pub const O_EXEC: u32 = 4194304;
pub const O_SEARCH: u32 = 4194304;
pub const O_DIRECT: u32 = 524288;
pub const FAPPEND: u32 = 8;
pub const FSYNC: u32 = 8192;
pub const FASYNC: u32 = 64;
pub const FNBIO: u32 = 4096;
pub const FNONBIO: u32 = 16384;
pub const FNDELAY: u32 = 16384;
pub const FREAD: u32 = 1;
pub const FWRITE: u32 = 2;
pub const FMARK: u32 = 16;
pub const FDEFER: u32 = 32;
pub const FSHLOCK: u32 = 128;
pub const FEXLOCK: u32 = 256;
pub const FOPEN: i32 = -1;
pub const FCREAT: u32 = 512;
pub const FTRUNC: u32 = 1024;
pub const FEXCL: u32 = 2048;
pub const FNOCTTY: u32 = 32768;
pub const FNONBLOCK: u32 = 16384;
pub const FD_CLOEXEC: u32 = 1;
pub const F_DUPFD: u32 = 0;
pub const F_GETFD: u32 = 1;
pub const F_SETFD: u32 = 2;
pub const F_GETFL: u32 = 3;
pub const F_SETFL: u32 = 4;
pub const F_GETOWN: u32 = 5;
pub const F_SETOWN: u32 = 6;
pub const F_GETLK: u32 = 7;
pub const F_SETLK: u32 = 8;
pub const F_SETLKW: u32 = 9;
pub const F_RGETLK: u32 = 10;
pub const F_RSETLK: u32 = 11;
pub const F_CNVT: u32 = 12;
pub const F_RSETLKW: u32 = 13;
pub const F_DUPFD_CLOEXEC: u32 = 14;
pub const F_RDLCK: u32 = 1;
pub const F_WRLCK: u32 = 2;
pub const F_UNLCK: u32 = 3;
pub const F_UNLKSYS: u32 = 4;
pub const AT_FDCWD: i32 = -2;
pub const AT_EACCESS: u32 = 1;
pub const AT_SYMLINK_NOFOLLOW: u32 = 2;
pub const AT_SYMLINK_FOLLOW: u32 = 4;
pub const AT_REMOVEDIR: u32 = 8;
pub const LOCK_SH: u32 = 1;
pub const LOCK_EX: u32 = 2;
pub const LOCK_NB: u32 = 4;
pub const LOCK_UN: u32 = 8;
pub const _IFMT: u32 = 61440;
pub const _IFDIR: u32 = 16384;
pub const _IFCHR: u32 = 8192;
pub const _IFBLK: u32 = 24576;
pub const _IFREG: u32 = 32768;
pub const _IFLNK: u32 = 40960;
pub const _IFSOCK: u32 = 49152;
pub const _IFIFO: u32 = 4096;
pub const S_BLKSIZE: u32 = 1024;
pub const S_ISUID: u32 = 2048;
pub const S_ISGID: u32 = 1024;
pub const S_ISVTX: u32 = 512;
pub const S_IREAD: u32 = 256;
pub const S_IWRITE: u32 = 128;
pub const S_IEXEC: u32 = 64;
pub const S_ENFMT: u32 = 1024;
pub const S_IFMT: u32 = 61440;
pub const S_IFDIR: u32 = 16384;
pub const S_IFCHR: u32 = 8192;
pub const S_IFBLK: u32 = 24576;
pub const S_IFREG: u32 = 32768;
pub const S_IFLNK: u32 = 40960;
pub const S_IFSOCK: u32 = 49152;
pub const S_IFIFO: u32 = 4096;
pub const S_IRUSR: u32 = 256;
pub const S_IWUSR: u32 = 128;
pub const S_IXUSR: u32 = 64;
pub const S_IRGRP: u32 = 32;
pub const S_IWGRP: u32 = 16;
pub const S_IXGRP: u32 = 8;
pub const S_IROTH: u32 = 4;
pub const S_IWOTH: u32 = 2;
pub const S_IXOTH: u32 = 1;
pub const DEFFILEMODE: u32 = 438;
pub const SYS_LIGHTWEIGHT_PROT: u32 = 1;
pub const MEM_LIBC_MALLOC: u32 = 1;
pub const MEMP_MEM_MALLOC: u32 = 1;
pub const MEM_ALIGNMENT: u32 = 4;
pub const MEMP_NUM_NETCONN: u32 = 10;
pub const MEMP_NUM_RAW_PCB: u32 = 16;
pub const MEMP_NUM_TCP_PCB: u32 = 16;
pub const MEMP_NUM_TCP_PCB_LISTEN: u32 = 16;
pub const MEMP_NUM_UDP_PCB: u32 = 16;
pub const ARP_QUEUEING: u32 = 1;
pub const IP_FRAG: u32 = 1;
pub const LWIP_IPV6_FRAG: u32 = 1;
pub const IP_REASS_MAXAGE: u32 = 3;
pub const IP_REASS_MAX_PBUFS: u32 = 10;
pub const LWIP_ICMP: u32 = 1;
pub const LWIP_RAW: u32 = 1;
pub const LWIP_DHCP: u32 = 1;
pub const DHCP_MAXRTX: u32 = 0;
pub const DHCP_DOES_ARP_CHECK: u32 = 1;
pub const DHCP_OPTIONS_LEN: u32 = 68;
pub const ESP_DHCP_DISABLE_VENDOR_CLASS_IDENTIFIER: u32 = 1;
pub const LWIP_IGMP: u32 = 1;
pub const LWIP_DNS: u32 = 1;
pub const DNS_MAX_SERVERS: u32 = 3;
pub const DNS_FALLBACK_SERVER_INDEX: u32 = 2;
pub const TCP_QUEUE_OOSEQ: u32 = 1;
pub const TCP_MSS: u32 = 1440;
pub const TCP_TMR_INTERVAL: u32 = 250;
pub const TCP_MSL: u32 = 60000;
pub const TCP_MAXRTX: u32 = 12;
pub const TCP_SYNMAXRTX: u32 = 12;
pub const TCP_LISTEN_BACKLOG: u32 = 1;
pub const TCP_OVERSIZE: u32 = 1440;
pub const LWIP_TCP_RTO_TIME: u32 = 1500;
pub const LWIP_NETIF_HOSTNAME: u32 = 1;
pub const LWIP_NETIF_TX_SINGLE_PBUF: u32 = 1;
pub const LWIP_NETIF_LOOPBACK: u32 = 1;
pub const LWIP_LOOPBACK_MAX_PBUFS: u32 = 8;
pub const TCPIP_THREAD_NAME: &[u8; 4usize] = b"tiT\0";
pub const TCPIP_THREAD_STACKSIZE: u32 = 3584;
pub const TCPIP_THREAD_PRIO: u32 = 18;
pub const TCPIP_MBOX_SIZE: u32 = 32;
pub const DEFAULT_UDP_RECVMBOX_SIZE: u32 = 6;
pub const DEFAULT_TCP_RECVMBOX_SIZE: u32 = 6;
pub const DEFAULT_ACCEPTMBOX_SIZE: u32 = 6;
pub const DEFAULT_THREAD_STACKSIZE: u32 = 3584;
pub const DEFAULT_THREAD_PRIO: u32 = 18;
pub const DEFAULT_RAW_RECVMBOX_SIZE: u32 = 6;
pub const LWIP_SO_SNDTIMEO: u32 = 1;
pub const LWIP_SO_RCVTIMEO: u32 = 1;
pub const LWIP_TCP_KEEPALIVE: u32 = 1;
pub const SO_REUSE: u32 = 1;
pub const LWIP_DNS_SUPPORT_MDNS_QUERIES: u32 = 1;
pub const SO_REUSE_RXTOALL: u32 = 1;
pub const LWIP_IPV6: u32 = 1;
pub const MEMP_NUM_ND6_QUEUE: u32 = 3;
pub const LWIP_ND6_NUM_NEIGHBORS: u32 = 5;
pub const LWIP_HOOK_FILENAME: &[u8; 21usize] = b"lwip_default_hooks.h\0";
pub const LWIP_POSIX_SOCKETS_IO_NAMES: u32 = 0;
pub const LWIP_SOCKET_OFFSET: u32 = 54;
pub const LWIP_IPV6_NUM_ADDRESSES: u32 = 3;
pub const ESP_LWIP: u32 = 1;
pub const ESP_LWIP_ARP: u32 = 1;
pub const ESP_PER_SOC_TCP_WND: u32 = 0;
pub const ESP_THREAD_SAFE: u32 = 1;
pub const ESP_DHCP: u32 = 1;
pub const ESP_DNS: u32 = 1;
pub const ESP_PERF: u32 = 0;
pub const ESP_RANDOM_TCP_PORT: u32 = 1;
pub const ESP_IP4_ATON: u32 = 1;
pub const ESP_LIGHT_SLEEP: u32 = 1;
pub const ESP_STATS_TCP: u32 = 0;
pub const ESP_DHCPS: u32 = 1;
pub const ESP_DHCPS_TIMER: u32 = 1;
pub const ESP_PING: u32 = 1;
pub const ESP_HAS_SELECT: u32 = 1;
pub const ESP_AUTO_RECV: u32 = 1;
pub const ESP_GRATUITOUS_ARP: u32 = 1;
pub const ESP_IP4_ROUTE: u32 = 1;
pub const ESP_AUTO_IP: u32 = 1;
pub const ESP_PBUF: u32 = 1;
pub const ESP_PPP: u32 = 1;
pub const ESP_IPV6: u32 = 1;
pub const ESP_SOCKET: u32 = 1;
pub const ESP_LWIP_SELECT: u32 = 1;
pub const ESP_LWIP_LOCK: u32 = 1;
pub const ESP_THREAD_PROTECTION: u32 = 1;
pub const ESP_IP_FORWARD: u32 = 1;
pub const ESP_LWIP_IGMP_TIMERS_ONDEMAND: u32 = 1;
pub const ESP_LWIP_MLD6_TIMERS_ONDEMAND: u32 = 1;
pub const TCP_SND_BUF: u32 = 5744;
pub const TCP_WND: u32 = 5744;
pub const CHECKSUM_CHECK_ICMP: u32 = 1;
pub const LWIP_NETCONN_FULLDUPLEX: u32 = 1;
pub const LWIP_NETCONN_SEM_PER_THREAD: u32 = 1;
pub const LWIP_TIMEVAL_PRIVATE: u32 = 0;
pub const SNTP_MAX_SERVERS: u32 = 1;
pub const SNTP_SERVER_DNS: u32 = 1;
pub const __error_t_defined: u32 = 1;
pub const EPERM: u32 = 1;
pub const ENOENT: u32 = 2;
pub const ESRCH: u32 = 3;
pub const EINTR: u32 = 4;
pub const EIO: u32 = 5;
pub const ENXIO: u32 = 6;
pub const E2BIG: u32 = 7;
pub const ENOEXEC: u32 = 8;
pub const EBADF: u32 = 9;
pub const ECHILD: u32 = 10;
pub const EAGAIN: u32 = 11;
pub const ENOMEM: u32 = 12;
pub const EACCES: u32 = 13;
pub const EFAULT: u32 = 14;
pub const EBUSY: u32 = 16;
pub const EEXIST: u32 = 17;
pub const EXDEV: u32 = 18;
pub const ENODEV: u32 = 19;
pub const ENOTDIR: u32 = 20;
pub const EISDIR: u32 = 21;
pub const EINVAL: u32 = 22;
pub const ENFILE: u32 = 23;
pub const EMFILE: u32 = 24;
pub const ENOTTY: u32 = 25;
pub const ETXTBSY: u32 = 26;
pub const EFBIG: u32 = 27;
pub const ENOSPC: u32 = 28;
pub const ESPIPE: u32 = 29;
pub const EROFS: u32 = 30;
pub const EMLINK: u32 = 31;
pub const EPIPE: u32 = 32;
pub const EDOM: u32 = 33;
pub const ERANGE: u32 = 34;
pub const ENOMSG: u32 = 35;
pub const EIDRM: u32 = 36;
pub const EDEADLK: u32 = 45;
pub const ENOLCK: u32 = 46;
pub const ENOSTR: u32 = 60;
pub const ENODATA: u32 = 61;
pub const ETIME: u32 = 62;
pub const ENOSR: u32 = 63;
pub const ENOLINK: u32 = 67;
pub const EPROTO: u32 = 71;
pub const EMULTIHOP: u32 = 74;
pub const EBADMSG: u32 = 77;
pub const EFTYPE: u32 = 79;
pub const ENOSYS: u32 = 88;
pub const ENOTEMPTY: u32 = 90;
pub const ENAMETOOLONG: u32 = 91;
pub const ELOOP: u32 = 92;
pub const EOPNOTSUPP: u32 = 95;
pub const EPFNOSUPPORT: u32 = 96;
pub const ECONNRESET: u32 = 104;
pub const ENOBUFS: u32 = 105;
pub const EAFNOSUPPORT: u32 = 106;
pub const EPROTOTYPE: u32 = 107;
pub const ENOTSOCK: u32 = 108;
pub const ENOPROTOOPT: u32 = 109;
pub const ECONNREFUSED: u32 = 111;
pub const EADDRINUSE: u32 = 112;
pub const ECONNABORTED: u32 = 113;
pub const ENETUNREACH: u32 = 114;
pub const ENETDOWN: u32 = 115;
pub const ETIMEDOUT: u32 = 116;
pub const EHOSTDOWN: u32 = 117;
pub const EHOSTUNREACH: u32 = 118;
pub const EINPROGRESS: u32 = 119;
pub const EALREADY: u32 = 120;
pub const EDESTADDRREQ: u32 = 121;
pub const EMSGSIZE: u32 = 122;
pub const EPROTONOSUPPORT: u32 = 123;
pub const EADDRNOTAVAIL: u32 = 125;
pub const ENETRESET: u32 = 126;
pub const EISCONN: u32 = 127;
pub const ENOTCONN: u32 = 128;
pub const ETOOMANYREFS: u32 = 129;
pub const EDQUOT: u32 = 132;
pub const ESTALE: u32 = 133;
pub const ENOTSUP: u32 = 134;
pub const EILSEQ: u32 = 138;
pub const EOVERFLOW: u32 = 139;
pub const ECANCELED: u32 = 140;
pub const ENOTRECOVERABLE: u32 = 141;
pub const EOWNERDEAD: u32 = 142;
pub const EWOULDBLOCK: u32 = 11;
pub const __ELASTERROR: u32 = 2000;
pub const ESHUTDOWN: u32 = 110;
pub const EAI_SOCKTYPE: u32 = 10;
pub const EAI_AGAIN: u32 = 2;
pub const EAI_BADFLAGS: u32 = 3;
pub const ERR_NEED_SCHED: u32 = 123;
pub const LWIP_COMPAT_MUTEX: u32 = 0;
pub const S16_F: &[u8; 2usize] = b"d\0";
pub const U16_F: &[u8; 2usize] = b"d\0";
pub const X16_F: &[u8; 2usize] = b"x\0";
pub const S32_F: &[u8; 2usize] = b"d\0";
pub const U32_F: &[u8; 2usize] = b"u\0";
pub const X32_F: &[u8; 2usize] = b"x\0";
pub const LWIP_NO_STDDEF_H: u32 = 0;
pub const LWIP_NO_STDINT_H: u32 = 0;
pub const LWIP_HAVE_INT64: u32 = 1;
pub const LWIP_NO_INTTYPES_H: u32 = 0;
pub const LWIP_NO_LIMITS_H: u32 = 0;
pub const LWIP_UINT32_MAX: u32 = 4294967295;
pub const LWIP_NO_CTYPE_H: u32 = 0;
pub const _U: u32 = 1;
pub const _L: u32 = 2;
pub const _N: u32 = 4;
pub const _S: u32 = 8;
pub const _P: u32 = 16;
pub const _C: u32 = 32;
pub const _X: u32 = 64;
pub const _B: u32 = 128;
pub const LWIP_DBG_LEVEL_ALL: u32 = 0;
pub const LWIP_DBG_LEVEL_WARNING: u32 = 1;
pub const LWIP_DBG_LEVEL_SERIOUS: u32 = 2;
pub const LWIP_DBG_LEVEL_SEVERE: u32 = 3;
pub const LWIP_DBG_MASK_LEVEL: u32 = 3;
pub const LWIP_DBG_LEVEL_OFF: u32 = 0;
pub const LWIP_DBG_ON: u32 = 128;
pub const LWIP_DBG_OFF: u32 = 0;
pub const LWIP_DBG_TRACE: u32 = 64;
pub const LWIP_DBG_STATE: u32 = 32;
pub const LWIP_DBG_FRESH: u32 = 16;
pub const LWIP_DBG_HALT: u32 = 8;
pub const NO_SYS: u32 = 0;
pub const LWIP_TIMERS: u32 = 1;
pub const LWIP_TIMERS_CUSTOM: u32 = 0;
pub const LWIP_MPU_COMPATIBLE: u32 = 0;
pub const LWIP_TCPIP_CORE_LOCKING_INPUT: u32 = 0;
pub const MEMP_MEM_INIT: u32 = 0;
pub const MEM_SIZE: u32 = 1600;
pub const MEMP_OVERFLOW_CHECK: u32 = 0;
pub const MEMP_SANITY_CHECK: u32 = 0;
pub const MEM_OVERFLOW_CHECK: u32 = 0;
pub const MEM_SANITY_CHECK: u32 = 0;
pub const MEM_USE_POOLS: u32 = 0;
pub const MEM_USE_POOLS_TRY_BIGGER_POOL: u32 = 0;
pub const MEMP_USE_CUSTOM_POOLS: u32 = 0;
pub const LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT: u32 = 0;
pub const MEMP_NUM_PBUF: u32 = 16;
pub const MEMP_NUM_TCP_SEG: u32 = 16;
pub const MEMP_NUM_ALTCP_PCB: u32 = 16;
pub const MEMP_NUM_REASSDATA: u32 = 5;
pub const MEMP_NUM_FRAG_PBUF: u32 = 15;
pub const MEMP_NUM_ARP_QUEUE: u32 = 30;
pub const MEMP_NUM_IGMP_GROUP: u32 = 8;
pub const MEMP_NUM_NETBUF: u32 = 2;
pub const MEMP_NUM_SELECT_CB: u32 = 4;
pub const MEMP_NUM_TCPIP_MSG_API: u32 = 8;
pub const MEMP_NUM_TCPIP_MSG_INPKT: u32 = 8;
pub const MEMP_NUM_NETDB: u32 = 1;
pub const MEMP_NUM_LOCALHOSTLIST: u32 = 1;
pub const PBUF_POOL_SIZE: u32 = 16;
pub const MEMP_NUM_API_MSG: u32 = 8;
pub const MEMP_NUM_DNS_API_MSG: u32 = 8;
pub const MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA: u32 = 8;
pub const MEMP_NUM_NETIFAPI_MSG: u32 = 8;
pub const LWIP_ARP: u32 = 1;
pub const ARP_TABLE_SIZE: u32 = 10;
pub const ARP_MAXAGE: u32 = 300;
pub const ARP_QUEUE_LEN: u32 = 3;
pub const ETHARP_SUPPORT_VLAN: u32 = 0;
pub const LWIP_ETHERNET: u32 = 1;
pub const ETH_PAD_SIZE: u32 = 0;
pub const ETHARP_SUPPORT_STATIC_ENTRIES: u32 = 0;
pub const LWIP_IPV4: u32 = 1;
pub const IP_OPTIONS_ALLOWED: u32 = 1;
pub const IP_DEFAULT_TTL: u32 = 255;
pub const IP_SOF_BROADCAST: u32 = 0;
pub const IP_SOF_BROADCAST_RECV: u32 = 0;
pub const IP_FORWARD_ALLOW_TX_ON_RX_NETIF: u32 = 0;
pub const ICMP_TTL: u32 = 255;
pub const RAW_TTL: u32 = 255;
pub const LWIP_DHCP_BOOTP_FILE: u32 = 0;
pub const LWIP_DHCP_GET_NTP_SRV: u32 = 0;
pub const LWIP_DHCP_MAX_DNS_SERVERS: u32 = 3;
pub const LWIP_AUTOIP: u32 = 0;
pub const LWIP_DHCP_AUTOIP_COOP: u32 = 0;
pub const ESP_IPV6_AUTOCONFIG: u32 = 0;
pub const LWIP_DHCP_AUTOIP_COOP_TRIES: u32 = 9;
pub const LWIP_MIB2_CALLBACKS: u32 = 0;
pub const DNS_TABLE_SIZE: u32 = 4;
pub const DNS_MAX_NAME_LENGTH: u32 = 256;
pub const DNS_MAX_RETRIES: u32 = 4;
pub const DNS_DOES_NAME_CHECK: u32 = 1;
pub const LWIP_DNS_SECURE_RAND_XID: u32 = 1;
pub const LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING: u32 = 2;
pub const LWIP_DNS_SECURE_RAND_SRC_PORT: u32 = 4;
pub const DNS_LOCAL_HOSTLIST: u32 = 0;
pub const DNS_LOCAL_HOSTLIST_IS_DYNAMIC: u32 = 0;
pub const LWIP_UDP: u32 = 1;
pub const LWIP_UDPLITE: u32 = 0;
pub const UDP_TTL: u32 = 255;
pub const LWIP_TCP: u32 = 1;
pub const TCP_TTL: u32 = 255;
pub const LWIP_TCP_MAX_SACK_NUM: u32 = 4;
pub const TCP_CALCULATE_EFF_SEND_MSS: u32 = 1;
pub const TCP_SND_QUEUELEN: u32 = 16;
pub const TCP_OOSEQ_MAX_BYTES: u32 = 0;
pub const TCP_OOSEQ_MAX_PBUFS: u32 = 0;
pub const TCP_DEFAULT_LISTEN_BACKLOG: u32 = 255;
pub const LWIP_TCP_TIMESTAMPS: u32 = 0;
pub const LWIP_EVENT_API: u32 = 0;
pub const LWIP_CALLBACK_API: u32 = 1;
pub const LWIP_WND_SCALE: u32 = 0;
pub const TCP_RCV_SCALE: u32 = 0;
pub const LWIP_TCP_PCB_NUM_EXT_ARGS: u32 = 0;
pub const LWIP_ALTCP: u32 = 0;
pub const LWIP_ALTCP_TLS: u32 = 0;
pub const PBUF_LINK_HLEN: u32 = 14;
pub const PBUF_LINK_ENCAPSULATION_HLEN: u32 = 0;
pub const LWIP_SINGLE_NETIF: u32 = 0;
pub const LWIP_NETIF_EXT_STATUS_CALLBACK: u32 = 0;
pub const LWIP_NETIF_LINK_CALLBACK: u32 = 0;
pub const LWIP_NETIF_REMOVE_CALLBACK: u32 = 0;
pub const LWIP_NETIF_HWADDRHINT: u32 = 0;
pub const LWIP_NUM_NETIF_CLIENT_DATA: u32 = 0;
pub const LWIP_LOOPIF_MULTICAST: u32 = 0;
pub const SLIPIF_THREAD_NAME: &[u8; 12usize] = b"slipif_loop\0";
pub const SLIPIF_THREAD_STACKSIZE: u32 = 0;
pub const SLIPIF_THREAD_PRIO: u32 = 1;
pub const DEFAULT_THREAD_NAME: &[u8; 5usize] = b"lwIP\0";
pub const LWIP_NETCONN: u32 = 1;
pub const LWIP_TCPIP_TIMEOUT: u32 = 0;
pub const LWIP_SOCKET: u32 = 1;
pub const LWIP_COMPAT_SOCKETS: u32 = 1;
pub const LWIP_SO_SNDRCVTIMEO_NONSTANDARD: u32 = 0;
pub const LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT: u32 = 20000;
pub const LWIP_FIONREAD_LINUXMODE: u32 = 0;
pub const LWIP_SOCKET_SELECT: u32 = 1;
pub const LWIP_SOCKET_POLL: u32 = 1;
pub const LINK_STATS: u32 = 0;
pub const ETHARP_STATS: u32 = 0;
pub const IP_STATS: u32 = 0;
pub const IPFRAG_STATS: u32 = 0;
pub const ICMP_STATS: u32 = 0;
pub const IGMP_STATS: u32 = 0;
pub const UDP_STATS: u32 = 0;
pub const TCP_STATS: u32 = 0;
pub const MEM_STATS: u32 = 0;
pub const MEMP_STATS: u32 = 0;
pub const SYS_STATS: u32 = 0;
pub const LWIP_STATS_DISPLAY: u32 = 0;
pub const IP6_STATS: u32 = 0;
pub const ICMP6_STATS: u32 = 0;
pub const IP6_FRAG_STATS: u32 = 0;
pub const MLD6_STATS: u32 = 0;
pub const ND6_STATS: u32 = 0;
pub const MIB2_STATS: u32 = 0;
pub const LWIP_CHECKSUM_CTRL_PER_NETIF: u32 = 0;
pub const CHECKSUM_GEN_IP: u32 = 1;
pub const CHECKSUM_GEN_UDP: u32 = 1;
pub const CHECKSUM_GEN_TCP: u32 = 1;
pub const CHECKSUM_GEN_ICMP: u32 = 1;
pub const CHECKSUM_GEN_ICMP6: u32 = 1;
pub const CHECKSUM_CHECK_TCP: u32 = 1;
pub const CHECKSUM_CHECK_ICMP6: u32 = 1;
pub const LWIP_CHECKSUM_ON_COPY: u32 = 0;
pub const IPV6_REASS_MAXAGE: u32 = 60;
pub const LWIP_IPV6_SCOPES_DEBUG: u32 = 0;
pub const LWIP_IPV6_SEND_ROUTER_SOLICIT: u32 = 1;
pub const LWIP_IPV6_AUTOCONFIG: u32 = 1;
pub const LWIP_IPV6_ADDRESS_LIFETIMES: u32 = 1;
pub const LWIP_IPV6_DUP_DETECT_ATTEMPTS: u32 = 1;
pub const LWIP_ICMP6: u32 = 1;
pub const LWIP_ICMP6_DATASIZE: u32 = 0;
pub const LWIP_ICMP6_HL: u32 = 255;
pub const LWIP_IPV6_MLD: u32 = 1;
pub const MEMP_NUM_MLD6_GROUP: u32 = 4;
pub const LWIP_ND6_QUEUEING: u32 = 1;
pub const ESP_ND6_QUEUEING: u32 = 1;
pub const LWIP_ND6_NUM_DESTINATIONS: u32 = 10;
pub const LWIP_ND6_NUM_PREFIXES: u32 = 5;
pub const LWIP_ND6_NUM_ROUTERS: u32 = 3;
pub const LWIP_ND6_MAX_MULTICAST_SOLICIT: u32 = 3;
pub const LWIP_ND6_MAX_UNICAST_SOLICIT: u32 = 3;
pub const LWIP_ND6_MAX_ANYCAST_DELAY_TIME: u32 = 1000;
pub const LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT: u32 = 3;
pub const LWIP_ND6_REACHABLE_TIME: u32 = 30000;
pub const LWIP_ND6_RETRANS_TIMER: u32 = 1000;
pub const LWIP_ND6_DELAY_FIRST_PROBE_TIME: u32 = 5000;
pub const LWIP_ND6_ALLOW_RA_UPDATES: u32 = 1;
pub const LWIP_ND6_TCP_REACHABILITY_HINTS: u32 = 1;
pub const LWIP_IPV6_DHCP6_STATEFUL: u32 = 0;
pub const LWIP_DHCP6_GET_NTP_SRV: u32 = 0;
pub const LWIP_DHCP6_MAX_NTP_SERVERS: u32 = 1;
pub const LWIP_DHCP6_MAX_DNS_SERVERS: u32 = 3;
pub const LWIP_DBG_MIN_LEVEL: u32 = 0;
pub const LWIP_DBG_TYPES_ON: u32 = 128;
pub const API_MSG_DEBUG: u32 = 0;
pub const IGMP_DEBUG: u32 = 0;
pub const INET_DEBUG: u32 = 0;
pub const IP_REASS_DEBUG: u32 = 0;
pub const RAW_DEBUG: u32 = 0;
pub const MEM_DEBUG: u32 = 0;
pub const SYS_DEBUG: u32 = 0;
pub const TIMERS_DEBUG: u32 = 0;
pub const TCP_FR_DEBUG: u32 = 0;
pub const TCP_RTO_DEBUG: u32 = 0;
pub const TCP_CWND_DEBUG: u32 = 0;
pub const TCP_WND_DEBUG: u32 = 0;
pub const TCP_RST_DEBUG: u32 = 0;
pub const TCP_QLEN_DEBUG: u32 = 0;
pub const UDP_DEBUG: u32 = 0;
pub const SLIP_DEBUG: u32 = 0;
pub const AUTOIP_DEBUG: u32 = 0;
pub const DNS_DEBUG: u32 = 0;
pub const DHCP6_DEBUG: u32 = 0;
pub const LWIP_TESTMODE: u32 = 0;
pub const NAPT_DEBUG: u32 = 0;
pub const LWIP_PERF: u32 = 0;
pub const IP_CLASSA_NET: u32 = 4278190080;
pub const IP_CLASSA_NSHIFT: u32 = 24;
pub const IP_CLASSA_HOST: u32 = 16777215;
pub const IP_CLASSA_MAX: u32 = 128;
pub const IP_CLASSB_NET: u32 = 4294901760;
pub const IP_CLASSB_NSHIFT: u32 = 16;
pub const IP_CLASSB_HOST: u32 = 65535;
pub const IP_CLASSB_MAX: u32 = 65536;
pub const IP_CLASSC_NET: u32 = 4294967040;
pub const IP_CLASSC_NSHIFT: u32 = 8;
pub const IP_CLASSC_HOST: u32 = 255;
pub const IP_CLASSD_NET: u32 = 4026531840;
pub const IP_CLASSD_NSHIFT: u32 = 28;
pub const IP_CLASSD_HOST: u32 = 268435455;
pub const IP_LOOPBACKNET: u32 = 127;
pub const IP4ADDR_STRLEN_MAX: u32 = 16;
pub const IP6_NO_ZONE: u32 = 0;
pub const IPV6_CUSTOM_SCOPES: u32 = 0;
pub const IP6_MULTICAST_SCOPE_RESERVED: u32 = 0;
pub const IP6_MULTICAST_SCOPE_RESERVED0: u32 = 0;
pub const IP6_MULTICAST_SCOPE_INTERFACE_LOCAL: u32 = 1;
pub const IP6_MULTICAST_SCOPE_LINK_LOCAL: u32 = 2;
pub const IP6_MULTICAST_SCOPE_RESERVED3: u32 = 3;
pub const IP6_MULTICAST_SCOPE_ADMIN_LOCAL: u32 = 4;
pub const IP6_MULTICAST_SCOPE_SITE_LOCAL: u32 = 5;
pub const IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL: u32 = 8;
pub const IP6_MULTICAST_SCOPE_GLOBAL: u32 = 14;
pub const IP6_MULTICAST_SCOPE_RESERVEDF: u32 = 15;
pub const IP6_ADDR_INVALID: u32 = 0;
pub const IP6_ADDR_TENTATIVE: u32 = 8;
pub const IP6_ADDR_TENTATIVE_1: u32 = 9;
pub const IP6_ADDR_TENTATIVE_2: u32 = 10;
pub const IP6_ADDR_TENTATIVE_3: u32 = 11;
pub const IP6_ADDR_TENTATIVE_4: u32 = 12;
pub const IP6_ADDR_TENTATIVE_5: u32 = 13;
pub const IP6_ADDR_TENTATIVE_6: u32 = 14;
pub const IP6_ADDR_TENTATIVE_7: u32 = 15;
pub const IP6_ADDR_VALID: u32 = 16;
pub const IP6_ADDR_PREFERRED: u32 = 48;
pub const IP6_ADDR_DEPRECATED: u32 = 16;
pub const IP6_ADDR_DUPLICATED: u32 = 64;
pub const IP6_ADDR_TENTATIVE_COUNT_MASK: u32 = 7;
pub const IP6_ADDR_LIFE_STATIC: u32 = 0;
pub const IP6_ADDR_LIFE_INFINITE: u32 = 4294967295;
pub const IP6ADDR_STRLEN_MAX: u32 = 46;
pub const IPADDR_STRLEN_MAX: u32 = 46;
pub const DHCPS_COARSE_TIMER_SECS: u32 = 1;
pub const DHCPS_MAX_LEASE: u32 = 100;
pub const DHCPS_LEASE_TIME_DEF: u32 = 120;
pub const DHCPS_LEASE_UNIT: u32 = 60;
pub const ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS: i32 = 20481;
pub const ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY: i32 = 20482;
pub const ESP_ERR_TCPIP_ADAPTER_DHCPC_START_FAILED: i32 = 20483;
pub const ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STARTED: i32 = 20484;
pub const ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPPED: i32 = 20485;
pub const ESP_ERR_TCPIP_ADAPTER_NO_MEM: i32 = 20486;
pub const ESP_ERR_TCPIP_ADAPTER_DHCP_NOT_STOPPED: i32 = 20487;
pub const ESP_WIFI_CRYPTO_VERSION: u32 = 1;
pub const ESP_WIFI_OS_ADAPTER_VERSION: u32 = 8;
pub const ESP_WIFI_OS_ADAPTER_MAGIC: u32 = 3735928495;
pub const OSI_FUNCS_TIME_BLOCKING: u32 = 4294967295;
pub const OSI_QUEUE_SEND_FRONT: u32 = 0;
pub const OSI_QUEUE_SEND_BACK: u32 = 1;
pub const OSI_QUEUE_SEND_OVERWRITE: u32 = 2;
pub const ESP_ERR_WIFI_NOT_INIT: i32 = 12289;
pub const ESP_ERR_WIFI_NOT_STARTED: i32 = 12290;
pub const ESP_ERR_WIFI_NOT_STOPPED: i32 = 12291;
pub const ESP_ERR_WIFI_IF: i32 = 12292;
pub const ESP_ERR_WIFI_MODE: i32 = 12293;
pub const ESP_ERR_WIFI_STATE: i32 = 12294;
pub const ESP_ERR_WIFI_CONN: i32 = 12295;
pub const ESP_ERR_WIFI_NVS: i32 = 12296;
pub const ESP_ERR_WIFI_MAC: i32 = 12297;
pub const ESP_ERR_WIFI_SSID: i32 = 12298;
pub const ESP_ERR_WIFI_PASSWORD: i32 = 12299;
pub const ESP_ERR_WIFI_TIMEOUT: i32 = 12300;
pub const ESP_ERR_WIFI_WAKE_FAIL: i32 = 12301;
pub const ESP_ERR_WIFI_WOULD_BLOCK: i32 = 12302;
pub const ESP_ERR_WIFI_NOT_CONNECT: i32 = 12303;
pub const ESP_ERR_WIFI_POST: i32 = 12306;
pub const ESP_ERR_WIFI_INIT_STATE: i32 = 12307;
pub const ESP_ERR_WIFI_STOP_STATE: i32 = 12308;
pub const ESP_ERR_WIFI_NOT_ASSOC: i32 = 12309;
pub const ESP_ERR_WIFI_TX_DISALLOW: i32 = 12310;
pub const WIFI_STATIC_TX_BUFFER_NUM: u32 = 0;
pub const WIFI_CACHE_TX_BUFFER_NUM: u32 = 0;
pub const WIFI_DYNAMIC_TX_BUFFER_NUM: u32 = 32;
pub const WIFI_CSI_ENABLED: u32 = 0;
pub const WIFI_AMPDU_RX_ENABLED: u32 = 1;
pub const WIFI_AMPDU_TX_ENABLED: u32 = 1;
pub const WIFI_AMSDU_TX_ENABLED: u32 = 0;
pub const WIFI_NVS_ENABLED: u32 = 1;
pub const WIFI_NANO_FORMAT_ENABLED: u32 = 0;
pub const WIFI_INIT_CONFIG_MAGIC: u32 = 523190095;
pub const WIFI_DEFAULT_RX_BA_WIN: u32 = 6;
pub const WIFI_TASK_CORE_ID: u32 = 0;
pub const WIFI_SOFTAP_BEACON_MAX_LEN: u32 = 752;
pub const WIFI_MGMT_SBUF_NUM: u32 = 32;
pub const WIFI_STA_DISCONNECTED_PM_ENABLED: u32 = 0;
pub const CONFIG_FEATURE_WPA3_SAE_BIT: u32 = 1;
pub const CONFIG_FEATURE_CACHE_TX_BUF_BIT: u32 = 2;
pub const CONFIG_FEATURE_FTM_INITIATOR_BIT: u32 = 4;
pub const CONFIG_FEATURE_FTM_RESPONDER_BIT: u32 = 8;
pub const MAX_WIFI_IFS: u32 = 2;
pub const ESP_ERR_ESPNOW_BASE: i32 = 12388;
pub const ESP_ERR_ESPNOW_NOT_INIT: i32 = 12389;
pub const ESP_ERR_ESPNOW_ARG: i32 = 12390;
pub const ESP_ERR_ESPNOW_NO_MEM: i32 = 12391;
pub const ESP_ERR_ESPNOW_FULL: i32 = 12392;
pub const ESP_ERR_ESPNOW_NOT_FOUND: i32 = 12393;
pub const ESP_ERR_ESPNOW_INTERNAL: i32 = 12394;
pub const ESP_ERR_ESPNOW_EXIST: i32 = 12395;
pub const ESP_ERR_ESPNOW_IF: i32 = 12396;
pub const ESP_NOW_ETH_ALEN: u32 = 6;
pub const ESP_NOW_KEY_LEN: u32 = 16;
pub const ESP_NOW_MAX_TOTAL_PEER_NUM: u32 = 20;
pub const ESP_NOW_MAX_ENCRYPT_PEER_NUM: u32 = 6;
pub const ESP_NOW_MAX_DATA_LEN: u32 = 250;
pub const DST_NONE: u32 = 0;
pub const DST_USA: u32 = 1;
pub const DST_AUST: u32 = 2;
pub const DST_WET: u32 = 3;
pub const DST_MET: u32 = 4;
pub const DST_EET: u32 = 5;
pub const DST_CAN: u32 = 6;
pub const SBT_MAX: u64 = 9223372036854775807;
pub const ITIMER_REAL: u32 = 0;
pub const ITIMER_VIRTUAL: u32 = 1;
pub const ITIMER_PROF: u32 = 2;
pub const VEOF: u32 = 0;
pub const VEOL: u32 = 1;
pub const VERASE: u32 = 2;
pub const VINTR: u32 = 3;
pub const VKILL: u32 = 4;
pub const VMIN: u32 = 5;
pub const VQUIT: u32 = 6;
pub const VSTART: u32 = 7;
pub const VSTOP: u32 = 8;
pub const VSUSP: u32 = 9;
pub const VTIME: u32 = 10;
pub const NCCS: u32 = 11;
pub const BRKINT: u32 = 1;
pub const ICRNL: u32 = 2;
pub const IGNBRK: u32 = 4;
pub const IGNCR: u32 = 8;
pub const IGNPAR: u32 = 16;
pub const INLCR: u32 = 32;
pub const INPCK: u32 = 64;
pub const ISTRIP: u32 = 128;
pub const IUCLC: u32 = 256;
pub const IXANY: u32 = 512;
pub const IXOFF: u32 = 1024;
pub const IXON: u32 = 2048;
pub const PARMRK: u32 = 4096;
pub const OPOST: u32 = 1;
pub const OLCUC: u32 = 2;
pub const ONLCR: u32 = 4;
pub const OCRNL: u32 = 8;
pub const ONOCR: u32 = 16;
pub const ONLRET: u32 = 32;
pub const OFILL: u32 = 64;
pub const NLDLY: u32 = 128;
pub const NL0: u32 = 0;
pub const NL1: u32 = 128;
pub const CRDLY: u32 = 768;
pub const CR0: u32 = 0;
pub const CR1: u32 = 256;
pub const CR2: u32 = 512;
pub const CR3: u32 = 768;
pub const TABDLY: u32 = 3072;
pub const TAB0: u32 = 0;
pub const TAB1: u32 = 1024;
pub const TAB2: u32 = 2048;
pub const TAB3: u32 = 3072;
pub const BSDLY: u32 = 4096;
pub const BS0: u32 = 0;
pub const BS1: u32 = 4096;
pub const VTDLY: u32 = 8192;
pub const VT0: u32 = 0;
pub const VT1: u32 = 8192;
pub const FFDLY: u32 = 16384;
pub const FF0: u32 = 0;
pub const FF1: u32 = 16384;
pub const B0: u32 = 0;
pub const B50: u32 = 1;
pub const B75: u32 = 2;
pub const B110: u32 = 3;
pub const B134: u32 = 4;
pub const B150: u32 = 5;
pub const B200: u32 = 6;
pub const B300: u32 = 7;
pub const B600: u32 = 8;
pub const B1200: u32 = 9;
pub const B1800: u32 = 10;
pub const B2400: u32 = 11;
pub const B4800: u32 = 12;
pub const B9600: u32 = 13;
pub const B19200: u32 = 14;
pub const B38400: u32 = 15;
pub const B57600: u32 = 16;
pub const B115200: u32 = 17;
pub const B230400: u32 = 18;
pub const B460800: u32 = 19;
pub const B500000: u32 = 20;
pub const B576000: u32 = 21;
pub const B921600: u32 = 22;
pub const B1000000: u32 = 23;
pub const B1152000: u32 = 24;
pub const B1500000: u32 = 25;
pub const B2000000: u32 = 26;
pub const B2500000: u32 = 27;
pub const B3000000: u32 = 28;
pub const B3500000: u32 = 29;
pub const B4000000: u32 = 30;
pub const CSIZE: u32 = 3;
pub const CS5: u32 = 0;
pub const CS6: u32 = 1;
pub const CS7: u32 = 2;
pub const CS8: u32 = 3;
pub const CSTOPB: u32 = 4;
pub const CREAD: u32 = 8;
pub const PARENB: u32 = 16;
pub const PARODD: u32 = 32;
pub const HUPCL: u32 = 64;
pub const CLOCAL: u32 = 128;
pub const CBAUD: u32 = 256;
pub const CBAUDEX: u32 = 512;
pub const BOTHER: u32 = 1024;
pub const ECHO: u32 = 1;
pub const ECHOE: u32 = 2;
pub const ECHOK: u32 = 4;
pub const ECHONL: u32 = 8;
pub const ICANON: u32 = 16;
pub const IEXTEN: u32 = 32;
pub const ISIG: u32 = 64;
pub const NOFLSH: u32 = 128;
pub const TOSTOP: u32 = 256;
pub const XCASE: u32 = 512;
pub const TCSANOW: u32 = 0;
pub const TCSADRAIN: u32 = 1;
pub const TCSAFLUSH: u32 = 2;
pub const TCIFLUSH: u32 = 0;
pub const TCIOFLUSH: u32 = 1;
pub const TCOFLUSH: u32 = 2;
pub const TCIOFF: u32 = 0;
pub const TCION: u32 = 1;
pub const TCOOFF: u32 = 2;
pub const TCOON: u32 = 3;
pub const POLLIN: u32 = 1;
pub const POLLRDNORM: u32 = 2;
pub const POLLRDBAND: u32 = 4;
pub const POLLPRI: u32 = 4;
pub const POLLOUT: u32 = 8;
pub const POLLWRNORM: u32 = 8;
pub const POLLWRBAND: u32 = 16;
pub const POLLERR: u32 = 32;
pub const POLLHUP: u32 = 64;
pub const POLLNVAL: u32 = 128;
pub const DT_UNKNOWN: u32 = 0;
pub const DT_REG: u32 = 1;
pub const DT_DIR: u32 = 2;
pub const MAXNAMLEN: u32 = 255;
pub const MAX_FDS: u32 = 64;
pub const ESP_VFS_PATH_MAX: u32 = 15;
pub const ESP_VFS_FLAG_DEFAULT: u32 = 0;
pub const ESP_VFS_FLAG_CONTEXT_PTR: u32 = 1;
pub const EFD_SUPPORT_ISR: u32 = 16;
pub const SCF_ITSDONE: u32 = 1;
pub const SCF_CMD_AC: u32 = 0;
pub const SCF_CMD_ADTC: u32 = 16;
pub const SCF_CMD_BC: u32 = 32;
pub const SCF_CMD_BCR: u32 = 48;
pub const SCF_CMD_READ: u32 = 64;
pub const SCF_RSP_BSY: u32 = 256;
pub const SCF_RSP_136: u32 = 512;
pub const SCF_RSP_CRC: u32 = 1024;
pub const SCF_RSP_IDX: u32 = 2048;
pub const SCF_RSP_PRESENT: u32 = 4096;
pub const SCF_RSP_R0: u32 = 0;
pub const SCF_RSP_R1: u32 = 7168;
pub const SCF_RSP_R1B: u32 = 7424;
pub const SCF_RSP_R2: u32 = 5632;
pub const SCF_RSP_R3: u32 = 4096;
pub const SCF_RSP_R4: u32 = 4096;
pub const SCF_RSP_R5: u32 = 7168;
pub const SCF_RSP_R5B: u32 = 7424;
pub const SCF_RSP_R6: u32 = 7168;
pub const SCF_RSP_R7: u32 = 7168;
pub const SCF_WAIT_BUSY: u32 = 8192;
pub const SDMMC_FREQ_DEFAULT: u32 = 20000;
pub const SDMMC_FREQ_HIGHSPEED: u32 = 40000;
pub const SDMMC_FREQ_PROBING: u32 = 400;
pub const SDMMC_FREQ_52M: u32 = 52000;
pub const SDMMC_FREQ_26M: u32 = 26000;
pub const LLDESC_TX_MBLK_SIZE: u32 = 268;
pub const LLDESC_RX_SMBLK_SIZE: u32 = 64;
pub const LLDESC_RX_MBLK_SIZE: u32 = 524;
pub const LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE: u32 = 64;
pub const LLDESC_RX_AMPDU_LEN_MBLK_SIZE: u32 = 256;
pub const LLDESC_TX_MBLK_NUM: u32 = 10;
pub const LLDESC_RX_MBLK_NUM: u32 = 10;
pub const LLDESC_RX_AMPDU_ENTRY_MBLK_NUM: u32 = 4;
pub const LLDESC_RX_AMPDU_LEN_MLBK_NUM: u32 = 8;
pub const LLDESC_OWNER_MASK: u32 = 2147483648;
pub const LLDESC_OWNER_SHIFT: u32 = 31;
pub const LLDESC_SW_OWNED: u32 = 0;
pub const LLDESC_HW_OWNED: u32 = 1;
pub const LLDESC_EOF_MASK: u32 = 1073741824;
pub const LLDESC_EOF_SHIFT: u32 = 30;
pub const LLDESC_SOSF_MASK: u32 = 536870912;
pub const LLDESC_SOSF_SHIFT: u32 = 29;
pub const LLDESC_LENGTH_MASK: u32 = 16773120;
pub const LLDESC_LENGTH_SHIFT: u32 = 12;
pub const LLDESC_SIZE_MASK: u32 = 4095;
pub const LLDESC_SIZE_SHIFT: u32 = 0;
pub const LLDESC_ADDR_MASK: u32 = 1048575;
pub const LLDESC_MAX_NUM_PER_DESC: u32 = 4092;
pub const LLDESC_MAX_NUM_PER_DESC_16B_ALIGNED: u32 = 4080;
pub const LLDESC_MAX_NUM_PER_DESC_32B_ALIGNED: u32 = 4064;
pub const USBPHY_VP_NUM: u32 = 42;
pub const USBPHY_VM_NUM: u32 = 41;
pub const USBPHY_RCV_NUM: u32 = 21;
pub const USBPHY_OEN_NUM: u32 = 40;
pub const USBPHY_VPO_NUM: u32 = 39;
pub const USBPHY_VMO_NUM: u32 = 38;
pub const USBPHY_DP_NUM: u32 = 20;
pub const USBPHY_DM_NUM: u32 = 19;
pub const GPIO_MATRIX_CONST_ONE_INPUT: u32 = 56;
pub const GPIO_MATRIX_CONST_ZERO_INPUT: u32 = 60;
pub const SPI_FUNC_NUM: u32 = 0;
pub const SPI_IOMUX_PIN_NUM_HD: u32 = 27;
pub const SPI_IOMUX_PIN_NUM_CS: u32 = 29;
pub const SPI_IOMUX_PIN_NUM_MOSI: u32 = 32;
pub const SPI_IOMUX_PIN_NUM_CLK: u32 = 30;
pub const SPI_IOMUX_PIN_NUM_MISO: u32 = 31;
pub const SPI_IOMUX_PIN_NUM_WP: u32 = 28;
pub const SPI2_FUNC_NUM: u32 = 4;
pub const SPI2_IOMUX_PIN_NUM_HD: u32 = 9;
pub const SPI2_IOMUX_PIN_NUM_CS: u32 = 10;
pub const SPI2_IOMUX_PIN_NUM_MOSI: u32 = 11;
pub const SPI2_IOMUX_PIN_NUM_CLK: u32 = 12;
pub const SPI2_IOMUX_PIN_NUM_MISO: u32 = 13;
pub const SPI2_IOMUX_PIN_NUM_WP: u32 = 14;
pub const SPI2_FUNC_NUM_OCT: u32 = 2;
pub const SPI2_IOMUX_PIN_NUM_HD_OCT: u32 = 33;
pub const SPI2_IOMUX_PIN_NUM_CS_OCT: u32 = 34;
pub const SPI2_IOMUX_PIN_NUM_MOSI_OCT: u32 = 35;
pub const SPI2_IOMUX_PIN_NUM_CLK_OCT: u32 = 36;
pub const SPI2_IOMUX_PIN_NUM_MISO_OCT: u32 = 37;
pub const SPI2_IOMUX_PIN_NUM_WP_OCT: u32 = 38;
pub const SPI2_IOMUX_PIN_NUM_IO4_OCT: u32 = 10;
pub const SPI2_IOMUX_PIN_NUM_IO5_OCT: u32 = 11;
pub const SPI2_IOMUX_PIN_NUM_IO6_OCT: u32 = 12;
pub const SPI2_IOMUX_PIN_NUM_IO7_OCT: u32 = 13;
pub const SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK: u32 = 6;
pub const SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD: u32 = 11;
pub const SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0: u32 = 7;
pub const SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1: u32 = 8;
pub const SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2: u32 = 9;
pub const SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3: u32 = 10;
pub const SDIO_SLAVE_SLOT0_FUNC: u32 = 0;
pub const SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK: u32 = 14;
pub const SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD: u32 = 15;
pub const SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0: u32 = 2;
pub const SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1: u32 = 4;
pub const SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2: u32 = 12;
pub const SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3: u32 = 13;
pub const SDIO_SLAVE_SLOT1_FUNC: u32 = 4;
pub const SOC_TOUCH_SHIELD_CHANNEL: u32 = 14;
pub const SOC_TOUCH_DENOISE_CHANNEL: u32 = 0;
pub const SPI_USR_V: u32 = 1;
pub const SPI_USR_S: u32 = 24;
pub const SPI_UPDATE_V: u32 = 1;
pub const SPI_UPDATE_S: u32 = 23;
pub const SPI_CONF_BITLEN: u32 = 262143;
pub const SPI_CONF_BITLEN_V: u32 = 262143;
pub const SPI_CONF_BITLEN_S: u32 = 0;
pub const SPI_USR_ADDR_VALUE: u32 = 4294967295;
pub const SPI_USR_ADDR_VALUE_V: u32 = 4294967295;
pub const SPI_USR_ADDR_VALUE_S: u32 = 0;
pub const SPI_WR_BIT_ORDER: u32 = 3;
pub const SPI_WR_BIT_ORDER_V: u32 = 3;
pub const SPI_WR_BIT_ORDER_S: u32 = 25;
pub const SPI_RD_BIT_ORDER: u32 = 3;
pub const SPI_RD_BIT_ORDER_V: u32 = 3;
pub const SPI_RD_BIT_ORDER_S: u32 = 23;
pub const SPI_WP_POL_V: u32 = 1;
pub const SPI_WP_POL_S: u32 = 21;
pub const SPI_HOLD_POL_V: u32 = 1;
pub const SPI_HOLD_POL_S: u32 = 20;
pub const SPI_D_POL_V: u32 = 1;
pub const SPI_D_POL_S: u32 = 19;
pub const SPI_Q_POL_V: u32 = 1;
pub const SPI_Q_POL_S: u32 = 18;
pub const SPI_FREAD_OCT_V: u32 = 1;
pub const SPI_FREAD_OCT_S: u32 = 16;
pub const SPI_FREAD_QUAD_V: u32 = 1;
pub const SPI_FREAD_QUAD_S: u32 = 15;
pub const SPI_FREAD_DUAL_V: u32 = 1;
pub const SPI_FREAD_DUAL_S: u32 = 14;
pub const SPI_FCMD_OCT_V: u32 = 1;
pub const SPI_FCMD_OCT_S: u32 = 10;
pub const SPI_FCMD_QUAD_V: u32 = 1;
pub const SPI_FCMD_QUAD_S: u32 = 9;
pub const SPI_FCMD_DUAL_V: u32 = 1;
pub const SPI_FCMD_DUAL_S: u32 = 8;
pub const SPI_FADDR_OCT_V: u32 = 1;
pub const SPI_FADDR_OCT_S: u32 = 7;
pub const SPI_FADDR_QUAD_V: u32 = 1;
pub const SPI_FADDR_QUAD_S: u32 = 6;
pub const SPI_FADDR_DUAL_V: u32 = 1;
pub const SPI_FADDR_DUAL_S: u32 = 5;
pub const SPI_DUMMY_OUT_V: u32 = 1;
pub const SPI_DUMMY_OUT_S: u32 = 3;
pub const SPI_CLK_EQU_SYSCLK_V: u32 = 1;
pub const SPI_CLK_EQU_SYSCLK_S: u32 = 31;
pub const SPI_CLKDIV_PRE: u32 = 15;
pub const SPI_CLKDIV_PRE_V: u32 = 15;
pub const SPI_CLKDIV_PRE_S: u32 = 18;
pub const SPI_CLKCNT_N: u32 = 63;
pub const SPI_CLKCNT_N_V: u32 = 63;
pub const SPI_CLKCNT_N_S: u32 = 12;
pub const SPI_CLKCNT_H: u32 = 63;
pub const SPI_CLKCNT_H_V: u32 = 63;
pub const SPI_CLKCNT_H_S: u32 = 6;
pub const SPI_CLKCNT_L: u32 = 63;
pub const SPI_CLKCNT_L_V: u32 = 63;
pub const SPI_CLKCNT_L_S: u32 = 0;
pub const SPI_USR_COMMAND_V: u32 = 1;
pub const SPI_USR_COMMAND_S: u32 = 31;
pub const SPI_USR_ADDR_V: u32 = 1;
pub const SPI_USR_ADDR_S: u32 = 30;
pub const SPI_USR_DUMMY_V: u32 = 1;
pub const SPI_USR_DUMMY_S: u32 = 29;
pub const SPI_USR_MISO_V: u32 = 1;
pub const SPI_USR_MISO_S: u32 = 28;
pub const SPI_USR_MOSI_V: u32 = 1;
pub const SPI_USR_MOSI_S: u32 = 27;
pub const SPI_USR_DUMMY_IDLE_V: u32 = 1;
pub const SPI_USR_DUMMY_IDLE_S: u32 = 26;
pub const SPI_USR_MOSI_HIGHPART_V: u32 = 1;
pub const SPI_USR_MOSI_HIGHPART_S: u32 = 25;
pub const SPI_USR_MISO_HIGHPART_V: u32 = 1;
pub const SPI_USR_MISO_HIGHPART_S: u32 = 24;
pub const SPI_SIO_V: u32 = 1;
pub const SPI_SIO_S: u32 = 17;
pub const SPI_USR_CONF_NXT_V: u32 = 1;
pub const SPI_USR_CONF_NXT_S: u32 = 15;
pub const SPI_FWRITE_OCT_V: u32 = 1;
pub const SPI_FWRITE_OCT_S: u32 = 14;
pub const SPI_FWRITE_QUAD_V: u32 = 1;
pub const SPI_FWRITE_QUAD_S: u32 = 13;
pub const SPI_FWRITE_DUAL_V: u32 = 1;
pub const SPI_FWRITE_DUAL_S: u32 = 12;
pub const SPI_CK_OUT_EDGE_V: u32 = 1;
pub const SPI_CK_OUT_EDGE_S: u32 = 9;
pub const SPI_RSCK_I_EDGE_V: u32 = 1;
pub const SPI_RSCK_I_EDGE_S: u32 = 8;
pub const SPI_CS_SETUP_V: u32 = 1;
pub const SPI_CS_SETUP_S: u32 = 7;
pub const SPI_CS_HOLD_V: u32 = 1;
pub const SPI_CS_HOLD_S: u32 = 6;
pub const SPI_TSCK_I_EDGE_V: u32 = 1;
pub const SPI_TSCK_I_EDGE_S: u32 = 5;
pub const SPI_OPI_MODE_V: u32 = 1;
pub const SPI_OPI_MODE_S: u32 = 4;
pub const SPI_QPI_MODE_V: u32 = 1;
pub const SPI_QPI_MODE_S: u32 = 3;
pub const SPI_DOUTDIN_V: u32 = 1;
pub const SPI_DOUTDIN_S: u32 = 0;
pub const SPI_USR_ADDR_BITLEN: u32 = 31;
pub const SPI_USR_ADDR_BITLEN_V: u32 = 31;
pub const SPI_USR_ADDR_BITLEN_S: u32 = 27;
pub const SPI_CS_HOLD_TIME: u32 = 31;
pub const SPI_CS_HOLD_TIME_V: u32 = 31;
pub const SPI_CS_HOLD_TIME_S: u32 = 22;
pub const SPI_CS_SETUP_TIME: u32 = 31;
pub const SPI_CS_SETUP_TIME_V: u32 = 31;
pub const SPI_CS_SETUP_TIME_S: u32 = 17;
pub const SPI_MST_WFULL_ERR_END_EN_V: u32 = 1;
pub const SPI_MST_WFULL_ERR_END_EN_S: u32 = 16;
pub const SPI_USR_DUMMY_CYCLELEN: u32 = 255;
pub const SPI_USR_DUMMY_CYCLELEN_V: u32 = 255;
pub const SPI_USR_DUMMY_CYCLELEN_S: u32 = 0;
pub const SPI_USR_COMMAND_BITLEN: u32 = 15;
pub const SPI_USR_COMMAND_BITLEN_V: u32 = 15;
pub const SPI_USR_COMMAND_BITLEN_S: u32 = 28;
pub const SPI_MST_REMPTY_ERR_END_EN_V: u32 = 1;
pub const SPI_MST_REMPTY_ERR_END_EN_S: u32 = 27;
pub const SPI_USR_COMMAND_VALUE: u32 = 65535;
pub const SPI_USR_COMMAND_VALUE_V: u32 = 65535;
pub const SPI_USR_COMMAND_VALUE_S: u32 = 0;
pub const SPI_MS_DATA_BITLEN: u32 = 262143;
pub const SPI_MS_DATA_BITLEN_V: u32 = 262143;
pub const SPI_MS_DATA_BITLEN_S: u32 = 0;
pub const SPI_QUAD_DIN_PIN_SWAP_V: u32 = 1;
pub const SPI_QUAD_DIN_PIN_SWAP_S: u32 = 31;
pub const SPI_CS_KEEP_ACTIVE_V: u32 = 1;
pub const SPI_CS_KEEP_ACTIVE_S: u32 = 30;
pub const SPI_CK_IDLE_EDGE_V: u32 = 1;
pub const SPI_CK_IDLE_EDGE_S: u32 = 29;
pub const SPI_DQS_IDLE_EDGE_V: u32 = 1;
pub const SPI_DQS_IDLE_EDGE_S: u32 = 24;
pub const SPI_SLAVE_CS_POL_V: u32 = 1;
pub const SPI_SLAVE_CS_POL_S: u32 = 23;
pub const SPI_CMD_DTR_EN_V: u32 = 1;
pub const SPI_CMD_DTR_EN_S: u32 = 19;
pub const SPI_ADDR_DTR_EN_V: u32 = 1;
pub const SPI_ADDR_DTR_EN_S: u32 = 18;
pub const SPI_DATA_DTR_EN_V: u32 = 1;
pub const SPI_DATA_DTR_EN_S: u32 = 17;
pub const SPI_CLK_DATA_DTR_EN_V: u32 = 1;
pub const SPI_CLK_DATA_DTR_EN_S: u32 = 16;
pub const SPI_MASTER_CS_POL: u32 = 63;
pub const SPI_MASTER_CS_POL_V: u32 = 63;
pub const SPI_MASTER_CS_POL_S: u32 = 7;
pub const SPI_CK_DIS_V: u32 = 1;
pub const SPI_CK_DIS_S: u32 = 6;
pub const SPI_CS5_DIS_V: u32 = 1;
pub const SPI_CS5_DIS_S: u32 = 5;
pub const SPI_CS4_DIS_V: u32 = 1;
pub const SPI_CS4_DIS_S: u32 = 4;
pub const SPI_CS3_DIS_V: u32 = 1;
pub const SPI_CS3_DIS_S: u32 = 3;
pub const SPI_CS2_DIS_V: u32 = 1;
pub const SPI_CS2_DIS_S: u32 = 2;
pub const SPI_CS1_DIS_V: u32 = 1;
pub const SPI_CS1_DIS_S: u32 = 1;
pub const SPI_CS0_DIS_V: u32 = 1;
pub const SPI_CS0_DIS_S: u32 = 0;
pub const SPI_TIMING_HCLK_ACTIVE_V: u32 = 1;
pub const SPI_TIMING_HCLK_ACTIVE_S: u32 = 16;
pub const SPI_DIN7_MODE: u32 = 3;
pub const SPI_DIN7_MODE_V: u32 = 3;
pub const SPI_DIN7_MODE_S: u32 = 14;
pub const SPI_DIN6_MODE: u32 = 3;
pub const SPI_DIN6_MODE_V: u32 = 3;
pub const SPI_DIN6_MODE_S: u32 = 12;
pub const SPI_DIN5_MODE: u32 = 3;
pub const SPI_DIN5_MODE_V: u32 = 3;
pub const SPI_DIN5_MODE_S: u32 = 10;
pub const SPI_DIN4_MODE: u32 = 3;
pub const SPI_DIN4_MODE_V: u32 = 3;
pub const SPI_DIN4_MODE_S: u32 = 8;
pub const SPI_DIN3_MODE: u32 = 3;
pub const SPI_DIN3_MODE_V: u32 = 3;
pub const SPI_DIN3_MODE_S: u32 = 6;
pub const SPI_DIN2_MODE: u32 = 3;
pub const SPI_DIN2_MODE_V: u32 = 3;
pub const SPI_DIN2_MODE_S: u32 = 4;
pub const SPI_DIN1_MODE: u32 = 3;
pub const SPI_DIN1_MODE_V: u32 = 3;
pub const SPI_DIN1_MODE_S: u32 = 2;
pub const SPI_DIN0_MODE: u32 = 3;
pub const SPI_DIN0_MODE_V: u32 = 3;
pub const SPI_DIN0_MODE_S: u32 = 0;
pub const SPI_DIN7_NUM: u32 = 3;
pub const SPI_DIN7_NUM_V: u32 = 3;
pub const SPI_DIN7_NUM_S: u32 = 14;
pub const SPI_DIN6_NUM: u32 = 3;
pub const SPI_DIN6_NUM_V: u32 = 3;
pub const SPI_DIN6_NUM_S: u32 = 12;
pub const SPI_DIN5_NUM: u32 = 3;
pub const SPI_DIN5_NUM_V: u32 = 3;
pub const SPI_DIN5_NUM_S: u32 = 10;
pub const SPI_DIN4_NUM: u32 = 3;
pub const SPI_DIN4_NUM_V: u32 = 3;
pub const SPI_DIN4_NUM_S: u32 = 8;
pub const SPI_DIN3_NUM: u32 = 3;
pub const SPI_DIN3_NUM_V: u32 = 3;
pub const SPI_DIN3_NUM_S: u32 = 6;
pub const SPI_DIN2_NUM: u32 = 3;
pub const SPI_DIN2_NUM_V: u32 = 3;
pub const SPI_DIN2_NUM_S: u32 = 4;
pub const SPI_DIN1_NUM: u32 = 3;
pub const SPI_DIN1_NUM_V: u32 = 3;
pub const SPI_DIN1_NUM_S: u32 = 2;
pub const SPI_DIN0_NUM: u32 = 3;
pub const SPI_DIN0_NUM_V: u32 = 3;
pub const SPI_DIN0_NUM_S: u32 = 0;
pub const SPI_D_DQS_MODE_V: u32 = 1;
pub const SPI_D_DQS_MODE_S: u32 = 8;
pub const SPI_DOUT7_MODE_V: u32 = 1;
pub const SPI_DOUT7_MODE_S: u32 = 7;
pub const SPI_DOUT6_MODE_V: u32 = 1;
pub const SPI_DOUT6_MODE_S: u32 = 6;
pub const SPI_DOUT5_MODE_V: u32 = 1;
pub const SPI_DOUT5_MODE_S: u32 = 5;
pub const SPI_DOUT4_MODE_V: u32 = 1;
pub const SPI_DOUT4_MODE_S: u32 = 4;
pub const SPI_DOUT3_MODE_V: u32 = 1;
pub const SPI_DOUT3_MODE_S: u32 = 3;
pub const SPI_DOUT2_MODE_V: u32 = 1;
pub const SPI_DOUT2_MODE_S: u32 = 2;
pub const SPI_DOUT1_MODE_V: u32 = 1;
pub const SPI_DOUT1_MODE_S: u32 = 1;
pub const SPI_DOUT0_MODE_V: u32 = 1;
pub const SPI_DOUT0_MODE_S: u32 = 0;
pub const SPI_DMA_AFIFO_RST_V: u32 = 1;
pub const SPI_DMA_AFIFO_RST_S: u32 = 31;
pub const SPI_BUF_AFIFO_RST_V: u32 = 1;
pub const SPI_BUF_AFIFO_RST_S: u32 = 30;
pub const SPI_RX_AFIFO_RST_V: u32 = 1;
pub const SPI_RX_AFIFO_RST_S: u32 = 29;
pub const SPI_DMA_TX_ENA_V: u32 = 1;
pub const SPI_DMA_TX_ENA_S: u32 = 28;
pub const SPI_DMA_RX_ENA_V: u32 = 1;
pub const SPI_DMA_RX_ENA_S: u32 = 27;
pub const SPI_RX_EOF_EN_V: u32 = 1;
pub const SPI_RX_EOF_EN_S: u32 = 21;
pub const SPI_SLV_TX_SEG_TRANS_CLR_EN_V: u32 = 1;
pub const SPI_SLV_TX_SEG_TRANS_CLR_EN_S: u32 = 20;
pub const SPI_SLV_RX_SEG_TRANS_CLR_EN_V: u32 = 1;
pub const SPI_SLV_RX_SEG_TRANS_CLR_EN_S: u32 = 19;
pub const SPI_DMA_SLV_SEG_TRANS_EN_V: u32 = 1;
pub const SPI_DMA_SLV_SEG_TRANS_EN_S: u32 = 18;
pub const SPI_DMA_INFIFO_FULL_V: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_S: u32 = 1;
pub const SPI_DMA_OUTFIFO_EMPTY_V: u32 = 1;
pub const SPI_DMA_OUTFIFO_EMPTY_S: u32 = 0;
pub const SPI_APP1_INT_ENA_V: u32 = 1;
pub const SPI_APP1_INT_ENA_S: u32 = 20;
pub const SPI_APP2_INT_ENA_V: u32 = 1;
pub const SPI_APP2_INT_ENA_S: u32 = 19;
pub const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V: u32 = 1;
pub const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S: u32 = 18;
pub const SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V: u32 = 1;
pub const SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S: u32 = 17;
pub const SPI_SLV_CMD_ERR_INT_ENA_V: u32 = 1;
pub const SPI_SLV_CMD_ERR_INT_ENA_S: u32 = 16;
pub const SPI_SLV_BUF_ADDR_ERR_INT_ENA_V: u32 = 1;
pub const SPI_SLV_BUF_ADDR_ERR_INT_ENA_S: u32 = 15;
pub const SPI_SEG_MAGIC_ERR_INT_ENA_V: u32 = 1;
pub const SPI_SEG_MAGIC_ERR_INT_ENA_S: u32 = 14;
pub const SPI_DMA_SEG_TRANS_DONE_INT_ENA_V: u32 = 1;
pub const SPI_DMA_SEG_TRANS_DONE_INT_ENA_S: u32 = 13;
pub const SPI_TRANS_DONE_INT_ENA_V: u32 = 1;
pub const SPI_TRANS_DONE_INT_ENA_S: u32 = 12;
pub const SPI_SLV_WR_BUF_DONE_INT_ENA_V: u32 = 1;
pub const SPI_SLV_WR_BUF_DONE_INT_ENA_S: u32 = 11;
pub const SPI_SLV_RD_BUF_DONE_INT_ENA_V: u32 = 1;
pub const SPI_SLV_RD_BUF_DONE_INT_ENA_S: u32 = 10;
pub const SPI_SLV_WR_DMA_DONE_INT_ENA_V: u32 = 1;
pub const SPI_SLV_WR_DMA_DONE_INT_ENA_S: u32 = 9;
pub const SPI_SLV_RD_DMA_DONE_INT_ENA_V: u32 = 1;
pub const SPI_SLV_RD_DMA_DONE_INT_ENA_S: u32 = 8;
pub const SPI_SLV_CMDA_INT_ENA_V: u32 = 1;
pub const SPI_SLV_CMDA_INT_ENA_S: u32 = 7;
pub const SPI_SLV_CMD9_INT_ENA_V: u32 = 1;
pub const SPI_SLV_CMD9_INT_ENA_S: u32 = 6;
pub const SPI_SLV_CMD8_INT_ENA_V: u32 = 1;
pub const SPI_SLV_CMD8_INT_ENA_S: u32 = 5;
pub const SPI_SLV_CMD7_INT_ENA_V: u32 = 1;
pub const SPI_SLV_CMD7_INT_ENA_S: u32 = 4;
pub const SPI_SLV_EN_QPI_INT_ENA_V: u32 = 1;
pub const SPI_SLV_EN_QPI_INT_ENA_S: u32 = 3;
pub const SPI_SLV_EX_QPI_INT_ENA_V: u32 = 1;
pub const SPI_SLV_EX_QPI_INT_ENA_S: u32 = 2;
pub const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V: u32 = 1;
pub const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S: u32 = 0;
pub const SPI_APP1_INT_CLR_V: u32 = 1;
pub const SPI_APP1_INT_CLR_S: u32 = 20;
pub const SPI_APP2_INT_CLR_V: u32 = 1;
pub const SPI_APP2_INT_CLR_S: u32 = 19;
pub const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V: u32 = 1;
pub const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S: u32 = 18;
pub const SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V: u32 = 1;
pub const SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S: u32 = 17;
pub const SPI_SLV_CMD_ERR_INT_CLR_V: u32 = 1;
pub const SPI_SLV_CMD_ERR_INT_CLR_S: u32 = 16;
pub const SPI_SLV_BUF_ADDR_ERR_INT_CLR_V: u32 = 1;
pub const SPI_SLV_BUF_ADDR_ERR_INT_CLR_S: u32 = 15;
pub const SPI_SEG_MAGIC_ERR_INT_CLR_V: u32 = 1;
pub const SPI_SEG_MAGIC_ERR_INT_CLR_S: u32 = 14;
pub const SPI_DMA_SEG_TRANS_DONE_INT_CLR_V: u32 = 1;
pub const SPI_DMA_SEG_TRANS_DONE_INT_CLR_S: u32 = 13;
pub const SPI_TRANS_DONE_INT_CLR_V: u32 = 1;
pub const SPI_TRANS_DONE_INT_CLR_S: u32 = 12;
pub const SPI_SLV_WR_BUF_DONE_INT_CLR_V: u32 = 1;
pub const SPI_SLV_WR_BUF_DONE_INT_CLR_S: u32 = 11;
pub const SPI_SLV_RD_BUF_DONE_INT_CLR_V: u32 = 1;
pub const SPI_SLV_RD_BUF_DONE_INT_CLR_S: u32 = 10;
pub const SPI_SLV_WR_DMA_DONE_INT_CLR_V: u32 = 1;
pub const SPI_SLV_WR_DMA_DONE_INT_CLR_S: u32 = 9;
pub const SPI_SLV_RD_DMA_DONE_INT_CLR_V: u32 = 1;
pub const SPI_SLV_RD_DMA_DONE_INT_CLR_S: u32 = 8;
pub const SPI_SLV_CMDA_INT_CLR_V: u32 = 1;
pub const SPI_SLV_CMDA_INT_CLR_S: u32 = 7;
pub const SPI_SLV_CMD9_INT_CLR_V: u32 = 1;
pub const SPI_SLV_CMD9_INT_CLR_S: u32 = 6;
pub const SPI_SLV_CMD8_INT_CLR_V: u32 = 1;
pub const SPI_SLV_CMD8_INT_CLR_S: u32 = 5;
pub const SPI_SLV_CMD7_INT_CLR_V: u32 = 1;
pub const SPI_SLV_CMD7_INT_CLR_S: u32 = 4;
pub const SPI_SLV_EN_QPI_INT_CLR_V: u32 = 1;
pub const SPI_SLV_EN_QPI_INT_CLR_S: u32 = 3;
pub const SPI_SLV_EX_QPI_INT_CLR_V: u32 = 1;
pub const SPI_SLV_EX_QPI_INT_CLR_S: u32 = 2;
pub const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V: u32 = 1;
pub const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S: u32 = 0;
pub const SPI_APP1_INT_RAW_V: u32 = 1;
pub const SPI_APP1_INT_RAW_S: u32 = 20;
pub const SPI_APP2_INT_RAW_V: u32 = 1;
pub const SPI_APP2_INT_RAW_S: u32 = 19;
pub const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V: u32 = 1;
pub const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S: u32 = 18;
pub const SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V: u32 = 1;
pub const SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S: u32 = 17;
pub const SPI_SLV_CMD_ERR_INT_RAW_V: u32 = 1;
pub const SPI_SLV_CMD_ERR_INT_RAW_S: u32 = 16;
pub const SPI_SLV_BUF_ADDR_ERR_INT_RAW_V: u32 = 1;
pub const SPI_SLV_BUF_ADDR_ERR_INT_RAW_S: u32 = 15;
pub const SPI_SEG_MAGIC_ERR_INT_RAW_V: u32 = 1;
pub const SPI_SEG_MAGIC_ERR_INT_RAW_S: u32 = 14;
pub const SPI_DMA_SEG_TRANS_DONE_INT_RAW_V: u32 = 1;
pub const SPI_DMA_SEG_TRANS_DONE_INT_RAW_S: u32 = 13;
pub const SPI_TRANS_DONE_INT_RAW_V: u32 = 1;
pub const SPI_TRANS_DONE_INT_RAW_S: u32 = 12;
pub const SPI_SLV_WR_BUF_DONE_INT_RAW_V: u32 = 1;
pub const SPI_SLV_WR_BUF_DONE_INT_RAW_S: u32 = 11;
pub const SPI_SLV_RD_BUF_DONE_INT_RAW_V: u32 = 1;
pub const SPI_SLV_RD_BUF_DONE_INT_RAW_S: u32 = 10;
pub const SPI_SLV_WR_DMA_DONE_INT_RAW_V: u32 = 1;
pub const SPI_SLV_WR_DMA_DONE_INT_RAW_S: u32 = 9;
pub const SPI_SLV_RD_DMA_DONE_INT_RAW_V: u32 = 1;
pub const SPI_SLV_RD_DMA_DONE_INT_RAW_S: u32 = 8;
pub const SPI_SLV_CMDA_INT_RAW_V: u32 = 1;
pub const SPI_SLV_CMDA_INT_RAW_S: u32 = 7;
pub const SPI_SLV_CMD9_INT_RAW_V: u32 = 1;
pub const SPI_SLV_CMD9_INT_RAW_S: u32 = 6;
pub const SPI_SLV_CMD8_INT_RAW_V: u32 = 1;
pub const SPI_SLV_CMD8_INT_RAW_S: u32 = 5;
pub const SPI_SLV_CMD7_INT_RAW_V: u32 = 1;
pub const SPI_SLV_CMD7_INT_RAW_S: u32 = 4;
pub const SPI_SLV_EN_QPI_INT_RAW_V: u32 = 1;
pub const SPI_SLV_EN_QPI_INT_RAW_S: u32 = 3;
pub const SPI_SLV_EX_QPI_INT_RAW_V: u32 = 1;
pub const SPI_SLV_EX_QPI_INT_RAW_S: u32 = 2;
pub const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V: u32 = 1;
pub const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S: u32 = 0;
pub const SPI_APP1_INT_ST_V: u32 = 1;
pub const SPI_APP1_INT_ST_S: u32 = 20;
pub const SPI_APP2_INT_ST_V: u32 = 1;
pub const SPI_APP2_INT_ST_S: u32 = 19;
pub const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V: u32 = 1;
pub const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S: u32 = 18;
pub const SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V: u32 = 1;
pub const SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S: u32 = 17;
pub const SPI_SLV_CMD_ERR_INT_ST_V: u32 = 1;
pub const SPI_SLV_CMD_ERR_INT_ST_S: u32 = 16;
pub const SPI_SLV_BUF_ADDR_ERR_INT_ST_V: u32 = 1;
pub const SPI_SLV_BUF_ADDR_ERR_INT_ST_S: u32 = 15;
pub const SPI_SEG_MAGIC_ERR_INT_ST_V: u32 = 1;
pub const SPI_SEG_MAGIC_ERR_INT_ST_S: u32 = 14;
pub const SPI_DMA_SEG_TRANS_DONE_INT_ST_V: u32 = 1;
pub const SPI_DMA_SEG_TRANS_DONE_INT_ST_S: u32 = 13;
pub const SPI_TRANS_DONE_INT_ST_V: u32 = 1;
pub const SPI_TRANS_DONE_INT_ST_S: u32 = 12;
pub const SPI_SLV_WR_BUF_DONE_INT_ST_V: u32 = 1;
pub const SPI_SLV_WR_BUF_DONE_INT_ST_S: u32 = 11;
pub const SPI_SLV_RD_BUF_DONE_INT_ST_V: u32 = 1;
pub const SPI_SLV_RD_BUF_DONE_INT_ST_S: u32 = 10;
pub const SPI_SLV_WR_DMA_DONE_INT_ST_V: u32 = 1;
pub const SPI_SLV_WR_DMA_DONE_INT_ST_S: u32 = 9;
pub const SPI_SLV_RD_DMA_DONE_INT_ST_V: u32 = 1;
pub const SPI_SLV_RD_DMA_DONE_INT_ST_S: u32 = 8;
pub const SPI_SLV_CMDA_INT_ST_V: u32 = 1;
pub const SPI_SLV_CMDA_INT_ST_S: u32 = 7;
pub const SPI_SLV_CMD9_INT_ST_V: u32 = 1;
pub const SPI_SLV_CMD9_INT_ST_S: u32 = 6;
pub const SPI_SLV_CMD8_INT_ST_V: u32 = 1;
pub const SPI_SLV_CMD8_INT_ST_S: u32 = 5;
pub const SPI_SLV_CMD7_INT_ST_V: u32 = 1;
pub const SPI_SLV_CMD7_INT_ST_S: u32 = 4;
pub const SPI_SLV_EN_QPI_INT_ST_V: u32 = 1;
pub const SPI_SLV_EN_QPI_INT_ST_S: u32 = 3;
pub const SPI_SLV_EX_QPI_INT_ST_V: u32 = 1;
pub const SPI_SLV_EX_QPI_INT_ST_S: u32 = 2;
pub const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V: u32 = 1;
pub const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_ERR_INT_ST_V: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_ERR_INT_ST_S: u32 = 0;
pub const SPI_APP1_INT_SET_V: u32 = 1;
pub const SPI_APP1_INT_SET_S: u32 = 20;
pub const SPI_APP2_INT_SET_V: u32 = 1;
pub const SPI_APP2_INT_SET_S: u32 = 19;
pub const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V: u32 = 1;
pub const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S: u32 = 18;
pub const SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V: u32 = 1;
pub const SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S: u32 = 17;
pub const SPI_SLV_CMD_ERR_INT_SET_V: u32 = 1;
pub const SPI_SLV_CMD_ERR_INT_SET_S: u32 = 16;
pub const SPI_SLV_BUF_ADDR_ERR_INT_SET_V: u32 = 1;
pub const SPI_SLV_BUF_ADDR_ERR_INT_SET_S: u32 = 15;
pub const SPI_SEG_MAGIC_ERR_INT_SET_V: u32 = 1;
pub const SPI_SEG_MAGIC_ERR_INT_SET_S: u32 = 14;
pub const SPI_DMA_SEG_TRANS_DONE_INT_SET_V: u32 = 1;
pub const SPI_DMA_SEG_TRANS_DONE_INT_SET_S: u32 = 13;
pub const SPI_TRANS_DONE_INT_SET_V: u32 = 1;
pub const SPI_TRANS_DONE_INT_SET_S: u32 = 12;
pub const SPI_SLV_WR_BUF_DONE_INT_SET_V: u32 = 1;
pub const SPI_SLV_WR_BUF_DONE_INT_SET_S: u32 = 11;
pub const SPI_SLV_RD_BUF_DONE_INT_SET_V: u32 = 1;
pub const SPI_SLV_RD_BUF_DONE_INT_SET_S: u32 = 10;
pub const SPI_SLV_WR_DMA_DONE_INT_SET_V: u32 = 1;
pub const SPI_SLV_WR_DMA_DONE_INT_SET_S: u32 = 9;
pub const SPI_SLV_RD_DMA_DONE_INT_SET_V: u32 = 1;
pub const SPI_SLV_RD_DMA_DONE_INT_SET_S: u32 = 8;
pub const SPI_SLV_CMDA_INT_SET_V: u32 = 1;
pub const SPI_SLV_CMDA_INT_SET_S: u32 = 7;
pub const SPI_SLV_CMD9_INT_SET_V: u32 = 1;
pub const SPI_SLV_CMD9_INT_SET_S: u32 = 6;
pub const SPI_SLV_CMD8_INT_SET_V: u32 = 1;
pub const SPI_SLV_CMD8_INT_SET_S: u32 = 5;
pub const SPI_SLV_CMD7_INT_SET_V: u32 = 1;
pub const SPI_SLV_CMD7_INT_SET_S: u32 = 4;
pub const SPI_SLV_EN_QPI_INT_SET_V: u32 = 1;
pub const SPI_SLV_EN_QPI_INT_SET_S: u32 = 3;
pub const SPI_SLV_EX_QPI_INT_SET_V: u32 = 1;
pub const SPI_SLV_EX_QPI_INT_SET_S: u32 = 2;
pub const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V: u32 = 1;
pub const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_ERR_INT_SET_V: u32 = 1;
pub const SPI_DMA_INFIFO_FULL_ERR_INT_SET_S: u32 = 0;
pub const SPI_BUF0: u32 = 4294967295;
pub const SPI_BUF0_V: u32 = 4294967295;
pub const SPI_BUF0_S: u32 = 0;
pub const SPI_BUF1: u32 = 4294967295;
pub const SPI_BUF1_V: u32 = 4294967295;
pub const SPI_BUF1_S: u32 = 0;
pub const SPI_BUF2: u32 = 4294967295;
pub const SPI_BUF2_V: u32 = 4294967295;
pub const SPI_BUF2_S: u32 = 0;
pub const SPI_BUF3: u32 = 4294967295;
pub const SPI_BUF3_V: u32 = 4294967295;
pub const SPI_BUF3_S: u32 = 0;
pub const SPI_BUF4: u32 = 4294967295;
pub const SPI_BUF4_V: u32 = 4294967295;
pub const SPI_BUF4_S: u32 = 0;
pub const SPI_BUF5: u32 = 4294967295;
pub const SPI_BUF5_V: u32 = 4294967295;
pub const SPI_BUF5_S: u32 = 0;
pub const SPI_BUF6: u32 = 4294967295;
pub const SPI_BUF6_V: u32 = 4294967295;
pub const SPI_BUF6_S: u32 = 0;
pub const SPI_BUF7: u32 = 4294967295;
pub const SPI_BUF7_V: u32 = 4294967295;
pub const SPI_BUF7_S: u32 = 0;
pub const SPI_BUF8: u32 = 4294967295;
pub const SPI_BUF8_V: u32 = 4294967295;
pub const SPI_BUF8_S: u32 = 0;
pub const SPI_BUF9: u32 = 4294967295;
pub const SPI_BUF9_V: u32 = 4294967295;
pub const SPI_BUF9_S: u32 = 0;
pub const SPI_BUF10: u32 = 4294967295;
pub const SPI_BUF10_V: u32 = 4294967295;
pub const SPI_BUF10_S: u32 = 0;
pub const SPI_BUF11: u32 = 4294967295;
pub const SPI_BUF11_V: u32 = 4294967295;
pub const SPI_BUF11_S: u32 = 0;
pub const SPI_BUF12: u32 = 4294967295;
pub const SPI_BUF12_V: u32 = 4294967295;
pub const SPI_BUF12_S: u32 = 0;
pub const SPI_BUF13: u32 = 4294967295;
pub const SPI_BUF13_V: u32 = 4294967295;
pub const SPI_BUF13_S: u32 = 0;
pub const SPI_BUF14: u32 = 4294967295;
pub const SPI_BUF14_V: u32 = 4294967295;
pub const SPI_BUF14_S: u32 = 0;
pub const SPI_BUF15: u32 = 4294967295;
pub const SPI_BUF15_V: u32 = 4294967295;
pub const SPI_BUF15_S: u32 = 0;
pub const SPI_USR_CONF_V: u32 = 1;
pub const SPI_USR_CONF_S: u32 = 28;
pub const SPI_SOFT_RESET_V: u32 = 1;
pub const SPI_SOFT_RESET_S: u32 = 27;
pub const SPI_SLAVE_MODE_V: u32 = 1;
pub const SPI_SLAVE_MODE_S: u32 = 26;
pub const SPI_DMA_SEG_MAGIC_VALUE: u32 = 15;
pub const SPI_DMA_SEG_MAGIC_VALUE_V: u32 = 15;
pub const SPI_DMA_SEG_MAGIC_VALUE_S: u32 = 22;
pub const SPI_SLV_WRBUF_BITLEN_EN_V: u32 = 1;
pub const SPI_SLV_WRBUF_BITLEN_EN_S: u32 = 11;
pub const SPI_SLV_RDBUF_BITLEN_EN_V: u32 = 1;
pub const SPI_SLV_RDBUF_BITLEN_EN_S: u32 = 10;
pub const SPI_SLV_WRDMA_BITLEN_EN_V: u32 = 1;
pub const SPI_SLV_WRDMA_BITLEN_EN_S: u32 = 9;
pub const SPI_SLV_RDDMA_BITLEN_EN_V: u32 = 1;
pub const SPI_SLV_RDDMA_BITLEN_EN_S: u32 = 8;
pub const SPI_RSCK_DATA_OUT_V: u32 = 1;
pub const SPI_RSCK_DATA_OUT_S: u32 = 3;
pub const SPI_CLK_MODE_13_V: u32 = 1;
pub const SPI_CLK_MODE_13_S: u32 = 2;
pub const SPI_CLK_MODE: u32 = 3;
pub const SPI_CLK_MODE_V: u32 = 3;
pub const SPI_CLK_MODE_S: u32 = 0;
pub const SPI_SLV_LAST_ADDR: u32 = 63;
pub const SPI_SLV_LAST_ADDR_V: u32 = 63;
pub const SPI_SLV_LAST_ADDR_S: u32 = 26;
pub const SPI_SLV_LAST_COMMAND: u32 = 255;
pub const SPI_SLV_LAST_COMMAND_V: u32 = 255;
pub const SPI_SLV_LAST_COMMAND_S: u32 = 18;
pub const SPI_SLV_DATA_BITLEN: u32 = 262143;
pub const SPI_SLV_DATA_BITLEN_V: u32 = 262143;
pub const SPI_SLV_DATA_BITLEN_S: u32 = 0;
pub const SPI_MST_CLK_SEL_V: u32 = 1;
pub const SPI_MST_CLK_SEL_S: u32 = 2;
pub const SPI_MST_CLK_ACTIVE_V: u32 = 1;
pub const SPI_MST_CLK_ACTIVE_S: u32 = 1;
pub const SPI_CLK_EN_V: u32 = 1;
pub const SPI_CLK_EN_S: u32 = 0;
pub const SPI_DATE: u32 = 268435455;
pub const SPI_DATE_V: u32 = 268435455;
pub const SPI_DATE_S: u32 = 0;
pub const SPI_MEM_FLASH_READ_V: u32 = 1;
pub const SPI_MEM_FLASH_READ_S: u32 = 31;
pub const SPI_MEM_FLASH_WREN_V: u32 = 1;
pub const SPI_MEM_FLASH_WREN_S: u32 = 30;
pub const SPI_MEM_FLASH_WRDI_V: u32 = 1;
pub const SPI_MEM_FLASH_WRDI_S: u32 = 29;
pub const SPI_MEM_FLASH_RDID_V: u32 = 1;
pub const SPI_MEM_FLASH_RDID_S: u32 = 28;
pub const SPI_MEM_FLASH_RDSR_V: u32 = 1;
pub const SPI_MEM_FLASH_RDSR_S: u32 = 27;
pub const SPI_MEM_FLASH_WRSR_V: u32 = 1;
pub const SPI_MEM_FLASH_WRSR_S: u32 = 26;
pub const SPI_MEM_FLASH_PP_V: u32 = 1;
pub const SPI_MEM_FLASH_PP_S: u32 = 25;
pub const SPI_MEM_FLASH_SE_V: u32 = 1;
pub const SPI_MEM_FLASH_SE_S: u32 = 24;
pub const SPI_MEM_FLASH_BE_V: u32 = 1;
pub const SPI_MEM_FLASH_BE_S: u32 = 23;
pub const SPI_MEM_FLASH_CE_V: u32 = 1;
pub const SPI_MEM_FLASH_CE_S: u32 = 22;
pub const SPI_MEM_FLASH_DP_V: u32 = 1;
pub const SPI_MEM_FLASH_DP_S: u32 = 21;
pub const SPI_MEM_FLASH_RES_V: u32 = 1;
pub const SPI_MEM_FLASH_RES_S: u32 = 20;
pub const SPI_MEM_FLASH_HPM_V: u32 = 1;
pub const SPI_MEM_FLASH_HPM_S: u32 = 19;
pub const SPI_MEM_USR_V: u32 = 1;
pub const SPI_MEM_USR_S: u32 = 18;
pub const SPI_MEM_FLASH_PE_V: u32 = 1;
pub const SPI_MEM_FLASH_PE_S: u32 = 17;
pub const SPI_MEM_USR_ADDR_VALUE: u32 = 4294967295;
pub const SPI_MEM_USR_ADDR_VALUE_V: u32 = 4294967295;
pub const SPI_MEM_USR_ADDR_VALUE_S: u32 = 0;
pub const SPI_MEM_FREAD_QIO_V: u32 = 1;
pub const SPI_MEM_FREAD_QIO_S: u32 = 24;
pub const SPI_MEM_FREAD_DIO_V: u32 = 1;
pub const SPI_MEM_FREAD_DIO_S: u32 = 23;
pub const SPI_MEM_WRSR_2B_V: u32 = 1;
pub const SPI_MEM_WRSR_2B_S: u32 = 22;
pub const SPI_MEM_WP_REG_V: u32 = 1;
pub const SPI_MEM_WP_REG_S: u32 = 21;
pub const SPI_MEM_FREAD_QUAD_V: u32 = 1;
pub const SPI_MEM_FREAD_QUAD_S: u32 = 20;
pub const SPI_MEM_D_POL_V: u32 = 1;
pub const SPI_MEM_D_POL_S: u32 = 19;
pub const SPI_MEM_Q_POL_V: u32 = 1;
pub const SPI_MEM_Q_POL_S: u32 = 18;
pub const SPI_MEM_RESANDRES_V: u32 = 1;
pub const SPI_MEM_RESANDRES_S: u32 = 15;
pub const SPI_MEM_FREAD_DUAL_V: u32 = 1;
pub const SPI_MEM_FREAD_DUAL_S: u32 = 14;
pub const SPI_MEM_FASTRD_MODE_V: u32 = 1;
pub const SPI_MEM_FASTRD_MODE_S: u32 = 13;
pub const SPI_MEM_TX_CRC_EN_V: u32 = 1;
pub const SPI_MEM_TX_CRC_EN_S: u32 = 11;
pub const SPI_MEM_FCS_CRC_EN_V: u32 = 1;
pub const SPI_MEM_FCS_CRC_EN_S: u32 = 10;
pub const SPI_MEM_FCMD_OCT_V: u32 = 1;
pub const SPI_MEM_FCMD_OCT_S: u32 = 9;
pub const SPI_MEM_FCMD_QUAD_V: u32 = 1;
pub const SPI_MEM_FCMD_QUAD_S: u32 = 8;
pub const SPI_MEM_FCMD_DUAL_V: u32 = 1;
pub const SPI_MEM_FCMD_DUAL_S: u32 = 7;
pub const SPI_MEM_FADDR_OCT_V: u32 = 1;
pub const SPI_MEM_FADDR_OCT_S: u32 = 6;
pub const SPI_MEM_FDIN_OCT_V: u32 = 1;
pub const SPI_MEM_FDIN_OCT_S: u32 = 5;
pub const SPI_MEM_FDOUT_OCT_V: u32 = 1;
pub const SPI_MEM_FDOUT_OCT_S: u32 = 4;
pub const SPI_MEM_FDUMMY_OUT_V: u32 = 1;
pub const SPI_MEM_FDUMMY_OUT_S: u32 = 3;
pub const SPI_MEM_RXFIFO_RST_V: u32 = 1;
pub const SPI_MEM_RXFIFO_RST_S: u32 = 30;
pub const SPI_MEM_CS_HOLD_DLY_RES: u32 = 1023;
pub const SPI_MEM_CS_HOLD_DLY_RES_V: u32 = 1023;
pub const SPI_MEM_CS_HOLD_DLY_RES_S: u32 = 2;
pub const SPI_MEM_CLK_MODE: u32 = 3;
pub const SPI_MEM_CLK_MODE_V: u32 = 3;
pub const SPI_MEM_CLK_MODE_S: u32 = 0;
pub const SPI_MEM_SYNC_RESET_V: u32 = 1;
pub const SPI_MEM_SYNC_RESET_S: u32 = 31;
pub const SPI_MEM_CS_HOLD_DELAY: u32 = 63;
pub const SPI_MEM_CS_HOLD_DELAY_V: u32 = 63;
pub const SPI_MEM_CS_HOLD_DELAY_S: u32 = 25;
pub const SPI_MEM_ECC_16TO18_BYTE_EN_V: u32 = 1;
pub const SPI_MEM_ECC_16TO18_BYTE_EN_S: u32 = 14;
pub const SPI_MEM_ECC_SKIP_PAGE_CORNER_V: u32 = 1;
pub const SPI_MEM_ECC_SKIP_PAGE_CORNER_S: u32 = 13;
pub const SPI_MEM_ECC_CS_HOLD_TIME: u32 = 7;
pub const SPI_MEM_ECC_CS_HOLD_TIME_V: u32 = 7;
pub const SPI_MEM_ECC_CS_HOLD_TIME_S: u32 = 10;
pub const SPI_MEM_CS_HOLD_TIME: u32 = 31;
pub const SPI_MEM_CS_HOLD_TIME_V: u32 = 31;
pub const SPI_MEM_CS_HOLD_TIME_S: u32 = 5;
pub const SPI_MEM_CS_SETUP_TIME: u32 = 31;
pub const SPI_MEM_CS_SETUP_TIME_V: u32 = 31;
pub const SPI_MEM_CS_SETUP_TIME_S: u32 = 0;
pub const SPI_MEM_CLK_EQU_SYSCLK_V: u32 = 1;
pub const SPI_MEM_CLK_EQU_SYSCLK_S: u32 = 31;
pub const SPI_MEM_CLKCNT_N: u32 = 255;
pub const SPI_MEM_CLKCNT_N_V: u32 = 255;
pub const SPI_MEM_CLKCNT_N_S: u32 = 16;
pub const SPI_MEM_CLKCNT_H: u32 = 255;
pub const SPI_MEM_CLKCNT_H_V: u32 = 255;
pub const SPI_MEM_CLKCNT_H_S: u32 = 8;
pub const SPI_MEM_CLKCNT_L: u32 = 255;
pub const SPI_MEM_CLKCNT_L_V: u32 = 255;
pub const SPI_MEM_CLKCNT_L_S: u32 = 0;
pub const SPI_MEM_USR_COMMAND_V: u32 = 1;
pub const SPI_MEM_USR_COMMAND_S: u32 = 31;
pub const SPI_MEM_USR_ADDR_V: u32 = 1;
pub const SPI_MEM_USR_ADDR_S: u32 = 30;
pub const SPI_MEM_USR_DUMMY_V: u32 = 1;
pub const SPI_MEM_USR_DUMMY_S: u32 = 29;
pub const SPI_MEM_USR_MISO_V: u32 = 1;
pub const SPI_MEM_USR_MISO_S: u32 = 28;
pub const SPI_MEM_USR_MOSI_V: u32 = 1;
pub const SPI_MEM_USR_MOSI_S: u32 = 27;
pub const SPI_MEM_USR_DUMMY_IDLE_V: u32 = 1;
pub const SPI_MEM_USR_DUMMY_IDLE_S: u32 = 26;
pub const SPI_MEM_USR_MOSI_HIGHPART_V: u32 = 1;
pub const SPI_MEM_USR_MOSI_HIGHPART_S: u32 = 25;
pub const SPI_MEM_USR_MISO_HIGHPART_V: u32 = 1;
pub const SPI_MEM_USR_MISO_HIGHPART_S: u32 = 24;
pub const SPI_MEM_FWRITE_QIO_V: u32 = 1;
pub const SPI_MEM_FWRITE_QIO_S: u32 = 15;
pub const SPI_MEM_FWRITE_DIO_V: u32 = 1;
pub const SPI_MEM_FWRITE_DIO_S: u32 = 14;
pub const SPI_MEM_FWRITE_QUAD_V: u32 = 1;
pub const SPI_MEM_FWRITE_QUAD_S: u32 = 13;
pub const SPI_MEM_FWRITE_DUAL_V: u32 = 1;
pub const SPI_MEM_FWRITE_DUAL_S: u32 = 12;
pub const SPI_MEM_CK_OUT_EDGE_V: u32 = 1;
pub const SPI_MEM_CK_OUT_EDGE_S: u32 = 9;
pub const SPI_MEM_CS_SETUP_V: u32 = 1;
pub const SPI_MEM_CS_SETUP_S: u32 = 7;
pub const SPI_MEM_CS_HOLD_V: u32 = 1;
pub const SPI_MEM_CS_HOLD_S: u32 = 6;
pub const SPI_MEM_USR_ADDR_BITLEN: u32 = 63;
pub const SPI_MEM_USR_ADDR_BITLEN_V: u32 = 63;
pub const SPI_MEM_USR_ADDR_BITLEN_S: u32 = 26;
pub const SPI_MEM_USR_DUMMY_CYCLELEN: u32 = 63;
pub const SPI_MEM_USR_DUMMY_CYCLELEN_V: u32 = 63;
pub const SPI_MEM_USR_DUMMY_CYCLELEN_S: u32 = 0;
pub const SPI_MEM_USR_COMMAND_BITLEN: u32 = 15;
pub const SPI_MEM_USR_COMMAND_BITLEN_V: u32 = 15;
pub const SPI_MEM_USR_COMMAND_BITLEN_S: u32 = 28;
pub const SPI_MEM_USR_COMMAND_VALUE: u32 = 65535;
pub const SPI_MEM_USR_COMMAND_VALUE_V: u32 = 65535;
pub const SPI_MEM_USR_COMMAND_VALUE_S: u32 = 0;
pub const SPI_MEM_USR_MOSI_DBITLEN: u32 = 1023;
pub const SPI_MEM_USR_MOSI_DBITLEN_V: u32 = 1023;
pub const SPI_MEM_USR_MOSI_DBITLEN_S: u32 = 0;
pub const SPI_MEM_USR_MISO_DBITLEN: u32 = 1023;
pub const SPI_MEM_USR_MISO_DBITLEN_V: u32 = 1023;
pub const SPI_MEM_USR_MISO_DBITLEN_S: u32 = 0;
pub const SPI_MEM_WB_MODE: u32 = 255;
pub const SPI_MEM_WB_MODE_V: u32 = 255;
pub const SPI_MEM_WB_MODE_S: u32 = 16;
pub const SPI_MEM_STATUS: u32 = 65535;
pub const SPI_MEM_STATUS_V: u32 = 65535;
pub const SPI_MEM_STATUS_S: u32 = 0;
pub const SPI_MEM_EXT_ADDR: u32 = 4294967295;
pub const SPI_MEM_EXT_ADDR_V: u32 = 4294967295;
pub const SPI_MEM_EXT_ADDR_S: u32 = 0;
pub const SPI_MEM_AUTO_PER_V: u32 = 1;
pub const SPI_MEM_AUTO_PER_S: u32 = 11;
pub const SPI_MEM_CS_KEEP_ACTIVE_V: u32 = 1;
pub const SPI_MEM_CS_KEEP_ACTIVE_S: u32 = 10;
pub const SPI_MEM_CK_IDLE_EDGE_V: u32 = 1;
pub const SPI_MEM_CK_IDLE_EDGE_S: u32 = 9;
pub const SPI_MEM_SSUB_PIN_V: u32 = 1;
pub const SPI_MEM_SSUB_PIN_S: u32 = 8;
pub const SPI_MEM_FSUB_PIN_V: u32 = 1;
pub const SPI_MEM_FSUB_PIN_S: u32 = 7;
pub const SPI_MEM_CS1_DIS_V: u32 = 1;
pub const SPI_MEM_CS1_DIS_S: u32 = 1;
pub const SPI_MEM_CS0_DIS_V: u32 = 1;
pub const SPI_MEM_CS0_DIS_S: u32 = 0;
pub const SPI_MEM_TX_CRC_DATA: u32 = 4294967295;
pub const SPI_MEM_TX_CRC_DATA_V: u32 = 4294967295;
pub const SPI_MEM_TX_CRC_DATA_S: u32 = 0;
pub const SPI_MEM_FADDR_QUAD_V: u32 = 1;
pub const SPI_MEM_FADDR_QUAD_S: u32 = 8;
pub const SPI_MEM_FDOUT_QUAD_V: u32 = 1;
pub const SPI_MEM_FDOUT_QUAD_S: u32 = 7;
pub const SPI_MEM_FDIN_QUAD_V: u32 = 1;
pub const SPI_MEM_FDIN_QUAD_S: u32 = 6;
pub const SPI_MEM_FADDR_DUAL_V: u32 = 1;
pub const SPI_MEM_FADDR_DUAL_S: u32 = 5;
pub const SPI_MEM_FDOUT_DUAL_V: u32 = 1;
pub const SPI_MEM_FDOUT_DUAL_S: u32 = 4;
pub const SPI_MEM_FDIN_DUAL_V: u32 = 1;
pub const SPI_MEM_FDIN_DUAL_S: u32 = 3;
pub const SPI_MEM_CACHE_FLASH_USR_CMD_V: u32 = 1;
pub const SPI_MEM_CACHE_FLASH_USR_CMD_S: u32 = 2;
pub const SPI_MEM_CACHE_USR_CMD_4BYTE_V: u32 = 1;
pub const SPI_MEM_CACHE_USR_CMD_4BYTE_S: u32 = 1;
pub const SPI_MEM_CACHE_REQ_EN_V: u32 = 1;
pub const SPI_MEM_CACHE_REQ_EN_S: u32 = 0;
pub const SPI_MEM_SRAM_WDUMMY_CYCLELEN: u32 = 63;
pub const SPI_MEM_SRAM_WDUMMY_CYCLELEN_V: u32 = 63;
pub const SPI_MEM_SRAM_WDUMMY_CYCLELEN_S: u32 = 22;
pub const SPI_MEM_SRAM_OCT_V: u32 = 1;
pub const SPI_MEM_SRAM_OCT_S: u32 = 21;
pub const SPI_MEM_CACHE_SRAM_USR_WCMD_V: u32 = 1;
pub const SPI_MEM_CACHE_SRAM_USR_WCMD_S: u32 = 20;
pub const SPI_MEM_SRAM_ADDR_BITLEN: u32 = 63;
pub const SPI_MEM_SRAM_ADDR_BITLEN_V: u32 = 63;
pub const SPI_MEM_SRAM_ADDR_BITLEN_S: u32 = 14;
pub const SPI_MEM_SRAM_RDUMMY_CYCLELEN: u32 = 63;
pub const SPI_MEM_SRAM_RDUMMY_CYCLELEN_V: u32 = 63;
pub const SPI_MEM_SRAM_RDUMMY_CYCLELEN_S: u32 = 6;
pub const SPI_MEM_CACHE_SRAM_USR_RCMD_V: u32 = 1;
pub const SPI_MEM_CACHE_SRAM_USR_RCMD_S: u32 = 5;
pub const SPI_MEM_USR_RD_SRAM_DUMMY_V: u32 = 1;
pub const SPI_MEM_USR_RD_SRAM_DUMMY_S: u32 = 4;
pub const SPI_MEM_USR_WR_SRAM_DUMMY_V: u32 = 1;
pub const SPI_MEM_USR_WR_SRAM_DUMMY_S: u32 = 3;
pub const SPI_MEM_USR_SRAM_QIO_V: u32 = 1;
pub const SPI_MEM_USR_SRAM_QIO_S: u32 = 2;
pub const SPI_MEM_USR_SRAM_DIO_V: u32 = 1;
pub const SPI_MEM_USR_SRAM_DIO_S: u32 = 1;
pub const SPI_MEM_CACHE_USR_SCMD_4BYTE_V: u32 = 1;
pub const SPI_MEM_CACHE_USR_SCMD_4BYTE_S: u32 = 0;
pub const SPI_MEM_SDUMMY_OUT_V: u32 = 1;
pub const SPI_MEM_SDUMMY_OUT_S: u32 = 22;
pub const SPI_MEM_SCMD_OCT_V: u32 = 1;
pub const SPI_MEM_SCMD_OCT_S: u32 = 21;
pub const SPI_MEM_SADDR_OCT_V: u32 = 1;
pub const SPI_MEM_SADDR_OCT_S: u32 = 20;
pub const SPI_MEM_SDOUT_OCT_V: u32 = 1;
pub const SPI_MEM_SDOUT_OCT_S: u32 = 19;
pub const SPI_MEM_SDIN_OCT_V: u32 = 1;
pub const SPI_MEM_SDIN_OCT_S: u32 = 18;
pub const SPI_MEM_SCMD_QUAD_V: u32 = 1;
pub const SPI_MEM_SCMD_QUAD_S: u32 = 17;
pub const SPI_MEM_SADDR_QUAD_V: u32 = 1;
pub const SPI_MEM_SADDR_QUAD_S: u32 = 16;
pub const SPI_MEM_SDOUT_QUAD_V: u32 = 1;
pub const SPI_MEM_SDOUT_QUAD_S: u32 = 15;
pub const SPI_MEM_SDIN_QUAD_V: u32 = 1;
pub const SPI_MEM_SDIN_QUAD_S: u32 = 14;
pub const SPI_MEM_SCMD_DUAL_V: u32 = 1;
pub const SPI_MEM_SCMD_DUAL_S: u32 = 13;
pub const SPI_MEM_SADDR_DUAL_V: u32 = 1;
pub const SPI_MEM_SADDR_DUAL_S: u32 = 12;
pub const SPI_MEM_SDOUT_DUAL_V: u32 = 1;
pub const SPI_MEM_SDOUT_DUAL_S: u32 = 11;
pub const SPI_MEM_SDIN_DUAL_V: u32 = 1;
pub const SPI_MEM_SDIN_DUAL_S: u32 = 10;
pub const SPI_MEM_SWB_MODE: u32 = 255;
pub const SPI_MEM_SWB_MODE_V: u32 = 255;
pub const SPI_MEM_SWB_MODE_S: u32 = 2;
pub const SPI_MEM_SCLK_MODE: u32 = 3;
pub const SPI_MEM_SCLK_MODE_V: u32 = 3;
pub const SPI_MEM_SCLK_MODE_S: u32 = 0;
pub const SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN: u32 = 15;
pub const SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V: u32 = 15;
pub const SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S: u32 = 28;
pub const SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE: u32 = 65535;
pub const SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V: u32 = 65535;
pub const SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S: u32 = 0;
pub const SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN: u32 = 15;
pub const SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V: u32 = 15;
pub const SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S: u32 = 28;
pub const SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE: u32 = 65535;
pub const SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V: u32 = 65535;
pub const SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S: u32 = 0;
pub const SPI_MEM_SCLK_EQU_SYSCLK_V: u32 = 1;
pub const SPI_MEM_SCLK_EQU_SYSCLK_S: u32 = 31;
pub const SPI_MEM_SCLKCNT_N: u32 = 255;
pub const SPI_MEM_SCLKCNT_N_V: u32 = 255;
pub const SPI_MEM_SCLKCNT_N_S: u32 = 16;
pub const SPI_MEM_SCLKCNT_H: u32 = 255;
pub const SPI_MEM_SCLKCNT_H_V: u32 = 255;
pub const SPI_MEM_SCLKCNT_H_S: u32 = 8;
pub const SPI_MEM_SCLKCNT_L: u32 = 255;
pub const SPI_MEM_SCLKCNT_L_V: u32 = 255;
pub const SPI_MEM_SCLKCNT_L_S: u32 = 0;
pub const SPI_MEM_ST: u32 = 7;
pub const SPI_MEM_ST_V: u32 = 7;
pub const SPI_MEM_ST_S: u32 = 0;
pub const SPI_MEM_BUF0: u32 = 4294967295;
pub const SPI_MEM_BUF0_V: u32 = 4294967295;
pub const SPI_MEM_BUF0_S: u32 = 0;
pub const SPI_MEM_BUF1: u32 = 4294967295;
pub const SPI_MEM_BUF1_V: u32 = 4294967295;
pub const SPI_MEM_BUF1_S: u32 = 0;
pub const SPI_MEM_BUF2: u32 = 4294967295;
pub const SPI_MEM_BUF2_V: u32 = 4294967295;
pub const SPI_MEM_BUF2_S: u32 = 0;
pub const SPI_MEM_BUF3: u32 = 4294967295;
pub const SPI_MEM_BUF3_V: u32 = 4294967295;
pub const SPI_MEM_BUF3_S: u32 = 0;
pub const SPI_MEM_BUF4: u32 = 4294967295;
pub const SPI_MEM_BUF4_V: u32 = 4294967295;
pub const SPI_MEM_BUF4_S: u32 = 0;
pub const SPI_MEM_BUF5: u32 = 4294967295;
pub const SPI_MEM_BUF5_V: u32 = 4294967295;
pub const SPI_MEM_BUF5_S: u32 = 0;
pub const SPI_MEM_BUF6: u32 = 4294967295;
pub const SPI_MEM_BUF6_V: u32 = 4294967295;
pub const SPI_MEM_BUF6_S: u32 = 0;
pub const SPI_MEM_BUF7: u32 = 4294967295;
pub const SPI_MEM_BUF7_V: u32 = 4294967295;
pub const SPI_MEM_BUF7_S: u32 = 0;
pub const SPI_MEM_BUF8: u32 = 4294967295;
pub const SPI_MEM_BUF8_V: u32 = 4294967295;
pub const SPI_MEM_BUF8_S: u32 = 0;
pub const SPI_MEM_BUF9: u32 = 4294967295;
pub const SPI_MEM_BUF9_V: u32 = 4294967295;
pub const SPI_MEM_BUF9_S: u32 = 0;
pub const SPI_MEM_BUF10: u32 = 4294967295;
pub const SPI_MEM_BUF10_V: u32 = 4294967295;
pub const SPI_MEM_BUF10_S: u32 = 0;
pub const SPI_MEM_BUF11: u32 = 4294967295;
pub const SPI_MEM_BUF11_V: u32 = 4294967295;
pub const SPI_MEM_BUF11_S: u32 = 0;
pub const SPI_MEM_BUF12: u32 = 4294967295;
pub const SPI_MEM_BUF12_V: u32 = 4294967295;
pub const SPI_MEM_BUF12_S: u32 = 0;
pub const SPI_MEM_BUF13: u32 = 4294967295;
pub const SPI_MEM_BUF13_V: u32 = 4294967295;
pub const SPI_MEM_BUF13_S: u32 = 0;
pub const SPI_MEM_BUF14: u32 = 4294967295;
pub const SPI_MEM_BUF14_V: u32 = 4294967295;
pub const SPI_MEM_BUF14_S: u32 = 0;
pub const SPI_MEM_BUF15: u32 = 4294967295;
pub const SPI_MEM_BUF15_V: u32 = 4294967295;
pub const SPI_MEM_BUF15_S: u32 = 0;
pub const SPI_MEM_WAITI_DUMMY_CYCLELEN: u32 = 63;
pub const SPI_MEM_WAITI_DUMMY_CYCLELEN_V: u32 = 63;
pub const SPI_MEM_WAITI_DUMMY_CYCLELEN_S: u32 = 10;
pub const SPI_MEM_WAITI_CMD: u32 = 255;
pub const SPI_MEM_WAITI_CMD_V: u32 = 255;
pub const SPI_MEM_WAITI_CMD_S: u32 = 2;
pub const SPI_MEM_WAITI_DUMMY_V: u32 = 1;
pub const SPI_MEM_WAITI_DUMMY_S: u32 = 1;
pub const SPI_MEM_WAITI_EN_V: u32 = 1;
pub const SPI_MEM_WAITI_EN_S: u32 = 0;
pub const SPI_MEM_PESR_IDLE_EN_V: u32 = 1;
pub const SPI_MEM_PESR_IDLE_EN_S: u32 = 5;
pub const SPI_MEM_PES_PER_EN_V: u32 = 1;
pub const SPI_MEM_PES_PER_EN_S: u32 = 4;
pub const SPI_MEM_FLASH_PES_WAIT_EN_V: u32 = 1;
pub const SPI_MEM_FLASH_PES_WAIT_EN_S: u32 = 3;
pub const SPI_MEM_FLASH_PER_WAIT_EN_V: u32 = 1;
pub const SPI_MEM_FLASH_PER_WAIT_EN_S: u32 = 2;
pub const SPI_MEM_FLASH_PES_V: u32 = 1;
pub const SPI_MEM_FLASH_PES_S: u32 = 1;
pub const SPI_MEM_FLASH_PER_V: u32 = 1;
pub const SPI_MEM_FLASH_PER_S: u32 = 0;
pub const SPI_MEM_FLASH_PES_COMMAND: u32 = 255;
pub const SPI_MEM_FLASH_PES_COMMAND_V: u32 = 255;
pub const SPI_MEM_FLASH_PES_COMMAND_S: u32 = 9;
pub const SPI_MEM_FLASH_PER_COMMAND: u32 = 255;
pub const SPI_MEM_FLASH_PER_COMMAND_V: u32 = 255;
pub const SPI_MEM_FLASH_PER_COMMAND_S: u32 = 1;
pub const SPI_MEM_FLASH_PES_EN_V: u32 = 1;
pub const SPI_MEM_FLASH_PES_EN_S: u32 = 0;
pub const SPI_MEM_FLASH_PES_DLY_256_V: u32 = 1;
pub const SPI_MEM_FLASH_PES_DLY_256_S: u32 = 6;
pub const SPI_MEM_FLASH_PER_DLY_256_V: u32 = 1;
pub const SPI_MEM_FLASH_PER_DLY_256_S: u32 = 5;
pub const SPI_MEM_FLASH_DP_DLY_256_V: u32 = 1;
pub const SPI_MEM_FLASH_DP_DLY_256_S: u32 = 4;
pub const SPI_MEM_FLASH_RES_DLY_256_V: u32 = 1;
pub const SPI_MEM_FLASH_RES_DLY_256_S: u32 = 3;
pub const SPI_MEM_FLASH_HPM_DLY_256_V: u32 = 1;
pub const SPI_MEM_FLASH_HPM_DLY_256_S: u32 = 2;
pub const SPI_MEM_FLASH_SUS_V: u32 = 1;
pub const SPI_MEM_FLASH_SUS_S: u32 = 0;
pub const SPI_MEM_EXTRA_DUMMY_CYCLELEN: u32 = 7;
pub const SPI_MEM_EXTRA_DUMMY_CYCLELEN_V: u32 = 7;
pub const SPI_MEM_EXTRA_DUMMY_CYCLELEN_S: u32 = 2;
pub const SPI_MEM_TIMING_CALI_V: u32 = 1;
pub const SPI_MEM_TIMING_CALI_S: u32 = 1;
pub const SPI_MEM_TIMING_CLK_ENA_V: u32 = 1;
pub const SPI_MEM_TIMING_CLK_ENA_S: u32 = 0;
pub const SPI_MEM_DINS_MODE: u32 = 7;
pub const SPI_MEM_DINS_MODE_V: u32 = 7;
pub const SPI_MEM_DINS_MODE_S: u32 = 24;
pub const SPI_MEM_DIN7_MODE: u32 = 7;
pub const SPI_MEM_DIN7_MODE_V: u32 = 7;
pub const SPI_MEM_DIN7_MODE_S: u32 = 21;
pub const SPI_MEM_DIN6_MODE: u32 = 7;
pub const SPI_MEM_DIN6_MODE_V: u32 = 7;
pub const SPI_MEM_DIN6_MODE_S: u32 = 18;
pub const SPI_MEM_DIN5_MODE: u32 = 7;
pub const SPI_MEM_DIN5_MODE_V: u32 = 7;
pub const SPI_MEM_DIN5_MODE_S: u32 = 15;
pub const SPI_MEM_DIN4_MODE: u32 = 7;
pub const SPI_MEM_DIN4_MODE_V: u32 = 7;
pub const SPI_MEM_DIN4_MODE_S: u32 = 12;
pub const SPI_MEM_DIN3_MODE: u32 = 7;
pub const SPI_MEM_DIN3_MODE_V: u32 = 7;
pub const SPI_MEM_DIN3_MODE_S: u32 = 9;
pub const SPI_MEM_DIN2_MODE: u32 = 7;
pub const SPI_MEM_DIN2_MODE_V: u32 = 7;
pub const SPI_MEM_DIN2_MODE_S: u32 = 6;
pub const SPI_MEM_DIN1_MODE: u32 = 7;
pub const SPI_MEM_DIN1_MODE_V: u32 = 7;
pub const SPI_MEM_DIN1_MODE_S: u32 = 3;
pub const SPI_MEM_DIN0_MODE: u32 = 7;
pub const SPI_MEM_DIN0_MODE_V: u32 = 7;
pub const SPI_MEM_DIN0_MODE_S: u32 = 0;
pub const SPI_MEM_DINS_NUM: u32 = 3;
pub const SPI_MEM_DINS_NUM_V: u32 = 3;
pub const SPI_MEM_DINS_NUM_S: u32 = 16;
pub const SPI_MEM_DIN7_NUM: u32 = 3;
pub const SPI_MEM_DIN7_NUM_V: u32 = 3;
pub const SPI_MEM_DIN7_NUM_S: u32 = 14;
pub const SPI_MEM_DIN6_NUM: u32 = 3;
pub const SPI_MEM_DIN6_NUM_V: u32 = 3;
pub const SPI_MEM_DIN6_NUM_S: u32 = 12;
pub const SPI_MEM_DIN5_NUM: u32 = 3;
pub const SPI_MEM_DIN5_NUM_V: u32 = 3;
pub const SPI_MEM_DIN5_NUM_S: u32 = 10;
pub const SPI_MEM_DIN4_NUM: u32 = 3;
pub const SPI_MEM_DIN4_NUM_V: u32 = 3;
pub const SPI_MEM_DIN4_NUM_S: u32 = 8;
pub const SPI_MEM_DIN3_NUM: u32 = 3;
pub const SPI_MEM_DIN3_NUM_V: u32 = 3;
pub const SPI_MEM_DIN3_NUM_S: u32 = 6;
pub const SPI_MEM_DIN2_NUM: u32 = 3;
pub const SPI_MEM_DIN2_NUM_V: u32 = 3;
pub const SPI_MEM_DIN2_NUM_S: u32 = 4;
pub const SPI_MEM_DIN1_NUM: u32 = 3;
pub const SPI_MEM_DIN1_NUM_V: u32 = 3;
pub const SPI_MEM_DIN1_NUM_S: u32 = 2;
pub const SPI_MEM_DIN0_NUM: u32 = 3;
pub const SPI_MEM_DIN0_NUM_V: u32 = 3;
pub const SPI_MEM_DIN0_NUM_S: u32 = 0;
pub const SPI_MEM_DOUTS_MODE_V: u32 = 1;
pub const SPI_MEM_DOUTS_MODE_S: u32 = 8;
pub const SPI_MEM_DOUT7_MODE_V: u32 = 1;
pub const SPI_MEM_DOUT7_MODE_S: u32 = 7;
pub const SPI_MEM_DOUT6_MODE_V: u32 = 1;
pub const SPI_MEM_DOUT6_MODE_S: u32 = 6;
pub const SPI_MEM_DOUT5_MODE_V: u32 = 1;
pub const SPI_MEM_DOUT5_MODE_S: u32 = 5;
pub const SPI_MEM_DOUT4_MODE_V: u32 = 1;
pub const SPI_MEM_DOUT4_MODE_S: u32 = 4;
pub const SPI_MEM_DOUT3_MODE_V: u32 = 1;
pub const SPI_MEM_DOUT3_MODE_S: u32 = 3;
pub const SPI_MEM_DOUT2_MODE_V: u32 = 1;
pub const SPI_MEM_DOUT2_MODE_S: u32 = 2;
pub const SPI_MEM_DOUT1_MODE_V: u32 = 1;
pub const SPI_MEM_DOUT1_MODE_S: u32 = 1;
pub const SPI_MEM_DOUT0_MODE_V: u32 = 1;
pub const SPI_MEM_DOUT0_MODE_S: u32 = 0;
pub const SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN: u32 = 7;
pub const SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S: u32 = 2;
pub const SPI_MEM_SPI_SMEM_TIMING_CALI_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_TIMING_CALI_S: u32 = 1;
pub const SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S: u32 = 0;
pub const SPI_MEM_SPI_SMEM_DINS_MODE: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DINS_MODE_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DINS_MODE_S: u32 = 24;
pub const SPI_MEM_SPI_SMEM_DIN7_MODE: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN7_MODE_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN7_MODE_S: u32 = 21;
pub const SPI_MEM_SPI_SMEM_DIN6_MODE: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN6_MODE_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN6_MODE_S: u32 = 18;
pub const SPI_MEM_SPI_SMEM_DIN5_MODE: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN5_MODE_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN5_MODE_S: u32 = 15;
pub const SPI_MEM_SPI_SMEM_DIN4_MODE: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN4_MODE_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN4_MODE_S: u32 = 12;
pub const SPI_MEM_SPI_SMEM_DIN3_MODE: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN3_MODE_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN3_MODE_S: u32 = 9;
pub const SPI_MEM_SPI_SMEM_DIN2_MODE: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN2_MODE_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN2_MODE_S: u32 = 6;
pub const SPI_MEM_SPI_SMEM_DIN1_MODE: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN1_MODE_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN1_MODE_S: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN0_MODE: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN0_MODE_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DIN0_MODE_S: u32 = 0;
pub const SPI_MEM_SPI_SMEM_DINS_NUM: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DINS_NUM_V: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DINS_NUM_S: u32 = 16;
pub const SPI_MEM_SPI_SMEM_DIN7_NUM: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN7_NUM_V: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN7_NUM_S: u32 = 14;
pub const SPI_MEM_SPI_SMEM_DIN6_NUM: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN6_NUM_V: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN6_NUM_S: u32 = 12;
pub const SPI_MEM_SPI_SMEM_DIN5_NUM: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN5_NUM_V: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN5_NUM_S: u32 = 10;
pub const SPI_MEM_SPI_SMEM_DIN4_NUM: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN4_NUM_V: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN4_NUM_S: u32 = 8;
pub const SPI_MEM_SPI_SMEM_DIN3_NUM: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN3_NUM_V: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN3_NUM_S: u32 = 6;
pub const SPI_MEM_SPI_SMEM_DIN2_NUM: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN2_NUM_V: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN2_NUM_S: u32 = 4;
pub const SPI_MEM_SPI_SMEM_DIN1_NUM: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN1_NUM_V: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN1_NUM_S: u32 = 2;
pub const SPI_MEM_SPI_SMEM_DIN0_NUM: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN0_NUM_V: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DIN0_NUM_S: u32 = 0;
pub const SPI_MEM_SPI_SMEM_DOUTS_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DOUTS_MODE_S: u32 = 8;
pub const SPI_MEM_SPI_SMEM_DOUT7_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DOUT7_MODE_S: u32 = 7;
pub const SPI_MEM_SPI_SMEM_DOUT6_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DOUT6_MODE_S: u32 = 6;
pub const SPI_MEM_SPI_SMEM_DOUT5_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DOUT5_MODE_S: u32 = 5;
pub const SPI_MEM_SPI_SMEM_DOUT4_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DOUT4_MODE_S: u32 = 4;
pub const SPI_MEM_SPI_SMEM_DOUT3_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DOUT3_MODE_S: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DOUT2_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DOUT2_MODE_S: u32 = 2;
pub const SPI_MEM_SPI_SMEM_DOUT1_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DOUT1_MODE_S: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DOUT0_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DOUT0_MODE_S: u32 = 0;
pub const SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S: u32 = 8;
pub const SPI_MEM_ECC_ERR_INT_NUM: u32 = 255;
pub const SPI_MEM_ECC_ERR_INT_NUM_V: u32 = 255;
pub const SPI_MEM_ECC_ERR_INT_NUM_S: u32 = 0;
pub const SPI_MEM_ECC_ERR_ADDR: u32 = 4294967295;
pub const SPI_MEM_ECC_ERR_ADDR_V: u32 = 4294967295;
pub const SPI_MEM_ECC_ERR_ADDR_S: u32 = 0;
pub const SPI_MEM_ECC_ERR_CNT: u32 = 255;
pub const SPI_MEM_ECC_ERR_CNT_V: u32 = 255;
pub const SPI_MEM_ECC_ERR_CNT_S: u32 = 17;
pub const SPI_MEM_ECC_BYTE_ERR_V: u32 = 1;
pub const SPI_MEM_ECC_BYTE_ERR_S: u32 = 16;
pub const SPI_MEM_ECC_CHK_ERR_BIT: u32 = 7;
pub const SPI_MEM_ECC_CHK_ERR_BIT_V: u32 = 7;
pub const SPI_MEM_ECC_CHK_ERR_BIT_S: u32 = 13;
pub const SPI_MEM_ECC_DATA_ERR_BIT: u32 = 127;
pub const SPI_MEM_ECC_DATA_ERR_BIT_V: u32 = 127;
pub const SPI_MEM_ECC_DATA_ERR_BIT_S: u32 = 6;
pub const SPI_MEM_SPI_SMEM_CS_HOLD_DELAY: u32 = 63;
pub const SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V: u32 = 63;
pub const SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S: u32 = 25;
pub const SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S: u32 = 24;
pub const SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S: u32 = 16;
pub const SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S: u32 = 15;
pub const SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME: u32 = 7;
pub const SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V: u32 = 7;
pub const SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S: u32 = 12;
pub const SPI_MEM_SPI_SMEM_CS_HOLD_TIME: u32 = 31;
pub const SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V: u32 = 31;
pub const SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S: u32 = 7;
pub const SPI_MEM_SPI_SMEM_CS_SETUP_TIME: u32 = 31;
pub const SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V: u32 = 31;
pub const SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S: u32 = 2;
pub const SPI_MEM_SPI_SMEM_CS_HOLD_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_CS_HOLD_S: u32 = 1;
pub const SPI_MEM_SPI_SMEM_CS_SETUP_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_CS_SETUP_S: u32 = 0;
pub const SPI_MEM_SPI_FMEM_HYPERBUS_CA_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_HYPERBUS_CA_S: u32 = 30;
pub const SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S: u32 = 29;
pub const SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S: u32 = 28;
pub const SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S: u32 = 27;
pub const SPI_MEM_SPI_FMEM_DQS_CA_IN_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_DQS_CA_IN_S: u32 = 26;
pub const SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S: u32 = 25;
pub const SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S: u32 = 24;
pub const SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S: u32 = 22;
pub const SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S: u32 = 21;
pub const SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD: u32 = 127;
pub const SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V: u32 = 127;
pub const SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S: u32 = 14;
pub const SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S: u32 = 13;
pub const SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S: u32 = 12;
pub const SPI_MEM_SPI_FMEM_OUTMINBYTELEN: u32 = 127;
pub const SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V: u32 = 127;
pub const SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S: u32 = 5;
pub const SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S: u32 = 4;
pub const SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S: u32 = 3;
pub const SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S: u32 = 2;
pub const SPI_MEM_SPI_FMEM_VAR_DUMMY_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_VAR_DUMMY_S: u32 = 1;
pub const SPI_MEM_SPI_FMEM_DDR_EN_V: u32 = 1;
pub const SPI_MEM_SPI_FMEM_DDR_EN_S: u32 = 0;
pub const SPI_MEM_SPI_SMEM_HYPERBUS_CA_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_HYPERBUS_CA_S: u32 = 30;
pub const SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S: u32 = 29;
pub const SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S: u32 = 28;
pub const SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S: u32 = 27;
pub const SPI_MEM_SPI_SMEM_DQS_CA_IN_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DQS_CA_IN_S: u32 = 26;
pub const SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S: u32 = 25;
pub const SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S: u32 = 24;
pub const SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S: u32 = 22;
pub const SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S: u32 = 21;
pub const SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD: u32 = 127;
pub const SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V: u32 = 127;
pub const SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S: u32 = 14;
pub const SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S: u32 = 13;
pub const SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S: u32 = 12;
pub const SPI_MEM_SPI_SMEM_OUTMINBYTELEN: u32 = 127;
pub const SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V: u32 = 127;
pub const SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S: u32 = 5;
pub const SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S: u32 = 4;
pub const SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S: u32 = 3;
pub const SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S: u32 = 2;
pub const SPI_MEM_SPI_SMEM_VAR_DUMMY_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_VAR_DUMMY_S: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DDR_EN_V: u32 = 1;
pub const SPI_MEM_SPI_SMEM_DDR_EN_S: u32 = 0;
pub const SPI_MEM_CLK_EN_V: u32 = 1;
pub const SPI_MEM_CLK_EN_S: u32 = 0;
pub const SPI_MEM_CORE_CLK_SEL: u32 = 3;
pub const SPI_MEM_CORE_CLK_SEL_V: u32 = 3;
pub const SPI_MEM_CORE_CLK_SEL_S: u32 = 0;
pub const SPI_MEM_ECC_ERR_INT_ENA_V: u32 = 1;
pub const SPI_MEM_ECC_ERR_INT_ENA_S: u32 = 4;
pub const SPI_MEM_BROWN_OUT_INT_ENA_V: u32 = 1;
pub const SPI_MEM_BROWN_OUT_INT_ENA_S: u32 = 3;
pub const SPI_MEM_TOTAL_TRANS_END_INT_ENA_V: u32 = 1;
pub const SPI_MEM_TOTAL_TRANS_END_INT_ENA_S: u32 = 2;
pub const SPI_MEM_PES_END_INT_ENA_V: u32 = 1;
pub const SPI_MEM_PES_END_INT_ENA_S: u32 = 1;
pub const SPI_MEM_PER_END_INT_ENA_V: u32 = 1;
pub const SPI_MEM_PER_END_INT_ENA_S: u32 = 0;
pub const SPI_MEM_ECC_ERR_INT_CLR_V: u32 = 1;
pub const SPI_MEM_ECC_ERR_INT_CLR_S: u32 = 4;
pub const SPI_MEM_BROWN_OUT_INT_CLR_V: u32 = 1;
pub const SPI_MEM_BROWN_OUT_INT_CLR_S: u32 = 3;
pub const SPI_MEM_TOTAL_TRANS_END_INT_CLR_V: u32 = 1;
pub const SPI_MEM_TOTAL_TRANS_END_INT_CLR_S: u32 = 2;
pub const SPI_MEM_PES_END_INT_CLR_V: u32 = 1;
pub const SPI_MEM_PES_END_INT_CLR_S: u32 = 1;
pub const SPI_MEM_PER_END_INT_CLR_V: u32 = 1;
pub const SPI_MEM_PER_END_INT_CLR_S: u32 = 0;
pub const SPI_MEM_ECC_ERR_INT_RAW_V: u32 = 1;
pub const SPI_MEM_ECC_ERR_INT_RAW_S: u32 = 4;
pub const SPI_MEM_BROWN_OUT_INT_RAW_V: u32 = 1;
pub const SPI_MEM_BROWN_OUT_INT_RAW_S: u32 = 3;
pub const SPI_MEM_TOTAL_TRANS_END_INT_RAW_V: u32 = 1;
pub const SPI_MEM_TOTAL_TRANS_END_INT_RAW_S: u32 = 2;
pub const SPI_MEM_PES_END_INT_RAW_V: u32 = 1;
pub const SPI_MEM_PES_END_INT_RAW_S: u32 = 1;
pub const SPI_MEM_PER_END_INT_RAW_V: u32 = 1;
pub const SPI_MEM_PER_END_INT_RAW_S: u32 = 0;
pub const SPI_MEM_ECC_ERR_INT_ST_V: u32 = 1;
pub const SPI_MEM_ECC_ERR_INT_ST_S: u32 = 4;
pub const SPI_MEM_BROWN_OUT_INT_ST_V: u32 = 1;
pub const SPI_MEM_BROWN_OUT_INT_ST_S: u32 = 3;
pub const SPI_MEM_TOTAL_TRANS_END_INT_ST_V: u32 = 1;
pub const SPI_MEM_TOTAL_TRANS_END_INT_ST_S: u32 = 2;
pub const SPI_MEM_PES_END_INT_ST_V: u32 = 1;
pub const SPI_MEM_PES_END_INT_ST_S: u32 = 1;
pub const SPI_MEM_PER_END_INT_ST_V: u32 = 1;
pub const SPI_MEM_PER_END_INT_ST_S: u32 = 0;
pub const SPI_MEM_DATE: u32 = 8388607;
pub const SPI_MEM_DATE_V: u32 = 8388607;
pub const SPI_MEM_DATE_S: u32 = 5;
pub const SPI_MEM_SPICLK_PAD_DRV_CTL_EN_V: u32 = 1;
pub const SPI_MEM_SPICLK_PAD_DRV_CTL_EN_S: u32 = 4;
pub const SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV: u32 = 3;
pub const SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V: u32 = 3;
pub const SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S: u32 = 2;
pub const SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV: u32 = 3;
pub const SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V: u32 = 3;
pub const SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S: u32 = 0;
pub const SPI_MAX_DMA_LEN: u32 = 4092;
pub const SPICOMMON_BUSFLAG_SLAVE: u32 = 0;
pub const SPICOMMON_BUSFLAG_MASTER: u32 = 1;
pub const SPICOMMON_BUSFLAG_IOMUX_PINS: u32 = 2;
pub const SPICOMMON_BUSFLAG_GPIO_PINS: u32 = 4;
pub const SPICOMMON_BUSFLAG_SCLK: u32 = 8;
pub const SPICOMMON_BUSFLAG_MISO: u32 = 16;
pub const SPICOMMON_BUSFLAG_MOSI: u32 = 32;
pub const SPICOMMON_BUSFLAG_DUAL: u32 = 64;
pub const SPICOMMON_BUSFLAG_WPHD: u32 = 128;
pub const SPICOMMON_BUSFLAG_QUAD: u32 = 192;
pub const SPICOMMON_BUSFLAG_IO4_IO7: u32 = 256;
pub const SPICOMMON_BUSFLAG_OCTAL: u32 = 448;
pub const SPICOMMON_BUSFLAG_NATIVE_PINS: u32 = 2;
pub const SPI_MASTER_FREQ_8M: u32 = 8000000;
pub const SPI_MASTER_FREQ_9M: u32 = 8888888;
pub const SPI_MASTER_FREQ_10M: u32 = 10000000;
pub const SPI_MASTER_FREQ_11M: u32 = 11428571;
pub const SPI_MASTER_FREQ_13M: u32 = 13333333;
pub const SPI_MASTER_FREQ_16M: u32 = 16000000;
pub const SPI_MASTER_FREQ_20M: u32 = 20000000;
pub const SPI_MASTER_FREQ_26M: u32 = 26666666;
pub const SPI_MASTER_FREQ_40M: u32 = 40000000;
pub const SPI_MASTER_FREQ_80M: u32 = 80000000;
pub const SPI_DEVICE_TXBIT_LSBFIRST: u32 = 1;
pub const SPI_DEVICE_RXBIT_LSBFIRST: u32 = 2;
pub const SPI_DEVICE_BIT_LSBFIRST: u32 = 3;
pub const SPI_DEVICE_3WIRE: u32 = 4;
pub const SPI_DEVICE_POSITIVE_CS: u32 = 8;
pub const SPI_DEVICE_HALFDUPLEX: u32 = 16;
pub const SPI_DEVICE_CLK_AS_CS: u32 = 32;
pub const SPI_DEVICE_NO_DUMMY: u32 = 64;
pub const SPI_DEVICE_DDRCLK: u32 = 128;
pub const SPI_TRANS_MODE_DIO: u32 = 1;
pub const SPI_TRANS_MODE_QIO: u32 = 2;
pub const SPI_TRANS_USE_RXDATA: u32 = 4;
pub const SPI_TRANS_USE_TXDATA: u32 = 8;
pub const SPI_TRANS_MODE_DIOQIO_ADDR: u32 = 16;
pub const SPI_TRANS_VARIABLE_CMD: u32 = 32;
pub const SPI_TRANS_VARIABLE_ADDR: u32 = 64;
pub const SPI_TRANS_VARIABLE_DUMMY: u32 = 128;
pub const SPI_TRANS_CS_KEEP_ACTIVE: u32 = 256;
pub const SPI_TRANS_MULTILINE_CMD: u32 = 512;
pub const SPI_TRANS_MODE_OCT: u32 = 1024;
pub const SPI_TRANS_MULTILINE_ADDR: u32 = 16;
pub const FF_DEFINED: u32 = 86604;
pub const FFCONF_DEF: u32 = 86604;
pub const FF_FS_READONLY: u32 = 0;
pub const FF_FS_MINIMIZE: u32 = 0;
pub const FF_USE_STRFUNC: u32 = 0;
pub const FF_USE_FIND: u32 = 0;
pub const FF_USE_MKFS: u32 = 1;
pub const FF_USE_EXPAND: u32 = 0;
pub const FF_USE_CHMOD: u32 = 1;
pub const FF_USE_LABEL: u32 = 0;
pub const FF_USE_FORWARD: u32 = 0;
pub const FF_CODE_PAGE: u32 = 437;
pub const FF_USE_LFN: u32 = 0;
pub const FF_LFN_UNICODE: u32 = 0;
pub const FF_LFN_BUF: u32 = 255;
pub const FF_SFN_BUF: u32 = 12;
pub const FF_STRF_ENCODE: u32 = 3;
pub const FF_FS_RPATH: u32 = 0;
pub const FF_VOLUMES: u32 = 2;
pub const FF_STR_VOLUME_ID: u32 = 0;
pub const FF_MULTI_PARTITION: u32 = 1;
pub const FF_SS_SDCARD: u32 = 512;
pub const FF_SS_WL: u32 = 4096;
pub const FF_USE_TRIM: u32 = 0;
pub const FF_FS_NOFSINFO: u32 = 0;
pub const FF_FS_EXFAT: u32 = 0;
pub const FF_FS_NORTC: u32 = 0;
pub const FF_NORTC_MON: u32 = 1;
pub const FF_NORTC_MDAY: u32 = 1;
pub const FF_NORTC_YEAR: u32 = 2018;
pub const FF_FS_LOCK: u32 = 0;
pub const FF_FS_REENTRANT: u32 = 1;
pub const NBBY: u32 = 8;
pub const HZ: u32 = 60;
pub const NOFILE: u32 = 60;
pub const PATHSIZE: u32 = 1024;
pub const MAXPATHLEN: u32 = 1024;
pub const FF_INTDEF: u32 = 2;
pub const FA_READ: u32 = 1;
pub const FA_WRITE: u32 = 2;
pub const FA_OPEN_EXISTING: u32 = 0;
pub const FA_CREATE_NEW: u32 = 4;
pub const FA_CREATE_ALWAYS: u32 = 8;
pub const FA_OPEN_ALWAYS: u32 = 16;
pub const FA_OPEN_APPEND: u32 = 48;
pub const FM_FAT: u32 = 1;
pub const FM_FAT32: u32 = 2;
pub const FM_EXFAT: u32 = 4;
pub const FM_ANY: u32 = 7;
pub const FM_SFD: u32 = 8;
pub const FS_FAT12: u32 = 1;
pub const FS_FAT16: u32 = 2;
pub const FS_FAT32: u32 = 3;
pub const FS_EXFAT: u32 = 4;
pub const AM_RDO: u32 = 1;
pub const AM_HID: u32 = 2;
pub const AM_SYS: u32 = 4;
pub const AM_DIR: u32 = 16;
pub const AM_ARC: u32 = 32;
pub const WL_INVALID_HANDLE: i32 = -1;
pub const FF_DRV_NOT_USED: u32 = 255;
pub const STA_NOINIT: u32 = 1;
pub const STA_NODISK: u32 = 2;
pub const STA_PROTECT: u32 = 4;
pub const CTRL_SYNC: u32 = 0;
pub const GET_SECTOR_COUNT: u32 = 1;
pub const GET_SECTOR_SIZE: u32 = 2;
pub const GET_BLOCK_SIZE: u32 = 3;
pub const CTRL_TRIM: u32 = 4;
pub const CTRL_POWER: u32 = 5;
pub const CTRL_LOCK: u32 = 6;
pub const CTRL_EJECT: u32 = 7;
pub const CTRL_FORMAT: u32 = 8;
pub const MMC_GET_TYPE: u32 = 10;
pub const MMC_GET_CSD: u32 = 11;
pub const MMC_GET_CID: u32 = 12;
pub const MMC_GET_OCR: u32 = 13;
pub const MMC_GET_SDSTAT: u32 = 14;
pub const ISDIO_READ: u32 = 55;
pub const ISDIO_WRITE: u32 = 56;
pub const ISDIO_MRITE: u32 = 57;
pub const ATA_GET_REV: u32 = 20;
pub const ATA_GET_MODEL: u32 = 21;
pub const ATA_GET_SN: u32 = 22;
pub const MMC_GO_IDLE_STATE: u32 = 0;
pub const MMC_SEND_OP_COND: u32 = 1;
pub const MMC_ALL_SEND_CID: u32 = 2;
pub const MMC_SET_RELATIVE_ADDR: u32 = 3;
pub const MMC_SWITCH: u32 = 6;
pub const MMC_SELECT_CARD: u32 = 7;
pub const MMC_SEND_EXT_CSD: u32 = 8;
pub const MMC_SEND_CSD: u32 = 9;
pub const MMC_SEND_CID: u32 = 10;
pub const MMC_READ_DAT_UNTIL_STOP: u32 = 11;
pub const MMC_STOP_TRANSMISSION: u32 = 12;
pub const MMC_SEND_STATUS: u32 = 13;
pub const MMC_SET_BLOCKLEN: u32 = 16;
pub const MMC_READ_BLOCK_SINGLE: u32 = 17;
pub const MMC_READ_BLOCK_MULTIPLE: u32 = 18;
pub const MMC_WRITE_DAT_UNTIL_STOP: u32 = 20;
pub const MMC_SET_BLOCK_COUNT: u32 = 23;
pub const MMC_WRITE_BLOCK_SINGLE: u32 = 24;
pub const MMC_WRITE_BLOCK_MULTIPLE: u32 = 25;
pub const MMC_APP_CMD: u32 = 55;
pub const SD_SEND_RELATIVE_ADDR: u32 = 3;
pub const SD_SEND_SWITCH_FUNC: u32 = 6;
pub const SD_SEND_IF_COND: u32 = 8;
pub const SD_READ_OCR: u32 = 58;
pub const SD_CRC_ON_OFF: u32 = 59;
pub const SD_APP_SET_BUS_WIDTH: u32 = 6;
pub const SD_APP_SD_STATUS: u32 = 13;
pub const SD_APP_OP_COND: u32 = 41;
pub const SD_APP_SEND_SCR: u32 = 51;
pub const SD_IO_SEND_OP_COND: u32 = 5;
pub const SD_IO_RW_DIRECT: u32 = 52;
pub const SD_IO_RW_EXTENDED: u32 = 53;
pub const MMC_OCR_MEM_READY: u32 = 2147483648;
pub const MMC_OCR_ACCESS_MODE_MASK: u32 = 1610612736;
pub const MMC_OCR_SECTOR_MODE: u32 = 1073741824;
pub const MMC_OCR_BYTE_MODE: u32 = 536870912;
pub const MMC_OCR_3_5V_3_6V: u32 = 8388608;
pub const MMC_OCR_3_4V_3_5V: u32 = 4194304;
pub const MMC_OCR_3_3V_3_4V: u32 = 2097152;
pub const MMC_OCR_3_2V_3_3V: u32 = 1048576;
pub const MMC_OCR_3_1V_3_2V: u32 = 524288;
pub const MMC_OCR_3_0V_3_1V: u32 = 262144;
pub const MMC_OCR_2_9V_3_0V: u32 = 131072;
pub const MMC_OCR_2_8V_2_9V: u32 = 65536;
pub const MMC_OCR_2_7V_2_8V: u32 = 32768;
pub const MMC_OCR_2_6V_2_7V: u32 = 16384;
pub const MMC_OCR_2_5V_2_6V: u32 = 8192;
pub const MMC_OCR_2_4V_2_5V: u32 = 4096;
pub const MMC_OCR_2_3V_2_4V: u32 = 2048;
pub const MMC_OCR_2_2V_2_3V: u32 = 1024;
pub const MMC_OCR_2_1V_2_2V: u32 = 512;
pub const MMC_OCR_2_0V_2_1V: u32 = 256;
pub const MMC_OCR_1_65V_1_95V: u32 = 128;
pub const SD_OCR_SDHC_CAP: u32 = 1073741824;
pub const SD_OCR_VOL_MASK: u32 = 16744448;
pub const MMC_R1_READY_FOR_DATA: u32 = 256;
pub const MMC_R1_APP_CMD: u32 = 32;
pub const MMC_R1_SWITCH_ERROR: u32 = 128;
pub const SD_SPI_R1_IDLE_STATE: u32 = 1;
pub const SD_SPI_R1_ERASE_RST: u32 = 2;
pub const SD_SPI_R1_ILLEGAL_CMD: u32 = 4;
pub const SD_SPI_R1_CMD_CRC_ERR: u32 = 8;
pub const SD_SPI_R1_ERASE_SEQ_ERR: u32 = 16;
pub const SD_SPI_R1_ADDR_ERR: u32 = 32;
pub const SD_SPI_R1_PARAM_ERR: u32 = 64;
pub const SD_SPI_R1_NO_RESPONSE: u32 = 128;
pub const SDIO_R1_FUNC_NUM_ERR: u32 = 16;
pub const SD_SPI_DATA_ACCEPTED: u32 = 2;
pub const SD_SPI_DATA_CRC_ERROR: u32 = 5;
pub const SD_SPI_DATA_WR_ERROR: u32 = 6;
pub const SD_ARG_BUS_WIDTH_1: u32 = 0;
pub const SD_ARG_BUS_WIDTH_4: u32 = 2;
pub const EXT_CSD_BUS_WIDTH: u32 = 183;
pub const EXT_CSD_HS_TIMING: u32 = 185;
pub const EXT_CSD_REV: u32 = 192;
pub const EXT_CSD_STRUCTURE: u32 = 194;
pub const EXT_CSD_CARD_TYPE: u32 = 196;
pub const EXT_CSD_SEC_COUNT: u32 = 212;
pub const EXT_CSD_PWR_CL_26_360: u32 = 203;
pub const EXT_CSD_PWR_CL_52_360: u32 = 202;
pub const EXT_CSD_PWR_CL_26_195: u32 = 201;
pub const EXT_CSD_PWR_CL_52_195: u32 = 200;
pub const EXT_CSD_POWER_CLASS: u32 = 187;
pub const EXT_CSD_CMD_SET: u32 = 191;
pub const EXT_CSD_S_CMD_SET: u32 = 504;
pub const EXT_CSD_CMD_SET_NORMAL: u32 = 1;
pub const EXT_CSD_CMD_SET_SECURE: u32 = 2;
pub const EXT_CSD_CMD_SET_CPSECURE: u32 = 4;
pub const EXT_CSD_HS_TIMING_BC: u32 = 0;
pub const EXT_CSD_HS_TIMING_HS: u32 = 1;
pub const EXT_CSD_HS_TIMING_HS200: u32 = 2;
pub const EXT_CSD_HS_TIMING_HS400: u32 = 3;
pub const EXT_CSD_BUS_WIDTH_1: u32 = 0;
pub const EXT_CSD_BUS_WIDTH_4: u32 = 1;
pub const EXT_CSD_BUS_WIDTH_8: u32 = 2;
pub const EXT_CSD_BUS_WIDTH_4_DDR: u32 = 5;
pub const EXT_CSD_BUS_WIDTH_8_DDR: u32 = 6;
pub const EXT_CSD_CARD_TYPE_F_26M: u32 = 1;
pub const EXT_CSD_CARD_TYPE_F_52M: u32 = 2;
pub const EXT_CSD_CARD_TYPE_F_52M_1_8V: u32 = 4;
pub const EXT_CSD_CARD_TYPE_F_52M_1_2V: u32 = 8;
pub const EXT_CSD_CARD_TYPE_26M: u32 = 1;
pub const EXT_CSD_CARD_TYPE_52M: u32 = 3;
pub const EXT_CSD_CARD_TYPE_52M_V18: u32 = 7;
pub const EXT_CSD_CARD_TYPE_52M_V12: u32 = 11;
pub const EXT_CSD_CARD_TYPE_52M_V12_18: u32 = 15;
pub const EXT_CSD_MMC_SIZE: u32 = 512;
pub const MMC_SWITCH_MODE_CMD_SET: u32 = 0;
pub const MMC_SWITCH_MODE_SET_BITS: u32 = 1;
pub const MMC_SWITCH_MODE_CLEAR_BITS: u32 = 2;
pub const MMC_SWITCH_MODE_WRITE_BYTE: u32 = 3;
pub const MMC_CSD_CSDVER_1_0: u32 = 1;
pub const MMC_CSD_CSDVER_2_0: u32 = 2;
pub const MMC_CSD_CSDVER_EXT_CSD: u32 = 3;
pub const MMC_CSD_MMCVER_1_0: u32 = 0;
pub const MMC_CSD_MMCVER_1_4: u32 = 1;
pub const MMC_CSD_MMCVER_2_0: u32 = 2;
pub const MMC_CSD_MMCVER_3_1: u32 = 3;
pub const MMC_CSD_MMCVER_4_0: u32 = 4;
pub const SD_CSD_CSDVER_1_0: u32 = 0;
pub const SD_CSD_CSDVER_2_0: u32 = 1;
pub const SD_CSD_TAAC_1_5_MSEC: u32 = 38;
pub const SD_CSD_SPEED_25_MHZ: u32 = 50;
pub const SD_CSD_SPEED_50_MHZ: u32 = 90;
pub const SD_CSD_CCC_BASIC: u32 = 1;
pub const SD_CSD_CCC_BR: u32 = 4;
pub const SD_CSD_CCC_BW: u32 = 16;
pub const SD_CSD_CCC_ERASE: u32 = 32;
pub const SD_CSD_CCC_WP: u32 = 64;
pub const SD_CSD_CCC_LC: u32 = 128;
pub const SD_CSD_CCC_AS: u32 = 256;
pub const SD_CSD_CCC_IOM: u32 = 512;
pub const SD_CSD_CCC_SWITCH: u32 = 1024;
pub const SD_CSD_V2_BL_LEN: u32 = 9;
pub const SD_CSD_VDD_RW_CURR_100mA: u32 = 7;
pub const SD_CSD_VDD_RW_CURR_80mA: u32 = 6;
pub const SD_CSD_RW_BL_LEN_2G: u32 = 10;
pub const SD_CSD_RW_BL_LEN_1G: u32 = 9;
pub const SCR_STRUCTURE_VER_1_0: u32 = 0;
pub const SCR_SD_SPEC_VER_1_0: u32 = 0;
pub const SCR_SD_SPEC_VER_1_10: u32 = 1;
pub const SCR_SD_SPEC_VER_2: u32 = 2;
pub const SCR_SD_SECURITY_NONE: u32 = 0;
pub const SCR_SD_SECURITY_1_0: u32 = 1;
pub const SCR_SD_SECURITY_1_0_2: u32 = 2;
pub const SCR_SD_BUS_WIDTHS_1BIT: u32 = 1;
pub const SCR_SD_BUS_WIDTHS_4BIT: u32 = 4;
pub const SD_SFUNC_GROUP_MAX: u32 = 6;
pub const SD_SFUNC_FUNC_MAX: u32 = 15;
pub const SD_ACCESS_MODE: u32 = 1;
pub const SD_ACCESS_MODE_SDR12: u32 = 0;
pub const SD_ACCESS_MODE_SDR25: u32 = 1;
pub const SD_ACCESS_MODE_SDR50: u32 = 2;
pub const SD_ACCESS_MODE_SDR104: u32 = 3;
pub const SD_ACCESS_MODE_DDR50: u32 = 4;
pub const SD_IO_OCR_MEM_READY: u32 = 2147483648;
pub const SD_IO_OCR_MEM_PRESENT: u32 = 134217728;
pub const SD_IO_OCR_MASK: u32 = 16777200;
pub const SD_ARG_CMD52_READ: u32 = 0;
pub const SD_ARG_CMD52_WRITE: u32 = 2147483648;
pub const SD_ARG_CMD52_FUNC_SHIFT: u32 = 28;
pub const SD_ARG_CMD52_FUNC_MASK: u32 = 7;
pub const SD_ARG_CMD52_EXCHANGE: u32 = 134217728;
pub const SD_ARG_CMD52_REG_SHIFT: u32 = 9;
pub const SD_ARG_CMD52_REG_MASK: u32 = 131071;
pub const SD_ARG_CMD52_DATA_SHIFT: u32 = 0;
pub const SD_ARG_CMD52_DATA_MASK: u32 = 255;
pub const SD_ARG_CMD53_READ: u32 = 0;
pub const SD_ARG_CMD53_WRITE: u32 = 2147483648;
pub const SD_ARG_CMD53_FUNC_SHIFT: u32 = 28;
pub const SD_ARG_CMD53_FUNC_MASK: u32 = 7;
pub const SD_ARG_CMD53_BLOCK_MODE: u32 = 134217728;
pub const SD_ARG_CMD53_INCREMENT: u32 = 67108864;
pub const SD_ARG_CMD53_REG_SHIFT: u32 = 9;
pub const SD_ARG_CMD53_REG_MASK: u32 = 131071;
pub const SD_ARG_CMD53_LENGTH_SHIFT: u32 = 0;
pub const SD_ARG_CMD53_LENGTH_MASK: u32 = 511;
pub const SD_ARG_CMD53_LENGTH_MAX: u32 = 512;
pub const SD_IO_CCCR_START: u32 = 0;
pub const SD_IO_CCCR_SIZE: u32 = 256;
pub const SD_IO_CCCR_FN_ENABLE: u32 = 2;
pub const SD_IO_CCCR_FN_READY: u32 = 3;
pub const SD_IO_CCCR_INT_ENABLE: u32 = 4;
pub const SD_IO_CCCR_INT_PENDING: u32 = 5;
pub const SD_IO_CCCR_CTL: u32 = 6;
pub const CCCR_CTL_RES: u32 = 8;
pub const SD_IO_CCCR_BUS_WIDTH: u32 = 7;
pub const CCCR_BUS_WIDTH_1: u32 = 0;
pub const CCCR_BUS_WIDTH_4: u32 = 2;
pub const CCCR_BUS_WIDTH_8: u32 = 3;
pub const CCCR_BUS_WIDTH_ECSI: u32 = 32;
pub const SD_IO_CCCR_CARD_CAP: u32 = 8;
pub const SD_IO_CCCR_CISPTR: u32 = 9;
pub const SD_IO_CCCR_BLKSIZEL: u32 = 16;
pub const SD_IO_CCCR_BLKSIZEH: u32 = 17;
pub const SD_IO_CCCR_HIGHSPEED: u32 = 19;
pub const SD_IO_FBR_START: u32 = 256;
pub const SD_IO_FBR_SIZE: u32 = 1792;
pub const SD_IO_CIS_START: u32 = 4096;
pub const SD_IO_CIS_SIZE: u32 = 94208;
pub const CISTPL_CODE_NULL: u32 = 0;
pub const CISTPL_CODE_DEVICE: u32 = 1;
pub const CISTPL_CODE_CHKSUM: u32 = 16;
pub const CISTPL_CODE_VERS1: u32 = 21;
pub const CISTPL_CODE_ALTSTR: u32 = 22;
pub const CISTPL_CODE_CONFIG: u32 = 26;
pub const CISTPL_CODE_CFTABLE_ENTRY: u32 = 27;
pub const CISTPL_CODE_MANFID: u32 = 32;
pub const CISTPL_CODE_FUNCID: u32 = 33;
pub const TPLFID_FUNCTION_SDIO: u32 = 12;
pub const CISTPL_CODE_FUNCE: u32 = 34;
pub const CISTPL_CODE_VENDER_BEGIN: u32 = 128;
pub const CISTPL_CODE_VENDER_END: u32 = 143;
pub const CISTPL_CODE_SDIO_STD: u32 = 145;
pub const CISTPL_CODE_SDIO_EXT: u32 = 146;
pub const CISTPL_CODE_END: u32 = 255;
pub const SDMMC_TIMING_LEGACY: u32 = 0;
pub const SDMMC_TIMING_HIGHSPEED: u32 = 1;
pub const SDMMC_TIMING_MMC_DDR52: u32 = 2;
pub const SNTP_GET_SERVERS_FROM_DHCP: u32 = 0;
pub const SNTP_GET_SERVERS_FROM_DHCPV6: u32 = 0;
pub const SNTP_CHECK_RESPONSE: u32 = 0;
pub const SNTP_COMP_ROUNDTRIP: u32 = 0;
pub const SNTP_STARTUP_DELAY: u32 = 1;
pub const SNTP_RECV_TIMEOUT: u32 = 15000;
pub const SNTP_RETRY_TIMEOUT: u32 = 15000;
pub const SNTP_RETRY_TIMEOUT_MAX: u32 = 150000;
pub const SNTP_RETRY_TIMEOUT_EXP: u32 = 1;
pub const SNTP_MONITOR_SERVER_REACHABILITY: u32 = 1;
pub const SNTP_OPMODE_POLL: u32 = 0;
pub const SNTP_OPMODE_LISTENONLY: u32 = 1;
pub const ESP_PING_COUNT_INFINITE: u32 = 0;
pub const MBEDTLS_SSL_IN_CONTENT_LEN: u32 = 16384;
pub const MBEDTLS_SSL_OUT_CONTENT_LEN: u32 = 4096;
pub const MBEDTLS_ERR_MPI_FILE_IO_ERROR: i32 = -2;
pub const MBEDTLS_ERR_MPI_BAD_INPUT_DATA: i32 = -4;
pub const MBEDTLS_ERR_MPI_INVALID_CHARACTER: i32 = -6;
pub const MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL: i32 = -8;
pub const MBEDTLS_ERR_MPI_NEGATIVE_VALUE: i32 = -10;
pub const MBEDTLS_ERR_MPI_DIVISION_BY_ZERO: i32 = -12;
pub const MBEDTLS_ERR_MPI_NOT_ACCEPTABLE: i32 = -14;
pub const MBEDTLS_ERR_MPI_ALLOC_FAILED: i32 = -16;
pub const MBEDTLS_MPI_MAX_LIMBS: u32 = 10000;
pub const MBEDTLS_MPI_WINDOW_SIZE: u32 = 6;
pub const MBEDTLS_MPI_MAX_SIZE: u32 = 1024;
pub const MBEDTLS_MPI_MAX_BITS: u32 = 8192;
pub const MBEDTLS_MPI_MAX_BITS_SCALE100: u32 = 819200;
pub const MBEDTLS_LN_2_DIV_LN_10_SCALE100: u32 = 332;
pub const MBEDTLS_MPI_RW_BUFFER_SIZE: u32 = 2484;
pub const MBEDTLS_ERR_ECP_BAD_INPUT_DATA: i32 = -20352;
pub const MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL: i32 = -20224;
pub const MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE: i32 = -20096;
pub const MBEDTLS_ERR_ECP_VERIFY_FAILED: i32 = -19968;
pub const MBEDTLS_ERR_ECP_ALLOC_FAILED: i32 = -19840;
pub const MBEDTLS_ERR_ECP_RANDOM_FAILED: i32 = -19712;
pub const MBEDTLS_ERR_ECP_INVALID_KEY: i32 = -19584;
pub const MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH: i32 = -19456;
pub const MBEDTLS_ERR_ECP_HW_ACCEL_FAILED: i32 = -19328;
pub const MBEDTLS_ERR_ECP_IN_PROGRESS: i32 = -19200;
pub const MBEDTLS_ECP_DP_MAX: u32 = 12;
pub const MBEDTLS_ECP_MAX_BITS_MIN: u32 = 521;
pub const MBEDTLS_ECP_MAX_BITS: u32 = 521;
pub const MBEDTLS_ECP_MAX_BYTES: u32 = 66;
pub const MBEDTLS_ECP_MAX_PT_LEN: u32 = 133;
pub const MBEDTLS_ECP_WINDOW_SIZE: u32 = 4;
pub const MBEDTLS_ECP_FIXED_POINT_OPTIM: u32 = 1;
pub const MBEDTLS_ECP_PF_UNCOMPRESSED: u32 = 0;
pub const MBEDTLS_ECP_PF_COMPRESSED: u32 = 1;
pub const MBEDTLS_ECP_TLS_NAMED_CURVE: u32 = 3;
pub const MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE: i32 = -20608;
pub const MBEDTLS_ERR_MD_BAD_INPUT_DATA: i32 = -20736;
pub const MBEDTLS_ERR_MD_ALLOC_FAILED: i32 = -20864;
pub const MBEDTLS_ERR_MD_FILE_IO_ERROR: i32 = -20992;
pub const MBEDTLS_ERR_MD_HW_ACCEL_FAILED: i32 = -21120;
pub const MBEDTLS_MD_MAX_SIZE: u32 = 64;
pub const MBEDTLS_MD_MAX_BLOCK_SIZE: u32 = 128;
pub const MBEDTLS_ERR_RSA_BAD_INPUT_DATA: i32 = -16512;
pub const MBEDTLS_ERR_RSA_INVALID_PADDING: i32 = -16640;
pub const MBEDTLS_ERR_RSA_KEY_GEN_FAILED: i32 = -16768;
pub const MBEDTLS_ERR_RSA_KEY_CHECK_FAILED: i32 = -16896;
pub const MBEDTLS_ERR_RSA_PUBLIC_FAILED: i32 = -17024;
pub const MBEDTLS_ERR_RSA_PRIVATE_FAILED: i32 = -17152;
pub const MBEDTLS_ERR_RSA_VERIFY_FAILED: i32 = -17280;
pub const MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE: i32 = -17408;
pub const MBEDTLS_ERR_RSA_RNG_FAILED: i32 = -17536;
pub const MBEDTLS_ERR_RSA_UNSUPPORTED_OPERATION: i32 = -17664;
pub const MBEDTLS_ERR_RSA_HW_ACCEL_FAILED: i32 = -17792;
pub const MBEDTLS_RSA_PUBLIC: u32 = 0;
pub const MBEDTLS_RSA_PRIVATE: u32 = 1;
pub const MBEDTLS_RSA_PKCS_V15: u32 = 0;
pub const MBEDTLS_RSA_PKCS_V21: u32 = 1;
pub const MBEDTLS_RSA_SIGN: u32 = 1;
pub const MBEDTLS_RSA_CRYPT: u32 = 2;
pub const MBEDTLS_RSA_SALT_LEN_ANY: i32 = -1;
pub const MBEDTLS_ERR_PK_ALLOC_FAILED: i32 = -16256;
pub const MBEDTLS_ERR_PK_TYPE_MISMATCH: i32 = -16128;
pub const MBEDTLS_ERR_PK_BAD_INPUT_DATA: i32 = -16000;
pub const MBEDTLS_ERR_PK_FILE_IO_ERROR: i32 = -15872;
pub const MBEDTLS_ERR_PK_KEY_INVALID_VERSION: i32 = -15744;
pub const MBEDTLS_ERR_PK_KEY_INVALID_FORMAT: i32 = -15616;
pub const MBEDTLS_ERR_PK_UNKNOWN_PK_ALG: i32 = -15488;
pub const MBEDTLS_ERR_PK_PASSWORD_REQUIRED: i32 = -15360;
pub const MBEDTLS_ERR_PK_PASSWORD_MISMATCH: i32 = -15232;
pub const MBEDTLS_ERR_PK_INVALID_PUBKEY: i32 = -15104;
pub const MBEDTLS_ERR_PK_INVALID_ALG: i32 = -14976;
pub const MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE: i32 = -14848;
pub const MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE: i32 = -14720;
pub const MBEDTLS_ERR_PK_SIG_LEN_MISMATCH: i32 = -14592;
pub const MBEDTLS_ERR_PK_HW_ACCEL_FAILED: i32 = -14464;
pub const MBEDTLS_PK_SIGNATURE_MAX_SIZE: u32 = 0;
pub const MBEDTLS_PK_DEBUG_MAX_ITEMS: u32 = 3;
pub const MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE: i32 = -24704;
pub const MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA: i32 = -24832;
pub const MBEDTLS_ERR_CIPHER_ALLOC_FAILED: i32 = -24960;
pub const MBEDTLS_ERR_CIPHER_INVALID_PADDING: i32 = -25088;
pub const MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED: i32 = -25216;
pub const MBEDTLS_ERR_CIPHER_AUTH_FAILED: i32 = -25344;
pub const MBEDTLS_ERR_CIPHER_INVALID_CONTEXT: i32 = -25472;
pub const MBEDTLS_ERR_CIPHER_HW_ACCEL_FAILED: i32 = -25600;
pub const MBEDTLS_CIPHER_VARIABLE_IV_LEN: u32 = 1;
pub const MBEDTLS_CIPHER_VARIABLE_KEY_LEN: u32 = 2;
pub const MBEDTLS_MAX_IV_LENGTH: u32 = 16;
pub const MBEDTLS_MAX_BLOCK_LENGTH: u32 = 16;
pub const MBEDTLS_MAX_KEY_LENGTH: u32 = 64;
pub const MBEDTLS_TLS_RSA_WITH_NULL_MD5: u32 = 1;
pub const MBEDTLS_TLS_RSA_WITH_NULL_SHA: u32 = 2;
pub const MBEDTLS_TLS_RSA_WITH_RC4_128_MD5: u32 = 4;
pub const MBEDTLS_TLS_RSA_WITH_RC4_128_SHA: u32 = 5;
pub const MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA: u32 = 9;
pub const MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA: u32 = 10;
pub const MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA: u32 = 21;
pub const MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA: u32 = 22;
pub const MBEDTLS_TLS_PSK_WITH_NULL_SHA: u32 = 44;
pub const MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA: u32 = 45;
pub const MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA: u32 = 46;
pub const MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA: u32 = 47;
pub const MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA: u32 = 51;
pub const MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA: u32 = 53;
pub const MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA: u32 = 57;
pub const MBEDTLS_TLS_RSA_WITH_NULL_SHA256: u32 = 59;
pub const MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256: u32 = 60;
pub const MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256: u32 = 61;
pub const MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA: u32 = 65;
pub const MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA: u32 = 69;
pub const MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256: u32 = 103;
pub const MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256: u32 = 107;
pub const MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA: u32 = 132;
pub const MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA: u32 = 136;
pub const MBEDTLS_TLS_PSK_WITH_RC4_128_SHA: u32 = 138;
pub const MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA: u32 = 139;
pub const MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA: u32 = 140;
pub const MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA: u32 = 141;
pub const MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA: u32 = 142;
pub const MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA: u32 = 143;
pub const MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA: u32 = 144;
pub const MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA: u32 = 145;
pub const MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA: u32 = 146;
pub const MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA: u32 = 147;
pub const MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA: u32 = 148;
pub const MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA: u32 = 149;
pub const MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256: u32 = 156;
pub const MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384: u32 = 157;
pub const MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256: u32 = 158;
pub const MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384: u32 = 159;
pub const MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256: u32 = 168;
pub const MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384: u32 = 169;
pub const MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256: u32 = 170;
pub const MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384: u32 = 171;
pub const MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256: u32 = 172;
pub const MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384: u32 = 173;
pub const MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256: u32 = 174;
pub const MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384: u32 = 175;
pub const MBEDTLS_TLS_PSK_WITH_NULL_SHA256: u32 = 176;
pub const MBEDTLS_TLS_PSK_WITH_NULL_SHA384: u32 = 177;
pub const MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256: u32 = 178;
pub const MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384: u32 = 179;
pub const MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256: u32 = 180;
pub const MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384: u32 = 181;
pub const MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256: u32 = 182;
pub const MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384: u32 = 183;
pub const MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256: u32 = 184;
pub const MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384: u32 = 185;
pub const MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256: u32 = 186;
pub const MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256: u32 = 190;
pub const MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256: u32 = 192;
pub const MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256: u32 = 196;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA: u32 = 49153;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA: u32 = 49154;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA: u32 = 49155;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA: u32 = 49156;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA: u32 = 49157;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA: u32 = 49158;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA: u32 = 49159;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA: u32 = 49160;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA: u32 = 49161;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA: u32 = 49162;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA: u32 = 49163;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA: u32 = 49164;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA: u32 = 49165;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA: u32 = 49166;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA: u32 = 49167;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA: u32 = 49168;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA: u32 = 49169;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA: u32 = 49170;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA: u32 = 49171;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA: u32 = 49172;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256: u32 = 49187;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384: u32 = 49188;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256: u32 = 49189;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384: u32 = 49190;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256: u32 = 49191;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384: u32 = 49192;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256: u32 = 49193;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384: u32 = 49194;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256: u32 = 49195;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384: u32 = 49196;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256: u32 = 49197;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384: u32 = 49198;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256: u32 = 49199;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384: u32 = 49200;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256: u32 = 49201;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384: u32 = 49202;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA: u32 = 49203;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA: u32 = 49204;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA: u32 = 49205;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA: u32 = 49206;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256: u32 = 49207;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384: u32 = 49208;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA: u32 = 49209;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256: u32 = 49210;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384: u32 = 49211;
pub const MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256: u32 = 49212;
pub const MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384: u32 = 49213;
pub const MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256: u32 = 49220;
pub const MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384: u32 = 49221;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256: u32 = 49224;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384: u32 = 49225;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256: u32 = 49226;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384: u32 = 49227;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256: u32 = 49228;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384: u32 = 49229;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256: u32 = 49230;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384: u32 = 49231;
pub const MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256: u32 = 49232;
pub const MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384: u32 = 49233;
pub const MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256: u32 = 49234;
pub const MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384: u32 = 49235;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256: u32 = 49244;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384: u32 = 49245;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256: u32 = 49246;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384: u32 = 49247;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256: u32 = 49248;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384: u32 = 49249;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256: u32 = 49250;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384: u32 = 49251;
pub const MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256: u32 = 49252;
pub const MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384: u32 = 49253;
pub const MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256: u32 = 49254;
pub const MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384: u32 = 49255;
pub const MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256: u32 = 49256;
pub const MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384: u32 = 49257;
pub const MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256: u32 = 49258;
pub const MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384: u32 = 49259;
pub const MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256: u32 = 49260;
pub const MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384: u32 = 49261;
pub const MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256: u32 = 49262;
pub const MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384: u32 = 49263;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256: u32 = 49264;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384: u32 = 49265;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256: u32 = 49266;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384: u32 = 49267;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256: u32 = 49268;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384: u32 = 49269;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256: u32 = 49270;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384: u32 = 49271;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256: u32 = 49272;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384: u32 = 49273;
pub const MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256: u32 = 49274;
pub const MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384: u32 = 49275;
pub const MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256: u32 = 49276;
pub const MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384: u32 = 49277;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256: u32 = 49286;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384: u32 = 49287;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256: u32 = 49288;
pub const MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384: u32 = 49289;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256: u32 = 49290;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384: u32 = 49291;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256: u32 = 49292;
pub const MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384: u32 = 49293;
pub const MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256: u32 = 49294;
pub const MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384: u32 = 49295;
pub const MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256: u32 = 49296;
pub const MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384: u32 = 49297;
pub const MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256: u32 = 49298;
pub const MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384: u32 = 49299;
pub const MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256: u32 = 49300;
pub const MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384: u32 = 49301;
pub const MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256: u32 = 49302;
pub const MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384: u32 = 49303;
pub const MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256: u32 = 49304;
pub const MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384: u32 = 49305;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256: u32 = 49306;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384: u32 = 49307;
pub const MBEDTLS_TLS_RSA_WITH_AES_128_CCM: u32 = 49308;
pub const MBEDTLS_TLS_RSA_WITH_AES_256_CCM: u32 = 49309;
pub const MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM: u32 = 49310;
pub const MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM: u32 = 49311;
pub const MBEDTLS_TLS_RSA_WITH_AES_128_CCM_8: u32 = 49312;
pub const MBEDTLS_TLS_RSA_WITH_AES_256_CCM_8: u32 = 49313;
pub const MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM_8: u32 = 49314;
pub const MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM_8: u32 = 49315;
pub const MBEDTLS_TLS_PSK_WITH_AES_128_CCM: u32 = 49316;
pub const MBEDTLS_TLS_PSK_WITH_AES_256_CCM: u32 = 49317;
pub const MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM: u32 = 49318;
pub const MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM: u32 = 49319;
pub const MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8: u32 = 49320;
pub const MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8: u32 = 49321;
pub const MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM_8: u32 = 49322;
pub const MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM_8: u32 = 49323;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM: u32 = 49324;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM: u32 = 49325;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8: u32 = 49326;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8: u32 = 49327;
pub const MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8: u32 = 49407;
pub const MBEDTLS_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256: u32 = 52392;
pub const MBEDTLS_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256: u32 = 52393;
pub const MBEDTLS_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256: u32 = 52394;
pub const MBEDTLS_TLS_PSK_WITH_CHACHA20_POLY1305_SHA256: u32 = 52395;
pub const MBEDTLS_TLS_ECDHE_PSK_WITH_CHACHA20_POLY1305_SHA256: u32 = 52396;
pub const MBEDTLS_TLS_DHE_PSK_WITH_CHACHA20_POLY1305_SHA256: u32 = 52397;
pub const MBEDTLS_TLS_RSA_PSK_WITH_CHACHA20_POLY1305_SHA256: u32 = 52398;
pub const MBEDTLS_CIPHERSUITE_WEAK: u32 = 1;
pub const MBEDTLS_CIPHERSUITE_SHORT_TAG: u32 = 2;
pub const MBEDTLS_CIPHERSUITE_NODTLS: u32 = 4;
pub const MBEDTLS_ERR_ASN1_OUT_OF_DATA: i32 = -96;
pub const MBEDTLS_ERR_ASN1_UNEXPECTED_TAG: i32 = -98;
pub const MBEDTLS_ERR_ASN1_INVALID_LENGTH: i32 = -100;
pub const MBEDTLS_ERR_ASN1_LENGTH_MISMATCH: i32 = -102;
pub const MBEDTLS_ERR_ASN1_INVALID_DATA: i32 = -104;
pub const MBEDTLS_ERR_ASN1_ALLOC_FAILED: i32 = -106;
pub const MBEDTLS_ERR_ASN1_BUF_TOO_SMALL: i32 = -108;
pub const MBEDTLS_ASN1_BOOLEAN: u32 = 1;
pub const MBEDTLS_ASN1_INTEGER: u32 = 2;
pub const MBEDTLS_ASN1_BIT_STRING: u32 = 3;
pub const MBEDTLS_ASN1_OCTET_STRING: u32 = 4;
pub const MBEDTLS_ASN1_NULL: u32 = 5;
pub const MBEDTLS_ASN1_OID: u32 = 6;
pub const MBEDTLS_ASN1_ENUMERATED: u32 = 10;
pub const MBEDTLS_ASN1_UTF8_STRING: u32 = 12;
pub const MBEDTLS_ASN1_SEQUENCE: u32 = 16;
pub const MBEDTLS_ASN1_SET: u32 = 17;
pub const MBEDTLS_ASN1_PRINTABLE_STRING: u32 = 19;
pub const MBEDTLS_ASN1_T61_STRING: u32 = 20;
pub const MBEDTLS_ASN1_IA5_STRING: u32 = 22;
pub const MBEDTLS_ASN1_UTC_TIME: u32 = 23;
pub const MBEDTLS_ASN1_GENERALIZED_TIME: u32 = 24;
pub const MBEDTLS_ASN1_UNIVERSAL_STRING: u32 = 28;
pub const MBEDTLS_ASN1_BMP_STRING: u32 = 30;
pub const MBEDTLS_ASN1_PRIMITIVE: u32 = 0;
pub const MBEDTLS_ASN1_CONSTRUCTED: u32 = 32;
pub const MBEDTLS_ASN1_CONTEXT_SPECIFIC: u32 = 128;
pub const MBEDTLS_ASN1_TAG_CLASS_MASK: u32 = 192;
pub const MBEDTLS_ASN1_TAG_PC_MASK: u32 = 32;
pub const MBEDTLS_ASN1_TAG_VALUE_MASK: u32 = 31;
pub const MBEDTLS_X509_MAX_INTERMEDIATE_CA: u32 = 8;
pub const MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE: i32 = -8320;
pub const MBEDTLS_ERR_X509_UNKNOWN_OID: i32 = -8448;
pub const MBEDTLS_ERR_X509_INVALID_FORMAT: i32 = -8576;
pub const MBEDTLS_ERR_X509_INVALID_VERSION: i32 = -8704;
pub const MBEDTLS_ERR_X509_INVALID_SERIAL: i32 = -8832;
pub const MBEDTLS_ERR_X509_INVALID_ALG: i32 = -8960;
pub const MBEDTLS_ERR_X509_INVALID_NAME: i32 = -9088;
pub const MBEDTLS_ERR_X509_INVALID_DATE: i32 = -9216;
pub const MBEDTLS_ERR_X509_INVALID_SIGNATURE: i32 = -9344;
pub const MBEDTLS_ERR_X509_INVALID_EXTENSIONS: i32 = -9472;
pub const MBEDTLS_ERR_X509_UNKNOWN_VERSION: i32 = -9600;
pub const MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG: i32 = -9728;
pub const MBEDTLS_ERR_X509_SIG_MISMATCH: i32 = -9856;
pub const MBEDTLS_ERR_X509_CERT_VERIFY_FAILED: i32 = -9984;
pub const MBEDTLS_ERR_X509_CERT_UNKNOWN_FORMAT: i32 = -10112;
pub const MBEDTLS_ERR_X509_BAD_INPUT_DATA: i32 = -10240;
pub const MBEDTLS_ERR_X509_ALLOC_FAILED: i32 = -10368;
pub const MBEDTLS_ERR_X509_FILE_IO_ERROR: i32 = -10496;
pub const MBEDTLS_ERR_X509_BUFFER_TOO_SMALL: i32 = -10624;
pub const MBEDTLS_ERR_X509_FATAL_ERROR: i32 = -12288;
pub const MBEDTLS_X509_BADCERT_EXPIRED: u32 = 1;
pub const MBEDTLS_X509_BADCERT_REVOKED: u32 = 2;
pub const MBEDTLS_X509_BADCERT_CN_MISMATCH: u32 = 4;
pub const MBEDTLS_X509_BADCERT_NOT_TRUSTED: u32 = 8;
pub const MBEDTLS_X509_BADCRL_NOT_TRUSTED: u32 = 16;
pub const MBEDTLS_X509_BADCRL_EXPIRED: u32 = 32;
pub const MBEDTLS_X509_BADCERT_MISSING: u32 = 64;
pub const MBEDTLS_X509_BADCERT_SKIP_VERIFY: u32 = 128;
pub const MBEDTLS_X509_BADCERT_OTHER: u32 = 256;
pub const MBEDTLS_X509_BADCERT_FUTURE: u32 = 512;
pub const MBEDTLS_X509_BADCRL_FUTURE: u32 = 1024;
pub const MBEDTLS_X509_BADCERT_KEY_USAGE: u32 = 2048;
pub const MBEDTLS_X509_BADCERT_EXT_KEY_USAGE: u32 = 4096;
pub const MBEDTLS_X509_BADCERT_NS_CERT_TYPE: u32 = 8192;
pub const MBEDTLS_X509_BADCERT_BAD_MD: u32 = 16384;
pub const MBEDTLS_X509_BADCERT_BAD_PK: u32 = 32768;
pub const MBEDTLS_X509_BADCERT_BAD_KEY: u32 = 65536;
pub const MBEDTLS_X509_BADCRL_BAD_MD: u32 = 131072;
pub const MBEDTLS_X509_BADCRL_BAD_PK: u32 = 262144;
pub const MBEDTLS_X509_BADCRL_BAD_KEY: u32 = 524288;
pub const MBEDTLS_X509_SAN_OTHER_NAME: u32 = 0;
pub const MBEDTLS_X509_SAN_RFC822_NAME: u32 = 1;
pub const MBEDTLS_X509_SAN_DNS_NAME: u32 = 2;
pub const MBEDTLS_X509_SAN_X400_ADDRESS_NAME: u32 = 3;
pub const MBEDTLS_X509_SAN_DIRECTORY_NAME: u32 = 4;
pub const MBEDTLS_X509_SAN_EDI_PARTY_NAME: u32 = 5;
pub const MBEDTLS_X509_SAN_UNIFORM_RESOURCE_IDENTIFIER: u32 = 6;
pub const MBEDTLS_X509_SAN_IP_ADDRESS: u32 = 7;
pub const MBEDTLS_X509_SAN_REGISTERED_ID: u32 = 8;
pub const MBEDTLS_X509_KU_DIGITAL_SIGNATURE: u32 = 128;
pub const MBEDTLS_X509_KU_NON_REPUDIATION: u32 = 64;
pub const MBEDTLS_X509_KU_KEY_ENCIPHERMENT: u32 = 32;
pub const MBEDTLS_X509_KU_DATA_ENCIPHERMENT: u32 = 16;
pub const MBEDTLS_X509_KU_KEY_AGREEMENT: u32 = 8;
pub const MBEDTLS_X509_KU_KEY_CERT_SIGN: u32 = 4;
pub const MBEDTLS_X509_KU_CRL_SIGN: u32 = 2;
pub const MBEDTLS_X509_KU_ENCIPHER_ONLY: u32 = 1;
pub const MBEDTLS_X509_KU_DECIPHER_ONLY: u32 = 32768;
pub const MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT: u32 = 128;
pub const MBEDTLS_X509_NS_CERT_TYPE_SSL_SERVER: u32 = 64;
pub const MBEDTLS_X509_NS_CERT_TYPE_EMAIL: u32 = 32;
pub const MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING: u32 = 16;
pub const MBEDTLS_X509_NS_CERT_TYPE_RESERVED: u32 = 8;
pub const MBEDTLS_X509_NS_CERT_TYPE_SSL_CA: u32 = 4;
pub const MBEDTLS_X509_NS_CERT_TYPE_EMAIL_CA: u32 = 2;
pub const MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING_CA: u32 = 1;
pub const MBEDTLS_X509_FORMAT_DER: u32 = 1;
pub const MBEDTLS_X509_FORMAT_PEM: u32 = 2;
pub const MBEDTLS_X509_MAX_DN_NAME_SIZE: u32 = 256;
pub const MBEDTLS_X509_CRT_VERSION_1: u32 = 0;
pub const MBEDTLS_X509_CRT_VERSION_2: u32 = 1;
pub const MBEDTLS_X509_CRT_VERSION_3: u32 = 2;
pub const MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN: u32 = 32;
pub const MBEDTLS_X509_RFC5280_UTC_TIME_LEN: u32 = 15;
pub const MBEDTLS_X509_MAX_FILE_PATH_LEN: u32 = 512;
pub const MBEDTLS_X509_MAX_VERIFY_CHAIN_SIZE: u32 = 10;
pub const MBEDTLS_ERR_DHM_BAD_INPUT_DATA: i32 = -12416;
pub const MBEDTLS_ERR_DHM_READ_PARAMS_FAILED: i32 = -12544;
pub const MBEDTLS_ERR_DHM_MAKE_PARAMS_FAILED: i32 = -12672;
pub const MBEDTLS_ERR_DHM_READ_PUBLIC_FAILED: i32 = -12800;
pub const MBEDTLS_ERR_DHM_MAKE_PUBLIC_FAILED: i32 = -12928;
pub const MBEDTLS_ERR_DHM_CALC_SECRET_FAILED: i32 = -13056;
pub const MBEDTLS_ERR_DHM_INVALID_FORMAT: i32 = -13184;
pub const MBEDTLS_ERR_DHM_ALLOC_FAILED: i32 = -13312;
pub const MBEDTLS_ERR_DHM_FILE_IO_ERROR: i32 = -13440;
pub const MBEDTLS_ERR_DHM_HW_ACCEL_FAILED: i32 = -13568;
pub const MBEDTLS_ERR_DHM_SET_GROUP_FAILED: i32 = -13696;
pub const MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE: i32 = -28800;
pub const MBEDTLS_ERR_SSL_BAD_INPUT_DATA: i32 = -28928;
pub const MBEDTLS_ERR_SSL_INVALID_MAC: i32 = -29056;
pub const MBEDTLS_ERR_SSL_INVALID_RECORD: i32 = -29184;
pub const MBEDTLS_ERR_SSL_CONN_EOF: i32 = -29312;
pub const MBEDTLS_ERR_SSL_UNKNOWN_CIPHER: i32 = -29440;
pub const MBEDTLS_ERR_SSL_NO_CIPHER_CHOSEN: i32 = -29568;
pub const MBEDTLS_ERR_SSL_NO_RNG: i32 = -29696;
pub const MBEDTLS_ERR_SSL_NO_CLIENT_CERTIFICATE: i32 = -29824;
pub const MBEDTLS_ERR_SSL_CERTIFICATE_TOO_LARGE: i32 = -29952;
pub const MBEDTLS_ERR_SSL_CERTIFICATE_REQUIRED: i32 = -30080;
pub const MBEDTLS_ERR_SSL_PRIVATE_KEY_REQUIRED: i32 = -30208;
pub const MBEDTLS_ERR_SSL_CA_CHAIN_REQUIRED: i32 = -30336;
pub const MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE: i32 = -30464;
pub const MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE: i32 = -30592;
pub const MBEDTLS_ERR_SSL_PEER_VERIFY_FAILED: i32 = -30720;
pub const MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: i32 = -30848;
pub const MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO: i32 = -30976;
pub const MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO: i32 = -31104;
pub const MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE: i32 = -31232;
pub const MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_REQUEST: i32 = -31360;
pub const MBEDTLS_ERR_SSL_BAD_HS_SERVER_KEY_EXCHANGE: i32 = -31488;
pub const MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO_DONE: i32 = -31616;
pub const MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE: i32 = -31744;
pub const MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_RP: i32 = -31872;
pub const MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_CS: i32 = -32000;
pub const MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_VERIFY: i32 = -32128;
pub const MBEDTLS_ERR_SSL_BAD_HS_CHANGE_CIPHER_SPEC: i32 = -32256;
pub const MBEDTLS_ERR_SSL_BAD_HS_FINISHED: i32 = -32384;
pub const MBEDTLS_ERR_SSL_ALLOC_FAILED: i32 = -32512;
pub const MBEDTLS_ERR_SSL_HW_ACCEL_FAILED: i32 = -32640;
pub const MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH: i32 = -28544;
pub const MBEDTLS_ERR_SSL_COMPRESSION_FAILED: i32 = -28416;
pub const MBEDTLS_ERR_SSL_BAD_HS_PROTOCOL_VERSION: i32 = -28288;
pub const MBEDTLS_ERR_SSL_BAD_HS_NEW_SESSION_TICKET: i32 = -28160;
pub const MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED: i32 = -28032;
pub const MBEDTLS_ERR_SSL_PK_TYPE_MISMATCH: i32 = -27904;
pub const MBEDTLS_ERR_SSL_UNKNOWN_IDENTITY: i32 = -27776;
pub const MBEDTLS_ERR_SSL_INTERNAL_ERROR: i32 = -27648;
pub const MBEDTLS_ERR_SSL_COUNTER_WRAPPING: i32 = -27520;
pub const MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO: i32 = -27392;
pub const MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED: i32 = -27264;
pub const MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL: i32 = -27136;
pub const MBEDTLS_ERR_SSL_NO_USABLE_CIPHERSUITE: i32 = -27008;
pub const MBEDTLS_ERR_SSL_WANT_READ: i32 = -26880;
pub const MBEDTLS_ERR_SSL_WANT_WRITE: i32 = -26752;
pub const MBEDTLS_ERR_SSL_TIMEOUT: i32 = -26624;
pub const MBEDTLS_ERR_SSL_CLIENT_RECONNECT: i32 = -26496;
pub const MBEDTLS_ERR_SSL_UNEXPECTED_RECORD: i32 = -26368;
pub const MBEDTLS_ERR_SSL_NON_FATAL: i32 = -26240;
pub const MBEDTLS_ERR_SSL_INVALID_VERIFY_HASH: i32 = -26112;
pub const MBEDTLS_ERR_SSL_CONTINUE_PROCESSING: i32 = -25984;
pub const MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS: i32 = -25856;
pub const MBEDTLS_ERR_SSL_EARLY_MESSAGE: i32 = -25728;
pub const MBEDTLS_ERR_SSL_UNEXPECTED_CID: i32 = -24576;
pub const MBEDTLS_ERR_SSL_VERSION_MISMATCH: i32 = -24320;
pub const MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS: i32 = -28672;
pub const MBEDTLS_ERR_SSL_BAD_CONFIG: i32 = -24192;
pub const MBEDTLS_SSL_MAJOR_VERSION_3: u32 = 3;
pub const MBEDTLS_SSL_MINOR_VERSION_0: u32 = 0;
pub const MBEDTLS_SSL_MINOR_VERSION_1: u32 = 1;
pub const MBEDTLS_SSL_MINOR_VERSION_2: u32 = 2;
pub const MBEDTLS_SSL_MINOR_VERSION_3: u32 = 3;
pub const MBEDTLS_SSL_MINOR_VERSION_4: u32 = 4;
pub const MBEDTLS_SSL_TRANSPORT_STREAM: u32 = 0;
pub const MBEDTLS_SSL_TRANSPORT_DATAGRAM: u32 = 1;
pub const MBEDTLS_SSL_MAX_HOST_NAME_LEN: u32 = 255;
pub const MBEDTLS_SSL_MAX_ALPN_NAME_LEN: u32 = 255;
pub const MBEDTLS_SSL_MAX_ALPN_LIST_LEN: u32 = 65535;
pub const MBEDTLS_SSL_MAX_FRAG_LEN_NONE: u32 = 0;
pub const MBEDTLS_SSL_MAX_FRAG_LEN_512: u32 = 1;
pub const MBEDTLS_SSL_MAX_FRAG_LEN_1024: u32 = 2;
pub const MBEDTLS_SSL_MAX_FRAG_LEN_2048: u32 = 3;
pub const MBEDTLS_SSL_MAX_FRAG_LEN_4096: u32 = 4;
pub const MBEDTLS_SSL_MAX_FRAG_LEN_INVALID: u32 = 5;
pub const MBEDTLS_SSL_IS_CLIENT: u32 = 0;
pub const MBEDTLS_SSL_IS_SERVER: u32 = 1;
pub const MBEDTLS_SSL_IS_NOT_FALLBACK: u32 = 0;
pub const MBEDTLS_SSL_IS_FALLBACK: u32 = 1;
pub const MBEDTLS_SSL_EXTENDED_MS_DISABLED: u32 = 0;
pub const MBEDTLS_SSL_EXTENDED_MS_ENABLED: u32 = 1;
pub const MBEDTLS_SSL_CID_DISABLED: u32 = 0;
pub const MBEDTLS_SSL_CID_ENABLED: u32 = 1;
pub const MBEDTLS_SSL_ETM_DISABLED: u32 = 0;
pub const MBEDTLS_SSL_ETM_ENABLED: u32 = 1;
pub const MBEDTLS_SSL_COMPRESS_NULL: u32 = 0;
pub const MBEDTLS_SSL_COMPRESS_DEFLATE: u32 = 1;
pub const MBEDTLS_SSL_VERIFY_NONE: u32 = 0;
pub const MBEDTLS_SSL_VERIFY_OPTIONAL: u32 = 1;
pub const MBEDTLS_SSL_VERIFY_REQUIRED: u32 = 2;
pub const MBEDTLS_SSL_VERIFY_UNSET: u32 = 3;
pub const MBEDTLS_SSL_LEGACY_RENEGOTIATION: u32 = 0;
pub const MBEDTLS_SSL_SECURE_RENEGOTIATION: u32 = 1;
pub const MBEDTLS_SSL_RENEGOTIATION_DISABLED: u32 = 0;
pub const MBEDTLS_SSL_RENEGOTIATION_ENABLED: u32 = 1;
pub const MBEDTLS_SSL_ANTI_REPLAY_DISABLED: u32 = 0;
pub const MBEDTLS_SSL_ANTI_REPLAY_ENABLED: u32 = 1;
pub const MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED: i32 = -1;
pub const MBEDTLS_SSL_RENEGO_MAX_RECORDS_DEFAULT: u32 = 16;
pub const MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION: u32 = 0;
pub const MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION: u32 = 1;
pub const MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE: u32 = 2;
pub const MBEDTLS_SSL_TRUNC_HMAC_DISABLED: u32 = 0;
pub const MBEDTLS_SSL_TRUNC_HMAC_ENABLED: u32 = 1;
pub const MBEDTLS_SSL_TRUNCATED_HMAC_LEN: u32 = 10;
pub const MBEDTLS_SSL_SESSION_TICKETS_DISABLED: u32 = 0;
pub const MBEDTLS_SSL_SESSION_TICKETS_ENABLED: u32 = 1;
pub const MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED: u32 = 0;
pub const MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED: u32 = 1;
pub const MBEDTLS_SSL_ARC4_ENABLED: u32 = 0;
pub const MBEDTLS_SSL_ARC4_DISABLED: u32 = 1;
pub const MBEDTLS_SSL_PRESET_DEFAULT: u32 = 0;
pub const MBEDTLS_SSL_PRESET_SUITEB: u32 = 2;
pub const MBEDTLS_SSL_CERT_REQ_CA_LIST_ENABLED: u32 = 1;
pub const MBEDTLS_SSL_CERT_REQ_CA_LIST_DISABLED: u32 = 0;
pub const MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED: u32 = 0;
pub const MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED: u32 = 1;
pub const MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MIN: u32 = 1000;
pub const MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MAX: u32 = 60000;
pub const MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME: u32 = 86400;
pub const MBEDTLS_SSL_MAX_CONTENT_LEN: u32 = 16384;
pub const MBEDTLS_SSL_DTLS_MAX_BUFFERING: u32 = 32768;
pub const MBEDTLS_SSL_CID_IN_LEN_MAX: u32 = 32;
pub const MBEDTLS_SSL_CID_OUT_LEN_MAX: u32 = 32;
pub const MBEDTLS_SSL_CID_PADDING_GRANULARITY: u32 = 16;
pub const MBEDTLS_SSL_TLS1_3_PADDING_GRANULARITY: u32 = 1;
pub const MBEDTLS_SSL_VERIFY_DATA_MAX_LEN: u32 = 12;
pub const MBEDTLS_SSL_EMPTY_RENEGOTIATION_INFO: u32 = 255;
pub const MBEDTLS_SSL_FALLBACK_SCSV_VALUE: u32 = 22016;
pub const MBEDTLS_SSL_HASH_NONE: u32 = 0;
pub const MBEDTLS_SSL_HASH_MD5: u32 = 1;
pub const MBEDTLS_SSL_HASH_SHA1: u32 = 2;
pub const MBEDTLS_SSL_HASH_SHA224: u32 = 3;
pub const MBEDTLS_SSL_HASH_SHA256: u32 = 4;
pub const MBEDTLS_SSL_HASH_SHA384: u32 = 5;
pub const MBEDTLS_SSL_HASH_SHA512: u32 = 6;
pub const MBEDTLS_SSL_SIG_ANON: u32 = 0;
pub const MBEDTLS_SSL_SIG_RSA: u32 = 1;
pub const MBEDTLS_SSL_SIG_ECDSA: u32 = 3;
pub const MBEDTLS_SSL_CERT_TYPE_RSA_SIGN: u32 = 1;
pub const MBEDTLS_SSL_CERT_TYPE_ECDSA_SIGN: u32 = 64;
pub const MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC: u32 = 20;
pub const MBEDTLS_SSL_MSG_ALERT: u32 = 21;
pub const MBEDTLS_SSL_MSG_HANDSHAKE: u32 = 22;
pub const MBEDTLS_SSL_MSG_APPLICATION_DATA: u32 = 23;
pub const MBEDTLS_SSL_MSG_CID: u32 = 25;
pub const MBEDTLS_SSL_ALERT_LEVEL_WARNING: u32 = 1;
pub const MBEDTLS_SSL_ALERT_LEVEL_FATAL: u32 = 2;
pub const MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY: u32 = 0;
pub const MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE: u32 = 10;
pub const MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC: u32 = 20;
pub const MBEDTLS_SSL_ALERT_MSG_DECRYPTION_FAILED: u32 = 21;
pub const MBEDTLS_SSL_ALERT_MSG_RECORD_OVERFLOW: u32 = 22;
pub const MBEDTLS_SSL_ALERT_MSG_DECOMPRESSION_FAILURE: u32 = 30;
pub const MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE: u32 = 40;
pub const MBEDTLS_SSL_ALERT_MSG_NO_CERT: u32 = 41;
pub const MBEDTLS_SSL_ALERT_MSG_BAD_CERT: u32 = 42;
pub const MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_CERT: u32 = 43;
pub const MBEDTLS_SSL_ALERT_MSG_CERT_REVOKED: u32 = 44;
pub const MBEDTLS_SSL_ALERT_MSG_CERT_EXPIRED: u32 = 45;
pub const MBEDTLS_SSL_ALERT_MSG_CERT_UNKNOWN: u32 = 46;
pub const MBEDTLS_SSL_ALERT_MSG_ILLEGAL_PARAMETER: u32 = 47;
pub const MBEDTLS_SSL_ALERT_MSG_UNKNOWN_CA: u32 = 48;
pub const MBEDTLS_SSL_ALERT_MSG_ACCESS_DENIED: u32 = 49;
pub const MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR: u32 = 50;
pub const MBEDTLS_SSL_ALERT_MSG_DECRYPT_ERROR: u32 = 51;
pub const MBEDTLS_SSL_ALERT_MSG_EXPORT_RESTRICTION: u32 = 60;
pub const MBEDTLS_SSL_ALERT_MSG_PROTOCOL_VERSION: u32 = 70;
pub const MBEDTLS_SSL_ALERT_MSG_INSUFFICIENT_SECURITY: u32 = 71;
pub const MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR: u32 = 80;
pub const MBEDTLS_SSL_ALERT_MSG_INAPROPRIATE_FALLBACK: u32 = 86;
pub const MBEDTLS_SSL_ALERT_MSG_USER_CANCELED: u32 = 90;
pub const MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION: u32 = 100;
pub const MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_EXT: u32 = 110;
pub const MBEDTLS_SSL_ALERT_MSG_UNRECOGNIZED_NAME: u32 = 112;
pub const MBEDTLS_SSL_ALERT_MSG_UNKNOWN_PSK_IDENTITY: u32 = 115;
pub const MBEDTLS_SSL_ALERT_MSG_NO_APPLICATION_PROTOCOL: u32 = 120;
pub const MBEDTLS_SSL_HS_HELLO_REQUEST: u32 = 0;
pub const MBEDTLS_SSL_HS_CLIENT_HELLO: u32 = 1;
pub const MBEDTLS_SSL_HS_SERVER_HELLO: u32 = 2;
pub const MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST: u32 = 3;
pub const MBEDTLS_SSL_HS_NEW_SESSION_TICKET: u32 = 4;
pub const MBEDTLS_SSL_HS_CERTIFICATE: u32 = 11;
pub const MBEDTLS_SSL_HS_SERVER_KEY_EXCHANGE: u32 = 12;
pub const MBEDTLS_SSL_HS_CERTIFICATE_REQUEST: u32 = 13;
pub const MBEDTLS_SSL_HS_SERVER_HELLO_DONE: u32 = 14;
pub const MBEDTLS_SSL_HS_CERTIFICATE_VERIFY: u32 = 15;
pub const MBEDTLS_SSL_HS_CLIENT_KEY_EXCHANGE: u32 = 16;
pub const MBEDTLS_SSL_HS_FINISHED: u32 = 20;
pub const MBEDTLS_TLS_EXT_SERVERNAME: u32 = 0;
pub const MBEDTLS_TLS_EXT_SERVERNAME_HOSTNAME: u32 = 0;
pub const MBEDTLS_TLS_EXT_MAX_FRAGMENT_LENGTH: u32 = 1;
pub const MBEDTLS_TLS_EXT_TRUNCATED_HMAC: u32 = 4;
pub const MBEDTLS_TLS_EXT_SUPPORTED_ELLIPTIC_CURVES: u32 = 10;
pub const MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS: u32 = 11;
pub const MBEDTLS_TLS_EXT_SIG_ALG: u32 = 13;
pub const MBEDTLS_TLS_EXT_USE_SRTP: u32 = 14;
pub const MBEDTLS_TLS_EXT_ALPN: u32 = 16;
pub const MBEDTLS_TLS_EXT_ENCRYPT_THEN_MAC: u32 = 22;
pub const MBEDTLS_TLS_EXT_EXTENDED_MASTER_SECRET: u32 = 23;
pub const MBEDTLS_TLS_EXT_SESSION_TICKET: u32 = 35;
pub const MBEDTLS_TLS_EXT_CID: u32 = 254;
pub const MBEDTLS_TLS_EXT_ECJPAKE_KKPP: u32 = 256;
pub const MBEDTLS_TLS_EXT_RENEGOTIATION_INFO: u32 = 65281;
pub const MBEDTLS_PSK_MAX_LEN: u32 = 32;
pub const PBUF_TRANSPORT_HLEN: u32 = 20;
pub const PBUF_IP_HLEN: u32 = 40;
pub const PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS: u32 = 128;
pub const PBUF_TYPE_FLAG_DATA_VOLATILE: u32 = 64;
pub const PBUF_TYPE_ALLOC_SRC_MASK: u32 = 15;
pub const PBUF_ALLOC_FLAG_RX: u32 = 256;
pub const PBUF_ALLOC_FLAG_DATA_CONTIGUOUS: u32 = 512;
pub const PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP: u32 = 0;
pub const PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF: u32 = 1;
pub const PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL: u32 = 2;
pub const PBUF_TYPE_ALLOC_SRC_MASK_APP_MIN: u32 = 3;
pub const PBUF_TYPE_ALLOC_SRC_MASK_APP_MAX: u32 = 15;
pub const PBUF_FLAG_PUSH: u32 = 1;
pub const PBUF_FLAG_IS_CUSTOM: u32 = 2;
pub const PBUF_FLAG_MCASTLOOP: u32 = 4;
pub const PBUF_FLAG_LLBCAST: u32 = 8;
pub const PBUF_FLAG_LLMCAST: u32 = 16;
pub const PBUF_FLAG_TCP_FIN: u32 = 32;
pub const PBUF_POOL_FREE_OOSEQ: u32 = 1;
pub const MEMP_SIZE: u32 = 0;
pub const NETIF_MAX_HWADDR_LEN: u32 = 6;
pub const NETIF_NAMESIZE: u32 = 6;
pub const NETIF_FLAG_UP: u32 = 1;
pub const NETIF_FLAG_BROADCAST: u32 = 2;
pub const NETIF_FLAG_LINK_UP: u32 = 4;
pub const NETIF_FLAG_ETHARP: u32 = 8;
pub const NETIF_FLAG_ETHERNET: u32 = 16;
pub const NETIF_FLAG_IGMP: u32 = 32;
pub const NETIF_FLAG_MLD6: u32 = 64;
pub const NETIF_FLAG_GARP: u32 = 128;
pub const NETIF_ADDR_IDX_MAX: u32 = 127;
pub const LWIP_NETIF_USE_HINTS: u32 = 0;
pub const NETIF_NO_INDEX: u32 = 0;
pub const LWIP_NSC_NONE: u32 = 0;
pub const LWIP_NSC_NETIF_ADDED: u32 = 1;
pub const LWIP_NSC_NETIF_REMOVED: u32 = 2;
pub const LWIP_NSC_LINK_CHANGED: u32 = 4;
pub const LWIP_NSC_STATUS_CHANGED: u32 = 8;
pub const LWIP_NSC_IPV4_ADDRESS_CHANGED: u32 = 16;
pub const LWIP_NSC_IPV4_GATEWAY_CHANGED: u32 = 32;
pub const LWIP_NSC_IPV4_NETMASK_CHANGED: u32 = 64;
pub const LWIP_NSC_IPV4_SETTINGS_CHANGED: u32 = 128;
pub const LWIP_NSC_IPV6_SET: u32 = 256;
pub const LWIP_NSC_IPV6_ADDR_STATE_CHANGED: u32 = 512;
pub const IN_CLASSA_NET: u32 = 4278190080;
pub const IN_CLASSA_NSHIFT: u32 = 24;
pub const IN_CLASSA_HOST: u32 = 16777215;
pub const IN_CLASSA_MAX: u32 = 128;
pub const IN_CLASSB_NET: u32 = 4294901760;
pub const IN_CLASSB_NSHIFT: u32 = 16;
pub const IN_CLASSB_HOST: u32 = 65535;
pub const IN_CLASSB_MAX: u32 = 65536;
pub const IN_CLASSC_NET: u32 = 4294967040;
pub const IN_CLASSC_NSHIFT: u32 = 8;
pub const IN_CLASSC_HOST: u32 = 255;
pub const IN_CLASSD_NET: u32 = 4026531840;
pub const IN_CLASSD_NSHIFT: u32 = 28;
pub const IN_CLASSD_HOST: u32 = 268435455;
pub const IN_LOOPBACKNET: u32 = 127;
pub const INET_ADDRSTRLEN: u32 = 16;
pub const INET6_ADDRSTRLEN: u32 = 46;
pub const SIN_ZERO_LEN: u32 = 8;
pub const MSG_TRUNC: u32 = 4;
pub const MSG_CTRUNC: u32 = 8;
pub const IFNAMSIZ: u32 = 6;
pub const SOCK_STREAM: u32 = 1;
pub const SOCK_DGRAM: u32 = 2;
pub const SOCK_RAW: u32 = 3;
pub const SO_REUSEADDR: u32 = 4;
pub const SO_KEEPALIVE: u32 = 8;
pub const SO_BROADCAST: u32 = 32;
pub const SO_DEBUG: u32 = 1;
pub const SO_ACCEPTCONN: u32 = 2;
pub const SO_DONTROUTE: u32 = 16;
pub const SO_USELOOPBACK: u32 = 64;
pub const SO_LINGER: u32 = 128;
pub const SO_OOBINLINE: u32 = 256;
pub const SO_REUSEPORT: u32 = 512;
pub const SO_SNDBUF: u32 = 4097;
pub const SO_RCVBUF: u32 = 4098;
pub const SO_SNDLOWAT: u32 = 4099;
pub const SO_RCVLOWAT: u32 = 4100;
pub const SO_SNDTIMEO: u32 = 4101;
pub const SO_RCVTIMEO: u32 = 4102;
pub const SO_ERROR: u32 = 4103;
pub const SO_TYPE: u32 = 4104;
pub const SO_CONTIMEO: u32 = 4105;
pub const SO_NO_CHECK: u32 = 4106;
pub const SO_BINDTODEVICE: u32 = 4107;
pub const SOL_SOCKET: u32 = 4095;
pub const AF_UNSPEC: u32 = 0;
pub const AF_INET: u32 = 2;
pub const AF_INET6: u32 = 10;
pub const PF_INET: u32 = 2;
pub const PF_INET6: u32 = 10;
pub const PF_UNSPEC: u32 = 0;
pub const IPPROTO_IP: u32 = 0;
pub const IPPROTO_ICMP: u32 = 1;
pub const IPPROTO_TCP: u32 = 6;
pub const IPPROTO_UDP: u32 = 17;
pub const IPPROTO_IPV6: u32 = 41;
pub const IPPROTO_ICMPV6: u32 = 58;
pub const IPPROTO_UDPLITE: u32 = 136;
pub const IPPROTO_RAW: u32 = 255;
pub const MSG_PEEK: u32 = 1;
pub const MSG_WAITALL: u32 = 2;
pub const MSG_OOB: u32 = 4;
pub const MSG_DONTWAIT: u32 = 8;
pub const MSG_MORE: u32 = 16;
pub const MSG_NOSIGNAL: u32 = 32;
pub const IP_TOS: u32 = 1;
pub const IP_TTL: u32 = 2;
pub const IP_PKTINFO: u32 = 8;
pub const TCP_NODELAY: u32 = 1;
pub const TCP_KEEPALIVE: u32 = 2;
pub const TCP_KEEPIDLE: u32 = 3;
pub const TCP_KEEPINTVL: u32 = 4;
pub const TCP_KEEPCNT: u32 = 5;
pub const IPV6_CHECKSUM: u32 = 7;
pub const IPV6_V6ONLY: u32 = 27;
pub const IP_MULTICAST_TTL: u32 = 5;
pub const IP_MULTICAST_IF: u32 = 6;
pub const IP_MULTICAST_LOOP: u32 = 7;
pub const IP_ADD_MEMBERSHIP: u32 = 3;
pub const IP_DROP_MEMBERSHIP: u32 = 4;
pub const IPV6_JOIN_GROUP: u32 = 12;
pub const IPV6_ADD_MEMBERSHIP: u32 = 12;
pub const IPV6_LEAVE_GROUP: u32 = 13;
pub const IPV6_DROP_MEMBERSHIP: u32 = 13;
pub const IPV6_MULTICAST_IF: u32 = 768;
pub const IPV6_MULTICAST_HOPS: u32 = 769;
pub const IPV6_MULTICAST_LOOP: u32 = 770;
pub const IPTOS_TOS_MASK: u32 = 30;
pub const IPTOS_LOWDELAY: u32 = 16;
pub const IPTOS_THROUGHPUT: u32 = 8;
pub const IPTOS_RELIABILITY: u32 = 4;
pub const IPTOS_LOWCOST: u32 = 2;
pub const IPTOS_MINCOST: u32 = 2;
pub const IPTOS_PREC_MASK: u32 = 224;
pub const IPTOS_PREC_NETCONTROL: u32 = 224;
pub const IPTOS_PREC_INTERNETCONTROL: u32 = 192;
pub const IPTOS_PREC_CRITIC_ECP: u32 = 160;
pub const IPTOS_PREC_FLASHOVERRIDE: u32 = 128;
pub const IPTOS_PREC_FLASH: u32 = 96;
pub const IPTOS_PREC_IMMEDIATE: u32 = 64;
pub const IPTOS_PREC_PRIORITY: u32 = 32;
pub const IPTOS_PREC_ROUTINE: u32 = 0;
pub const IOCPARM_MASK: u32 = 127;
pub const IOC_VOID: u32 = 536870912;
pub const IOC_OUT: u32 = 1073741824;
pub const IOC_IN: u32 = 2147483648;
pub const IOC_INOUT: u32 = 3221225472;
pub const O_NDELAY: u32 = 16384;
pub const SHUT_RD: u32 = 0;
pub const SHUT_WR: u32 = 1;
pub const SHUT_RDWR: u32 = 2;
pub const LWIP_SELECT_MAXNFDS: u32 = 64;
pub const IF_NAMESIZE: u32 = 6;
pub const MSG_DONTROUTE: u32 = 4;
pub const SOCK_SEQPACKET: u32 = 5;
pub const MSG_EOR: u32 = 8;
pub const SOMAXCONN: u32 = 128;
pub const IPV6_UNICAST_HOPS: u32 = 4;
pub const NI_MAXHOST: u32 = 1025;
pub const NI_MAXSERV: u32 = 32;
pub const NI_NUMERICSERV: u32 = 8;
pub const NI_DGRAM: u32 = 16;
pub const ESP_ERR_ESP_TLS_BASE: i32 = 32768;
pub const ESP_ERR_ESP_TLS_CANNOT_RESOLVE_HOSTNAME: i32 = 32769;
pub const ESP_ERR_ESP_TLS_CANNOT_CREATE_SOCKET: i32 = 32770;
pub const ESP_ERR_ESP_TLS_UNSUPPORTED_PROTOCOL_FAMILY: i32 = 32771;
pub const ESP_ERR_ESP_TLS_FAILED_CONNECT_TO_HOST: i32 = 32772;
pub const ESP_ERR_ESP_TLS_SOCKET_SETOPT_FAILED: i32 = 32773;
pub const ESP_ERR_ESP_TLS_CONNECTION_TIMEOUT: i32 = 32774;
pub const ESP_ERR_ESP_TLS_SE_FAILED: i32 = 32775;
pub const ESP_ERR_ESP_TLS_TCP_CLOSED_FIN: i32 = 32776;
pub const ESP_ERR_MBEDTLS_CERT_PARTLY_OK: i32 = 32784;
pub const ESP_ERR_MBEDTLS_CTR_DRBG_SEED_FAILED: i32 = 32785;
pub const ESP_ERR_MBEDTLS_SSL_SET_HOSTNAME_FAILED: i32 = 32786;
pub const ESP_ERR_MBEDTLS_SSL_CONFIG_DEFAULTS_FAILED: i32 = 32787;
pub const ESP_ERR_MBEDTLS_SSL_CONF_ALPN_PROTOCOLS_FAILED: i32 = 32788;
pub const ESP_ERR_MBEDTLS_X509_CRT_PARSE_FAILED: i32 = 32789;
pub const ESP_ERR_MBEDTLS_SSL_CONF_OWN_CERT_FAILED: i32 = 32790;
pub const ESP_ERR_MBEDTLS_SSL_SETUP_FAILED: i32 = 32791;
pub const ESP_ERR_MBEDTLS_SSL_WRITE_FAILED: i32 = 32792;
pub const ESP_ERR_MBEDTLS_PK_PARSE_KEY_FAILED: i32 = 32793;
pub const ESP_ERR_MBEDTLS_SSL_HANDSHAKE_FAILED: i32 = 32794;
pub const ESP_ERR_MBEDTLS_SSL_CONF_PSK_FAILED: i32 = 32795;
pub const ESP_ERR_MBEDTLS_SSL_TICKET_SETUP_FAILED: i32 = 32796;
pub const ESP_ERR_WOLFSSL_SSL_SET_HOSTNAME_FAILED: i32 = 32817;
pub const ESP_ERR_WOLFSSL_SSL_CONF_ALPN_PROTOCOLS_FAILED: i32 = 32818;
pub const ESP_ERR_WOLFSSL_CERT_VERIFY_SETUP_FAILED: i32 = 32819;
pub const ESP_ERR_WOLFSSL_KEY_VERIFY_SETUP_FAILED: i32 = 32820;
pub const ESP_ERR_WOLFSSL_SSL_HANDSHAKE_FAILED: i32 = 32821;
pub const ESP_ERR_WOLFSSL_CTX_SETUP_FAILED: i32 = 32822;
pub const ESP_ERR_WOLFSSL_SSL_SETUP_FAILED: i32 = 32823;
pub const ESP_ERR_WOLFSSL_SSL_WRITE_FAILED: i32 = 32824;
pub const ESP_TLS_ERR_SSL_WANT_READ: i32 = -26880;
pub const ESP_TLS_ERR_SSL_WANT_WRITE: i32 = -26752;
pub const ESP_TLS_ERR_SSL_TIMEOUT: i32 = -26624;
pub const MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED: i32 = -112;
pub const MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED: i32 = -114;
pub const MBEDTLS_PLATFORM_STD_EXIT_SUCCESS: u32 = 0;
pub const MBEDTLS_PLATFORM_STD_EXIT_FAILURE: u32 = 1;
pub const MBEDTLS_PLATFORM_STD_NV_SEED_FILE: &[u8; 9usize] = b"seedfile\0";
pub const MBEDTLS_EXIT_SUCCESS: u32 = 0;
pub const MBEDTLS_EXIT_FAILURE: u32 = 1;
pub const MBEDTLS_ERR_NET_SOCKET_FAILED: i32 = -66;
pub const MBEDTLS_ERR_NET_CONNECT_FAILED: i32 = -68;
pub const MBEDTLS_ERR_NET_BIND_FAILED: i32 = -70;
pub const MBEDTLS_ERR_NET_LISTEN_FAILED: i32 = -72;
pub const MBEDTLS_ERR_NET_ACCEPT_FAILED: i32 = -74;
pub const MBEDTLS_ERR_NET_RECV_FAILED: i32 = -76;
pub const MBEDTLS_ERR_NET_SEND_FAILED: i32 = -78;
pub const MBEDTLS_ERR_NET_CONN_RESET: i32 = -80;
pub const MBEDTLS_ERR_NET_UNKNOWN_HOST: i32 = -82;
pub const MBEDTLS_ERR_NET_BUFFER_TOO_SMALL: i32 = -67;
pub const MBEDTLS_ERR_NET_INVALID_CONTEXT: i32 = -69;
pub const MBEDTLS_ERR_NET_POLL_FAILED: i32 = -71;
pub const MBEDTLS_ERR_NET_BAD_INPUT_DATA: i32 = -73;
pub const MBEDTLS_NET_LISTEN_BACKLOG: u32 = 10;
pub const MBEDTLS_NET_PROTO_TCP: u32 = 0;
pub const MBEDTLS_NET_PROTO_UDP: u32 = 1;
pub const MBEDTLS_NET_POLL_READ: u32 = 1;
pub const MBEDTLS_NET_POLL_WRITE: u32 = 2;
pub const MBEDTLS_ERR_SHA512_HW_ACCEL_FAILED: i32 = -57;
pub const MBEDTLS_ERR_SHA512_BAD_INPUT_DATA: i32 = -117;
pub const MBEDTLS_ERR_ENTROPY_SOURCE_FAILED: i32 = -60;
pub const MBEDTLS_ERR_ENTROPY_MAX_SOURCES: i32 = -62;
pub const MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED: i32 = -64;
pub const MBEDTLS_ERR_ENTROPY_NO_STRONG_SOURCE: i32 = -61;
pub const MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR: i32 = -63;
pub const MBEDTLS_ENTROPY_MAX_SOURCES: u32 = 20;
pub const MBEDTLS_ENTROPY_MAX_GATHER: u32 = 128;
pub const MBEDTLS_ENTROPY_BLOCK_SIZE: u32 = 64;
pub const MBEDTLS_ENTROPY_MAX_SEED_SIZE: u32 = 1024;
pub const MBEDTLS_ENTROPY_SOURCE_MANUAL: u32 = 20;
pub const MBEDTLS_ENTROPY_SOURCE_STRONG: u32 = 1;
pub const MBEDTLS_ENTROPY_SOURCE_WEAK: u32 = 0;
pub const MBEDTLS_AES_ENCRYPT: u32 = 1;
pub const MBEDTLS_AES_DECRYPT: u32 = 0;
pub const MBEDTLS_ERR_AES_INVALID_KEY_LENGTH: i32 = -32;
pub const MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH: i32 = -34;
pub const MBEDTLS_ERR_AES_BAD_INPUT_DATA: i32 = -33;
pub const MBEDTLS_ERR_AES_FEATURE_UNAVAILABLE: i32 = -35;
pub const MBEDTLS_ERR_AES_HW_ACCEL_FAILED: i32 = -37;
pub const ESP_AES_ENCRYPT: u32 = 1;
pub const ESP_AES_DECRYPT: u32 = 0;
pub const AES_BLOCK_BYTES: u32 = 16;
pub const AES_BLOCK_WORDS: u32 = 4;
pub const IV_BYTES: u32 = 16;
pub const IV_WORDS: u32 = 4;
pub const TAG_BYTES: u32 = 16;
pub const TAG_WORDS: u32 = 4;
pub const AES_128_KEY_BYTES: u32 = 16;
pub const AES_192_KEY_BYTES: u32 = 24;
pub const AES_256_KEY_BYTES: u32 = 32;
pub const ERR_ESP_AES_INVALID_KEY_LENGTH: i32 = -32;
pub const ERR_ESP_AES_INVALID_INPUT_LENGTH: i32 = -34;
pub const MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED: i32 = -52;
pub const MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG: i32 = -54;
pub const MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG: i32 = -56;
pub const MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR: i32 = -58;
pub const MBEDTLS_CTR_DRBG_BLOCKSIZE: u32 = 16;
pub const MBEDTLS_CTR_DRBG_KEYSIZE: u32 = 32;
pub const MBEDTLS_CTR_DRBG_KEYBITS: u32 = 256;
pub const MBEDTLS_CTR_DRBG_SEEDLEN: u32 = 48;
pub const MBEDTLS_CTR_DRBG_ENTROPY_LEN: u32 = 48;
pub const MBEDTLS_CTR_DRBG_RESEED_INTERVAL: u32 = 10000;
pub const MBEDTLS_CTR_DRBG_MAX_INPUT: u32 = 256;
pub const MBEDTLS_CTR_DRBG_MAX_REQUEST: u32 = 1024;
pub const MBEDTLS_CTR_DRBG_MAX_SEED_INPUT: u32 = 384;
pub const MBEDTLS_CTR_DRBG_PR_OFF: u32 = 0;
pub const MBEDTLS_CTR_DRBG_PR_ON: u32 = 1;
pub const MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN: u32 = 0;
pub const MBEDTLS_ERR_ERROR_GENERIC_ERROR: i32 = -1;
pub const MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED: i32 = -110;
pub const ESP_PARTITION_MAGIC: u32 = 20650;
pub const ESP_PARTITION_MAGIC_MD5: u32 = 60395;
pub const PART_TYPE_APP: u32 = 0;
pub const PART_SUBTYPE_FACTORY: u32 = 0;
pub const PART_SUBTYPE_OTA_FLAG: u32 = 16;
pub const PART_SUBTYPE_OTA_MASK: u32 = 15;
pub const PART_SUBTYPE_TEST: u32 = 32;
pub const PART_TYPE_DATA: u32 = 1;
pub const PART_SUBTYPE_DATA_OTA: u32 = 0;
pub const PART_SUBTYPE_DATA_RF: u32 = 1;
pub const PART_SUBTYPE_DATA_WIFI: u32 = 2;
pub const PART_SUBTYPE_DATA_NVS_KEYS: u32 = 4;
pub const PART_SUBTYPE_DATA_EFUSE_EM: u32 = 5;
pub const PART_TYPE_END: u32 = 255;
pub const PART_SUBTYPE_END: u32 = 255;
pub const PART_FLAG_ENCRYPTED: u32 = 1;
pub const ESP_PARTITION_MD5_OFFSET: u32 = 16;
pub const ESP_BOOTLOADER_DIGEST_OFFSET: u32 = 0;
pub const ESP_BOOTLOADER_OFFSET: u32 = 0;
pub const ESP_PARTITION_TABLE_OFFSET: u32 = 32768;
pub const ESP_PARTITION_TABLE_MAX_LEN: u32 = 3072;
pub const ESP_IMAGE_HEADER_MAGIC: u32 = 233;
pub const ESP_IMAGE_MAX_SEGMENTS: u32 = 16;
pub const ESP_APP_DESC_MAGIC_WORD: u32 = 2882360370;
pub const ESP_ERR_IMAGE_BASE: i32 = 8192;
pub const ESP_ERR_IMAGE_FLASH_FAIL: i32 = 8193;
pub const ESP_ERR_IMAGE_INVALID: i32 = 8194;
pub const ESP_IMAGE_HASH_LEN: u32 = 32;
pub const OTA_SIZE_UNKNOWN: u32 = 4294967295;
pub const OTA_WITH_SEQUENTIAL_WRITES: u32 = 4294967294;
pub const ESP_ERR_OTA_BASE: i32 = 5376;
pub const ESP_ERR_OTA_PARTITION_CONFLICT: i32 = 5377;
pub const ESP_ERR_OTA_SELECT_INFO_INVALID: i32 = 5378;
pub const ESP_ERR_OTA_VALIDATE_FAILED: i32 = 5379;
pub const ESP_ERR_OTA_SMALL_SEC_VER: i32 = 5380;
pub const ESP_ERR_OTA_ROLLBACK_FAILED: i32 = 5381;
pub const ESP_ERR_OTA_ROLLBACK_INVALID_STATE: i32 = 5382;
pub const HTTP_PARSER_VERSION_MAJOR: u32 = 2;
pub const HTTP_PARSER_VERSION_MINOR: u32 = 7;
pub const HTTP_PARSER_VERSION_PATCH: u32 = 0;
pub const HTTP_PARSER_STRICT: u32 = 1;
pub const HTTP_MAX_HEADER_SIZE: u32 = 81920;
pub const DEFAULT_HTTP_BUF_SIZE: u32 = 512;
pub const ESP_ERR_HTTP_BASE: i32 = 28672;
pub const ESP_ERR_HTTP_MAX_REDIRECT: i32 = 28673;
pub const ESP_ERR_HTTP_CONNECT: i32 = 28674;
pub const ESP_ERR_HTTP_WRITE_DATA: i32 = 28675;
pub const ESP_ERR_HTTP_FETCH_HEADER: i32 = 28676;
pub const ESP_ERR_HTTP_INVALID_TRANSPORT: i32 = 28677;
pub const ESP_ERR_HTTP_CONNECTING: i32 = 28678;
pub const ESP_ERR_HTTP_EAGAIN: i32 = 28679;
pub const ESP_ERR_HTTP_CONNECTION_CLOSED: i32 = 28680;
pub const ESP_ERR_HTTPD_BASE: i32 = 45056;
pub const ESP_ERR_HTTPD_HANDLERS_FULL: i32 = 45057;
pub const ESP_ERR_HTTPD_HANDLER_EXISTS: i32 = 45058;
pub const ESP_ERR_HTTPD_INVALID_REQ: i32 = 45059;
pub const ESP_ERR_HTTPD_RESULT_TRUNC: i32 = 45060;
pub const ESP_ERR_HTTPD_RESP_HDR: i32 = 45061;
pub const ESP_ERR_HTTPD_RESP_SEND: i32 = 45062;
pub const ESP_ERR_HTTPD_ALLOC_MEM: i32 = 45063;
pub const ESP_ERR_HTTPD_TASK: i32 = 45064;
pub const HTTPD_RESP_USE_STRLEN: i32 = -1;
pub const HTTPD_MAX_REQ_HDR_LEN: u32 = 512;
pub const HTTPD_MAX_URI_LEN: u32 = 512;
pub const HTTPD_SOCK_ERR_FAIL: i32 = -1;
pub const HTTPD_SOCK_ERR_INVALID: i32 = -2;
pub const HTTPD_SOCK_ERR_TIMEOUT: i32 = -3;
pub const HTTPD_200: &[u8; 7usize] = b"200 OK\0";
pub const HTTPD_204: &[u8; 15usize] = b"204 No Content\0";
pub const HTTPD_207: &[u8; 17usize] = b"207 Multi-Status\0";
pub const HTTPD_400: &[u8; 16usize] = b"400 Bad Request\0";
pub const HTTPD_404: &[u8; 14usize] = b"404 Not Found\0";
pub const HTTPD_408: &[u8; 20usize] = b"408 Request Timeout\0";
pub const HTTPD_500: &[u8; 26usize] = b"500 Internal Server Error\0";
pub const HTTPD_TYPE_JSON: &[u8; 17usize] = b"application/json\0";
pub const HTTPD_TYPE_TEXT: &[u8; 10usize] = b"text/html\0";
pub const HTTPD_TYPE_OCTET: &[u8; 25usize] = b"application/octet-stream\0";
pub const MDNS_TYPE_A: u32 = 1;
pub const MDNS_TYPE_PTR: u32 = 12;
pub const MDNS_TYPE_TXT: u32 = 16;
pub const MDNS_TYPE_AAAA: u32 = 28;
pub const MDNS_TYPE_SRV: u32 = 33;
pub const MDNS_TYPE_OPT: u32 = 41;
pub const MDNS_TYPE_NSEC: u32 = 47;
pub const MDNS_TYPE_ANY: u32 = 255;
pub const ESP_ERR_NVS_BASE: i32 = 4352;
pub const ESP_ERR_NVS_NOT_INITIALIZED: i32 = 4353;
pub const ESP_ERR_NVS_NOT_FOUND: i32 = 4354;
pub const ESP_ERR_NVS_TYPE_MISMATCH: i32 = 4355;
pub const ESP_ERR_NVS_READ_ONLY: i32 = 4356;
pub const ESP_ERR_NVS_NOT_ENOUGH_SPACE: i32 = 4357;
pub const ESP_ERR_NVS_INVALID_NAME: i32 = 4358;
pub const ESP_ERR_NVS_INVALID_HANDLE: i32 = 4359;
pub const ESP_ERR_NVS_REMOVE_FAILED: i32 = 4360;
pub const ESP_ERR_NVS_KEY_TOO_LONG: i32 = 4361;
pub const ESP_ERR_NVS_PAGE_FULL: i32 = 4362;
pub const ESP_ERR_NVS_INVALID_STATE: i32 = 4363;
pub const ESP_ERR_NVS_INVALID_LENGTH: i32 = 4364;
pub const ESP_ERR_NVS_NO_FREE_PAGES: i32 = 4365;
pub const ESP_ERR_NVS_VALUE_TOO_LONG: i32 = 4366;
pub const ESP_ERR_NVS_PART_NOT_FOUND: i32 = 4367;
pub const ESP_ERR_NVS_NEW_VERSION_FOUND: i32 = 4368;
pub const ESP_ERR_NVS_XTS_ENCR_FAILED: i32 = 4369;
pub const ESP_ERR_NVS_XTS_DECR_FAILED: i32 = 4370;
pub const ESP_ERR_NVS_XTS_CFG_FAILED: i32 = 4371;
pub const ESP_ERR_NVS_XTS_CFG_NOT_FOUND: i32 = 4372;
pub const ESP_ERR_NVS_ENCR_NOT_SUPPORTED: i32 = 4373;
pub const ESP_ERR_NVS_KEYS_NOT_INITIALIZED: i32 = 4374;
pub const ESP_ERR_NVS_CORRUPT_KEY_PART: i32 = 4375;
pub const ESP_ERR_NVS_WRONG_ENCRYPTION: i32 = 4377;
pub const ESP_ERR_NVS_CONTENT_DIFFERS: i32 = 4376;
pub const NVS_DEFAULT_PART_NAME: &[u8; 4usize] = b"nvs\0";
pub const NVS_PART_NAME_MAX_SIZE: u32 = 16;
pub const NVS_KEY_NAME_MAX_SIZE: u32 = 16;
pub const NVS_KEY_SIZE: u32 = 32;
pub const MAX_BLE_DEVNAME_LEN: u32 = 29;
pub const BLE_UUID128_VAL_LENGTH: u32 = 16;
pub const MAX_BLE_MANUFACTURER_DATA_LEN: u32 = 29;
pub const RTC_GPIO_NUMBER: u32 = 22;
pub const RTCIO_GPIO0_CHANNEL: u32 = 0;
pub const RTCIO_CHANNEL_0_GPIO_NUM: u32 = 0;
pub const RTCIO_GPIO1_CHANNEL: u32 = 1;
pub const RTCIO_CHANNEL_1_GPIO_NUM: u32 = 1;
pub const RTCIO_GPIO2_CHANNEL: u32 = 2;
pub const RTCIO_CHANNEL_2_GPIO_NUM: u32 = 2;
pub const RTCIO_GPIO3_CHANNEL: u32 = 3;
pub const RTCIO_CHANNEL_3_GPIO_NUM: u32 = 3;
pub const RTCIO_GPIO4_CHANNEL: u32 = 4;
pub const RTCIO_CHANNEL_4_GPIO_NUM: u32 = 4;
pub const RTCIO_GPIO5_CHANNEL: u32 = 5;
pub const RTCIO_CHANNEL_5_GPIO_NUM: u32 = 5;
pub const RTCIO_GPIO6_CHANNEL: u32 = 6;
pub const RTCIO_CHANNEL_6_GPIO_NUM: u32 = 6;
pub const RTCIO_GPIO7_CHANNEL: u32 = 7;
pub const RTCIO_CHANNEL_7_GPIO_NUM: u32 = 7;
pub const RTCIO_GPIO8_CHANNEL: u32 = 8;
pub const RTCIO_CHANNEL_8_GPIO_NUM: u32 = 8;
pub const RTCIO_GPIO9_CHANNEL: u32 = 9;
pub const RTCIO_CHANNEL_9_GPIO_NUM: u32 = 9;
pub const RTCIO_GPIO10_CHANNEL: u32 = 10;
pub const RTCIO_CHANNEL_10_GPIO_NUM: u32 = 10;
pub const RTCIO_GPIO11_CHANNEL: u32 = 11;
pub const RTCIO_CHANNEL_11_GPIO_NUM: u32 = 11;
pub const RTCIO_GPIO12_CHANNEL: u32 = 12;
pub const RTCIO_CHANNEL_12_GPIO_NUM: u32 = 12;
pub const RTCIO_GPIO13_CHANNEL: u32 = 13;
pub const RTCIO_CHANNEL_13_GPIO_NUM: u32 = 13;
pub const RTCIO_GPIO14_CHANNEL: u32 = 14;
pub const RTCIO_CHANNEL_14_GPIO_NUM: u32 = 14;
pub const RTCIO_GPIO15_CHANNEL: u32 = 15;
pub const RTCIO_CHANNEL_15_GPIO_NUM: u32 = 15;
pub const RTCIO_GPIO16_CHANNEL: u32 = 16;
pub const RTCIO_CHANNEL_16_GPIO_NUM: u32 = 16;
pub const RTCIO_GPIO17_CHANNEL: u32 = 17;
pub const RTCIO_CHANNEL_17_GPIO_NUM: u32 = 17;
pub const RTCIO_GPIO18_CHANNEL: u32 = 18;
pub const RTCIO_CHANNEL_18_GPIO_NUM: u32 = 18;
pub const RTCIO_GPIO19_CHANNEL: u32 = 19;
pub const RTCIO_CHANNEL_19_GPIO_NUM: u32 = 19;
pub const RTCIO_GPIO20_CHANNEL: u32 = 20;
pub const RTCIO_CHANNEL_20_GPIO_NUM: u32 = 20;
pub const RTCIO_GPIO21_CHANNEL: u32 = 21;
pub const RTCIO_CHANNEL_21_GPIO_NUM: u32 = 21;
pub const RTC_GPIO_OUT_REG: u32 = 1610646528;
pub const RTC_GPIO_OUT_DATA: u32 = 4194303;
pub const RTC_GPIO_OUT_DATA_V: u32 = 4194303;
pub const RTC_GPIO_OUT_DATA_S: u32 = 10;
pub const RTC_GPIO_OUT_W1TS_REG: u32 = 1610646532;
pub const RTC_GPIO_OUT_DATA_W1TS: u32 = 4194303;
pub const RTC_GPIO_OUT_DATA_W1TS_V: u32 = 4194303;
pub const RTC_GPIO_OUT_DATA_W1TS_S: u32 = 10;
pub const RTC_GPIO_OUT_W1TC_REG: u32 = 1610646536;
pub const RTC_GPIO_OUT_DATA_W1TC: u32 = 4194303;
pub const RTC_GPIO_OUT_DATA_W1TC_V: u32 = 4194303;
pub const RTC_GPIO_OUT_DATA_W1TC_S: u32 = 10;
pub const RTC_GPIO_ENABLE_REG: u32 = 1610646540;
pub const RTC_GPIO_ENABLE: u32 = 4194303;
pub const RTC_GPIO_ENABLE_V: u32 = 4194303;
pub const RTC_GPIO_ENABLE_S: u32 = 10;
pub const RTC_GPIO_ENABLE_W1TS_REG: u32 = 1610646544;
pub const RTC_GPIO_ENABLE_W1TS: u32 = 4194303;
pub const RTC_GPIO_ENABLE_W1TS_V: u32 = 4194303;
pub const RTC_GPIO_ENABLE_W1TS_S: u32 = 10;
pub const RTC_GPIO_ENABLE_W1TC_REG: u32 = 1610646548;
pub const RTC_GPIO_ENABLE_W1TC: u32 = 4194303;
pub const RTC_GPIO_ENABLE_W1TC_V: u32 = 4194303;
pub const RTC_GPIO_ENABLE_W1TC_S: u32 = 10;
pub const RTC_GPIO_STATUS_REG: u32 = 1610646552;
pub const RTC_GPIO_STATUS_INT: u32 = 4194303;
pub const RTC_GPIO_STATUS_INT_V: u32 = 4194303;
pub const RTC_GPIO_STATUS_INT_S: u32 = 10;
pub const RTC_GPIO_STATUS_W1TS_REG: u32 = 1610646556;
pub const RTC_GPIO_STATUS_INT_W1TS: u32 = 4194303;
pub const RTC_GPIO_STATUS_INT_W1TS_V: u32 = 4194303;
pub const RTC_GPIO_STATUS_INT_W1TS_S: u32 = 10;
pub const RTC_GPIO_STATUS_W1TC_REG: u32 = 1610646560;
pub const RTC_GPIO_STATUS_INT_W1TC: u32 = 4194303;
pub const RTC_GPIO_STATUS_INT_W1TC_V: u32 = 4194303;
pub const RTC_GPIO_STATUS_INT_W1TC_S: u32 = 10;
pub const RTC_GPIO_IN_REG: u32 = 1610646564;
pub const RTC_GPIO_IN_NEXT: u32 = 4194303;
pub const RTC_GPIO_IN_NEXT_V: u32 = 4194303;
pub const RTC_GPIO_IN_NEXT_S: u32 = 10;
pub const RTC_GPIO_PIN0_REG: u32 = 1610646568;
pub const RTC_GPIO_PIN0_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN0_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN0_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN0_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN0_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN0_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN0_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN1_REG: u32 = 1610646572;
pub const RTC_GPIO_PIN1_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN1_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN1_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN1_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN1_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN1_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN1_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN2_REG: u32 = 1610646576;
pub const RTC_GPIO_PIN2_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN2_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN2_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN2_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN2_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN2_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN2_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN3_REG: u32 = 1610646580;
pub const RTC_GPIO_PIN3_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN3_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN3_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN3_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN3_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN3_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN3_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN4_REG: u32 = 1610646584;
pub const RTC_GPIO_PIN4_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN4_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN4_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN4_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN4_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN4_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN4_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN5_REG: u32 = 1610646588;
pub const RTC_GPIO_PIN5_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN5_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN5_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN5_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN5_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN5_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN5_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN6_REG: u32 = 1610646592;
pub const RTC_GPIO_PIN6_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN6_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN6_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN6_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN6_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN6_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN6_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN7_REG: u32 = 1610646596;
pub const RTC_GPIO_PIN7_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN7_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN7_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN7_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN7_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN7_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN7_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN8_REG: u32 = 1610646600;
pub const RTC_GPIO_PIN8_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN8_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN8_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN8_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN8_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN8_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN8_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN9_REG: u32 = 1610646604;
pub const RTC_GPIO_PIN9_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN9_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN9_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN9_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN9_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN9_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN9_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN10_REG: u32 = 1610646608;
pub const RTC_GPIO_PIN10_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN10_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN10_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN10_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN10_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN10_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN10_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN11_REG: u32 = 1610646612;
pub const RTC_GPIO_PIN11_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN11_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN11_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN11_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN11_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN11_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN11_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN12_REG: u32 = 1610646616;
pub const RTC_GPIO_PIN12_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN12_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN12_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN12_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN12_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN12_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN12_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN13_REG: u32 = 1610646620;
pub const RTC_GPIO_PIN13_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN13_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN13_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN13_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN13_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN13_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN13_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN14_REG: u32 = 1610646624;
pub const RTC_GPIO_PIN14_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN14_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN14_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN14_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN14_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN14_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN14_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN15_REG: u32 = 1610646628;
pub const RTC_GPIO_PIN15_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN15_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN15_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN15_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN15_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN15_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN15_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN16_REG: u32 = 1610646632;
pub const RTC_GPIO_PIN16_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN16_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN16_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN16_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN16_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN16_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN16_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN17_REG: u32 = 1610646636;
pub const RTC_GPIO_PIN17_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN17_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN17_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN17_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN17_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN17_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN17_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN18_REG: u32 = 1610646640;
pub const RTC_GPIO_PIN18_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN18_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN18_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN18_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN18_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN18_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN18_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN19_REG: u32 = 1610646644;
pub const RTC_GPIO_PIN19_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN19_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN19_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN19_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN19_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN19_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN19_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN20_REG: u32 = 1610646648;
pub const RTC_GPIO_PIN20_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN20_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN20_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN20_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN20_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN20_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN20_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN21_REG: u32 = 1610646652;
pub const RTC_GPIO_PIN21_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN21_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN21_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN21_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN21_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN21_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN21_PAD_DRIVER_S: u32 = 2;
pub const RTC_IO_RTC_DEBUG_SEL_REG: u32 = 1610646656;
pub const RTC_IO_DEBUG_12M_NO_GATING_V: u32 = 1;
pub const RTC_IO_DEBUG_12M_NO_GATING_S: u32 = 25;
pub const RTC_IO_DEBUG_SEL4: u32 = 31;
pub const RTC_IO_DEBUG_SEL4_V: u32 = 31;
pub const RTC_IO_DEBUG_SEL4_S: u32 = 20;
pub const RTC_IO_DEBUG_SEL3: u32 = 31;
pub const RTC_IO_DEBUG_SEL3_V: u32 = 31;
pub const RTC_IO_DEBUG_SEL3_S: u32 = 15;
pub const RTC_IO_DEBUG_SEL2: u32 = 31;
pub const RTC_IO_DEBUG_SEL2_V: u32 = 31;
pub const RTC_IO_DEBUG_SEL2_S: u32 = 10;
pub const RTC_IO_DEBUG_SEL1: u32 = 31;
pub const RTC_IO_DEBUG_SEL1_V: u32 = 31;
pub const RTC_IO_DEBUG_SEL1_S: u32 = 5;
pub const RTC_IO_DEBUG_SEL0: u32 = 31;
pub const RTC_IO_DEBUG_SEL0_V: u32 = 31;
pub const RTC_IO_DEBUG_SEL0_S: u32 = 0;
pub const RTC_IO_TOUCH_PAD0_REG: u32 = 1610646660;
pub const RTC_IO_TOUCH_PAD0_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD0_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD0_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD0_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD0_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD0_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD0_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD0_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD0_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD0_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD0_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD0_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD0_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD0_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD0_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD0_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD1_REG: u32 = 1610646664;
pub const RTC_IO_TOUCH_PAD1_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD1_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD1_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD1_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD1_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD1_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD1_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD1_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD1_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD1_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD1_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD1_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD1_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD1_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD1_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD1_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD2_REG: u32 = 1610646668;
pub const RTC_IO_TOUCH_PAD2_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD2_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD2_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD2_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD2_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD2_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD2_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD2_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD2_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD2_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD2_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD2_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD2_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD2_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD2_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD2_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD3_REG: u32 = 1610646672;
pub const RTC_IO_TOUCH_PAD3_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD3_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD3_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD3_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD3_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD3_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD3_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD3_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD3_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD3_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD3_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD3_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD3_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD3_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD3_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD3_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD4_REG: u32 = 1610646676;
pub const RTC_IO_TOUCH_PAD4_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD4_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD4_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD4_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD4_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD4_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD4_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD4_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD4_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD4_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD4_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD4_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD4_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD4_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD4_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD4_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD5_REG: u32 = 1610646680;
pub const RTC_IO_TOUCH_PAD5_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD5_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD5_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD5_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD5_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD5_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD5_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD5_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD5_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD5_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD5_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD5_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD5_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD5_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD5_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD5_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD6_REG: u32 = 1610646684;
pub const RTC_IO_TOUCH_PAD6_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD6_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD6_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD6_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD6_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD6_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD6_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD6_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD6_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD6_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD6_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD6_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD6_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD6_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD6_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD6_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD7_REG: u32 = 1610646688;
pub const RTC_IO_TOUCH_PAD7_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD7_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD7_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD7_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD7_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD7_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD7_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD7_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD7_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD7_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD7_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD7_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD7_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD7_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD7_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD7_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD8_REG: u32 = 1610646692;
pub const RTC_IO_TOUCH_PAD8_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD8_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD8_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD8_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD8_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD8_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD8_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD8_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD8_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD8_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD8_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD8_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD8_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD8_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD8_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD8_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD9_REG: u32 = 1610646696;
pub const RTC_IO_TOUCH_PAD9_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD9_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD9_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD9_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD9_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD9_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD9_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD9_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD9_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD9_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD9_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD9_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD9_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD9_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD9_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD9_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD10_REG: u32 = 1610646700;
pub const RTC_IO_TOUCH_PAD10_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD10_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD10_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD10_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD10_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD10_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD10_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD10_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD10_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD10_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD10_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD10_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD10_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD10_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD10_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD10_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD10_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD10_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD10_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD10_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD10_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD10_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD10_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD10_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD10_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD10_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD11_REG: u32 = 1610646704;
pub const RTC_IO_TOUCH_PAD11_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD11_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD11_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD11_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD11_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD11_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD11_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD11_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD11_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD11_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD11_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD11_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD11_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD11_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD11_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD11_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD11_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD11_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD11_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD11_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD11_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD11_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD11_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD11_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD11_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD11_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD12_REG: u32 = 1610646708;
pub const RTC_IO_TOUCH_PAD12_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD12_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD12_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD12_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD12_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD12_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD12_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD12_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD12_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD12_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD12_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD12_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD12_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD12_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD12_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD12_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD12_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD12_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD12_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD12_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD12_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD12_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD12_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD12_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD12_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD12_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD13_REG: u32 = 1610646712;
pub const RTC_IO_TOUCH_PAD13_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD13_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD13_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD13_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD13_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD13_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD13_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD13_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD13_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD13_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD13_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD13_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD13_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD13_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD13_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD13_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD13_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD13_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD13_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD13_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD13_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD13_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD13_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD13_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD13_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD13_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD14_REG: u32 = 1610646716;
pub const RTC_IO_TOUCH_PAD14_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD14_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD14_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD14_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD14_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD14_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD14_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD14_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD14_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD14_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD14_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD14_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD14_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD14_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD14_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD14_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD14_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD14_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD14_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD14_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD14_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD14_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD14_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD14_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD14_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD14_FUN_IE_S: u32 = 13;
pub const RTC_IO_XTAL_32P_PAD_REG: u32 = 1610646720;
pub const RTC_IO_X32P_DRV: u32 = 3;
pub const RTC_IO_X32P_DRV_V: u32 = 3;
pub const RTC_IO_X32P_DRV_S: u32 = 29;
pub const RTC_IO_X32P_RDE_V: u32 = 1;
pub const RTC_IO_X32P_RDE_S: u32 = 28;
pub const RTC_IO_X32P_RUE_V: u32 = 1;
pub const RTC_IO_X32P_RUE_S: u32 = 27;
pub const RTC_IO_X32P_MUX_SEL_V: u32 = 1;
pub const RTC_IO_X32P_MUX_SEL_S: u32 = 19;
pub const RTC_IO_X32P_FUN_SEL: u32 = 3;
pub const RTC_IO_X32P_FUN_SEL_V: u32 = 3;
pub const RTC_IO_X32P_FUN_SEL_S: u32 = 17;
pub const RTC_IO_X32P_SLP_SEL_V: u32 = 1;
pub const RTC_IO_X32P_SLP_SEL_S: u32 = 16;
pub const RTC_IO_X32P_SLP_IE_V: u32 = 1;
pub const RTC_IO_X32P_SLP_IE_S: u32 = 15;
pub const RTC_IO_X32P_SLP_OE_V: u32 = 1;
pub const RTC_IO_X32P_SLP_OE_S: u32 = 14;
pub const RTC_IO_X32P_FUN_IE_V: u32 = 1;
pub const RTC_IO_X32P_FUN_IE_S: u32 = 13;
pub const RTC_IO_XTAL_32N_PAD_REG: u32 = 1610646724;
pub const RTC_IO_X32N_DRV: u32 = 3;
pub const RTC_IO_X32N_DRV_V: u32 = 3;
pub const RTC_IO_X32N_DRV_S: u32 = 29;
pub const RTC_IO_X32N_RDE_V: u32 = 1;
pub const RTC_IO_X32N_RDE_S: u32 = 28;
pub const RTC_IO_X32N_RUE_V: u32 = 1;
pub const RTC_IO_X32N_RUE_S: u32 = 27;
pub const RTC_IO_X32N_MUX_SEL_V: u32 = 1;
pub const RTC_IO_X32N_MUX_SEL_S: u32 = 19;
pub const RTC_IO_X32N_FUN_SEL: u32 = 3;
pub const RTC_IO_X32N_FUN_SEL_V: u32 = 3;
pub const RTC_IO_X32N_FUN_SEL_S: u32 = 17;
pub const RTC_IO_X32N_SLP_SEL_V: u32 = 1;
pub const RTC_IO_X32N_SLP_SEL_S: u32 = 16;
pub const RTC_IO_X32N_SLP_IE_V: u32 = 1;
pub const RTC_IO_X32N_SLP_IE_S: u32 = 15;
pub const RTC_IO_X32N_SLP_OE_V: u32 = 1;
pub const RTC_IO_X32N_SLP_OE_S: u32 = 14;
pub const RTC_IO_X32N_FUN_IE_V: u32 = 1;
pub const RTC_IO_X32N_FUN_IE_S: u32 = 13;
pub const RTC_IO_PAD_DAC1_REG: u32 = 1610646728;
pub const RTC_IO_PDAC1_DRV: u32 = 3;
pub const RTC_IO_PDAC1_DRV_V: u32 = 3;
pub const RTC_IO_PDAC1_DRV_S: u32 = 29;
pub const RTC_IO_PDAC1_RDE_V: u32 = 1;
pub const RTC_IO_PDAC1_RDE_S: u32 = 28;
pub const RTC_IO_PDAC1_RUE_V: u32 = 1;
pub const RTC_IO_PDAC1_RUE_S: u32 = 27;
pub const RTC_IO_PDAC1_MUX_SEL_V: u32 = 1;
pub const RTC_IO_PDAC1_MUX_SEL_S: u32 = 19;
pub const RTC_IO_PDAC1_FUN_SEL: u32 = 3;
pub const RTC_IO_PDAC1_FUN_SEL_V: u32 = 3;
pub const RTC_IO_PDAC1_FUN_SEL_S: u32 = 17;
pub const RTC_IO_PDAC1_SLP_SEL_V: u32 = 1;
pub const RTC_IO_PDAC1_SLP_SEL_S: u32 = 16;
pub const RTC_IO_PDAC1_SLP_IE_V: u32 = 1;
pub const RTC_IO_PDAC1_SLP_IE_S: u32 = 15;
pub const RTC_IO_PDAC1_SLP_OE_V: u32 = 1;
pub const RTC_IO_PDAC1_SLP_OE_S: u32 = 14;
pub const RTC_IO_PDAC1_FUN_IE_V: u32 = 1;
pub const RTC_IO_PDAC1_FUN_IE_S: u32 = 13;
pub const RTC_IO_PDAC1_DAC_XPD_FORCE_V: u32 = 1;
pub const RTC_IO_PDAC1_DAC_XPD_FORCE_S: u32 = 12;
pub const RTC_IO_PDAC1_XPD_DAC_V: u32 = 1;
pub const RTC_IO_PDAC1_XPD_DAC_S: u32 = 11;
pub const RTC_IO_PDAC1_DAC: u32 = 255;
pub const RTC_IO_PDAC1_DAC_V: u32 = 255;
pub const RTC_IO_PDAC1_DAC_S: u32 = 3;
pub const RTC_IO_PAD_DAC2_REG: u32 = 1610646732;
pub const RTC_IO_PDAC2_DRV: u32 = 3;
pub const RTC_IO_PDAC2_DRV_V: u32 = 3;
pub const RTC_IO_PDAC2_DRV_S: u32 = 29;
pub const RTC_IO_PDAC2_RDE_V: u32 = 1;
pub const RTC_IO_PDAC2_RDE_S: u32 = 28;
pub const RTC_IO_PDAC2_RUE_V: u32 = 1;
pub const RTC_IO_PDAC2_RUE_S: u32 = 27;
pub const RTC_IO_PDAC2_MUX_SEL_V: u32 = 1;
pub const RTC_IO_PDAC2_MUX_SEL_S: u32 = 19;
pub const RTC_IO_PDAC2_FUN_SEL: u32 = 3;
pub const RTC_IO_PDAC2_FUN_SEL_V: u32 = 3;
pub const RTC_IO_PDAC2_FUN_SEL_S: u32 = 17;
pub const RTC_IO_PDAC2_SLP_SEL_V: u32 = 1;
pub const RTC_IO_PDAC2_SLP_SEL_S: u32 = 16;
pub const RTC_IO_PDAC2_SLP_IE_V: u32 = 1;
pub const RTC_IO_PDAC2_SLP_IE_S: u32 = 15;
pub const RTC_IO_PDAC2_SLP_OE_V: u32 = 1;
pub const RTC_IO_PDAC2_SLP_OE_S: u32 = 14;
pub const RTC_IO_PDAC2_FUN_IE_V: u32 = 1;
pub const RTC_IO_PDAC2_FUN_IE_S: u32 = 13;
pub const RTC_IO_PDAC2_DAC_XPD_FORCE_V: u32 = 1;
pub const RTC_IO_PDAC2_DAC_XPD_FORCE_S: u32 = 12;
pub const RTC_IO_PDAC2_XPD_DAC_V: u32 = 1;
pub const RTC_IO_PDAC2_XPD_DAC_S: u32 = 11;
pub const RTC_IO_PDAC2_DAC: u32 = 255;
pub const RTC_IO_PDAC2_DAC_V: u32 = 255;
pub const RTC_IO_PDAC2_DAC_S: u32 = 3;
pub const RTC_IO_RTC_PAD19_REG: u32 = 1610646736;
pub const RTC_IO_PAD19_DRV: u32 = 3;
pub const RTC_IO_PAD19_DRV_V: u32 = 3;
pub const RTC_IO_PAD19_DRV_S: u32 = 29;
pub const RTC_IO_PAD19_RDE_V: u32 = 1;
pub const RTC_IO_PAD19_RDE_S: u32 = 28;
pub const RTC_IO_PAD19_RUE_V: u32 = 1;
pub const RTC_IO_PAD19_RUE_S: u32 = 27;
pub const RTC_IO_PAD19_MUX_SEL_V: u32 = 1;
pub const RTC_IO_PAD19_MUX_SEL_S: u32 = 19;
pub const RTC_IO_PAD19_FUN_SEL: u32 = 3;
pub const RTC_IO_PAD19_FUN_SEL_V: u32 = 3;
pub const RTC_IO_PAD19_FUN_SEL_S: u32 = 17;
pub const RTC_IO_PAD19_SLP_SEL_V: u32 = 1;
pub const RTC_IO_PAD19_SLP_SEL_S: u32 = 16;
pub const RTC_IO_PAD19_SLP_IE_V: u32 = 1;
pub const RTC_IO_PAD19_SLP_IE_S: u32 = 15;
pub const RTC_IO_PAD19_SLP_OE_V: u32 = 1;
pub const RTC_IO_PAD19_SLP_OE_S: u32 = 14;
pub const RTC_IO_PAD19_FUN_IE_V: u32 = 1;
pub const RTC_IO_PAD19_FUN_IE_S: u32 = 13;
pub const RTC_IO_RTC_PAD20_REG: u32 = 1610646740;
pub const RTC_IO_PAD20_DRV: u32 = 3;
pub const RTC_IO_PAD20_DRV_V: u32 = 3;
pub const RTC_IO_PAD20_DRV_S: u32 = 29;
pub const RTC_IO_PAD20_RDE_V: u32 = 1;
pub const RTC_IO_PAD20_RDE_S: u32 = 28;
pub const RTC_IO_PAD20_RUE_V: u32 = 1;
pub const RTC_IO_PAD20_RUE_S: u32 = 27;
pub const RTC_IO_PAD20_MUX_SEL_V: u32 = 1;
pub const RTC_IO_PAD20_MUX_SEL_S: u32 = 19;
pub const RTC_IO_PAD20_FUN_SEL: u32 = 3;
pub const RTC_IO_PAD20_FUN_SEL_V: u32 = 3;
pub const RTC_IO_PAD20_FUN_SEL_S: u32 = 17;
pub const RTC_IO_PAD20_SLP_SEL_V: u32 = 1;
pub const RTC_IO_PAD20_SLP_SEL_S: u32 = 16;
pub const RTC_IO_PAD20_SLP_IE_V: u32 = 1;
pub const RTC_IO_PAD20_SLP_IE_S: u32 = 15;
pub const RTC_IO_PAD20_SLP_OE_V: u32 = 1;
pub const RTC_IO_PAD20_SLP_OE_S: u32 = 14;
pub const RTC_IO_PAD20_FUN_IE_V: u32 = 1;
pub const RTC_IO_PAD20_FUN_IE_S: u32 = 13;
pub const RTC_IO_RTC_PAD21_REG: u32 = 1610646744;
pub const RTC_IO_PAD21_DRV: u32 = 3;
pub const RTC_IO_PAD21_DRV_V: u32 = 3;
pub const RTC_IO_PAD21_DRV_S: u32 = 29;
pub const RTC_IO_PAD21_RDE_V: u32 = 1;
pub const RTC_IO_PAD21_RDE_S: u32 = 28;
pub const RTC_IO_PAD21_RUE_V: u32 = 1;
pub const RTC_IO_PAD21_RUE_S: u32 = 27;
pub const RTC_IO_PAD21_MUX_SEL_V: u32 = 1;
pub const RTC_IO_PAD21_MUX_SEL_S: u32 = 19;
pub const RTC_IO_PAD21_FUN_SEL: u32 = 3;
pub const RTC_IO_PAD21_FUN_SEL_V: u32 = 3;
pub const RTC_IO_PAD21_FUN_SEL_S: u32 = 17;
pub const RTC_IO_PAD21_SLP_SEL_V: u32 = 1;
pub const RTC_IO_PAD21_SLP_SEL_S: u32 = 16;
pub const RTC_IO_PAD21_SLP_IE_V: u32 = 1;
pub const RTC_IO_PAD21_SLP_IE_S: u32 = 15;
pub const RTC_IO_PAD21_SLP_OE_V: u32 = 1;
pub const RTC_IO_PAD21_SLP_OE_S: u32 = 14;
pub const RTC_IO_PAD21_FUN_IE_V: u32 = 1;
pub const RTC_IO_PAD21_FUN_IE_S: u32 = 13;
pub const RTC_IO_EXT_WAKEUP0_REG: u32 = 1610646748;
pub const RTC_IO_EXT_WAKEUP0_SEL: u32 = 31;
pub const RTC_IO_EXT_WAKEUP0_SEL_V: u32 = 31;
pub const RTC_IO_EXT_WAKEUP0_SEL_S: u32 = 27;
pub const RTC_IO_XTL_EXT_CTR_REG: u32 = 1610646752;
pub const RTC_IO_XTL_EXT_CTR_SEL: u32 = 31;
pub const RTC_IO_XTL_EXT_CTR_SEL_V: u32 = 31;
pub const RTC_IO_XTL_EXT_CTR_SEL_S: u32 = 27;
pub const RTC_IO_SAR_I2C_IO_REG: u32 = 1610646756;
pub const RTC_IO_SAR_I2C_SDA_SEL: u32 = 3;
pub const RTC_IO_SAR_I2C_SDA_SEL_V: u32 = 3;
pub const RTC_IO_SAR_I2C_SDA_SEL_S: u32 = 30;
pub const RTC_IO_SAR_I2C_SCL_SEL: u32 = 3;
pub const RTC_IO_SAR_I2C_SCL_SEL_V: u32 = 3;
pub const RTC_IO_SAR_I2C_SCL_SEL_S: u32 = 28;
pub const RTC_IO_SAR_DEBUG_BIT_SEL: u32 = 31;
pub const RTC_IO_SAR_DEBUG_BIT_SEL_V: u32 = 31;
pub const RTC_IO_SAR_DEBUG_BIT_SEL_S: u32 = 23;
pub const RTC_IO_TOUCH_CTRL_REG: u32 = 1610646760;
pub const RTC_IO_IO_TOUCH_BUFMODE_V: u32 = 1;
pub const RTC_IO_IO_TOUCH_BUFMODE_S: u32 = 4;
pub const RTC_IO_IO_TOUCH_BUFSEL: u32 = 15;
pub const RTC_IO_IO_TOUCH_BUFSEL_V: u32 = 15;
pub const RTC_IO_IO_TOUCH_BUFSEL_S: u32 = 0;
pub const RTC_IO_DATE_REG: u32 = 1610647036;
pub const RTC_IO_DATE: u32 = 268435455;
pub const RTC_IO_DATE_V: u32 = 268435455;
pub const RTC_IO_DATE_S: u32 = 0;
pub const RTC_CNTL_SWD_WKEY_VALUE: u32 = 2401055018;
pub const RTC_CNTL_OPTIONS0_REG: u32 = 1610645504;
pub const RTC_CNTL_SW_SYS_RST_V: u32 = 1;
pub const RTC_CNTL_SW_SYS_RST_S: u32 = 31;
pub const RTC_CNTL_DG_WRAP_FORCE_NORST_V: u32 = 1;
pub const RTC_CNTL_DG_WRAP_FORCE_NORST_S: u32 = 30;
pub const RTC_CNTL_DG_WRAP_FORCE_RST_V: u32 = 1;
pub const RTC_CNTL_DG_WRAP_FORCE_RST_S: u32 = 29;
pub const RTC_CNTL_ANALOG_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_ANALOG_FORCE_NOISO_S: u32 = 28;
pub const RTC_CNTL_PLL_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_PLL_FORCE_NOISO_S: u32 = 27;
pub const RTC_CNTL_XTL_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_XTL_FORCE_NOISO_S: u32 = 26;
pub const RTC_CNTL_ANALOG_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_ANALOG_FORCE_ISO_S: u32 = 25;
pub const RTC_CNTL_PLL_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_PLL_FORCE_ISO_S: u32 = 24;
pub const RTC_CNTL_XTL_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_XTL_FORCE_ISO_S: u32 = 23;
pub const RTC_CNTL_XTL_EN_WAIT: u32 = 15;
pub const RTC_CNTL_XTL_EN_WAIT_V: u32 = 15;
pub const RTC_CNTL_XTL_EN_WAIT_S: u32 = 14;
pub const RTC_CNTL_XTL_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_XTL_FORCE_PU_S: u32 = 13;
pub const RTC_CNTL_XTL_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_XTL_FORCE_PD_S: u32 = 12;
pub const RTC_CNTL_BBPLL_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_BBPLL_FORCE_PU_S: u32 = 11;
pub const RTC_CNTL_BBPLL_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_BBPLL_FORCE_PD_S: u32 = 10;
pub const RTC_CNTL_BBPLL_I2C_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_BBPLL_I2C_FORCE_PU_S: u32 = 9;
pub const RTC_CNTL_BBPLL_I2C_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_BBPLL_I2C_FORCE_PD_S: u32 = 8;
pub const RTC_CNTL_BB_I2C_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_BB_I2C_FORCE_PU_S: u32 = 7;
pub const RTC_CNTL_BB_I2C_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_BB_I2C_FORCE_PD_S: u32 = 6;
pub const RTC_CNTL_SW_PROCPU_RST_V: u32 = 1;
pub const RTC_CNTL_SW_PROCPU_RST_S: u32 = 5;
pub const RTC_CNTL_SW_APPCPU_RST_V: u32 = 1;
pub const RTC_CNTL_SW_APPCPU_RST_S: u32 = 4;
pub const RTC_CNTL_SW_STALL_PROCPU_C0: u32 = 3;
pub const RTC_CNTL_SW_STALL_PROCPU_C0_V: u32 = 3;
pub const RTC_CNTL_SW_STALL_PROCPU_C0_S: u32 = 2;
pub const RTC_CNTL_SW_STALL_APPCPU_C0: u32 = 3;
pub const RTC_CNTL_SW_STALL_APPCPU_C0_V: u32 = 3;
pub const RTC_CNTL_SW_STALL_APPCPU_C0_S: u32 = 0;
pub const RTC_CNTL_SLP_TIMER0_REG: u32 = 1610645508;
pub const RTC_CNTL_SLP_VAL_LO: u32 = 4294967295;
pub const RTC_CNTL_SLP_VAL_LO_V: u32 = 4294967295;
pub const RTC_CNTL_SLP_VAL_LO_S: u32 = 0;
pub const RTC_CNTL_SLP_TIMER1_REG: u32 = 1610645512;
pub const RTC_CNTL_MAIN_TIMER_ALARM_EN_V: u32 = 1;
pub const RTC_CNTL_MAIN_TIMER_ALARM_EN_S: u32 = 16;
pub const RTC_CNTL_SLP_VAL_HI: u32 = 65535;
pub const RTC_CNTL_SLP_VAL_HI_V: u32 = 65535;
pub const RTC_CNTL_SLP_VAL_HI_S: u32 = 0;
pub const RTC_CNTL_TIME_UPDATE_REG: u32 = 1610645516;
pub const RTC_CNTL_TIME_UPDATE_V: u32 = 1;
pub const RTC_CNTL_TIME_UPDATE_S: u32 = 31;
pub const RTC_CNTL_TIMER_SYS_RST_V: u32 = 1;
pub const RTC_CNTL_TIMER_SYS_RST_S: u32 = 29;
pub const RTC_CNTL_TIMER_XTL_OFF_V: u32 = 1;
pub const RTC_CNTL_TIMER_XTL_OFF_S: u32 = 28;
pub const RTC_CNTL_TIMER_SYS_STALL_V: u32 = 1;
pub const RTC_CNTL_TIMER_SYS_STALL_S: u32 = 27;
pub const RTC_CNTL_TIME_LOW0_REG: u32 = 1610645520;
pub const RTC_CNTL_TIMER_VALUE0_LOW: u32 = 4294967295;
pub const RTC_CNTL_TIMER_VALUE0_LOW_V: u32 = 4294967295;
pub const RTC_CNTL_TIMER_VALUE0_LOW_S: u32 = 0;
pub const RTC_CNTL_TIME_HIGH0_REG: u32 = 1610645524;
pub const RTC_CNTL_TIMER_VALUE0_HIGH: u32 = 65535;
pub const RTC_CNTL_TIMER_VALUE0_HIGH_V: u32 = 65535;
pub const RTC_CNTL_TIMER_VALUE0_HIGH_S: u32 = 0;
pub const RTC_CNTL_STATE0_REG: u32 = 1610645528;
pub const RTC_CNTL_SLEEP_EN_V: u32 = 1;
pub const RTC_CNTL_SLEEP_EN_S: u32 = 31;
pub const RTC_CNTL_SLP_REJECT_V: u32 = 1;
pub const RTC_CNTL_SLP_REJECT_S: u32 = 30;
pub const RTC_CNTL_SLP_WAKEUP_V: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_S: u32 = 29;
pub const RTC_CNTL_SDIO_ACTIVE_IND_V: u32 = 1;
pub const RTC_CNTL_SDIO_ACTIVE_IND_S: u32 = 28;
pub const RTC_CNTL_APB2RTC_BRIDGE_SEL_V: u32 = 1;
pub const RTC_CNTL_APB2RTC_BRIDGE_SEL_S: u32 = 22;
pub const RTC_CNTL_SLP_REJECT_CAUSE_CLR_V: u32 = 1;
pub const RTC_CNTL_SLP_REJECT_CAUSE_CLR_S: u32 = 1;
pub const RTC_CNTL_SW_CPU_INT_V: u32 = 1;
pub const RTC_CNTL_SW_CPU_INT_S: u32 = 0;
pub const RTC_CNTL_TIMER1_REG: u32 = 1610645532;
pub const RTC_CNTL_PLL_BUF_WAIT: u32 = 255;
pub const RTC_CNTL_PLL_BUF_WAIT_V: u32 = 255;
pub const RTC_CNTL_PLL_BUF_WAIT_S: u32 = 24;
pub const RTC_CNTL_XTL_BUF_WAIT: u32 = 1023;
pub const RTC_CNTL_XTL_BUF_WAIT_V: u32 = 1023;
pub const RTC_CNTL_XTL_BUF_WAIT_S: u32 = 14;
pub const RTC_CNTL_CK8M_WAIT: u32 = 255;
pub const RTC_CNTL_CK8M_WAIT_V: u32 = 255;
pub const RTC_CNTL_CK8M_WAIT_S: u32 = 6;
pub const RTC_CNTL_CPU_STALL_WAIT: u32 = 31;
pub const RTC_CNTL_CPU_STALL_WAIT_V: u32 = 31;
pub const RTC_CNTL_CPU_STALL_WAIT_S: u32 = 1;
pub const RTC_CNTL_CPU_STALL_EN_V: u32 = 1;
pub const RTC_CNTL_CPU_STALL_EN_S: u32 = 0;
pub const RTC_CNTL_TIMER2_REG: u32 = 1610645536;
pub const RTC_CNTL_MIN_TIME_CK8M_OFF: u32 = 255;
pub const RTC_CNTL_MIN_TIME_CK8M_OFF_V: u32 = 255;
pub const RTC_CNTL_MIN_TIME_CK8M_OFF_S: u32 = 24;
pub const RTC_CNTL_ULPCP_TOUCH_START_WAIT: u32 = 511;
pub const RTC_CNTL_ULPCP_TOUCH_START_WAIT_V: u32 = 511;
pub const RTC_CNTL_ULPCP_TOUCH_START_WAIT_S: u32 = 15;
pub const RTC_CNTL_TIMER3_REG: u32 = 1610645540;
pub const RTC_CNTL_BT_POWERUP_TIMER: u32 = 127;
pub const RTC_CNTL_BT_POWERUP_TIMER_V: u32 = 127;
pub const RTC_CNTL_BT_POWERUP_TIMER_S: u32 = 25;
pub const RTC_CNTL_BT_WAIT_TIMER: u32 = 511;
pub const RTC_CNTL_BT_WAIT_TIMER_V: u32 = 511;
pub const RTC_CNTL_BT_WAIT_TIMER_S: u32 = 16;
pub const RTC_CNTL_WIFI_POWERUP_TIMER: u32 = 127;
pub const RTC_CNTL_WIFI_POWERUP_TIMER_V: u32 = 127;
pub const RTC_CNTL_WIFI_POWERUP_TIMER_S: u32 = 9;
pub const RTC_CNTL_WIFI_WAIT_TIMER: u32 = 511;
pub const RTC_CNTL_WIFI_WAIT_TIMER_V: u32 = 511;
pub const RTC_CNTL_WIFI_WAIT_TIMER_S: u32 = 0;
pub const RTC_CNTL_TIMER4_REG: u32 = 1610645544;
pub const RTC_CNTL_DG_WRAP_POWERUP_TIMER: u32 = 127;
pub const RTC_CNTL_DG_WRAP_POWERUP_TIMER_V: u32 = 127;
pub const RTC_CNTL_DG_WRAP_POWERUP_TIMER_S: u32 = 25;
pub const RTC_CNTL_DG_WRAP_WAIT_TIMER: u32 = 511;
pub const RTC_CNTL_DG_WRAP_WAIT_TIMER_V: u32 = 511;
pub const RTC_CNTL_DG_WRAP_WAIT_TIMER_S: u32 = 16;
pub const RTC_CNTL_POWERUP_TIMER: u32 = 127;
pub const RTC_CNTL_POWERUP_TIMER_V: u32 = 127;
pub const RTC_CNTL_POWERUP_TIMER_S: u32 = 9;
pub const RTC_CNTL_WAIT_TIMER: u32 = 511;
pub const RTC_CNTL_WAIT_TIMER_V: u32 = 511;
pub const RTC_CNTL_WAIT_TIMER_S: u32 = 0;
pub const RTC_CNTL_TIMER5_REG: u32 = 1610645548;
pub const RTC_CNTL_MIN_SLP_VAL: u32 = 255;
pub const RTC_CNTL_MIN_SLP_VAL_V: u32 = 255;
pub const RTC_CNTL_MIN_SLP_VAL_S: u32 = 8;
pub const RTC_CNTL_MIN_SLP_VAL_MIN: u32 = 2;
pub const RTC_CNTL_TIMER6_REG: u32 = 1610645552;
pub const RTC_CNTL_DG_PERI_POWERUP_TIMER: u32 = 127;
pub const RTC_CNTL_DG_PERI_POWERUP_TIMER_V: u32 = 127;
pub const RTC_CNTL_DG_PERI_POWERUP_TIMER_S: u32 = 25;
pub const RTC_CNTL_DG_PERI_WAIT_TIMER: u32 = 511;
pub const RTC_CNTL_DG_PERI_WAIT_TIMER_V: u32 = 511;
pub const RTC_CNTL_DG_PERI_WAIT_TIMER_S: u32 = 16;
pub const RTC_CNTL_CPU_TOP_POWERUP_TIMER: u32 = 127;
pub const RTC_CNTL_CPU_TOP_POWERUP_TIMER_V: u32 = 127;
pub const RTC_CNTL_CPU_TOP_POWERUP_TIMER_S: u32 = 9;
pub const RTC_CNTL_CPU_TOP_WAIT_TIMER: u32 = 511;
pub const RTC_CNTL_CPU_TOP_WAIT_TIMER_V: u32 = 511;
pub const RTC_CNTL_CPU_TOP_WAIT_TIMER_S: u32 = 0;
pub const RTC_CNTL_ANA_CONF_REG: u32 = 1610645556;
pub const RTC_CNTL_PLL_I2C_PU_V: u32 = 1;
pub const RTC_CNTL_PLL_I2C_PU_S: u32 = 31;
pub const RTC_CNTL_CKGEN_I2C_PU_V: u32 = 1;
pub const RTC_CNTL_CKGEN_I2C_PU_S: u32 = 30;
pub const RTC_CNTL_RFRX_PBUS_PU_V: u32 = 1;
pub const RTC_CNTL_RFRX_PBUS_PU_S: u32 = 28;
pub const RTC_CNTL_TXRF_I2C_PU_V: u32 = 1;
pub const RTC_CNTL_TXRF_I2C_PU_S: u32 = 27;
pub const RTC_CNTL_PVTMON_PU_V: u32 = 1;
pub const RTC_CNTL_PVTMON_PU_S: u32 = 26;
pub const RTC_CNTL_BBPLL_CAL_SLP_START_V: u32 = 1;
pub const RTC_CNTL_BBPLL_CAL_SLP_START_S: u32 = 25;
pub const RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V: u32 = 1;
pub const RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S: u32 = 24;
pub const RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V: u32 = 1;
pub const RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S: u32 = 23;
pub const RTC_CNTL_SAR_I2C_PU_V: u32 = 1;
pub const RTC_CNTL_SAR_I2C_PU_S: u32 = 22;
pub const RTC_CNTL_GLITCH_RST_EN_V: u32 = 1;
pub const RTC_CNTL_GLITCH_RST_EN_S: u32 = 20;
pub const RTC_CNTL_I2C_RESET_POR_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_I2C_RESET_POR_FORCE_PU_S: u32 = 19;
pub const RTC_CNTL_I2C_RESET_POR_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_I2C_RESET_POR_FORCE_PD_S: u32 = 18;
pub const RTC_CNTL_RESET_STATE_REG: u32 = 1610645560;
pub const RTC_CNTL_PRO_DRESET_MASK_V: u32 = 1;
pub const RTC_CNTL_PRO_DRESET_MASK_S: u32 = 25;
pub const RTC_CNTL_APP_DRESET_MASK_V: u32 = 1;
pub const RTC_CNTL_APP_DRESET_MASK_S: u32 = 24;
pub const RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V: u32 = 1;
pub const RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S: u32 = 23;
pub const RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V: u32 = 1;
pub const RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S: u32 = 22;
pub const RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V: u32 = 1;
pub const RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S: u32 = 21;
pub const RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V: u32 = 1;
pub const RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S: u32 = 20;
pub const RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V: u32 = 1;
pub const RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S: u32 = 19;
pub const RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V: u32 = 1;
pub const RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S: u32 = 18;
pub const RTC_CNTL_RESET_FLAG_APPCPU_CLR_V: u32 = 1;
pub const RTC_CNTL_RESET_FLAG_APPCPU_CLR_S: u32 = 17;
pub const RTC_CNTL_RESET_FLAG_PROCPU_CLR_V: u32 = 1;
pub const RTC_CNTL_RESET_FLAG_PROCPU_CLR_S: u32 = 16;
pub const RTC_CNTL_RESET_FLAG_APPCPU_V: u32 = 1;
pub const RTC_CNTL_RESET_FLAG_APPCPU_S: u32 = 15;
pub const RTC_CNTL_RESET_FLAG_PROCPU_V: u32 = 1;
pub const RTC_CNTL_RESET_FLAG_PROCPU_S: u32 = 14;
pub const RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V: u32 = 1;
pub const RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S: u32 = 13;
pub const RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V: u32 = 1;
pub const RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S: u32 = 12;
pub const RTC_CNTL_RESET_CAUSE_APPCPU: u32 = 63;
pub const RTC_CNTL_RESET_CAUSE_APPCPU_V: u32 = 63;
pub const RTC_CNTL_RESET_CAUSE_APPCPU_S: u32 = 6;
pub const RTC_CNTL_RESET_CAUSE_PROCPU: u32 = 63;
pub const RTC_CNTL_RESET_CAUSE_PROCPU_V: u32 = 63;
pub const RTC_CNTL_RESET_CAUSE_PROCPU_S: u32 = 0;
pub const RTC_CNTL_WAKEUP_STATE_REG: u32 = 1610645564;
pub const RTC_CNTL_WAKEUP_ENA: u32 = 131071;
pub const RTC_CNTL_WAKEUP_ENA_V: u32 = 131071;
pub const RTC_CNTL_WAKEUP_ENA_S: u32 = 15;
pub const RTC_CNTL_INT_ENA_REG: u32 = 1610645568;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S: u32 = 20;
pub const RTC_CNTL_GLITCH_DET_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_GLITCH_DET_INT_ENA_S: u32 = 19;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S: u32 = 18;
pub const RTC_CNTL_COCPU_TRAP_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_COCPU_TRAP_INT_ENA_S: u32 = 17;
pub const RTC_CNTL_XTAL32K_DEAD_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_DEAD_INT_ENA_S: u32 = 16;
pub const RTC_CNTL_SWD_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_SWD_INT_ENA_S: u32 = 15;
pub const RTC_CNTL_SARADC2_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_SARADC2_INT_ENA_S: u32 = 14;
pub const RTC_CNTL_COCPU_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_COCPU_INT_ENA_S: u32 = 13;
pub const RTC_CNTL_TSENS_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_TSENS_INT_ENA_S: u32 = 12;
pub const RTC_CNTL_SARADC1_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_SARADC1_INT_ENA_S: u32 = 11;
pub const RTC_CNTL_MAIN_TIMER_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_MAIN_TIMER_INT_ENA_S: u32 = 10;
pub const RTC_CNTL_BROWN_OUT_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_INT_ENA_S: u32 = 9;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S: u32 = 8;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S: u32 = 7;
pub const RTC_CNTL_TOUCH_DONE_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_TOUCH_DONE_INT_ENA_S: u32 = 6;
pub const RTC_CNTL_ULP_CP_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_INT_ENA_S: u32 = 5;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S: u32 = 4;
pub const RTC_CNTL_WDT_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_WDT_INT_ENA_S: u32 = 3;
pub const RTC_CNTL_SDIO_IDLE_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_SDIO_IDLE_INT_ENA_S: u32 = 2;
pub const RTC_CNTL_SLP_REJECT_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_SLP_REJECT_INT_ENA_S: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_ENA_V: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_ENA_S: u32 = 0;
pub const RTC_CNTL_INT_RAW_REG: u32 = 1610645572;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S: u32 = 20;
pub const RTC_CNTL_GLITCH_DET_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_GLITCH_DET_INT_RAW_S: u32 = 19;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S: u32 = 18;
pub const RTC_CNTL_COCPU_TRAP_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_COCPU_TRAP_INT_RAW_S: u32 = 17;
pub const RTC_CNTL_XTAL32K_DEAD_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_DEAD_INT_RAW_S: u32 = 16;
pub const RTC_CNTL_SWD_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_SWD_INT_RAW_S: u32 = 15;
pub const RTC_CNTL_SARADC2_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_SARADC2_INT_RAW_S: u32 = 14;
pub const RTC_CNTL_COCPU_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_COCPU_INT_RAW_S: u32 = 13;
pub const RTC_CNTL_TSENS_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_TSENS_INT_RAW_S: u32 = 12;
pub const RTC_CNTL_SARADC1_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_SARADC1_INT_RAW_S: u32 = 11;
pub const RTC_CNTL_MAIN_TIMER_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_MAIN_TIMER_INT_RAW_S: u32 = 10;
pub const RTC_CNTL_BROWN_OUT_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_INT_RAW_S: u32 = 9;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S: u32 = 8;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S: u32 = 7;
pub const RTC_CNTL_TOUCH_DONE_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_TOUCH_DONE_INT_RAW_S: u32 = 6;
pub const RTC_CNTL_ULP_CP_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_INT_RAW_S: u32 = 5;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S: u32 = 4;
pub const RTC_CNTL_WDT_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_WDT_INT_RAW_S: u32 = 3;
pub const RTC_CNTL_SDIO_IDLE_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_SDIO_IDLE_INT_RAW_S: u32 = 2;
pub const RTC_CNTL_SLP_REJECT_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_SLP_REJECT_INT_RAW_S: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_RAW_V: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_RAW_S: u32 = 0;
pub const RTC_CNTL_INT_ST_REG: u32 = 1610645576;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V: u32 = 1;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S: u32 = 20;
pub const RTC_CNTL_GLITCH_DET_INT_ST_V: u32 = 1;
pub const RTC_CNTL_GLITCH_DET_INT_ST_S: u32 = 19;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V: u32 = 1;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S: u32 = 18;
pub const RTC_CNTL_COCPU_TRAP_INT_ST_V: u32 = 1;
pub const RTC_CNTL_COCPU_TRAP_INT_ST_S: u32 = 17;
pub const RTC_CNTL_XTAL32K_DEAD_INT_ST_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_DEAD_INT_ST_S: u32 = 16;
pub const RTC_CNTL_SWD_INT_ST_V: u32 = 1;
pub const RTC_CNTL_SWD_INT_ST_S: u32 = 15;
pub const RTC_CNTL_SARADC2_INT_ST_V: u32 = 1;
pub const RTC_CNTL_SARADC2_INT_ST_S: u32 = 14;
pub const RTC_CNTL_COCPU_INT_ST_V: u32 = 1;
pub const RTC_CNTL_COCPU_INT_ST_S: u32 = 13;
pub const RTC_CNTL_TSENS_INT_ST_V: u32 = 1;
pub const RTC_CNTL_TSENS_INT_ST_S: u32 = 12;
pub const RTC_CNTL_SARADC1_INT_ST_V: u32 = 1;
pub const RTC_CNTL_SARADC1_INT_ST_S: u32 = 11;
pub const RTC_CNTL_MAIN_TIMER_INT_ST_V: u32 = 1;
pub const RTC_CNTL_MAIN_TIMER_INT_ST_S: u32 = 10;
pub const RTC_CNTL_BROWN_OUT_INT_ST_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_INT_ST_S: u32 = 9;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_ST_V: u32 = 1;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_ST_S: u32 = 8;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_ST_V: u32 = 1;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_ST_S: u32 = 7;
pub const RTC_CNTL_TOUCH_DONE_INT_ST_V: u32 = 1;
pub const RTC_CNTL_TOUCH_DONE_INT_ST_S: u32 = 6;
pub const RTC_CNTL_ULP_CP_INT_ST_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_INT_ST_S: u32 = 5;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V: u32 = 1;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S: u32 = 4;
pub const RTC_CNTL_WDT_INT_ST_V: u32 = 1;
pub const RTC_CNTL_WDT_INT_ST_S: u32 = 3;
pub const RTC_CNTL_SDIO_IDLE_INT_ST_V: u32 = 1;
pub const RTC_CNTL_SDIO_IDLE_INT_ST_S: u32 = 2;
pub const RTC_CNTL_SLP_REJECT_INT_ST_V: u32 = 1;
pub const RTC_CNTL_SLP_REJECT_INT_ST_S: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_ST_V: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_ST_S: u32 = 0;
pub const RTC_CNTL_INT_CLR_REG: u32 = 1610645580;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S: u32 = 20;
pub const RTC_CNTL_GLITCH_DET_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_GLITCH_DET_INT_CLR_S: u32 = 19;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S: u32 = 18;
pub const RTC_CNTL_COCPU_TRAP_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_COCPU_TRAP_INT_CLR_S: u32 = 17;
pub const RTC_CNTL_XTAL32K_DEAD_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_DEAD_INT_CLR_S: u32 = 16;
pub const RTC_CNTL_SWD_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_SWD_INT_CLR_S: u32 = 15;
pub const RTC_CNTL_SARADC2_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_SARADC2_INT_CLR_S: u32 = 14;
pub const RTC_CNTL_COCPU_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_COCPU_INT_CLR_S: u32 = 13;
pub const RTC_CNTL_TSENS_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_TSENS_INT_CLR_S: u32 = 12;
pub const RTC_CNTL_SARADC1_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_SARADC1_INT_CLR_S: u32 = 11;
pub const RTC_CNTL_MAIN_TIMER_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_MAIN_TIMER_INT_CLR_S: u32 = 10;
pub const RTC_CNTL_BROWN_OUT_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_INT_CLR_S: u32 = 9;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S: u32 = 8;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S: u32 = 7;
pub const RTC_CNTL_TOUCH_DONE_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_TOUCH_DONE_INT_CLR_S: u32 = 6;
pub const RTC_CNTL_ULP_CP_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_INT_CLR_S: u32 = 5;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S: u32 = 4;
pub const RTC_CNTL_WDT_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_WDT_INT_CLR_S: u32 = 3;
pub const RTC_CNTL_SDIO_IDLE_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_SDIO_IDLE_INT_CLR_S: u32 = 2;
pub const RTC_CNTL_SLP_REJECT_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_SLP_REJECT_INT_CLR_S: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_CLR_V: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_CLR_S: u32 = 0;
pub const RTC_CNTL_STORE0_REG: u32 = 1610645584;
pub const RTC_CNTL_SCRATCH0: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH0_V: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH0_S: u32 = 0;
pub const RTC_CNTL_STORE1_REG: u32 = 1610645588;
pub const RTC_CNTL_SCRATCH1: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH1_V: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH1_S: u32 = 0;
pub const RTC_CNTL_STORE2_REG: u32 = 1610645592;
pub const RTC_CNTL_SCRATCH2: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH2_V: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH2_S: u32 = 0;
pub const RTC_CNTL_STORE3_REG: u32 = 1610645596;
pub const RTC_CNTL_SCRATCH3: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH3_V: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH3_S: u32 = 0;
pub const RTC_CNTL_EXT_XTL_CONF_REG: u32 = 1610645600;
pub const RTC_CNTL_XTL_EXT_CTR_EN_V: u32 = 1;
pub const RTC_CNTL_XTL_EXT_CTR_EN_S: u32 = 31;
pub const RTC_CNTL_XTL_EXT_CTR_LV_V: u32 = 1;
pub const RTC_CNTL_XTL_EXT_CTR_LV_S: u32 = 30;
pub const RTC_CNTL_XTAL32K_GPIO_SEL_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_GPIO_SEL_S: u32 = 23;
pub const RTC_CNTL_WDT_STATE: u32 = 7;
pub const RTC_CNTL_WDT_STATE_V: u32 = 7;
pub const RTC_CNTL_WDT_STATE_S: u32 = 20;
pub const RTC_CNTL_DAC_XTAL_32K: u32 = 7;
pub const RTC_CNTL_DAC_XTAL_32K_V: u32 = 7;
pub const RTC_CNTL_DAC_XTAL_32K_S: u32 = 17;
pub const RTC_CNTL_XPD_XTAL_32K_V: u32 = 1;
pub const RTC_CNTL_XPD_XTAL_32K_S: u32 = 16;
pub const RTC_CNTL_DRES_XTAL_32K: u32 = 7;
pub const RTC_CNTL_DRES_XTAL_32K_V: u32 = 7;
pub const RTC_CNTL_DRES_XTAL_32K_S: u32 = 13;
pub const RTC_CNTL_DGM_XTAL_32K: u32 = 7;
pub const RTC_CNTL_DGM_XTAL_32K_V: u32 = 7;
pub const RTC_CNTL_DGM_XTAL_32K_S: u32 = 10;
pub const RTC_CNTL_DBUF_XTAL_32K_V: u32 = 1;
pub const RTC_CNTL_DBUF_XTAL_32K_S: u32 = 9;
pub const RTC_CNTL_ENCKINIT_XTAL_32K_V: u32 = 1;
pub const RTC_CNTL_ENCKINIT_XTAL_32K_S: u32 = 8;
pub const RTC_CNTL_XTAL32K_XPD_FORCE_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_XPD_FORCE_S: u32 = 7;
pub const RTC_CNTL_XTAL32K_AUTO_RETURN_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_AUTO_RETURN_S: u32 = 6;
pub const RTC_CNTL_XTAL32K_AUTO_RESTART_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_AUTO_RESTART_S: u32 = 5;
pub const RTC_CNTL_XTAL32K_AUTO_BACKUP_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_AUTO_BACKUP_S: u32 = 4;
pub const RTC_CNTL_XTAL32K_EXT_CLK_FO_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_EXT_CLK_FO_S: u32 = 3;
pub const RTC_CNTL_XTAL32K_WDT_RESET_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_WDT_RESET_S: u32 = 2;
pub const RTC_CNTL_XTAL32K_WDT_CLK_FO_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_WDT_CLK_FO_S: u32 = 1;
pub const RTC_CNTL_XTAL32K_WDT_EN_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_WDT_EN_S: u32 = 0;
pub const RTC_CNTL_EXT_WAKEUP_CONF_REG: u32 = 1610645604;
pub const RTC_CNTL_EXT_WAKEUP1_LV_V: u32 = 1;
pub const RTC_CNTL_EXT_WAKEUP1_LV_S: u32 = 31;
pub const RTC_CNTL_EXT_WAKEUP0_LV_V: u32 = 1;
pub const RTC_CNTL_EXT_WAKEUP0_LV_S: u32 = 30;
pub const RTC_CNTL_GPIO_WAKEUP_FILTER_V: u32 = 1;
pub const RTC_CNTL_GPIO_WAKEUP_FILTER_S: u32 = 29;
pub const RTC_CNTL_SLP_REJECT_CONF_REG: u32 = 1610645608;
pub const RTC_CNTL_DEEP_SLP_REJECT_EN_V: u32 = 1;
pub const RTC_CNTL_DEEP_SLP_REJECT_EN_S: u32 = 31;
pub const RTC_CNTL_LIGHT_SLP_REJECT_EN_V: u32 = 1;
pub const RTC_CNTL_LIGHT_SLP_REJECT_EN_S: u32 = 30;
pub const RTC_CNTL_SLEEP_REJECT_ENA: u32 = 262143;
pub const RTC_CNTL_SLEEP_REJECT_ENA_V: u32 = 262143;
pub const RTC_CNTL_SLEEP_REJECT_ENA_S: u32 = 12;
pub const RTC_CNTL_CPU_PERIOD_CONF_REG: u32 = 1610645612;
pub const RTC_CNTL_CPUPERIOD_SEL: u32 = 3;
pub const RTC_CNTL_CPUPERIOD_SEL_V: u32 = 3;
pub const RTC_CNTL_CPUPERIOD_SEL_S: u32 = 30;
pub const RTC_CNTL_CPUSEL_CONF_V: u32 = 1;
pub const RTC_CNTL_CPUSEL_CONF_S: u32 = 29;
pub const RTC_CNTL_SDIO_ACT_CONF_REG: u32 = 1610645616;
pub const RTC_CNTL_SDIO_ACT_DNUM: u32 = 1023;
pub const RTC_CNTL_SDIO_ACT_DNUM_V: u32 = 1023;
pub const RTC_CNTL_SDIO_ACT_DNUM_S: u32 = 22;
pub const RTC_CNTL_CLK_CONF_REG: u32 = 1610645620;
pub const RTC_CNTL_ANA_CLK_RTC_SEL: u32 = 3;
pub const RTC_CNTL_ANA_CLK_RTC_SEL_V: u32 = 3;
pub const RTC_CNTL_ANA_CLK_RTC_SEL_S: u32 = 30;
pub const RTC_CNTL_FAST_CLK_RTC_SEL_V: u32 = 1;
pub const RTC_CNTL_FAST_CLK_RTC_SEL_S: u32 = 29;
pub const RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V: u32 = 1;
pub const RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S: u32 = 28;
pub const RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V: u32 = 1;
pub const RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S: u32 = 27;
pub const RTC_CNTL_CK8M_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_CK8M_FORCE_PU_S: u32 = 26;
pub const RTC_CNTL_CK8M_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_CK8M_FORCE_PD_S: u32 = 25;
pub const RTC_CNTL_CK8M_DFREQ: u32 = 255;
pub const RTC_CNTL_CK8M_DFREQ_V: u32 = 255;
pub const RTC_CNTL_CK8M_DFREQ_S: u32 = 17;
pub const RTC_CNTL_CK8M_FORCE_NOGATING_V: u32 = 1;
pub const RTC_CNTL_CK8M_FORCE_NOGATING_S: u32 = 16;
pub const RTC_CNTL_XTAL_FORCE_NOGATING_V: u32 = 1;
pub const RTC_CNTL_XTAL_FORCE_NOGATING_S: u32 = 15;
pub const RTC_CNTL_CK8M_DIV_SEL: u32 = 7;
pub const RTC_CNTL_CK8M_DIV_SEL_V: u32 = 7;
pub const RTC_CNTL_CK8M_DIV_SEL_S: u32 = 12;
pub const RTC_CNTL_DIG_CLK8M_EN_V: u32 = 1;
pub const RTC_CNTL_DIG_CLK8M_EN_S: u32 = 10;
pub const RTC_CNTL_DIG_CLK8M_D256_EN_V: u32 = 1;
pub const RTC_CNTL_DIG_CLK8M_D256_EN_S: u32 = 9;
pub const RTC_CNTL_DIG_XTAL32K_EN_V: u32 = 1;
pub const RTC_CNTL_DIG_XTAL32K_EN_S: u32 = 8;
pub const RTC_CNTL_ENB_CK8M_DIV_V: u32 = 1;
pub const RTC_CNTL_ENB_CK8M_DIV_S: u32 = 7;
pub const RTC_CNTL_ENB_CK8M_V: u32 = 1;
pub const RTC_CNTL_ENB_CK8M_S: u32 = 6;
pub const RTC_CNTL_CK8M_DIV: u32 = 3;
pub const RTC_CNTL_CK8M_DIV_V: u32 = 3;
pub const RTC_CNTL_CK8M_DIV_S: u32 = 4;
pub const RTC_CNTL_CK8M_DIV_SEL_VLD_V: u32 = 1;
pub const RTC_CNTL_CK8M_DIV_SEL_VLD_S: u32 = 3;
pub const RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V: u32 = 1;
pub const RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S: u32 = 2;
pub const RTC_CNTL_EFUSE_CLK_FORCE_GATING_V: u32 = 1;
pub const RTC_CNTL_EFUSE_CLK_FORCE_GATING_S: u32 = 1;
pub const RTC_CNTL_SLOW_CLK_CONF_REG: u32 = 1610645624;
pub const RTC_CNTL_SLOW_CLK_NEXT_EDGE_V: u32 = 1;
pub const RTC_CNTL_SLOW_CLK_NEXT_EDGE_S: u32 = 31;
pub const RTC_CNTL_ANA_CLK_DIV: u32 = 255;
pub const RTC_CNTL_ANA_CLK_DIV_V: u32 = 255;
pub const RTC_CNTL_ANA_CLK_DIV_S: u32 = 23;
pub const RTC_CNTL_ANA_CLK_DIV_VLD_V: u32 = 1;
pub const RTC_CNTL_ANA_CLK_DIV_VLD_S: u32 = 22;
pub const RTC_CNTL_SDIO_CONF_REG: u32 = 1610645628;
pub const RTC_CNTL_XPD_SDIO_REG_V: u32 = 1;
pub const RTC_CNTL_XPD_SDIO_REG_S: u32 = 31;
pub const RTC_CNTL_DREFH_SDIO: u32 = 3;
pub const RTC_CNTL_DREFH_SDIO_V: u32 = 3;
pub const RTC_CNTL_DREFH_SDIO_S: u32 = 29;
pub const RTC_CNTL_DREFM_SDIO: u32 = 3;
pub const RTC_CNTL_DREFM_SDIO_V: u32 = 3;
pub const RTC_CNTL_DREFM_SDIO_S: u32 = 27;
pub const RTC_CNTL_DREFL_SDIO: u32 = 3;
pub const RTC_CNTL_DREFL_SDIO_V: u32 = 3;
pub const RTC_CNTL_DREFL_SDIO_S: u32 = 25;
pub const RTC_CNTL_REG1P8_READY_V: u32 = 1;
pub const RTC_CNTL_REG1P8_READY_S: u32 = 24;
pub const RTC_CNTL_SDIO_TIEH_V: u32 = 1;
pub const RTC_CNTL_SDIO_TIEH_S: u32 = 23;
pub const RTC_CNTL_SDIO_FORCE_V: u32 = 1;
pub const RTC_CNTL_SDIO_FORCE_S: u32 = 22;
pub const RTC_CNTL_SDIO_PD_EN_V: u32 = 1;
pub const RTC_CNTL_SDIO_PD_EN_S: u32 = 21;
pub const RTC_CNTL_SDIO_ENCURLIM_V: u32 = 1;
pub const RTC_CNTL_SDIO_ENCURLIM_S: u32 = 20;
pub const RTC_CNTL_SDIO_MODECURLIM_V: u32 = 1;
pub const RTC_CNTL_SDIO_MODECURLIM_S: u32 = 19;
pub const RTC_CNTL_SDIO_DCURLIM: u32 = 7;
pub const RTC_CNTL_SDIO_DCURLIM_V: u32 = 7;
pub const RTC_CNTL_SDIO_DCURLIM_S: u32 = 16;
pub const RTC_CNTL_SDIO_EN_INITI_V: u32 = 1;
pub const RTC_CNTL_SDIO_EN_INITI_S: u32 = 15;
pub const RTC_CNTL_SDIO_INITI: u32 = 3;
pub const RTC_CNTL_SDIO_INITI_V: u32 = 3;
pub const RTC_CNTL_SDIO_INITI_S: u32 = 13;
pub const RTC_CNTL_SDIO_DCAP: u32 = 3;
pub const RTC_CNTL_SDIO_DCAP_V: u32 = 3;
pub const RTC_CNTL_SDIO_DCAP_S: u32 = 11;
pub const RTC_CNTL_SDIO_DTHDRV: u32 = 3;
pub const RTC_CNTL_SDIO_DTHDRV_V: u32 = 3;
pub const RTC_CNTL_SDIO_DTHDRV_S: u32 = 9;
pub const RTC_CNTL_SDIO_TIMER_TARGET: u32 = 255;
pub const RTC_CNTL_SDIO_TIMER_TARGET_V: u32 = 255;
pub const RTC_CNTL_SDIO_TIMER_TARGET_S: u32 = 0;
pub const RTC_CNTL_BIAS_CONF_REG: u32 = 1610645632;
pub const RTC_CNTL_DBG_ATTEN_WAKEUP: u32 = 15;
pub const RTC_CNTL_DBG_ATTEN_WAKEUP_V: u32 = 15;
pub const RTC_CNTL_DBG_ATTEN_WAKEUP_S: u32 = 26;
pub const RTC_CNTL_DBG_ATTEN_MONITOR: u32 = 15;
pub const RTC_CNTL_DBG_ATTEN_MONITOR_V: u32 = 15;
pub const RTC_CNTL_DBG_ATTEN_MONITOR_S: u32 = 22;
pub const RTC_CNTL_DBG_ATTEN_DEEP_SLP: u32 = 15;
pub const RTC_CNTL_DBG_ATTEN_DEEP_SLP_V: u32 = 15;
pub const RTC_CNTL_DBG_ATTEN_DEEP_SLP_S: u32 = 18;
pub const RTC_CNTL_BIAS_SLEEP_MONITOR_V: u32 = 1;
pub const RTC_CNTL_BIAS_SLEEP_MONITOR_S: u32 = 17;
pub const RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V: u32 = 1;
pub const RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S: u32 = 16;
pub const RTC_CNTL_PD_CUR_MONITOR_V: u32 = 1;
pub const RTC_CNTL_PD_CUR_MONITOR_S: u32 = 15;
pub const RTC_CNTL_PD_CUR_DEEP_SLP_V: u32 = 1;
pub const RTC_CNTL_PD_CUR_DEEP_SLP_S: u32 = 14;
pub const RTC_CNTL_BIAS_BUF_MONITOR_V: u32 = 1;
pub const RTC_CNTL_BIAS_BUF_MONITOR_S: u32 = 13;
pub const RTC_CNTL_BIAS_BUF_DEEP_SLP_V: u32 = 1;
pub const RTC_CNTL_BIAS_BUF_DEEP_SLP_S: u32 = 12;
pub const RTC_CNTL_BIAS_BUF_WAKE_V: u32 = 1;
pub const RTC_CNTL_BIAS_BUF_WAKE_S: u32 = 11;
pub const RTC_CNTL_BIAS_BUF_IDLE_V: u32 = 1;
pub const RTC_CNTL_BIAS_BUF_IDLE_S: u32 = 10;
pub const RTC_CNTL_REG: u32 = 1610645636;
pub const RTC_CNTL_REGULATOR_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_REGULATOR_FORCE_PU_S: u32 = 31;
pub const RTC_CNTL_REGULATOR_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_REGULATOR_FORCE_PD_S: u32 = 30;
pub const RTC_CNTL_DBOOST_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_DBOOST_FORCE_PU_S: u32 = 29;
pub const RTC_CNTL_DBOOST_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_DBOOST_FORCE_PD_S: u32 = 28;
pub const RTC_CNTL_DIG_DBIAS_0V85: u32 = 0;
pub const RTC_CNTL_DIG_DBIAS_0V90: u32 = 1;
pub const RTC_CNTL_DIG_DBIAS_0V95: u32 = 2;
pub const RTC_CNTL_DIG_DBIAS_1V00: u32 = 3;
pub const RTC_CNTL_DIG_DBIAS_1V05: u32 = 4;
pub const RTC_CNTL_DIG_DBIAS_1V10: u32 = 5;
pub const RTC_CNTL_DIG_DBIAS_1V15: u32 = 6;
pub const RTC_CNTL_DIG_DBIAS_1V20: u32 = 7;
pub const RTC_CNTL_SCK_DCAP: u32 = 255;
pub const RTC_CNTL_SCK_DCAP_V: u32 = 255;
pub const RTC_CNTL_SCK_DCAP_S: u32 = 14;
pub const RTC_CNTL_DIG_CAL_EN_V: u32 = 1;
pub const RTC_CNTL_DIG_CAL_EN_S: u32 = 7;
pub const RTC_CNTL_PWC_REG: u32 = 1610645640;
pub const RTC_CNTL_PAD_FORCE_HOLD_V: u32 = 1;
pub const RTC_CNTL_PAD_FORCE_HOLD_S: u32 = 21;
pub const RTC_CNTL_PD_EN_V: u32 = 1;
pub const RTC_CNTL_PD_EN_S: u32 = 20;
pub const RTC_CNTL_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_FORCE_PU_S: u32 = 19;
pub const RTC_CNTL_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_FORCE_PD_S: u32 = 18;
pub const RTC_CNTL_SLOWMEM_FORCE_LPU_V: u32 = 1;
pub const RTC_CNTL_SLOWMEM_FORCE_LPU_S: u32 = 11;
pub const RTC_CNTL_SLOWMEM_FORCE_LPD_V: u32 = 1;
pub const RTC_CNTL_SLOWMEM_FORCE_LPD_S: u32 = 10;
pub const RTC_CNTL_SLOWMEM_FOLW_CPU_V: u32 = 1;
pub const RTC_CNTL_SLOWMEM_FOLW_CPU_S: u32 = 9;
pub const RTC_CNTL_FASTMEM_FORCE_LPU_V: u32 = 1;
pub const RTC_CNTL_FASTMEM_FORCE_LPU_S: u32 = 8;
pub const RTC_CNTL_FASTMEM_FORCE_LPD_V: u32 = 1;
pub const RTC_CNTL_FASTMEM_FORCE_LPD_S: u32 = 7;
pub const RTC_CNTL_FASTMEM_FOLW_CPU_V: u32 = 1;
pub const RTC_CNTL_FASTMEM_FOLW_CPU_S: u32 = 6;
pub const RTC_CNTL_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_FORCE_NOISO_S: u32 = 5;
pub const RTC_CNTL_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_FORCE_ISO_S: u32 = 4;
pub const RTC_CNTL_SLOWMEM_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_SLOWMEM_FORCE_ISO_S: u32 = 3;
pub const RTC_CNTL_SLOWMEM_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_SLOWMEM_FORCE_NOISO_S: u32 = 2;
pub const RTC_CNTL_FASTMEM_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_FASTMEM_FORCE_ISO_S: u32 = 1;
pub const RTC_CNTL_FASTMEM_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_FASTMEM_FORCE_NOISO_S: u32 = 0;
pub const RTC_CNTL_REGULATOR_DRV_CTRL_REG: u32 = 1610645644;
pub const RTC_CNTL_DG_VDD_DRV_B_MONITOR: u32 = 255;
pub const RTC_CNTL_DG_VDD_DRV_B_MONITOR_V: u32 = 255;
pub const RTC_CNTL_DG_VDD_DRV_B_MONITOR_S: u32 = 20;
pub const RTC_CNTL_DG_VDD_DRV_B_SLP: u32 = 255;
pub const RTC_CNTL_DG_VDD_DRV_B_SLP_V: u32 = 255;
pub const RTC_CNTL_DG_VDD_DRV_B_SLP_S: u32 = 12;
pub const RTC_CNTL_REGULATOR_DRV_B_SLP: u32 = 63;
pub const RTC_CNTL_REGULATOR_DRV_B_SLP_V: u32 = 63;
pub const RTC_CNTL_REGULATOR_DRV_B_SLP_S: u32 = 6;
pub const RTC_CNTL_REGULATOR_DRV_B_MONITOR: u32 = 63;
pub const RTC_CNTL_REGULATOR_DRV_B_MONITOR_V: u32 = 63;
pub const RTC_CNTL_REGULATOR_DRV_B_MONITOR_S: u32 = 0;
pub const RTC_CNTL_DIG_PWC_REG: u32 = 1610645648;
pub const RTC_CNTL_DG_WRAP_PD_EN_V: u32 = 1;
pub const RTC_CNTL_DG_WRAP_PD_EN_S: u32 = 31;
pub const RTC_CNTL_WIFI_PD_EN_V: u32 = 1;
pub const RTC_CNTL_WIFI_PD_EN_S: u32 = 30;
pub const RTC_CNTL_CPU_TOP_PD_EN_V: u32 = 1;
pub const RTC_CNTL_CPU_TOP_PD_EN_S: u32 = 29;
pub const RTC_CNTL_DG_PERI_PD_EN_V: u32 = 1;
pub const RTC_CNTL_DG_PERI_PD_EN_S: u32 = 28;
pub const RTC_CNTL_BT_PD_EN_V: u32 = 1;
pub const RTC_CNTL_BT_PD_EN_S: u32 = 27;
pub const RTC_CNTL_CPU_TOP_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_CPU_TOP_FORCE_PU_S: u32 = 22;
pub const RTC_CNTL_CPU_TOP_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_CPU_TOP_FORCE_PD_S: u32 = 21;
pub const RTC_CNTL_DG_WRAP_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_DG_WRAP_FORCE_PU_S: u32 = 20;
pub const RTC_CNTL_DG_WRAP_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_DG_WRAP_FORCE_PD_S: u32 = 19;
pub const RTC_CNTL_WIFI_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_WIFI_FORCE_PU_S: u32 = 18;
pub const RTC_CNTL_WIFI_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_WIFI_FORCE_PD_S: u32 = 17;
pub const RTC_CNTL_DG_PERI_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_DG_PERI_FORCE_PU_S: u32 = 14;
pub const RTC_CNTL_DG_PERI_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_DG_PERI_FORCE_PD_S: u32 = 13;
pub const RTC_CNTL_BT_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_BT_FORCE_PU_S: u32 = 12;
pub const RTC_CNTL_BT_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_BT_FORCE_PD_S: u32 = 11;
pub const RTC_CNTL_LSLP_MEM_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_LSLP_MEM_FORCE_PU_S: u32 = 4;
pub const RTC_CNTL_LSLP_MEM_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_LSLP_MEM_FORCE_PD_S: u32 = 3;
pub const RTC_CNTL_DIG_ISO_REG: u32 = 1610645652;
pub const RTC_CNTL_DG_WRAP_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_DG_WRAP_FORCE_NOISO_S: u32 = 31;
pub const RTC_CNTL_DG_WRAP_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_DG_WRAP_FORCE_ISO_S: u32 = 30;
pub const RTC_CNTL_WIFI_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_WIFI_FORCE_NOISO_S: u32 = 29;
pub const RTC_CNTL_WIFI_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_WIFI_FORCE_ISO_S: u32 = 28;
pub const RTC_CNTL_CPU_TOP_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_CPU_TOP_FORCE_NOISO_S: u32 = 27;
pub const RTC_CNTL_CPU_TOP_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_CPU_TOP_FORCE_ISO_S: u32 = 26;
pub const RTC_CNTL_DG_PERI_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_DG_PERI_FORCE_NOISO_S: u32 = 25;
pub const RTC_CNTL_DG_PERI_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_DG_PERI_FORCE_ISO_S: u32 = 24;
pub const RTC_CNTL_BT_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_BT_FORCE_NOISO_S: u32 = 23;
pub const RTC_CNTL_BT_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_BT_FORCE_ISO_S: u32 = 22;
pub const RTC_CNTL_DG_PAD_FORCE_HOLD_V: u32 = 1;
pub const RTC_CNTL_DG_PAD_FORCE_HOLD_S: u32 = 15;
pub const RTC_CNTL_DG_PAD_FORCE_UNHOLD_V: u32 = 1;
pub const RTC_CNTL_DG_PAD_FORCE_UNHOLD_S: u32 = 14;
pub const RTC_CNTL_DG_PAD_FORCE_ISO_V: u32 = 1;
pub const RTC_CNTL_DG_PAD_FORCE_ISO_S: u32 = 13;
pub const RTC_CNTL_DG_PAD_FORCE_NOISO_V: u32 = 1;
pub const RTC_CNTL_DG_PAD_FORCE_NOISO_S: u32 = 12;
pub const RTC_CNTL_DG_PAD_AUTOHOLD_EN_V: u32 = 1;
pub const RTC_CNTL_DG_PAD_AUTOHOLD_EN_S: u32 = 11;
pub const RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V: u32 = 1;
pub const RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S: u32 = 10;
pub const RTC_CNTL_DG_PAD_AUTOHOLD_V: u32 = 1;
pub const RTC_CNTL_DG_PAD_AUTOHOLD_S: u32 = 9;
pub const RTC_CNTL_DIG_ISO_FORCE_ON_V: u32 = 1;
pub const RTC_CNTL_DIG_ISO_FORCE_ON_S: u32 = 8;
pub const RTC_CNTL_DIG_ISO_FORCE_OFF_V: u32 = 1;
pub const RTC_CNTL_DIG_ISO_FORCE_OFF_S: u32 = 7;
pub const RTC_CNTL_WDTCONFIG0_REG: u32 = 1610645656;
pub const RTC_CNTL_WDT_EN_V: u32 = 1;
pub const RTC_CNTL_WDT_EN_S: u32 = 31;
pub const RTC_CNTL_WDT_STG0: u32 = 7;
pub const RTC_CNTL_WDT_STG0_V: u32 = 7;
pub const RTC_CNTL_WDT_STG0_S: u32 = 28;
pub const RTC_CNTL_WDT_STG1: u32 = 7;
pub const RTC_CNTL_WDT_STG1_V: u32 = 7;
pub const RTC_CNTL_WDT_STG1_S: u32 = 25;
pub const RTC_CNTL_WDT_STG2: u32 = 7;
pub const RTC_CNTL_WDT_STG2_V: u32 = 7;
pub const RTC_CNTL_WDT_STG2_S: u32 = 22;
pub const RTC_CNTL_WDT_STG3: u32 = 7;
pub const RTC_CNTL_WDT_STG3_V: u32 = 7;
pub const RTC_CNTL_WDT_STG3_S: u32 = 19;
pub const RTC_CNTL_WDT_CPU_RESET_LENGTH: u32 = 7;
pub const RTC_CNTL_WDT_CPU_RESET_LENGTH_V: u32 = 7;
pub const RTC_CNTL_WDT_CPU_RESET_LENGTH_S: u32 = 16;
pub const RTC_CNTL_WDT_SYS_RESET_LENGTH: u32 = 7;
pub const RTC_CNTL_WDT_SYS_RESET_LENGTH_V: u32 = 7;
pub const RTC_CNTL_WDT_SYS_RESET_LENGTH_S: u32 = 13;
pub const RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V: u32 = 1;
pub const RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S: u32 = 12;
pub const RTC_CNTL_WDT_PROCPU_RESET_EN_V: u32 = 1;
pub const RTC_CNTL_WDT_PROCPU_RESET_EN_S: u32 = 11;
pub const RTC_CNTL_WDT_APPCPU_RESET_EN_V: u32 = 1;
pub const RTC_CNTL_WDT_APPCPU_RESET_EN_S: u32 = 10;
pub const RTC_CNTL_WDT_PAUSE_IN_SLP_V: u32 = 1;
pub const RTC_CNTL_WDT_PAUSE_IN_SLP_S: u32 = 9;
pub const RTC_CNTL_WDT_CHIP_RESET_EN_V: u32 = 1;
pub const RTC_CNTL_WDT_CHIP_RESET_EN_S: u32 = 8;
pub const RTC_CNTL_WDT_CHIP_RESET_WIDTH: u32 = 255;
pub const RTC_CNTL_WDT_CHIP_RESET_WIDTH_V: u32 = 255;
pub const RTC_CNTL_WDT_CHIP_RESET_WIDTH_S: u32 = 0;
pub const RTC_CNTL_WDTCONFIG1_REG: u32 = 1610645660;
pub const RTC_CNTL_WDT_STG0_HOLD: u32 = 4294967295;
pub const RTC_CNTL_WDT_STG0_HOLD_V: u32 = 4294967295;
pub const RTC_CNTL_WDT_STG0_HOLD_S: u32 = 0;
pub const RTC_CNTL_WDTCONFIG2_REG: u32 = 1610645664;
pub const RTC_CNTL_WDT_STG1_HOLD: u32 = 4294967295;
pub const RTC_CNTL_WDT_STG1_HOLD_V: u32 = 4294967295;
pub const RTC_CNTL_WDT_STG1_HOLD_S: u32 = 0;
pub const RTC_CNTL_WDTCONFIG3_REG: u32 = 1610645668;
pub const RTC_CNTL_WDT_STG2_HOLD: u32 = 4294967295;
pub const RTC_CNTL_WDT_STG2_HOLD_V: u32 = 4294967295;
pub const RTC_CNTL_WDT_STG2_HOLD_S: u32 = 0;
pub const RTC_CNTL_WDTCONFIG4_REG: u32 = 1610645672;
pub const RTC_CNTL_WDT_STG3_HOLD: u32 = 4294967295;
pub const RTC_CNTL_WDT_STG3_HOLD_V: u32 = 4294967295;
pub const RTC_CNTL_WDT_STG3_HOLD_S: u32 = 0;
pub const RTC_CNTL_WDTFEED_REG: u32 = 1610645676;
pub const RTC_CNTL_WDT_FEED_V: u32 = 1;
pub const RTC_CNTL_WDT_FEED_S: u32 = 31;
pub const RTC_CNTL_WDTWPROTECT_REG: u32 = 1610645680;
pub const RTC_CNTL_WDT_WKEY: u32 = 4294967295;
pub const RTC_CNTL_WDT_WKEY_V: u32 = 4294967295;
pub const RTC_CNTL_WDT_WKEY_S: u32 = 0;
pub const RTC_CNTL_SWD_CONF_REG: u32 = 1610645684;
pub const RTC_CNTL_SWD_AUTO_FEED_EN_V: u32 = 1;
pub const RTC_CNTL_SWD_AUTO_FEED_EN_S: u32 = 31;
pub const RTC_CNTL_SWD_DISABLE_V: u32 = 1;
pub const RTC_CNTL_SWD_DISABLE_S: u32 = 30;
pub const RTC_CNTL_SWD_FEED_V: u32 = 1;
pub const RTC_CNTL_SWD_FEED_S: u32 = 29;
pub const RTC_CNTL_SWD_RST_FLAG_CLR_V: u32 = 1;
pub const RTC_CNTL_SWD_RST_FLAG_CLR_S: u32 = 28;
pub const RTC_CNTL_SWD_SIGNAL_WIDTH: u32 = 1023;
pub const RTC_CNTL_SWD_SIGNAL_WIDTH_V: u32 = 1023;
pub const RTC_CNTL_SWD_SIGNAL_WIDTH_S: u32 = 18;
pub const RTC_CNTL_SWD_BYPASS_RST_V: u32 = 1;
pub const RTC_CNTL_SWD_BYPASS_RST_S: u32 = 17;
pub const RTC_CNTL_SWD_FEED_INT_V: u32 = 1;
pub const RTC_CNTL_SWD_FEED_INT_S: u32 = 1;
pub const RTC_CNTL_SWD_RESET_FLAG_V: u32 = 1;
pub const RTC_CNTL_SWD_RESET_FLAG_S: u32 = 0;
pub const RTC_CNTL_SWD_WPROTECT_REG: u32 = 1610645688;
pub const RTC_CNTL_SWD_WKEY: u32 = 4294967295;
pub const RTC_CNTL_SWD_WKEY_V: u32 = 4294967295;
pub const RTC_CNTL_SWD_WKEY_S: u32 = 0;
pub const RTC_CNTL_SW_CPU_STALL_REG: u32 = 1610645692;
pub const RTC_CNTL_SW_STALL_PROCPU_C1: u32 = 63;
pub const RTC_CNTL_SW_STALL_PROCPU_C1_V: u32 = 63;
pub const RTC_CNTL_SW_STALL_PROCPU_C1_S: u32 = 26;
pub const RTC_CNTL_SW_STALL_APPCPU_C1: u32 = 63;
pub const RTC_CNTL_SW_STALL_APPCPU_C1_V: u32 = 63;
pub const RTC_CNTL_SW_STALL_APPCPU_C1_S: u32 = 20;
pub const RTC_CNTL_STORE4_REG: u32 = 1610645696;
pub const RTC_CNTL_SCRATCH4: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH4_V: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH4_S: u32 = 0;
pub const RTC_CNTL_STORE5_REG: u32 = 1610645700;
pub const RTC_CNTL_SCRATCH5: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH5_V: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH5_S: u32 = 0;
pub const RTC_CNTL_STORE6_REG: u32 = 1610645704;
pub const RTC_CNTL_SCRATCH6: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH6_V: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH6_S: u32 = 0;
pub const RTC_CNTL_STORE7_REG: u32 = 1610645708;
pub const RTC_CNTL_SCRATCH7: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH7_V: u32 = 4294967295;
pub const RTC_CNTL_SCRATCH7_S: u32 = 0;
pub const RTC_CNTL_LOW_POWER_ST_REG: u32 = 1610645712;
pub const RTC_CNTL_MAIN_STATE: u32 = 15;
pub const RTC_CNTL_MAIN_STATE_V: u32 = 15;
pub const RTC_CNTL_MAIN_STATE_S: u32 = 28;
pub const RTC_CNTL_MAIN_STATE_IN_IDLE_V: u32 = 1;
pub const RTC_CNTL_MAIN_STATE_IN_IDLE_S: u32 = 27;
pub const RTC_CNTL_MAIN_STATE_IN_SLP_V: u32 = 1;
pub const RTC_CNTL_MAIN_STATE_IN_SLP_S: u32 = 26;
pub const RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V: u32 = 1;
pub const RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S: u32 = 25;
pub const RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V: u32 = 1;
pub const RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S: u32 = 24;
pub const RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V: u32 = 1;
pub const RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S: u32 = 23;
pub const RTC_CNTL_IN_LOW_POWER_STATE_V: u32 = 1;
pub const RTC_CNTL_IN_LOW_POWER_STATE_S: u32 = 22;
pub const RTC_CNTL_IN_WAKEUP_STATE_V: u32 = 1;
pub const RTC_CNTL_IN_WAKEUP_STATE_S: u32 = 21;
pub const RTC_CNTL_MAIN_STATE_WAIT_END_V: u32 = 1;
pub const RTC_CNTL_MAIN_STATE_WAIT_END_S: u32 = 20;
pub const RTC_CNTL_RDY_FOR_WAKEUP_V: u32 = 1;
pub const RTC_CNTL_RDY_FOR_WAKEUP_S: u32 = 19;
pub const RTC_CNTL_MAIN_STATE_PLL_ON_V: u32 = 1;
pub const RTC_CNTL_MAIN_STATE_PLL_ON_S: u32 = 18;
pub const RTC_CNTL_MAIN_STATE_XTAL_ISO_V: u32 = 1;
pub const RTC_CNTL_MAIN_STATE_XTAL_ISO_S: u32 = 17;
pub const RTC_CNTL_COCPU_STATE_DONE_V: u32 = 1;
pub const RTC_CNTL_COCPU_STATE_DONE_S: u32 = 16;
pub const RTC_CNTL_COCPU_STATE_SLP_V: u32 = 1;
pub const RTC_CNTL_COCPU_STATE_SLP_S: u32 = 15;
pub const RTC_CNTL_COCPU_STATE_SWITCH_V: u32 = 1;
pub const RTC_CNTL_COCPU_STATE_SWITCH_S: u32 = 14;
pub const RTC_CNTL_COCPU_STATE_START_V: u32 = 1;
pub const RTC_CNTL_COCPU_STATE_START_S: u32 = 13;
pub const RTC_CNTL_TOUCH_STATE_DONE_V: u32 = 1;
pub const RTC_CNTL_TOUCH_STATE_DONE_S: u32 = 12;
pub const RTC_CNTL_TOUCH_STATE_SLP_V: u32 = 1;
pub const RTC_CNTL_TOUCH_STATE_SLP_S: u32 = 11;
pub const RTC_CNTL_TOUCH_STATE_SWITCH_V: u32 = 1;
pub const RTC_CNTL_TOUCH_STATE_SWITCH_S: u32 = 10;
pub const RTC_CNTL_TOUCH_STATE_START_V: u32 = 1;
pub const RTC_CNTL_TOUCH_STATE_START_S: u32 = 9;
pub const RTC_CNTL_XPD_DIG_V: u32 = 1;
pub const RTC_CNTL_XPD_DIG_S: u32 = 8;
pub const RTC_CNTL_DIG_ISO_V: u32 = 1;
pub const RTC_CNTL_DIG_ISO_S: u32 = 7;
pub const RTC_CNTL_XPD_WIFI_V: u32 = 1;
pub const RTC_CNTL_XPD_WIFI_S: u32 = 6;
pub const RTC_CNTL_WIFI_ISO_V: u32 = 1;
pub const RTC_CNTL_WIFI_ISO_S: u32 = 5;
pub const RTC_CNTL_XPD_RTC_PERI_V: u32 = 1;
pub const RTC_CNTL_XPD_RTC_PERI_S: u32 = 4;
pub const RTC_CNTL_PERI_ISO_V: u32 = 1;
pub const RTC_CNTL_PERI_ISO_S: u32 = 3;
pub const RTC_CNTL_XPD_DIG_DCDC_V: u32 = 1;
pub const RTC_CNTL_XPD_DIG_DCDC_S: u32 = 2;
pub const RTC_CNTL_XPD_ROM0_V: u32 = 1;
pub const RTC_CNTL_XPD_ROM0_S: u32 = 0;
pub const RTC_CNTL_DIAG0_REG: u32 = 1610645716;
pub const RTC_CNTL_LOW_POWER_DIAG1: u32 = 4294967295;
pub const RTC_CNTL_LOW_POWER_DIAG1_V: u32 = 4294967295;
pub const RTC_CNTL_LOW_POWER_DIAG1_S: u32 = 0;
pub const RTC_CNTL_PAD_HOLD_REG: u32 = 1610645720;
pub const RTC_CNTL_PAD21_HOLD_V: u32 = 1;
pub const RTC_CNTL_PAD21_HOLD_S: u32 = 21;
pub const RTC_CNTL_PAD20_HOLD_V: u32 = 1;
pub const RTC_CNTL_PAD20_HOLD_S: u32 = 20;
pub const RTC_CNTL_PAD19_HOLD_V: u32 = 1;
pub const RTC_CNTL_PAD19_HOLD_S: u32 = 19;
pub const RTC_CNTL_PDAC2_HOLD_V: u32 = 1;
pub const RTC_CNTL_PDAC2_HOLD_S: u32 = 18;
pub const RTC_CNTL_PDAC1_HOLD_V: u32 = 1;
pub const RTC_CNTL_PDAC1_HOLD_S: u32 = 17;
pub const RTC_CNTL_X32N_HOLD_V: u32 = 1;
pub const RTC_CNTL_X32N_HOLD_S: u32 = 16;
pub const RTC_CNTL_X32P_HOLD_V: u32 = 1;
pub const RTC_CNTL_X32P_HOLD_S: u32 = 15;
pub const RTC_CNTL_TOUCH_PAD14_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD14_HOLD_S: u32 = 14;
pub const RTC_CNTL_TOUCH_PAD13_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD13_HOLD_S: u32 = 13;
pub const RTC_CNTL_TOUCH_PAD12_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD12_HOLD_S: u32 = 12;
pub const RTC_CNTL_TOUCH_PAD11_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD11_HOLD_S: u32 = 11;
pub const RTC_CNTL_TOUCH_PAD10_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD10_HOLD_S: u32 = 10;
pub const RTC_CNTL_TOUCH_PAD9_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD9_HOLD_S: u32 = 9;
pub const RTC_CNTL_TOUCH_PAD8_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD8_HOLD_S: u32 = 8;
pub const RTC_CNTL_TOUCH_PAD7_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD7_HOLD_S: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD6_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD6_HOLD_S: u32 = 6;
pub const RTC_CNTL_TOUCH_PAD5_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD5_HOLD_S: u32 = 5;
pub const RTC_CNTL_TOUCH_PAD4_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD4_HOLD_S: u32 = 4;
pub const RTC_CNTL_TOUCH_PAD3_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD3_HOLD_S: u32 = 3;
pub const RTC_CNTL_TOUCH_PAD2_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD2_HOLD_S: u32 = 2;
pub const RTC_CNTL_TOUCH_PAD1_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD1_HOLD_S: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD0_HOLD_V: u32 = 1;
pub const RTC_CNTL_TOUCH_PAD0_HOLD_S: u32 = 0;
pub const RTC_CNTL_DIG_PAD_HOLD_REG: u32 = 1610645724;
pub const RTC_CNTL_DIG_PAD_HOLD: u32 = 4294967295;
pub const RTC_CNTL_DIG_PAD_HOLD_V: u32 = 4294967295;
pub const RTC_CNTL_DIG_PAD_HOLD_S: u32 = 0;
pub const RTC_CNTL_EXT_WAKEUP1_REG: u32 = 1610645728;
pub const RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V: u32 = 1;
pub const RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S: u32 = 22;
pub const RTC_CNTL_EXT_WAKEUP1_SEL: u32 = 4194303;
pub const RTC_CNTL_EXT_WAKEUP1_SEL_V: u32 = 4194303;
pub const RTC_CNTL_EXT_WAKEUP1_SEL_S: u32 = 0;
pub const RTC_CNTL_EXT_WAKEUP1_STATUS_REG: u32 = 1610645732;
pub const RTC_CNTL_EXT_WAKEUP1_STATUS: u32 = 4194303;
pub const RTC_CNTL_EXT_WAKEUP1_STATUS_V: u32 = 4194303;
pub const RTC_CNTL_EXT_WAKEUP1_STATUS_S: u32 = 0;
pub const RTC_CNTL_BROWN_OUT_REG: u32 = 1610645736;
pub const RTC_CNTL_BROWN_OUT_DET_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_DET_S: u32 = 31;
pub const RTC_CNTL_BROWN_OUT_ENA_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_ENA_S: u32 = 30;
pub const RTC_CNTL_BROWN_OUT_CNT_CLR_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_CNT_CLR_S: u32 = 29;
pub const RTC_CNTL_BROWN_OUT_ANA_RST_EN_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_ANA_RST_EN_S: u32 = 28;
pub const RTC_CNTL_BROWN_OUT_RST_SEL_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_RST_SEL_S: u32 = 27;
pub const RTC_CNTL_BROWN_OUT_RST_ENA_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_RST_ENA_S: u32 = 26;
pub const RTC_CNTL_BROWN_OUT_RST_WAIT: u32 = 1023;
pub const RTC_CNTL_BROWN_OUT_RST_WAIT_V: u32 = 1023;
pub const RTC_CNTL_BROWN_OUT_RST_WAIT_S: u32 = 16;
pub const RTC_CNTL_BROWN_OUT_PD_RF_ENA_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_PD_RF_ENA_S: u32 = 15;
pub const RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S: u32 = 14;
pub const RTC_CNTL_BROWN_OUT_INT_WAIT: u32 = 1023;
pub const RTC_CNTL_BROWN_OUT_INT_WAIT_V: u32 = 1023;
pub const RTC_CNTL_BROWN_OUT_INT_WAIT_S: u32 = 4;
pub const RTC_CNTL_TIME_LOW1_REG: u32 = 1610645740;
pub const RTC_CNTL_TIMER_VALUE1_LOW: u32 = 4294967295;
pub const RTC_CNTL_TIMER_VALUE1_LOW_V: u32 = 4294967295;
pub const RTC_CNTL_TIMER_VALUE1_LOW_S: u32 = 0;
pub const RTC_CNTL_TIME_HIGH1_REG: u32 = 1610645744;
pub const RTC_CNTL_TIMER_VALUE1_HIGH: u32 = 65535;
pub const RTC_CNTL_TIMER_VALUE1_HIGH_V: u32 = 65535;
pub const RTC_CNTL_TIMER_VALUE1_HIGH_S: u32 = 0;
pub const RTC_CNTL_XTAL32K_CLK_FACTOR_REG: u32 = 1610645748;
pub const RTC_CNTL_XTAL32K_CLK_FACTOR: u32 = 4294967295;
pub const RTC_CNTL_XTAL32K_CLK_FACTOR_V: u32 = 4294967295;
pub const RTC_CNTL_XTAL32K_CLK_FACTOR_S: u32 = 0;
pub const RTC_CNTL_XTAL32K_CONF_REG: u32 = 1610645752;
pub const RTC_CNTL_XTAL32K_STABLE_THRES: u32 = 15;
pub const RTC_CNTL_XTAL32K_STABLE_THRES_V: u32 = 15;
pub const RTC_CNTL_XTAL32K_STABLE_THRES_S: u32 = 28;
pub const RTC_CNTL_XTAL32K_WDT_TIMEOUT: u32 = 255;
pub const RTC_CNTL_XTAL32K_WDT_TIMEOUT_V: u32 = 255;
pub const RTC_CNTL_XTAL32K_WDT_TIMEOUT_S: u32 = 20;
pub const RTC_CNTL_XTAL32K_RESTART_WAIT: u32 = 65535;
pub const RTC_CNTL_XTAL32K_RESTART_WAIT_V: u32 = 65535;
pub const RTC_CNTL_XTAL32K_RESTART_WAIT_S: u32 = 4;
pub const RTC_CNTL_XTAL32K_RETURN_WAIT: u32 = 15;
pub const RTC_CNTL_XTAL32K_RETURN_WAIT_V: u32 = 15;
pub const RTC_CNTL_XTAL32K_RETURN_WAIT_S: u32 = 0;
pub const RTC_CNTL_ULP_CP_TIMER_REG: u32 = 1610645756;
pub const RTC_CNTL_ULP_CP_SLP_TIMER_EN_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_SLP_TIMER_EN_S: u32 = 31;
pub const RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S: u32 = 30;
pub const RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S: u32 = 29;
pub const RTC_CNTL_ULP_CP_PC_INIT: u32 = 2047;
pub const RTC_CNTL_ULP_CP_PC_INIT_V: u32 = 2047;
pub const RTC_CNTL_ULP_CP_PC_INIT_S: u32 = 0;
pub const RTC_CNTL_ULP_CP_CTRL_REG: u32 = 1610645760;
pub const RTC_CNTL_ULP_CP_START_TOP_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_START_TOP_S: u32 = 31;
pub const RTC_CNTL_ULP_CP_FORCE_START_TOP_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_FORCE_START_TOP_S: u32 = 30;
pub const RTC_CNTL_ULP_CP_RESET_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_RESET_S: u32 = 29;
pub const RTC_CNTL_ULP_CP_CLK_FO_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_CLK_FO_S: u32 = 28;
pub const RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S: u32 = 22;
pub const RTC_CNTL_ULP_CP_MEM_ADDR_SIZE: u32 = 2047;
pub const RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V: u32 = 2047;
pub const RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S: u32 = 11;
pub const RTC_CNTL_ULP_CP_MEM_ADDR_INIT: u32 = 2047;
pub const RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V: u32 = 2047;
pub const RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S: u32 = 0;
pub const RTC_CNTL_COCPU_CTRL_REG: u32 = 1610645764;
pub const RTC_CNTL_COCPU_CLKGATE_EN_V: u32 = 1;
pub const RTC_CNTL_COCPU_CLKGATE_EN_S: u32 = 27;
pub const RTC_CNTL_COCPU_SW_INT_TRIGGER_V: u32 = 1;
pub const RTC_CNTL_COCPU_SW_INT_TRIGGER_S: u32 = 26;
pub const RTC_CNTL_COCPU_DONE_V: u32 = 1;
pub const RTC_CNTL_COCPU_DONE_S: u32 = 25;
pub const RTC_CNTL_COCPU_DONE_FORCE_V: u32 = 1;
pub const RTC_CNTL_COCPU_DONE_FORCE_S: u32 = 24;
pub const RTC_CNTL_COCPU_SEL_V: u32 = 1;
pub const RTC_CNTL_COCPU_SEL_S: u32 = 23;
pub const RTC_CNTL_COCPU_SHUT_RESET_EN_V: u32 = 1;
pub const RTC_CNTL_COCPU_SHUT_RESET_EN_S: u32 = 22;
pub const RTC_CNTL_COCPU_SHUT_2_CLK_DIS: u32 = 255;
pub const RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V: u32 = 255;
pub const RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S: u32 = 14;
pub const RTC_CNTL_COCPU_SHUT_V: u32 = 1;
pub const RTC_CNTL_COCPU_SHUT_S: u32 = 13;
pub const RTC_CNTL_COCPU_START_2_INTR_EN: u32 = 63;
pub const RTC_CNTL_COCPU_START_2_INTR_EN_V: u32 = 63;
pub const RTC_CNTL_COCPU_START_2_INTR_EN_S: u32 = 7;
pub const RTC_CNTL_COCPU_START_2_RESET_DIS: u32 = 63;
pub const RTC_CNTL_COCPU_START_2_RESET_DIS_V: u32 = 63;
pub const RTC_CNTL_COCPU_START_2_RESET_DIS_S: u32 = 1;
pub const RTC_CNTL_COCPU_CLK_FO_V: u32 = 1;
pub const RTC_CNTL_COCPU_CLK_FO_S: u32 = 0;
pub const RTC_CNTL_TOUCH_CTRL1_REG: u32 = 1610645768;
pub const RTC_CNTL_TOUCH_MEAS_NUM: u32 = 65535;
pub const RTC_CNTL_TOUCH_MEAS_NUM_V: u32 = 65535;
pub const RTC_CNTL_TOUCH_MEAS_NUM_S: u32 = 16;
pub const RTC_CNTL_TOUCH_SLEEP_CYCLES: u32 = 65535;
pub const RTC_CNTL_TOUCH_SLEEP_CYCLES_V: u32 = 65535;
pub const RTC_CNTL_TOUCH_SLEEP_CYCLES_S: u32 = 0;
pub const RTC_CNTL_TOUCH_CTRL2_REG: u32 = 1610645772;
pub const RTC_CNTL_TOUCH_CLKGATE_EN_V: u32 = 1;
pub const RTC_CNTL_TOUCH_CLKGATE_EN_S: u32 = 31;
pub const RTC_CNTL_TOUCH_CLK_FO_V: u32 = 1;
pub const RTC_CNTL_TOUCH_CLK_FO_S: u32 = 30;
pub const RTC_CNTL_TOUCH_RESET_V: u32 = 1;
pub const RTC_CNTL_TOUCH_RESET_S: u32 = 29;
pub const RTC_CNTL_TOUCH_TIMER_FORCE_DONE: u32 = 3;
pub const RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V: u32 = 3;
pub const RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S: u32 = 27;
pub const RTC_CNTL_TOUCH_SLP_CYC_DIV: u32 = 3;
pub const RTC_CNTL_TOUCH_SLP_CYC_DIV_V: u32 = 3;
pub const RTC_CNTL_TOUCH_SLP_CYC_DIV_S: u32 = 25;
pub const RTC_CNTL_TOUCH_XPD_WAIT: u32 = 255;
pub const RTC_CNTL_TOUCH_XPD_WAIT_V: u32 = 255;
pub const RTC_CNTL_TOUCH_XPD_WAIT_S: u32 = 17;
pub const RTC_CNTL_TOUCH_START_FORCE_V: u32 = 1;
pub const RTC_CNTL_TOUCH_START_FORCE_S: u32 = 16;
pub const RTC_CNTL_TOUCH_START_EN_V: u32 = 1;
pub const RTC_CNTL_TOUCH_START_EN_S: u32 = 15;
pub const RTC_CNTL_TOUCH_START_FSM_EN_V: u32 = 1;
pub const RTC_CNTL_TOUCH_START_FSM_EN_S: u32 = 14;
pub const RTC_CNTL_TOUCH_SLP_TIMER_EN_V: u32 = 1;
pub const RTC_CNTL_TOUCH_SLP_TIMER_EN_S: u32 = 13;
pub const RTC_CNTL_TOUCH_DBIAS_V: u32 = 1;
pub const RTC_CNTL_TOUCH_DBIAS_S: u32 = 12;
pub const RTC_CNTL_TOUCH_REFC: u32 = 7;
pub const RTC_CNTL_TOUCH_REFC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_REFC_S: u32 = 9;
pub const RTC_CNTL_TOUCH_XPD_BIAS_V: u32 = 1;
pub const RTC_CNTL_TOUCH_XPD_BIAS_S: u32 = 8;
pub const RTC_CNTL_TOUCH_DREFH: u32 = 3;
pub const RTC_CNTL_TOUCH_DREFH_V: u32 = 3;
pub const RTC_CNTL_TOUCH_DREFH_S: u32 = 6;
pub const RTC_CNTL_TOUCH_DREFL: u32 = 3;
pub const RTC_CNTL_TOUCH_DREFL_V: u32 = 3;
pub const RTC_CNTL_TOUCH_DREFL_S: u32 = 4;
pub const RTC_CNTL_TOUCH_DRANGE: u32 = 3;
pub const RTC_CNTL_TOUCH_DRANGE_V: u32 = 3;
pub const RTC_CNTL_TOUCH_DRANGE_S: u32 = 2;
pub const RTC_CNTL_TOUCH_SCAN_CTRL_REG: u32 = 1610645776;
pub const RTC_CNTL_TOUCH_OUT_RING: u32 = 15;
pub const RTC_CNTL_TOUCH_OUT_RING_V: u32 = 15;
pub const RTC_CNTL_TOUCH_OUT_RING_S: u32 = 28;
pub const RTC_CNTL_TOUCH_BUFDRV: u32 = 7;
pub const RTC_CNTL_TOUCH_BUFDRV_V: u32 = 7;
pub const RTC_CNTL_TOUCH_BUFDRV_S: u32 = 25;
pub const RTC_CNTL_TOUCH_SCAN_PAD_MAP: u32 = 32767;
pub const RTC_CNTL_TOUCH_SCAN_PAD_MAP_V: u32 = 32767;
pub const RTC_CNTL_TOUCH_SCAN_PAD_MAP_S: u32 = 10;
pub const RTC_CNTL_TOUCH_SHIELD_PAD_EN_V: u32 = 1;
pub const RTC_CNTL_TOUCH_SHIELD_PAD_EN_S: u32 = 9;
pub const RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V: u32 = 1;
pub const RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S: u32 = 8;
pub const RTC_CNTL_TOUCH_DENOISE_EN_V: u32 = 1;
pub const RTC_CNTL_TOUCH_DENOISE_EN_S: u32 = 2;
pub const RTC_CNTL_TOUCH_DENOISE_RES: u32 = 3;
pub const RTC_CNTL_TOUCH_DENOISE_RES_V: u32 = 3;
pub const RTC_CNTL_TOUCH_DENOISE_RES_S: u32 = 0;
pub const RTC_CNTL_TOUCH_SLP_THRES_REG: u32 = 1610645780;
pub const RTC_CNTL_TOUCH_SLP_PAD: u32 = 31;
pub const RTC_CNTL_TOUCH_SLP_PAD_V: u32 = 31;
pub const RTC_CNTL_TOUCH_SLP_PAD_S: u32 = 27;
pub const RTC_CNTL_TOUCH_SLP_APPROACH_EN_V: u32 = 1;
pub const RTC_CNTL_TOUCH_SLP_APPROACH_EN_S: u32 = 26;
pub const RTC_CNTL_TOUCH_SLP_TH: u32 = 4194303;
pub const RTC_CNTL_TOUCH_SLP_TH_V: u32 = 4194303;
pub const RTC_CNTL_TOUCH_SLP_TH_S: u32 = 0;
pub const RTC_CNTL_TOUCH_APPROACH_REG: u32 = 1610645784;
pub const RTC_CNTL_TOUCH_APPROACH_MEAS_TIME: u32 = 255;
pub const RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V: u32 = 255;
pub const RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S: u32 = 24;
pub const RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V: u32 = 1;
pub const RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S: u32 = 23;
pub const RTC_CNTL_TOUCH_FILTER_CTRL_REG: u32 = 1610645788;
pub const RTC_CNTL_TOUCH_FILTER_EN_V: u32 = 1;
pub const RTC_CNTL_TOUCH_FILTER_EN_S: u32 = 31;
pub const RTC_CNTL_TOUCH_FILTER_MODE: u32 = 7;
pub const RTC_CNTL_TOUCH_FILTER_MODE_V: u32 = 7;
pub const RTC_CNTL_TOUCH_FILTER_MODE_S: u32 = 28;
pub const RTC_CNTL_TOUCH_DEBOUNCE: u32 = 7;
pub const RTC_CNTL_TOUCH_DEBOUNCE_V: u32 = 7;
pub const RTC_CNTL_TOUCH_DEBOUNCE_S: u32 = 25;
pub const RTC_CNTL_TOUCH_CONFIG3: u32 = 3;
pub const RTC_CNTL_TOUCH_CONFIG3_V: u32 = 3;
pub const RTC_CNTL_TOUCH_CONFIG3_S: u32 = 23;
pub const RTC_CNTL_TOUCH_NOISE_THRES: u32 = 3;
pub const RTC_CNTL_TOUCH_NOISE_THRES_V: u32 = 3;
pub const RTC_CNTL_TOUCH_NOISE_THRES_S: u32 = 21;
pub const RTC_CNTL_TOUCH_CONFIG2: u32 = 3;
pub const RTC_CNTL_TOUCH_CONFIG2_V: u32 = 3;
pub const RTC_CNTL_TOUCH_CONFIG2_S: u32 = 19;
pub const RTC_CNTL_TOUCH_CONFIG1: u32 = 15;
pub const RTC_CNTL_TOUCH_CONFIG1_V: u32 = 15;
pub const RTC_CNTL_TOUCH_CONFIG1_S: u32 = 15;
pub const RTC_CNTL_TOUCH_JITTER_STEP: u32 = 15;
pub const RTC_CNTL_TOUCH_JITTER_STEP_V: u32 = 15;
pub const RTC_CNTL_TOUCH_JITTER_STEP_S: u32 = 11;
pub const RTC_CNTL_TOUCH_SMOOTH_LVL: u32 = 3;
pub const RTC_CNTL_TOUCH_SMOOTH_LVL_V: u32 = 3;
pub const RTC_CNTL_TOUCH_SMOOTH_LVL_S: u32 = 9;
pub const RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V: u32 = 1;
pub const RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S: u32 = 8;
pub const RTC_CNTL_TOUCH_BYPASS_NEG_THRES_V: u32 = 1;
pub const RTC_CNTL_TOUCH_BYPASS_NEG_THRES_S: u32 = 7;
pub const RTC_CNTL_USB_CONF_REG: u32 = 1610645792;
pub const RTC_CNTL_SW_HW_USB_PHY_SEL_V: u32 = 1;
pub const RTC_CNTL_SW_HW_USB_PHY_SEL_S: u32 = 20;
pub const RTC_CNTL_SW_USB_PHY_SEL_V: u32 = 1;
pub const RTC_CNTL_SW_USB_PHY_SEL_S: u32 = 19;
pub const RTC_CNTL_IO_MUX_RESET_DISABLE_V: u32 = 1;
pub const RTC_CNTL_IO_MUX_RESET_DISABLE_S: u32 = 18;
pub const RTC_CNTL_USB_RESET_DISABLE_V: u32 = 1;
pub const RTC_CNTL_USB_RESET_DISABLE_S: u32 = 17;
pub const RTC_CNTL_USB_TX_EN_OVERRIDE_V: u32 = 1;
pub const RTC_CNTL_USB_TX_EN_OVERRIDE_S: u32 = 16;
pub const RTC_CNTL_USB_TX_EN_V: u32 = 1;
pub const RTC_CNTL_USB_TX_EN_S: u32 = 15;
pub const RTC_CNTL_USB_TXP_V: u32 = 1;
pub const RTC_CNTL_USB_TXP_S: u32 = 14;
pub const RTC_CNTL_USB_TXM_V: u32 = 1;
pub const RTC_CNTL_USB_TXM_S: u32 = 13;
pub const RTC_CNTL_USB_PAD_ENABLE_V: u32 = 1;
pub const RTC_CNTL_USB_PAD_ENABLE_S: u32 = 12;
pub const RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V: u32 = 1;
pub const RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S: u32 = 11;
pub const RTC_CNTL_USB_PULLUP_VALUE_V: u32 = 1;
pub const RTC_CNTL_USB_PULLUP_VALUE_S: u32 = 10;
pub const RTC_CNTL_USB_DM_PULLDOWN_V: u32 = 1;
pub const RTC_CNTL_USB_DM_PULLDOWN_S: u32 = 9;
pub const RTC_CNTL_USB_DM_PULLUP_V: u32 = 1;
pub const RTC_CNTL_USB_DM_PULLUP_S: u32 = 8;
pub const RTC_CNTL_USB_DP_PULLDOWN_V: u32 = 1;
pub const RTC_CNTL_USB_DP_PULLDOWN_S: u32 = 7;
pub const RTC_CNTL_USB_DP_PULLUP_V: u32 = 1;
pub const RTC_CNTL_USB_DP_PULLUP_S: u32 = 6;
pub const RTC_CNTL_USB_PAD_PULL_OVERRIDE_V: u32 = 1;
pub const RTC_CNTL_USB_PAD_PULL_OVERRIDE_S: u32 = 5;
pub const RTC_CNTL_USB_VREF_OVERRIDE_V: u32 = 1;
pub const RTC_CNTL_USB_VREF_OVERRIDE_S: u32 = 4;
pub const RTC_CNTL_USB_VREFL: u32 = 3;
pub const RTC_CNTL_USB_VREFL_V: u32 = 3;
pub const RTC_CNTL_USB_VREFL_S: u32 = 2;
pub const RTC_CNTL_USB_VREFH: u32 = 3;
pub const RTC_CNTL_USB_VREFH_V: u32 = 3;
pub const RTC_CNTL_USB_VREFH_S: u32 = 0;
pub const RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG: u32 = 1610645796;
pub const RTC_CNTL_TOUCH_TIMEOUT_EN_V: u32 = 1;
pub const RTC_CNTL_TOUCH_TIMEOUT_EN_S: u32 = 22;
pub const RTC_CNTL_TOUCH_TIMEOUT_NUM: u32 = 4194303;
pub const RTC_CNTL_TOUCH_TIMEOUT_NUM_V: u32 = 4194303;
pub const RTC_CNTL_TOUCH_TIMEOUT_NUM_S: u32 = 0;
pub const RTC_CNTL_SLP_REJECT_CAUSE_REG: u32 = 1610645800;
pub const RTC_CNTL_REJECT_CAUSE: u32 = 262143;
pub const RTC_CNTL_REJECT_CAUSE_V: u32 = 262143;
pub const RTC_CNTL_REJECT_CAUSE_S: u32 = 0;
pub const RTC_CNTL_OPTION1_REG: u32 = 1610645804;
pub const RTC_CNTL_FORCE_DOWNLOAD_BOOT_V: u32 = 1;
pub const RTC_CNTL_FORCE_DOWNLOAD_BOOT_S: u32 = 0;
pub const RTC_CNTL_SLP_WAKEUP_CAUSE_REG: u32 = 1610645808;
pub const RTC_CNTL_WAKEUP_CAUSE: u32 = 131071;
pub const RTC_CNTL_WAKEUP_CAUSE_V: u32 = 131071;
pub const RTC_CNTL_WAKEUP_CAUSE_S: u32 = 0;
pub const RTC_CNTL_ULP_CP_TIMER_1_REG: u32 = 1610645812;
pub const RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE: u32 = 16777215;
pub const RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V: u32 = 16777215;
pub const RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S: u32 = 8;
pub const RTC_CNTL_INT_ENA_W1TS_REG: u32 = 1610645816;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S: u32 = 20;
pub const RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S: u32 = 19;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S: u32 = 18;
pub const RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S: u32 = 17;
pub const RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S: u32 = 16;
pub const RTC_CNTL_SWD_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_SWD_INT_ENA_W1TS_S: u32 = 15;
pub const RTC_CNTL_SARADC2_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_SARADC2_INT_ENA_W1TS_S: u32 = 14;
pub const RTC_CNTL_COCPU_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_COCPU_INT_ENA_W1TS_S: u32 = 13;
pub const RTC_CNTL_TSENS_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_TSENS_INT_ENA_W1TS_S: u32 = 12;
pub const RTC_CNTL_SARADC1_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_SARADC1_INT_ENA_W1TS_S: u32 = 11;
pub const RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S: u32 = 10;
pub const RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S: u32 = 9;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S: u32 = 8;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S: u32 = 7;
pub const RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S: u32 = 6;
pub const RTC_CNTL_ULP_CP_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_INT_ENA_W1TS_S: u32 = 5;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S: u32 = 4;
pub const RTC_CNTL_WDT_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_WDT_INT_ENA_W1TS_S: u32 = 3;
pub const RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S: u32 = 2;
pub const RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S: u32 = 0;
pub const RTC_CNTL_INT_ENA_W1TC_REG: u32 = 1610645820;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S: u32 = 20;
pub const RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S: u32 = 19;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S: u32 = 18;
pub const RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S: u32 = 17;
pub const RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S: u32 = 16;
pub const RTC_CNTL_SWD_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_SWD_INT_ENA_W1TC_S: u32 = 15;
pub const RTC_CNTL_SARADC2_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_SARADC2_INT_ENA_W1TC_S: u32 = 14;
pub const RTC_CNTL_COCPU_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_COCPU_INT_ENA_W1TC_S: u32 = 13;
pub const RTC_CNTL_TSENS_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_TSENS_INT_ENA_W1TC_S: u32 = 12;
pub const RTC_CNTL_SARADC1_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_SARADC1_INT_ENA_W1TC_S: u32 = 11;
pub const RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S: u32 = 10;
pub const RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S: u32 = 9;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S: u32 = 8;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S: u32 = 7;
pub const RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S: u32 = 6;
pub const RTC_CNTL_ULP_CP_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_ULP_CP_INT_ENA_W1TC_S: u32 = 5;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S: u32 = 4;
pub const RTC_CNTL_WDT_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_WDT_INT_ENA_W1TC_S: u32 = 3;
pub const RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S: u32 = 2;
pub const RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V: u32 = 1;
pub const RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S: u32 = 0;
pub const RTC_CNTL_RETENTION_CTRL_REG: u32 = 1610645824;
pub const RTC_CNTL_RETENTION_WAIT: u32 = 127;
pub const RTC_CNTL_RETENTION_WAIT_V: u32 = 127;
pub const RTC_CNTL_RETENTION_WAIT_S: u32 = 25;
pub const RTC_CNTL_RETENTION_EN_V: u32 = 1;
pub const RTC_CNTL_RETENTION_EN_S: u32 = 24;
pub const RTC_CNTL_RETENTION_CLKOFF_WAIT: u32 = 15;
pub const RTC_CNTL_RETENTION_CLKOFF_WAIT_V: u32 = 15;
pub const RTC_CNTL_RETENTION_CLKOFF_WAIT_S: u32 = 20;
pub const RTC_CNTL_RETENTION_DONE_WAIT: u32 = 7;
pub const RTC_CNTL_RETENTION_DONE_WAIT_V: u32 = 7;
pub const RTC_CNTL_RETENTION_DONE_WAIT_S: u32 = 17;
pub const RTC_CNTL_RETENTION_CLK_SEL_V: u32 = 1;
pub const RTC_CNTL_RETENTION_CLK_SEL_S: u32 = 16;
pub const RTC_CNTL_RETENTION_TARGET: u32 = 3;
pub const RTC_CNTL_RETENTION_TARGET_V: u32 = 3;
pub const RTC_CNTL_RETENTION_TARGET_S: u32 = 14;
pub const RTC_CNTL_RETENTION_TAG_MODE: u32 = 15;
pub const RTC_CNTL_RETENTION_TAG_MODE_V: u32 = 15;
pub const RTC_CNTL_RETENTION_TAG_MODE_S: u32 = 10;
pub const RTC_CNTL_PG_CTRL_REG: u32 = 1610645828;
pub const RTC_CNTL_POWER_GLITCH_EN_V: u32 = 1;
pub const RTC_CNTL_POWER_GLITCH_EN_S: u32 = 31;
pub const RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V: u32 = 1;
pub const RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S: u32 = 30;
pub const RTC_CNTL_POWER_GLITCH_FORCE_PU_V: u32 = 1;
pub const RTC_CNTL_POWER_GLITCH_FORCE_PU_S: u32 = 29;
pub const RTC_CNTL_POWER_GLITCH_FORCE_PD_V: u32 = 1;
pub const RTC_CNTL_POWER_GLITCH_FORCE_PD_S: u32 = 28;
pub const RTC_CNTL_POWER_GLITCH_DSENSE: u32 = 3;
pub const RTC_CNTL_POWER_GLITCH_DSENSE_V: u32 = 3;
pub const RTC_CNTL_POWER_GLITCH_DSENSE_S: u32 = 26;
pub const RTC_CNTL_FIB_SEL_REG: u32 = 1610645832;
pub const RTC_CNTL_FIB_SEL: u32 = 7;
pub const RTC_CNTL_FIB_SEL_V: u32 = 7;
pub const RTC_CNTL_FIB_SEL_S: u32 = 0;
pub const RTC_CNTL_TOUCH_DAC_REG: u32 = 1610645836;
pub const RTC_CNTL_TOUCH_PAD0_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD0_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD0_DAC_S: u32 = 29;
pub const RTC_CNTL_TOUCH_PAD1_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD1_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD1_DAC_S: u32 = 26;
pub const RTC_CNTL_TOUCH_PAD2_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD2_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD2_DAC_S: u32 = 23;
pub const RTC_CNTL_TOUCH_PAD3_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD3_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD3_DAC_S: u32 = 20;
pub const RTC_CNTL_TOUCH_PAD4_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD4_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD4_DAC_S: u32 = 17;
pub const RTC_CNTL_TOUCH_PAD5_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD5_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD5_DAC_S: u32 = 14;
pub const RTC_CNTL_TOUCH_PAD6_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD6_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD6_DAC_S: u32 = 11;
pub const RTC_CNTL_TOUCH_PAD7_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD7_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD7_DAC_S: u32 = 8;
pub const RTC_CNTL_TOUCH_PAD8_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD8_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD8_DAC_S: u32 = 5;
pub const RTC_CNTL_TOUCH_PAD9_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD9_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD9_DAC_S: u32 = 2;
pub const RTC_CNTL_TOUCH_DAC1_REG: u32 = 1610645840;
pub const RTC_CNTL_TOUCH_PAD10_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD10_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD10_DAC_S: u32 = 29;
pub const RTC_CNTL_TOUCH_PAD11_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD11_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD11_DAC_S: u32 = 26;
pub const RTC_CNTL_TOUCH_PAD12_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD12_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD12_DAC_S: u32 = 23;
pub const RTC_CNTL_TOUCH_PAD13_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD13_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD13_DAC_S: u32 = 20;
pub const RTC_CNTL_TOUCH_PAD14_DAC: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD14_DAC_V: u32 = 7;
pub const RTC_CNTL_TOUCH_PAD14_DAC_S: u32 = 17;
pub const RTC_CNTL_COCPU_DISABLE_REG: u32 = 1610645844;
pub const RTC_CNTL_DISABLE_RTC_CPU_V: u32 = 1;
pub const RTC_CNTL_DISABLE_RTC_CPU_S: u32 = 31;
pub const RTC_CNTL_DATE_REG: u32 = 1610646012;
pub const RTC_CNTL_DATE: u32 = 268435455;
pub const RTC_CNTL_DATE_V: u32 = 268435455;
pub const RTC_CNTL_DATE_S: u32 = 0;
pub const TWAI_EXTD_ID_MASK: u32 = 536870911;
pub const TWAI_STD_ID_MASK: u32 = 2047;
pub const TWAI_FRAME_MAX_DLC: u32 = 8;
pub const TWAI_FRAME_EXTD_ID_LEN_BYTES: u32 = 4;
pub const TWAI_FRAME_STD_ID_LEN_BYTES: u32 = 2;
pub const TWAI_ERR_PASS_THRESH: u32 = 128;
pub const TWAI_MSG_FLAG_NONE: u32 = 0;
pub const TWAI_MSG_FLAG_EXTD: u32 = 1;
pub const TWAI_MSG_FLAG_RTR: u32 = 2;
pub const TWAI_MSG_FLAG_SS: u32 = 4;
pub const TWAI_MSG_FLAG_SELF: u32 = 8;
pub const TWAI_MSG_FLAG_DLC_NON_COMP: u32 = 16;
pub const TWAI_BRP_MAX: u32 = 16384;
pub const TWAI_BRP_MIN: u32 = 2;
pub const TWAI_ALERT_TX_IDLE: u32 = 1;
pub const TWAI_ALERT_TX_SUCCESS: u32 = 2;
pub const TWAI_ALERT_RX_DATA: u32 = 4;
pub const TWAI_ALERT_BELOW_ERR_WARN: u32 = 8;
pub const TWAI_ALERT_ERR_ACTIVE: u32 = 16;
pub const TWAI_ALERT_RECOVERY_IN_PROGRESS: u32 = 32;
pub const TWAI_ALERT_BUS_RECOVERED: u32 = 64;
pub const TWAI_ALERT_ARB_LOST: u32 = 128;
pub const TWAI_ALERT_ABOVE_ERR_WARN: u32 = 256;
pub const TWAI_ALERT_BUS_ERROR: u32 = 512;
pub const TWAI_ALERT_TX_FAILED: u32 = 1024;
pub const TWAI_ALERT_RX_QUEUE_FULL: u32 = 2048;
pub const TWAI_ALERT_ERR_PASS: u32 = 4096;
pub const TWAI_ALERT_BUS_OFF: u32 = 8192;
pub const TWAI_ALERT_RX_FIFO_OVERRUN: u32 = 16384;
pub const TWAI_ALERT_TX_RETRIED: u32 = 32768;
pub const TWAI_ALERT_PERIPH_RESET: u32 = 65536;
pub const TWAI_ALERT_ALL: u32 = 131071;
pub const TWAI_ALERT_NONE: u32 = 0;
pub const TWAI_ALERT_AND_LOG: u32 = 131072;
pub const I2C_CLK_FREQ_MAX: i32 = -1;
pub const I2C_APB_CLK_FREQ: u32 = 80000000;
pub const I2C_NUM_MAX: u32 = 2;
pub const I2C_NUM_0: u32 = 0;
pub const I2C_NUM_1: u32 = 1;
pub const I2C_SCLK_SRC_FLAG_FOR_NOMAL: u32 = 0;
pub const I2C_SCLK_SRC_FLAG_AWARE_DFS: u32 = 1;
pub const I2C_SCLK_SRC_FLAG_LIGHT_SLEEP: u32 = 2;
pub const I2C_INTERNAL_STRUCT_SIZE: u32 = 24;
pub const I2S_TX_HUNG_INT_RAW_V: u32 = 1;
pub const I2S_TX_HUNG_INT_RAW_S: u32 = 3;
pub const I2S_RX_HUNG_INT_RAW_V: u32 = 1;
pub const I2S_RX_HUNG_INT_RAW_S: u32 = 2;
pub const I2S_TX_DONE_INT_RAW_V: u32 = 1;
pub const I2S_TX_DONE_INT_RAW_S: u32 = 1;
pub const I2S_RX_DONE_INT_RAW_V: u32 = 1;
pub const I2S_RX_DONE_INT_RAW_S: u32 = 0;
pub const I2S_TX_HUNG_INT_ST_V: u32 = 1;
pub const I2S_TX_HUNG_INT_ST_S: u32 = 3;
pub const I2S_RX_HUNG_INT_ST_V: u32 = 1;
pub const I2S_RX_HUNG_INT_ST_S: u32 = 2;
pub const I2S_TX_DONE_INT_ST_V: u32 = 1;
pub const I2S_TX_DONE_INT_ST_S: u32 = 1;
pub const I2S_RX_DONE_INT_ST_V: u32 = 1;
pub const I2S_RX_DONE_INT_ST_S: u32 = 0;
pub const I2S_TX_HUNG_INT_ENA_V: u32 = 1;
pub const I2S_TX_HUNG_INT_ENA_S: u32 = 3;
pub const I2S_RX_HUNG_INT_ENA_V: u32 = 1;
pub const I2S_RX_HUNG_INT_ENA_S: u32 = 2;
pub const I2S_TX_DONE_INT_ENA_V: u32 = 1;
pub const I2S_TX_DONE_INT_ENA_S: u32 = 1;
pub const I2S_RX_DONE_INT_ENA_V: u32 = 1;
pub const I2S_RX_DONE_INT_ENA_S: u32 = 0;
pub const I2S_TX_HUNG_INT_CLR_V: u32 = 1;
pub const I2S_TX_HUNG_INT_CLR_S: u32 = 3;
pub const I2S_RX_HUNG_INT_CLR_V: u32 = 1;
pub const I2S_RX_HUNG_INT_CLR_S: u32 = 2;
pub const I2S_TX_DONE_INT_CLR_V: u32 = 1;
pub const I2S_TX_DONE_INT_CLR_S: u32 = 1;
pub const I2S_RX_DONE_INT_CLR_V: u32 = 1;
pub const I2S_RX_DONE_INT_CLR_S: u32 = 0;
pub const I2S_RX_PDM_SINC_DSR_16_EN_V: u32 = 1;
pub const I2S_RX_PDM_SINC_DSR_16_EN_S: u32 = 22;
pub const I2S_RX_PDM2PCM_EN_V: u32 = 1;
pub const I2S_RX_PDM2PCM_EN_S: u32 = 21;
pub const I2S_RX_PDM_EN_V: u32 = 1;
pub const I2S_RX_PDM_EN_S: u32 = 20;
pub const I2S_RX_TDM_EN_V: u32 = 1;
pub const I2S_RX_TDM_EN_S: u32 = 19;
pub const I2S_RX_BIT_ORDER_V: u32 = 1;
pub const I2S_RX_BIT_ORDER_S: u32 = 18;
pub const I2S_RX_WS_IDLE_POL_V: u32 = 1;
pub const I2S_RX_WS_IDLE_POL_S: u32 = 17;
pub const I2S_RX_24_FILL_EN_V: u32 = 1;
pub const I2S_RX_24_FILL_EN_S: u32 = 16;
pub const I2S_RX_LEFT_ALIGN_V: u32 = 1;
pub const I2S_RX_LEFT_ALIGN_S: u32 = 15;
pub const I2S_RX_STOP_MODE: u32 = 3;
pub const I2S_RX_STOP_MODE_V: u32 = 3;
pub const I2S_RX_STOP_MODE_S: u32 = 13;
pub const I2S_RX_PCM_BYPASS_V: u32 = 1;
pub const I2S_RX_PCM_BYPASS_S: u32 = 12;
pub const I2S_RX_PCM_CONF: u32 = 3;
pub const I2S_RX_PCM_CONF_V: u32 = 3;
pub const I2S_RX_PCM_CONF_S: u32 = 10;
pub const I2S_RX_MONO_FST_VLD_V: u32 = 1;
pub const I2S_RX_MONO_FST_VLD_S: u32 = 9;
pub const I2S_RX_UPDATE_V: u32 = 1;
pub const I2S_RX_UPDATE_S: u32 = 8;
pub const I2S_RX_BIG_ENDIAN_V: u32 = 1;
pub const I2S_RX_BIG_ENDIAN_S: u32 = 7;
pub const I2S_RX_MONO_V: u32 = 1;
pub const I2S_RX_MONO_S: u32 = 5;
pub const I2S_RX_SLAVE_MOD_V: u32 = 1;
pub const I2S_RX_SLAVE_MOD_S: u32 = 3;
pub const I2S_RX_START_V: u32 = 1;
pub const I2S_RX_START_S: u32 = 2;
pub const I2S_RX_FIFO_RESET_V: u32 = 1;
pub const I2S_RX_FIFO_RESET_S: u32 = 1;
pub const I2S_RX_RESET_V: u32 = 1;
pub const I2S_RX_RESET_S: u32 = 0;
pub const I2S_SIG_LOOPBACK_V: u32 = 1;
pub const I2S_SIG_LOOPBACK_S: u32 = 27;
pub const I2S_TX_CHAN_MOD: u32 = 7;
pub const I2S_TX_CHAN_MOD_V: u32 = 7;
pub const I2S_TX_CHAN_MOD_S: u32 = 24;
pub const I2S_TX_PDM_EN_V: u32 = 1;
pub const I2S_TX_PDM_EN_S: u32 = 20;
pub const I2S_TX_TDM_EN_V: u32 = 1;
pub const I2S_TX_TDM_EN_S: u32 = 19;
pub const I2S_TX_BIT_ORDER_V: u32 = 1;
pub const I2S_TX_BIT_ORDER_S: u32 = 18;
pub const I2S_TX_WS_IDLE_POL_V: u32 = 1;
pub const I2S_TX_WS_IDLE_POL_S: u32 = 17;
pub const I2S_TX_24_FILL_EN_V: u32 = 1;
pub const I2S_TX_24_FILL_EN_S: u32 = 16;
pub const I2S_TX_LEFT_ALIGN_V: u32 = 1;
pub const I2S_TX_LEFT_ALIGN_S: u32 = 15;
pub const I2S_TX_STOP_EN_V: u32 = 1;
pub const I2S_TX_STOP_EN_S: u32 = 13;
pub const I2S_TX_PCM_BYPASS_V: u32 = 1;
pub const I2S_TX_PCM_BYPASS_S: u32 = 12;
pub const I2S_TX_PCM_CONF: u32 = 3;
pub const I2S_TX_PCM_CONF_V: u32 = 3;
pub const I2S_TX_PCM_CONF_S: u32 = 10;
pub const I2S_TX_MONO_FST_VLD_V: u32 = 1;
pub const I2S_TX_MONO_FST_VLD_S: u32 = 9;
pub const I2S_TX_UPDATE_V: u32 = 1;
pub const I2S_TX_UPDATE_S: u32 = 8;
pub const I2S_TX_BIG_ENDIAN_V: u32 = 1;
pub const I2S_TX_BIG_ENDIAN_S: u32 = 7;
pub const I2S_TX_CHAN_EQUAL_V: u32 = 1;
pub const I2S_TX_CHAN_EQUAL_S: u32 = 6;
pub const I2S_TX_MONO_V: u32 = 1;
pub const I2S_TX_MONO_S: u32 = 5;
pub const I2S_TX_SLAVE_MOD_V: u32 = 1;
pub const I2S_TX_SLAVE_MOD_S: u32 = 3;
pub const I2S_TX_START_V: u32 = 1;
pub const I2S_TX_START_S: u32 = 2;
pub const I2S_TX_FIFO_RESET_V: u32 = 1;
pub const I2S_TX_FIFO_RESET_S: u32 = 1;
pub const I2S_TX_RESET_V: u32 = 1;
pub const I2S_TX_RESET_S: u32 = 0;
pub const I2S_RX_MSB_SHIFT_V: u32 = 1;
pub const I2S_RX_MSB_SHIFT_S: u32 = 29;
pub const I2S_RX_TDM_CHAN_BITS: u32 = 31;
pub const I2S_RX_TDM_CHAN_BITS_V: u32 = 31;
pub const I2S_RX_TDM_CHAN_BITS_S: u32 = 24;
pub const I2S_RX_HALF_SAMPLE_BITS: u32 = 63;
pub const I2S_RX_HALF_SAMPLE_BITS_V: u32 = 63;
pub const I2S_RX_HALF_SAMPLE_BITS_S: u32 = 18;
pub const I2S_RX_BITS_MOD: u32 = 31;
pub const I2S_RX_BITS_MOD_V: u32 = 31;
pub const I2S_RX_BITS_MOD_S: u32 = 13;
pub const I2S_RX_BCK_DIV_NUM: u32 = 63;
pub const I2S_RX_BCK_DIV_NUM_V: u32 = 63;
pub const I2S_RX_BCK_DIV_NUM_S: u32 = 7;
pub const I2S_RX_TDM_WS_WIDTH: u32 = 127;
pub const I2S_RX_TDM_WS_WIDTH_V: u32 = 127;
pub const I2S_RX_TDM_WS_WIDTH_S: u32 = 0;
pub const I2S_TX_BCK_NO_DLY_V: u32 = 1;
pub const I2S_TX_BCK_NO_DLY_S: u32 = 30;
pub const I2S_TX_MSB_SHIFT_V: u32 = 1;
pub const I2S_TX_MSB_SHIFT_S: u32 = 29;
pub const I2S_TX_TDM_CHAN_BITS: u32 = 31;
pub const I2S_TX_TDM_CHAN_BITS_V: u32 = 31;
pub const I2S_TX_TDM_CHAN_BITS_S: u32 = 24;
pub const I2S_TX_HALF_SAMPLE_BITS: u32 = 63;
pub const I2S_TX_HALF_SAMPLE_BITS_V: u32 = 63;
pub const I2S_TX_HALF_SAMPLE_BITS_S: u32 = 18;
pub const I2S_TX_BITS_MOD: u32 = 31;
pub const I2S_TX_BITS_MOD_V: u32 = 31;
pub const I2S_TX_BITS_MOD_S: u32 = 13;
pub const I2S_TX_BCK_DIV_NUM: u32 = 63;
pub const I2S_TX_BCK_DIV_NUM_V: u32 = 63;
pub const I2S_TX_BCK_DIV_NUM_S: u32 = 7;
pub const I2S_TX_TDM_WS_WIDTH: u32 = 127;
pub const I2S_TX_TDM_WS_WIDTH_V: u32 = 127;
pub const I2S_TX_TDM_WS_WIDTH_S: u32 = 0;
pub const I2S_MCLK_SEL_V: u32 = 1;
pub const I2S_MCLK_SEL_S: u32 = 29;
pub const I2S_RX_CLK_SEL: u32 = 3;
pub const I2S_RX_CLK_SEL_V: u32 = 3;
pub const I2S_RX_CLK_SEL_S: u32 = 27;
pub const I2S_RX_CLK_ACTIVE_V: u32 = 1;
pub const I2S_RX_CLK_ACTIVE_S: u32 = 26;
pub const I2S_RX_CLKM_DIV_NUM: u32 = 255;
pub const I2S_RX_CLKM_DIV_NUM_V: u32 = 255;
pub const I2S_RX_CLKM_DIV_NUM_S: u32 = 0;
pub const I2S_CLK_EN_V: u32 = 1;
pub const I2S_CLK_EN_S: u32 = 29;
pub const I2S_TX_CLK_SEL: u32 = 3;
pub const I2S_TX_CLK_SEL_V: u32 = 3;
pub const I2S_TX_CLK_SEL_S: u32 = 27;
pub const I2S_TX_CLK_ACTIVE_V: u32 = 1;
pub const I2S_TX_CLK_ACTIVE_S: u32 = 26;
pub const I2S_TX_CLKM_DIV_NUM: u32 = 255;
pub const I2S_TX_CLKM_DIV_NUM_V: u32 = 255;
pub const I2S_TX_CLKM_DIV_NUM_S: u32 = 0;
pub const I2S_RX_CLKM_DIV_YN1_V: u32 = 1;
pub const I2S_RX_CLKM_DIV_YN1_S: u32 = 27;
pub const I2S_RX_CLKM_DIV_X: u32 = 511;
pub const I2S_RX_CLKM_DIV_X_V: u32 = 511;
pub const I2S_RX_CLKM_DIV_X_S: u32 = 18;
pub const I2S_RX_CLKM_DIV_Y: u32 = 511;
pub const I2S_RX_CLKM_DIV_Y_V: u32 = 511;
pub const I2S_RX_CLKM_DIV_Y_S: u32 = 9;
pub const I2S_RX_CLKM_DIV_Z: u32 = 511;
pub const I2S_RX_CLKM_DIV_Z_V: u32 = 511;
pub const I2S_RX_CLKM_DIV_Z_S: u32 = 0;
pub const I2S_TX_CLKM_DIV_YN1_V: u32 = 1;
pub const I2S_TX_CLKM_DIV_YN1_S: u32 = 27;
pub const I2S_TX_CLKM_DIV_X: u32 = 511;
pub const I2S_TX_CLKM_DIV_X_V: u32 = 511;
pub const I2S_TX_CLKM_DIV_X_S: u32 = 18;
pub const I2S_TX_CLKM_DIV_Y: u32 = 511;
pub const I2S_TX_CLKM_DIV_Y_V: u32 = 511;
pub const I2S_TX_CLKM_DIV_Y_S: u32 = 9;
pub const I2S_TX_CLKM_DIV_Z: u32 = 511;
pub const I2S_TX_CLKM_DIV_Z_V: u32 = 511;
pub const I2S_TX_CLKM_DIV_Z_S: u32 = 0;
pub const I2S_PCM2PDM_CONV_EN_V: u32 = 1;
pub const I2S_PCM2PDM_CONV_EN_S: u32 = 25;
pub const I2S_TX_PDM_DAC_MODE_EN_V: u32 = 1;
pub const I2S_TX_PDM_DAC_MODE_EN_S: u32 = 24;
pub const I2S_TX_PDM_DAC_2OUT_EN_V: u32 = 1;
pub const I2S_TX_PDM_DAC_2OUT_EN_S: u32 = 23;
pub const I2S_TX_PDM_SIGMADELTA_DITHER_V: u32 = 1;
pub const I2S_TX_PDM_SIGMADELTA_DITHER_S: u32 = 22;
pub const I2S_TX_PDM_SIGMADELTA_DITHER2_V: u32 = 1;
pub const I2S_TX_PDM_SIGMADELTA_DITHER2_S: u32 = 21;
pub const I2S_TX_PDM_SIGMADELTA_IN_SHIFT: u32 = 3;
pub const I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V: u32 = 3;
pub const I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S: u32 = 19;
pub const I2S_TX_PDM_SINC_IN_SHIFT: u32 = 3;
pub const I2S_TX_PDM_SINC_IN_SHIFT_V: u32 = 3;
pub const I2S_TX_PDM_SINC_IN_SHIFT_S: u32 = 17;
pub const I2S_TX_PDM_LP_IN_SHIFT: u32 = 3;
pub const I2S_TX_PDM_LP_IN_SHIFT_V: u32 = 3;
pub const I2S_TX_PDM_LP_IN_SHIFT_S: u32 = 15;
pub const I2S_TX_PDM_HP_IN_SHIFT: u32 = 3;
pub const I2S_TX_PDM_HP_IN_SHIFT_V: u32 = 3;
pub const I2S_TX_PDM_HP_IN_SHIFT_S: u32 = 13;
pub const I2S_TX_PDM_PRESCALE: u32 = 255;
pub const I2S_TX_PDM_PRESCALE_V: u32 = 255;
pub const I2S_TX_PDM_PRESCALE_S: u32 = 5;
pub const I2S_TX_PDM_SINC_OSR2: u32 = 15;
pub const I2S_TX_PDM_SINC_OSR2_V: u32 = 15;
pub const I2S_TX_PDM_SINC_OSR2_S: u32 = 1;
pub const I2S_TX_PDM_HP_BYPASS_V: u32 = 1;
pub const I2S_TX_PDM_HP_BYPASS_S: u32 = 0;
pub const I2S_TX_IIR_HP_MULT12_0: u32 = 7;
pub const I2S_TX_IIR_HP_MULT12_0_V: u32 = 7;
pub const I2S_TX_IIR_HP_MULT12_0_S: u32 = 23;
pub const I2S_TX_IIR_HP_MULT12_5: u32 = 7;
pub const I2S_TX_IIR_HP_MULT12_5_V: u32 = 7;
pub const I2S_TX_IIR_HP_MULT12_5_S: u32 = 20;
pub const I2S_TX_PDM_FS: u32 = 1023;
pub const I2S_TX_PDM_FS_V: u32 = 1023;
pub const I2S_TX_PDM_FS_S: u32 = 10;
pub const I2S_TX_PDM_FP: u32 = 1023;
pub const I2S_TX_PDM_FP_V: u32 = 1023;
pub const I2S_TX_PDM_FP_S: u32 = 0;
pub const I2S_RX_TDM_TOT_CHAN_NUM: u32 = 15;
pub const I2S_RX_TDM_TOT_CHAN_NUM_V: u32 = 15;
pub const I2S_RX_TDM_TOT_CHAN_NUM_S: u32 = 16;
pub const I2S_RX_TDM_CHAN15_EN_V: u32 = 1;
pub const I2S_RX_TDM_CHAN15_EN_S: u32 = 15;
pub const I2S_RX_TDM_CHAN14_EN_V: u32 = 1;
pub const I2S_RX_TDM_CHAN14_EN_S: u32 = 14;
pub const I2S_RX_TDM_CHAN13_EN_V: u32 = 1;
pub const I2S_RX_TDM_CHAN13_EN_S: u32 = 13;
pub const I2S_RX_TDM_CHAN12_EN_V: u32 = 1;
pub const I2S_RX_TDM_CHAN12_EN_S: u32 = 12;
pub const I2S_RX_TDM_CHAN11_EN_V: u32 = 1;
pub const I2S_RX_TDM_CHAN11_EN_S: u32 = 11;
pub const I2S_RX_TDM_CHAN10_EN_V: u32 = 1;
pub const I2S_RX_TDM_CHAN10_EN_S: u32 = 10;
pub const I2S_RX_TDM_CHAN9_EN_V: u32 = 1;
pub const I2S_RX_TDM_CHAN9_EN_S: u32 = 9;
pub const I2S_RX_TDM_CHAN8_EN_V: u32 = 1;
pub const I2S_RX_TDM_CHAN8_EN_S: u32 = 8;
pub const I2S_RX_TDM_PDM_CHAN7_EN_V: u32 = 1;
pub const I2S_RX_TDM_PDM_CHAN7_EN_S: u32 = 7;
pub const I2S_RX_TDM_PDM_CHAN6_EN_V: u32 = 1;
pub const I2S_RX_TDM_PDM_CHAN6_EN_S: u32 = 6;
pub const I2S_RX_TDM_PDM_CHAN5_EN_V: u32 = 1;
pub const I2S_RX_TDM_PDM_CHAN5_EN_S: u32 = 5;
pub const I2S_RX_TDM_PDM_CHAN4_EN_V: u32 = 1;
pub const I2S_RX_TDM_PDM_CHAN4_EN_S: u32 = 4;
pub const I2S_RX_TDM_PDM_CHAN3_EN_V: u32 = 1;
pub const I2S_RX_TDM_PDM_CHAN3_EN_S: u32 = 3;
pub const I2S_RX_TDM_PDM_CHAN2_EN_V: u32 = 1;
pub const I2S_RX_TDM_PDM_CHAN2_EN_S: u32 = 2;
pub const I2S_RX_TDM_PDM_CHAN1_EN_V: u32 = 1;
pub const I2S_RX_TDM_PDM_CHAN1_EN_S: u32 = 1;
pub const I2S_RX_TDM_PDM_CHAN0_EN_V: u32 = 1;
pub const I2S_RX_TDM_PDM_CHAN0_EN_S: u32 = 0;
pub const I2S_TX_TDM_SKIP_MSK_EN_V: u32 = 1;
pub const I2S_TX_TDM_SKIP_MSK_EN_S: u32 = 20;
pub const I2S_TX_TDM_TOT_CHAN_NUM: u32 = 15;
pub const I2S_TX_TDM_TOT_CHAN_NUM_V: u32 = 15;
pub const I2S_TX_TDM_TOT_CHAN_NUM_S: u32 = 16;
pub const I2S_TX_TDM_CHAN15_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN15_EN_S: u32 = 15;
pub const I2S_TX_TDM_CHAN14_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN14_EN_S: u32 = 14;
pub const I2S_TX_TDM_CHAN13_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN13_EN_S: u32 = 13;
pub const I2S_TX_TDM_CHAN12_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN12_EN_S: u32 = 12;
pub const I2S_TX_TDM_CHAN11_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN11_EN_S: u32 = 11;
pub const I2S_TX_TDM_CHAN10_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN10_EN_S: u32 = 10;
pub const I2S_TX_TDM_CHAN9_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN9_EN_S: u32 = 9;
pub const I2S_TX_TDM_CHAN8_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN8_EN_S: u32 = 8;
pub const I2S_TX_TDM_CHAN7_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN7_EN_S: u32 = 7;
pub const I2S_TX_TDM_CHAN6_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN6_EN_S: u32 = 6;
pub const I2S_TX_TDM_CHAN5_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN5_EN_S: u32 = 5;
pub const I2S_TX_TDM_CHAN4_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN4_EN_S: u32 = 4;
pub const I2S_TX_TDM_CHAN3_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN3_EN_S: u32 = 3;
pub const I2S_TX_TDM_CHAN2_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN2_EN_S: u32 = 2;
pub const I2S_TX_TDM_CHAN1_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN1_EN_S: u32 = 1;
pub const I2S_TX_TDM_CHAN0_EN_V: u32 = 1;
pub const I2S_TX_TDM_CHAN0_EN_S: u32 = 0;
pub const I2S_RX_BCK_IN_DM: u32 = 3;
pub const I2S_RX_BCK_IN_DM_V: u32 = 3;
pub const I2S_RX_BCK_IN_DM_S: u32 = 28;
pub const I2S_RX_WS_IN_DM: u32 = 3;
pub const I2S_RX_WS_IN_DM_V: u32 = 3;
pub const I2S_RX_WS_IN_DM_S: u32 = 24;
pub const I2S_RX_BCK_OUT_DM: u32 = 3;
pub const I2S_RX_BCK_OUT_DM_V: u32 = 3;
pub const I2S_RX_BCK_OUT_DM_S: u32 = 20;
pub const I2S_RX_WS_OUT_DM: u32 = 3;
pub const I2S_RX_WS_OUT_DM_V: u32 = 3;
pub const I2S_RX_WS_OUT_DM_S: u32 = 16;
pub const I2S_RX_SD3_IN_DM: u32 = 3;
pub const I2S_RX_SD3_IN_DM_V: u32 = 3;
pub const I2S_RX_SD3_IN_DM_S: u32 = 12;
pub const I2S_RX_SD2_IN_DM: u32 = 3;
pub const I2S_RX_SD2_IN_DM_V: u32 = 3;
pub const I2S_RX_SD2_IN_DM_S: u32 = 8;
pub const I2S_RX_SD1_IN_DM: u32 = 3;
pub const I2S_RX_SD1_IN_DM_V: u32 = 3;
pub const I2S_RX_SD1_IN_DM_S: u32 = 4;
pub const I2S_RX_SD_IN_DM: u32 = 3;
pub const I2S_RX_SD_IN_DM_V: u32 = 3;
pub const I2S_RX_SD_IN_DM_S: u32 = 0;
pub const I2S_TX_BCK_IN_DM: u32 = 3;
pub const I2S_TX_BCK_IN_DM_V: u32 = 3;
pub const I2S_TX_BCK_IN_DM_S: u32 = 28;
pub const I2S_TX_WS_IN_DM: u32 = 3;
pub const I2S_TX_WS_IN_DM_V: u32 = 3;
pub const I2S_TX_WS_IN_DM_S: u32 = 24;
pub const I2S_TX_BCK_OUT_DM: u32 = 3;
pub const I2S_TX_BCK_OUT_DM_V: u32 = 3;
pub const I2S_TX_BCK_OUT_DM_S: u32 = 20;
pub const I2S_TX_WS_OUT_DM: u32 = 3;
pub const I2S_TX_WS_OUT_DM_V: u32 = 3;
pub const I2S_TX_WS_OUT_DM_S: u32 = 16;
pub const I2S_TX_SD1_OUT_DM: u32 = 3;
pub const I2S_TX_SD1_OUT_DM_V: u32 = 3;
pub const I2S_TX_SD1_OUT_DM_S: u32 = 4;
pub const I2S_TX_SD_OUT_DM: u32 = 3;
pub const I2S_TX_SD_OUT_DM_V: u32 = 3;
pub const I2S_TX_SD_OUT_DM_S: u32 = 0;
pub const I2S_LC_FIFO_TIMEOUT_ENA_V: u32 = 1;
pub const I2S_LC_FIFO_TIMEOUT_ENA_S: u32 = 11;
pub const I2S_LC_FIFO_TIMEOUT_SHIFT: u32 = 7;
pub const I2S_LC_FIFO_TIMEOUT_SHIFT_V: u32 = 7;
pub const I2S_LC_FIFO_TIMEOUT_SHIFT_S: u32 = 8;
pub const I2S_LC_FIFO_TIMEOUT: u32 = 255;
pub const I2S_LC_FIFO_TIMEOUT_V: u32 = 255;
pub const I2S_LC_FIFO_TIMEOUT_S: u32 = 0;
pub const I2S_RX_EOF_NUM: u32 = 4095;
pub const I2S_RX_EOF_NUM_V: u32 = 4095;
pub const I2S_RX_EOF_NUM_S: u32 = 0;
pub const I2S_SINGLE_DATA: u32 = 4294967295;
pub const I2S_SINGLE_DATA_V: u32 = 4294967295;
pub const I2S_SINGLE_DATA_S: u32 = 0;
pub const I2S_TX_IDLE_V: u32 = 1;
pub const I2S_TX_IDLE_S: u32 = 0;
pub const I2S_DATE: u32 = 268435455;
pub const I2S_DATE_V: u32 = 268435455;
pub const I2S_DATE_S: u32 = 0;
pub const I2S_PIN_NO_CHANGE: i32 = -1;
pub const LEDC_APB_CLK_HZ: u32 = 80000000;
pub const LEDC_REF_CLK_HZ: u32 = 1000000;
pub const LEDC_ERR_DUTY: u32 = 4294967295;
pub const LEDC_ERR_VAL: i32 = -1;
pub const PCNT_PIN_NOT_USED: i32 = -1;
pub const PCNT_MODE_MAX: u32 = 3;
pub const PCNT_COUNT_MAX: u32 = 3;
pub const RMT_CHANNEL_FLAGS_AWARE_DFS: u32 = 1;
pub const RMT_CHANNEL_FLAGS_INVERT_SIG: u32 = 2;
pub const RMT_CHANNEL_FLAGS_ALWAYS_ON: u32 = 1;
pub const RMT_MEM_ITEM_NUM: u32 = 48;
pub const SDMMC_HOST_SLOT_0: u32 = 0;
pub const SDMMC_HOST_SLOT_1: u32 = 1;
pub const SDMMC_SLOT_WIDTH_DEFAULT: u32 = 0;
pub const GPIO_SIGMADELTA0_REG: u32 = 1610632960;
pub const GPIO_SD0_PRESCALE: u32 = 255;
pub const GPIO_SD0_PRESCALE_V: u32 = 255;
pub const GPIO_SD0_PRESCALE_S: u32 = 8;
pub const GPIO_SD0_IN: u32 = 255;
pub const GPIO_SD0_IN_V: u32 = 255;
pub const GPIO_SD0_IN_S: u32 = 0;
pub const GPIO_SIGMADELTA1_REG: u32 = 1610632964;
pub const GPIO_SD1_PRESCALE: u32 = 255;
pub const GPIO_SD1_PRESCALE_V: u32 = 255;
pub const GPIO_SD1_PRESCALE_S: u32 = 8;
pub const GPIO_SD1_IN: u32 = 255;
pub const GPIO_SD1_IN_V: u32 = 255;
pub const GPIO_SD1_IN_S: u32 = 0;
pub const GPIO_SIGMADELTA2_REG: u32 = 1610632968;
pub const GPIO_SD2_PRESCALE: u32 = 255;
pub const GPIO_SD2_PRESCALE_V: u32 = 255;
pub const GPIO_SD2_PRESCALE_S: u32 = 8;
pub const GPIO_SD2_IN: u32 = 255;
pub const GPIO_SD2_IN_V: u32 = 255;
pub const GPIO_SD2_IN_S: u32 = 0;
pub const GPIO_SIGMADELTA3_REG: u32 = 1610632972;
pub const GPIO_SD3_PRESCALE: u32 = 255;
pub const GPIO_SD3_PRESCALE_V: u32 = 255;
pub const GPIO_SD3_PRESCALE_S: u32 = 8;
pub const GPIO_SD3_IN: u32 = 255;
pub const GPIO_SD3_IN_V: u32 = 255;
pub const GPIO_SD3_IN_S: u32 = 0;
pub const GPIO_SIGMADELTA4_REG: u32 = 1610632976;
pub const GPIO_SD4_PRESCALE: u32 = 255;
pub const GPIO_SD4_PRESCALE_V: u32 = 255;
pub const GPIO_SD4_PRESCALE_S: u32 = 8;
pub const GPIO_SD4_IN: u32 = 255;
pub const GPIO_SD4_IN_V: u32 = 255;
pub const GPIO_SD4_IN_S: u32 = 0;
pub const GPIO_SIGMADELTA5_REG: u32 = 1610632980;
pub const GPIO_SD5_PRESCALE: u32 = 255;
pub const GPIO_SD5_PRESCALE_V: u32 = 255;
pub const GPIO_SD5_PRESCALE_S: u32 = 8;
pub const GPIO_SD5_IN: u32 = 255;
pub const GPIO_SD5_IN_V: u32 = 255;
pub const GPIO_SD5_IN_S: u32 = 0;
pub const GPIO_SIGMADELTA6_REG: u32 = 1610632984;
pub const GPIO_SD6_PRESCALE: u32 = 255;
pub const GPIO_SD6_PRESCALE_V: u32 = 255;
pub const GPIO_SD6_PRESCALE_S: u32 = 8;
pub const GPIO_SD6_IN: u32 = 255;
pub const GPIO_SD6_IN_V: u32 = 255;
pub const GPIO_SD6_IN_S: u32 = 0;
pub const GPIO_SIGMADELTA7_REG: u32 = 1610632988;
pub const GPIO_SD7_PRESCALE: u32 = 255;
pub const GPIO_SD7_PRESCALE_V: u32 = 255;
pub const GPIO_SD7_PRESCALE_S: u32 = 8;
pub const GPIO_SD7_IN: u32 = 255;
pub const GPIO_SD7_IN_V: u32 = 255;
pub const GPIO_SD7_IN_S: u32 = 0;
pub const GPIO_SIGMADELTA_CG_REG: u32 = 1610632992;
pub const GPIO_SD_CLK_EN_V: u32 = 1;
pub const GPIO_SD_CLK_EN_S: u32 = 31;
pub const GPIO_SIGMADELTA_MISC_REG: u32 = 1610632996;
pub const GPIO_SPI_SWAP_V: u32 = 1;
pub const GPIO_SPI_SWAP_S: u32 = 31;
pub const GPIO_FUNCTION_CLK_EN_V: u32 = 1;
pub const GPIO_FUNCTION_CLK_EN_S: u32 = 30;
pub const GPIO_SIGMADELTA_VERSION_REG: u32 = 1610633000;
pub const GPIO_SD_DATE: u32 = 268435455;
pub const GPIO_SD_DATE_V: u32 = 268435455;
pub const GPIO_SD_DATE_S: u32 = 0;
pub const SPI_SLAVE_TXBIT_LSBFIRST: u32 = 1;
pub const SPI_SLAVE_RXBIT_LSBFIRST: u32 = 2;
pub const SPI_SLAVE_BIT_LSBFIRST: u32 = 3;
pub const TIMG_T0_USE_XTAL_V: u32 = 1;
pub const TIMG_T0_USE_XTAL_S: u32 = 9;
pub const TIMG_T0_ALARM_EN_V: u32 = 1;
pub const TIMG_T0_ALARM_EN_S: u32 = 10;
pub const TIMG_T0_DIVIDER: u32 = 65535;
pub const TIMG_T0_DIVIDER_V: u32 = 65535;
pub const TIMG_T0_DIVIDER_S: u32 = 13;
pub const TIMG_T0_AUTORELOAD_V: u32 = 1;
pub const TIMG_T0_AUTORELOAD_S: u32 = 29;
pub const TIMG_T0_INCREASE_V: u32 = 1;
pub const TIMG_T0_INCREASE_S: u32 = 30;
pub const TIMG_T0_EN_V: u32 = 1;
pub const TIMG_T0_EN_S: u32 = 31;
pub const TIMG_T0_LO: u32 = 4294967295;
pub const TIMG_T0_LO_V: u32 = 4294967295;
pub const TIMG_T0_LO_S: u32 = 0;
pub const TIMG_T0_HI: u32 = 4194303;
pub const TIMG_T0_HI_V: u32 = 4194303;
pub const TIMG_T0_HI_S: u32 = 0;
pub const TIMG_T0_UPDATE_V: u32 = 1;
pub const TIMG_T0_UPDATE_S: u32 = 31;
pub const TIMG_T0_ALARM_LO: u32 = 4294967295;
pub const TIMG_T0_ALARM_LO_V: u32 = 4294967295;
pub const TIMG_T0_ALARM_LO_S: u32 = 0;
pub const TIMG_T0_ALARM_HI: u32 = 4194303;
pub const TIMG_T0_ALARM_HI_V: u32 = 4194303;
pub const TIMG_T0_ALARM_HI_S: u32 = 0;
pub const TIMG_T0_LOAD_LO: u32 = 4294967295;
pub const TIMG_T0_LOAD_LO_V: u32 = 4294967295;
pub const TIMG_T0_LOAD_LO_S: u32 = 0;
pub const TIMG_T0_LOAD_HI: u32 = 4194303;
pub const TIMG_T0_LOAD_HI_V: u32 = 4194303;
pub const TIMG_T0_LOAD_HI_S: u32 = 0;
pub const TIMG_T0_LOAD: u32 = 4294967295;
pub const TIMG_T0_LOAD_V: u32 = 4294967295;
pub const TIMG_T0_LOAD_S: u32 = 0;
pub const TIMG_T1_USE_XTAL_V: u32 = 1;
pub const TIMG_T1_USE_XTAL_S: u32 = 9;
pub const TIMG_T1_ALARM_EN_V: u32 = 1;
pub const TIMG_T1_ALARM_EN_S: u32 = 10;
pub const TIMG_T1_DIVIDER: u32 = 65535;
pub const TIMG_T1_DIVIDER_V: u32 = 65535;
pub const TIMG_T1_DIVIDER_S: u32 = 13;
pub const TIMG_T1_AUTORELOAD_V: u32 = 1;
pub const TIMG_T1_AUTORELOAD_S: u32 = 29;
pub const TIMG_T1_INCREASE_V: u32 = 1;
pub const TIMG_T1_INCREASE_S: u32 = 30;
pub const TIMG_T1_EN_V: u32 = 1;
pub const TIMG_T1_EN_S: u32 = 31;
pub const TIMG_T1_LO: u32 = 4294967295;
pub const TIMG_T1_LO_V: u32 = 4294967295;
pub const TIMG_T1_LO_S: u32 = 0;
pub const TIMG_T1_HI: u32 = 4194303;
pub const TIMG_T1_HI_V: u32 = 4194303;
pub const TIMG_T1_HI_S: u32 = 0;
pub const TIMG_T1_UPDATE_V: u32 = 1;
pub const TIMG_T1_UPDATE_S: u32 = 31;
pub const TIMG_T1_ALARM_LO: u32 = 4294967295;
pub const TIMG_T1_ALARM_LO_V: u32 = 4294967295;
pub const TIMG_T1_ALARM_LO_S: u32 = 0;
pub const TIMG_T1_ALARM_HI: u32 = 4194303;
pub const TIMG_T1_ALARM_HI_V: u32 = 4194303;
pub const TIMG_T1_ALARM_HI_S: u32 = 0;
pub const TIMG_T1_LOAD_LO: u32 = 4294967295;
pub const TIMG_T1_LOAD_LO_V: u32 = 4294967295;
pub const TIMG_T1_LOAD_LO_S: u32 = 0;
pub const TIMG_T1_LOAD_HI: u32 = 4194303;
pub const TIMG_T1_LOAD_HI_V: u32 = 4194303;
pub const TIMG_T1_LOAD_HI_S: u32 = 0;
pub const TIMG_T1_LOAD: u32 = 4294967295;
pub const TIMG_T1_LOAD_V: u32 = 4294967295;
pub const TIMG_T1_LOAD_S: u32 = 0;
pub const TIMG_WDT_APPCPU_RESET_EN_V: u32 = 1;
pub const TIMG_WDT_APPCPU_RESET_EN_S: u32 = 12;
pub const TIMG_WDT_PROCPU_RESET_EN_V: u32 = 1;
pub const TIMG_WDT_PROCPU_RESET_EN_S: u32 = 13;
pub const TIMG_WDT_FLASHBOOT_MOD_EN_V: u32 = 1;
pub const TIMG_WDT_FLASHBOOT_MOD_EN_S: u32 = 14;
pub const TIMG_WDT_SYS_RESET_LENGTH: u32 = 7;
pub const TIMG_WDT_SYS_RESET_LENGTH_V: u32 = 7;
pub const TIMG_WDT_SYS_RESET_LENGTH_S: u32 = 15;
pub const TIMG_WDT_CPU_RESET_LENGTH: u32 = 7;
pub const TIMG_WDT_CPU_RESET_LENGTH_V: u32 = 7;
pub const TIMG_WDT_CPU_RESET_LENGTH_S: u32 = 18;
pub const TIMG_WDT_STG3: u32 = 3;
pub const TIMG_WDT_STG3_V: u32 = 3;
pub const TIMG_WDT_STG3_S: u32 = 23;
pub const TIMG_WDT_STG2: u32 = 3;
pub const TIMG_WDT_STG2_V: u32 = 3;
pub const TIMG_WDT_STG2_S: u32 = 25;
pub const TIMG_WDT_STG1: u32 = 3;
pub const TIMG_WDT_STG1_V: u32 = 3;
pub const TIMG_WDT_STG1_S: u32 = 27;
pub const TIMG_WDT_STG0: u32 = 3;
pub const TIMG_WDT_STG0_V: u32 = 3;
pub const TIMG_WDT_STG0_S: u32 = 29;
pub const TIMG_WDT_EN_V: u32 = 1;
pub const TIMG_WDT_EN_S: u32 = 31;
pub const TIMG_WDT_CLK_PRESCALE: u32 = 65535;
pub const TIMG_WDT_CLK_PRESCALE_V: u32 = 65535;
pub const TIMG_WDT_CLK_PRESCALE_S: u32 = 16;
pub const TIMG_WDT_STG0_HOLD: u32 = 4294967295;
pub const TIMG_WDT_STG0_HOLD_V: u32 = 4294967295;
pub const TIMG_WDT_STG0_HOLD_S: u32 = 0;
pub const TIMG_WDT_STG1_HOLD: u32 = 4294967295;
pub const TIMG_WDT_STG1_HOLD_V: u32 = 4294967295;
pub const TIMG_WDT_STG1_HOLD_S: u32 = 0;
pub const TIMG_WDT_STG2_HOLD: u32 = 4294967295;
pub const TIMG_WDT_STG2_HOLD_V: u32 = 4294967295;
pub const TIMG_WDT_STG2_HOLD_S: u32 = 0;
pub const TIMG_WDT_STG3_HOLD: u32 = 4294967295;
pub const TIMG_WDT_STG3_HOLD_V: u32 = 4294967295;
pub const TIMG_WDT_STG3_HOLD_S: u32 = 0;
pub const TIMG_WDT_FEED: u32 = 4294967295;
pub const TIMG_WDT_FEED_V: u32 = 4294967295;
pub const TIMG_WDT_FEED_S: u32 = 0;
pub const TIMG_WDT_WKEY: u32 = 4294967295;
pub const TIMG_WDT_WKEY_V: u32 = 4294967295;
pub const TIMG_WDT_WKEY_S: u32 = 0;
pub const TIMG_RTC_CALI_START_CYCLING_V: u32 = 1;
pub const TIMG_RTC_CALI_START_CYCLING_S: u32 = 12;
pub const TIMG_RTC_CALI_CLK_SEL: u32 = 3;
pub const TIMG_RTC_CALI_CLK_SEL_V: u32 = 3;
pub const TIMG_RTC_CALI_CLK_SEL_S: u32 = 13;
pub const TIMG_RTC_CALI_RDY_V: u32 = 1;
pub const TIMG_RTC_CALI_RDY_S: u32 = 15;
pub const TIMG_RTC_CALI_MAX: u32 = 32767;
pub const TIMG_RTC_CALI_MAX_V: u32 = 32767;
pub const TIMG_RTC_CALI_MAX_S: u32 = 16;
pub const TIMG_RTC_CALI_START_V: u32 = 1;
pub const TIMG_RTC_CALI_START_S: u32 = 31;
pub const TIMG_RTC_CALI_CYCLING_DATA_VLD_V: u32 = 1;
pub const TIMG_RTC_CALI_CYCLING_DATA_VLD_S: u32 = 0;
pub const TIMG_RTC_CALI_VALUE: u32 = 33554431;
pub const TIMG_RTC_CALI_VALUE_V: u32 = 33554431;
pub const TIMG_RTC_CALI_VALUE_S: u32 = 7;
pub const TIMG_T0_INT_ENA_V: u32 = 1;
pub const TIMG_T0_INT_ENA_S: u32 = 0;
pub const TIMG_T1_INT_ENA_V: u32 = 1;
pub const TIMG_T1_INT_ENA_S: u32 = 1;
pub const TIMG_WDT_INT_ENA_V: u32 = 1;
pub const TIMG_WDT_INT_ENA_S: u32 = 2;
pub const TIMG_T0_INT_RAW_V: u32 = 1;
pub const TIMG_T0_INT_RAW_S: u32 = 0;
pub const TIMG_T1_INT_RAW_V: u32 = 1;
pub const TIMG_T1_INT_RAW_S: u32 = 1;
pub const TIMG_WDT_INT_RAW_V: u32 = 1;
pub const TIMG_WDT_INT_RAW_S: u32 = 2;
pub const TIMG_T0_INT_ST_V: u32 = 1;
pub const TIMG_T0_INT_ST_S: u32 = 0;
pub const TIMG_T1_INT_ST_V: u32 = 1;
pub const TIMG_T1_INT_ST_S: u32 = 1;
pub const TIMG_WDT_INT_ST_V: u32 = 1;
pub const TIMG_WDT_INT_ST_S: u32 = 2;
pub const TIMG_T0_INT_CLR_V: u32 = 1;
pub const TIMG_T0_INT_CLR_S: u32 = 0;
pub const TIMG_T1_INT_CLR_V: u32 = 1;
pub const TIMG_T1_INT_CLR_S: u32 = 1;
pub const TIMG_WDT_INT_CLR_V: u32 = 1;
pub const TIMG_WDT_INT_CLR_S: u32 = 2;
pub const TIMG_RTC_CALI_TIMEOUT_V: u32 = 1;
pub const TIMG_RTC_CALI_TIMEOUT_S: u32 = 0;
pub const TIMG_RTC_CALI_TIMEOUT_RST_CNT: u32 = 15;
pub const TIMG_RTC_CALI_TIMEOUT_RST_CNT_V: u32 = 15;
pub const TIMG_RTC_CALI_TIMEOUT_RST_CNT_S: u32 = 3;
pub const TIMG_RTC_CALI_TIMEOUT_THRES: u32 = 33554431;
pub const TIMG_RTC_CALI_TIMEOUT_THRES_V: u32 = 33554431;
pub const TIMG_RTC_CALI_TIMEOUT_THRES_S: u32 = 7;
pub const TIMG_NTIMERS_DATE: u32 = 268435455;
pub const TIMG_NTIMERS_DATE_V: u32 = 268435455;
pub const TIMG_NTIMERS_DATE_S: u32 = 0;
pub const TIMG_CLK_EN_V: u32 = 1;
pub const TIMG_CLK_EN_S: u32 = 31;
pub const TIMER_BASE_CLK: u32 = 80000000;
pub const UART_NUM_0: u32 = 0;
pub const UART_NUM_1: u32 = 1;
pub const UART_NUM_2: u32 = 2;
pub const UART_NUM_MAX: u32 = 3;
pub const UART_PIN_NO_CHANGE: i32 = -1;
pub const UART_FIFO_LEN: u32 = 128;
pub const UART_BITRATE_MAX: u32 = 5000000;
pub const APP_ELF_SHA256_SZ: u32 = 17;
pub const PTHREAD_CANCEL_ENABLE: u32 = 0;
pub const PTHREAD_CANCEL_DISABLE: u32 = 1;
pub const PTHREAD_CANCEL_DEFERRED: u32 = 0;
pub const PTHREAD_CANCEL_ASYNCHRONOUS: u32 = 1;
pub const PTHREAD_STACK_MIN: u32 = 768;
pub const USB_B_DESCRIPTOR_TYPE_DEVICE: u32 = 1;
pub const USB_B_DESCRIPTOR_TYPE_CONFIGURATION: u32 = 2;
pub const USB_B_DESCRIPTOR_TYPE_STRING: u32 = 3;
pub const USB_B_DESCRIPTOR_TYPE_INTERFACE: u32 = 4;
pub const USB_B_DESCRIPTOR_TYPE_ENDPOINT: u32 = 5;
pub const USB_B_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: u32 = 6;
pub const USB_B_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION: u32 = 7;
pub const USB_B_DESCRIPTOR_TYPE_INTERFACE_POWER: u32 = 8;
pub const USB_B_DESCRIPTOR_TYPE_OTG: u32 = 9;
pub const USB_B_DESCRIPTOR_TYPE_DEBUG: u32 = 10;
pub const USB_B_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION: u32 = 11;
pub const USB_B_DESCRIPTOR_TYPE_SECURITY: u32 = 12;
pub const USB_B_DESCRIPTOR_TYPE_KEY: u32 = 13;
pub const USB_B_DESCRIPTOR_TYPE_ENCRYPTION_TYPE: u32 = 14;
pub const USB_B_DESCRIPTOR_TYPE_BOS: u32 = 15;
pub const USB_B_DESCRIPTOR_TYPE_DEVICE_CAPABILITY: u32 = 16;
pub const USB_B_DESCRIPTOR_TYPE_WIRELESS_ENDPOINT_COMP: u32 = 17;
pub const USB_B_DESCRIPTOR_TYPE_WIRE_ADAPTER: u32 = 33;
pub const USB_B_DESCRIPTOR_TYPE_RPIPE: u32 = 34;
pub const USB_B_DESCRIPTOR_TYPE_CS_RADIO_CONTROL: u32 = 35;
pub const USB_B_DESCRIPTOR_TYPE_PIPE_USAGE: u32 = 36;
pub const USB_SETUP_PACKET_SIZE: u32 = 8;
pub const USB_BM_REQUEST_TYPE_DIR_OUT: u32 = 0;
pub const USB_BM_REQUEST_TYPE_DIR_IN: u32 = 128;
pub const USB_BM_REQUEST_TYPE_TYPE_STANDARD: u32 = 0;
pub const USB_BM_REQUEST_TYPE_TYPE_CLASS: u32 = 32;
pub const USB_BM_REQUEST_TYPE_TYPE_VENDOR: u32 = 64;
pub const USB_BM_REQUEST_TYPE_TYPE_RESERVED: u32 = 96;
pub const USB_BM_REQUEST_TYPE_TYPE_MASK: u32 = 96;
pub const USB_BM_REQUEST_TYPE_RECIP_DEVICE: u32 = 0;
pub const USB_BM_REQUEST_TYPE_RECIP_INTERFACE: u32 = 1;
pub const USB_BM_REQUEST_TYPE_RECIP_ENDPOINT: u32 = 2;
pub const USB_BM_REQUEST_TYPE_RECIP_OTHER: u32 = 3;
pub const USB_BM_REQUEST_TYPE_RECIP_MASK: u32 = 31;
pub const USB_B_REQUEST_GET_STATUS: u32 = 0;
pub const USB_B_REQUEST_CLEAR_FEATURE: u32 = 1;
pub const USB_B_REQUEST_SET_FEATURE: u32 = 3;
pub const USB_B_REQUEST_SET_ADDRESS: u32 = 5;
pub const USB_B_REQUEST_GET_DESCRIPTOR: u32 = 6;
pub const USB_B_REQUEST_SET_DESCRIPTOR: u32 = 7;
pub const USB_B_REQUEST_GET_CONFIGURATION: u32 = 8;
pub const USB_B_REQUEST_SET_CONFIGURATION: u32 = 9;
pub const USB_B_REQUEST_GET_INTERFACE: u32 = 10;
pub const USB_B_REQUEST_SET_INTERFACE: u32 = 11;
pub const USB_B_REQUEST_SYNCH_FRAME: u32 = 12;
pub const USB_W_VALUE_DT_DEVICE: u32 = 1;
pub const USB_W_VALUE_DT_CONFIG: u32 = 2;
pub const USB_W_VALUE_DT_STRING: u32 = 3;
pub const USB_W_VALUE_DT_INTERFACE: u32 = 4;
pub const USB_W_VALUE_DT_ENDPOINT: u32 = 5;
pub const USB_W_VALUE_DT_DEVICE_QUALIFIER: u32 = 6;
pub const USB_W_VALUE_DT_OTHER_SPEED_CONFIG: u32 = 7;
pub const USB_W_VALUE_DT_INTERFACE_POWER: u32 = 8;
pub const USB_STANDARD_DESC_SIZE: u32 = 2;
pub const USB_DEVICE_DESC_SIZE: u32 = 18;
pub const USB_CLASS_PER_INTERFACE: u32 = 0;
pub const USB_CLASS_AUDIO: u32 = 1;
pub const USB_CLASS_COMM: u32 = 2;
pub const USB_CLASS_HID: u32 = 3;
pub const USB_CLASS_PHYSICAL: u32 = 5;
pub const USB_CLASS_STILL_IMAGE: u32 = 6;
pub const USB_CLASS_PRINTER: u32 = 7;
pub const USB_CLASS_MASS_STORAGE: u32 = 8;
pub const USB_CLASS_HUB: u32 = 9;
pub const USB_CLASS_CDC_DATA: u32 = 10;
pub const USB_CLASS_CSCID: u32 = 11;
pub const USB_CLASS_CONTENT_SEC: u32 = 13;
pub const USB_CLASS_VIDEO: u32 = 14;
pub const USB_CLASS_WIRELESS_CONTROLLER: u32 = 224;
pub const USB_CLASS_PERSONAL_HEALTHCARE: u32 = 15;
pub const USB_CLASS_AUDIO_VIDEO: u32 = 16;
pub const USB_CLASS_BILLBOARD: u32 = 17;
pub const USB_CLASS_USB_TYPE_C_BRIDGE: u32 = 18;
pub const USB_CLASS_MISC: u32 = 239;
pub const USB_CLASS_APP_SPEC: u32 = 254;
pub const USB_CLASS_VENDOR_SPEC: u32 = 255;
pub const USB_SUBCLASS_VENDOR_SPEC: u32 = 255;
pub const USB_CONFIG_DESC_SIZE: u32 = 9;
pub const USB_BM_ATTRIBUTES_ONE: u32 = 128;
pub const USB_BM_ATTRIBUTES_SELFPOWER: u32 = 64;
pub const USB_BM_ATTRIBUTES_WAKEUP: u32 = 32;
pub const USB_BM_ATTRIBUTES_BATTERY: u32 = 16;
pub const USB_IAD_DESC_SIZE: u32 = 9;
pub const USB_INTF_DESC_SIZE: u32 = 9;
pub const USB_EP_DESC_SIZE: u32 = 7;
pub const USB_B_ENDPOINT_ADDRESS_EP_NUM_MASK: u32 = 15;
pub const USB_B_ENDPOINT_ADDRESS_EP_DIR_MASK: u32 = 128;
pub const USB_BM_ATTRIBUTES_XFERTYPE_MASK: u32 = 3;
pub const USB_BM_ATTRIBUTES_XFER_CONTROL: u32 = 0;
pub const USB_BM_ATTRIBUTES_XFER_ISOC: u32 = 1;
pub const USB_BM_ATTRIBUTES_XFER_BULK: u32 = 2;
pub const USB_BM_ATTRIBUTES_XFER_INT: u32 = 3;
pub const USB_BM_ATTRIBUTES_SYNCTYPE_MASK: u32 = 12;
pub const USB_BM_ATTRIBUTES_SYNC_NONE: u32 = 0;
pub const USB_BM_ATTRIBUTES_SYNC_ASYNC: u32 = 4;
pub const USB_BM_ATTRIBUTES_SYNC_ADAPTIVE: u32 = 8;
pub const USB_BM_ATTRIBUTES_SYNC_SYNC: u32 = 12;
pub const USB_BM_ATTRIBUTES_USAGETYPE_MASK: u32 = 48;
pub const USB_BM_ATTRIBUTES_USAGE_DATA: u32 = 0;
pub const USB_BM_ATTRIBUTES_USAGE_FEEDBACK: u32 = 16;
pub const USB_BM_ATTRIBUTES_USAGE_IMPLICIT_FB: u32 = 32;
pub const USB_STR_DESC_SIZE: u32 = 2;
pub const USB_TRANSFER_FLAG_ZERO_PACK: u32 = 1;
pub const USB_HOST_LIB_EVENT_FLAGS_NO_CLIENTS: u32 = 1;
pub const USB_HOST_LIB_EVENT_FLAGS_ALL_FREE: u32 = 2;
pub type __int8_t = c_types::c_schar;
pub type __uint8_t = c_types::c_uchar;
pub type __int16_t = c_types::c_short;
pub type __uint16_t = c_types::c_ushort;
pub type __int32_t = c_types::c_int;
pub type __uint32_t = c_types::c_uint;
pub type __int64_t = c_types::c_longlong;
pub type __uint64_t = c_types::c_ulonglong;
pub type __int_least8_t = c_types::c_schar;
pub type __uint_least8_t = c_types::c_uchar;
pub type __int_least16_t = c_types::c_short;
pub type __uint_least16_t = c_types::c_ushort;
pub type __int_least32_t = c_types::c_int;
pub type __uint_least32_t = c_types::c_uint;
pub type __int_least64_t = c_types::c_longlong;
pub type __uint_least64_t = c_types::c_ulonglong;
pub type __intmax_t = c_types::c_longlong;
pub type __uintmax_t = c_types::c_ulonglong;
pub type __intptr_t = c_types::c_int;
pub type __uintptr_t = c_types::c_uint;
pub type intmax_t = __intmax_t;
pub type uintmax_t = __uintmax_t;
pub type int_least8_t = __int_least8_t;
pub type uint_least8_t = __uint_least8_t;
pub type int_least16_t = __int_least16_t;
pub type uint_least16_t = __uint_least16_t;
pub type int_least32_t = __int_least32_t;
pub type uint_least32_t = __uint_least32_t;
pub type int_least64_t = __int_least64_t;
pub type uint_least64_t = __uint_least64_t;
pub type int_fast8_t = c_types::c_schar;
pub type uint_fast8_t = c_types::c_uchar;
pub type int_fast16_t = c_types::c_short;
pub type uint_fast16_t = c_types::c_ushort;
pub type int_fast32_t = c_types::c_int;
pub type uint_fast32_t = c_types::c_uint;
pub type int_fast64_t = c_types::c_longlong;
pub type uint_fast64_t = c_types::c_ulonglong;
pub type size_t = c_types::c_uint;
pub type wchar_t = c_types::c_uchar;
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct max_align_t {
pub __clang_max_align_nonce1: c_types::c_longlong,
pub __clang_max_align_nonce2: f64,
}
pub type va_list = [u32; 3usize];
pub type __gnuc_va_list = [u32; 3usize];
pub type wint_t = c_types::c_uint;
pub type __blkcnt_t = c_types::c_long;
pub type __blksize_t = c_types::c_long;
pub type __fsblkcnt_t = __uint64_t;
pub type __fsfilcnt_t = __uint32_t;
pub type _off_t = c_types::c_long;
pub type __pid_t = c_types::c_int;
pub type __dev_t = c_types::c_short;
pub type __uid_t = c_types::c_ushort;
pub type __gid_t = c_types::c_ushort;
pub type __id_t = __uint32_t;
pub type __ino_t = c_types::c_ushort;
pub type __mode_t = __uint32_t;
pub type _off64_t = c_types::c_longlong;
pub type __off_t = _off_t;
pub type __loff_t = _off64_t;
pub type __key_t = c_types::c_long;
pub type _fpos_t = c_types::c_long;
pub type __size_t = c_types::c_uint;
pub type _ssize_t = c_types::c_int;
pub type __ssize_t = _ssize_t;
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _mbstate_t {
pub __count: c_types::c_int,
pub __value: _mbstate_t__bindgen_ty_1,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _mbstate_t__bindgen_ty_1 {
pub __wch: wint_t,
pub __wchb: [c_types::c_uchar; 4usize],
}
impl Default for _mbstate_t__bindgen_ty_1 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
impl Default for _mbstate_t {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
pub type _iconv_t = *mut c_types::c_void;
pub type __clock_t = c_types::c_ulong;
pub type __time_t = c_types::c_long;
pub type __clockid_t = c_types::c_ulong;
pub type __timer_t = c_types::c_ulong;
pub type __sa_family_t = __uint8_t;
pub type __socklen_t = __uint32_t;
pub type __nl_item = c_types::c_int;
pub type __nlink_t = c_types::c_ushort;
pub type __suseconds_t = c_types::c_long;
pub type __useconds_t = c_types::c_ulong;
pub type __va_list = [u32; 3usize];
pub type __ULong = c_types::c_ulong;
pub type _LOCK_T = *mut __lock;
extern "C" {
pub fn __retarget_lock_init(lock: *mut _LOCK_T);
}
extern "C" {
pub fn __retarget_lock_init_recursive(lock: *mut _LOCK_T);
}
extern "C" {
pub fn __retarget_lock_close(lock: _LOCK_T);
}
extern "C" {
pub fn __retarget_lock_close_recursive(lock: _LOCK_T);
}
extern "C" {
pub fn __retarget_lock_acquire(lock: _LOCK_T);
}
extern "C" {
pub fn __retarget_lock_acquire_recursive(lock: _LOCK_T);
}
extern "C" {
pub fn __retarget_lock_try_acquire(lock: _LOCK_T) -> c_types::c_int;
}
extern "C" {
pub fn __retarget_lock_try_acquire_recursive(lock: _LOCK_T) -> c_types::c_int;
}
extern "C" {
pub fn __retarget_lock_release(lock: _LOCK_T);
}
extern "C" {
pub fn __retarget_lock_release_recursive(lock: _LOCK_T);
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct __lock {
pub reserved: [c_types::c_int; 23usize],
}
pub type _lock_t = _LOCK_T;
extern "C" {
pub fn _lock_init(plock: *mut _lock_t);
}
extern "C" {
pub fn _lock_init_recursive(plock: *mut _lock_t);
}
extern "C" {
pub fn _lock_close(plock: *mut _lock_t);
}
extern "C" {
pub fn _lock_close_recursive(plock: *mut _lock_t);
}
extern "C" {
pub fn _lock_acquire(plock: *mut _lock_t);
}
extern "C" {
pub fn _lock_acquire_recursive(plock: *mut _lock_t);
}
extern "C" {
pub fn _lock_try_acquire(plock: *mut _lock_t) -> c_types::c_int;
}
extern "C" {
pub fn _lock_try_acquire_recursive(plock: *mut _lock_t) -> c_types::c_int;
}
extern "C" {
pub fn _lock_release(plock: *mut _lock_t);
}
extern "C" {
pub fn _lock_release_recursive(plock: *mut _lock_t);
}
pub type _flock_t = _LOCK_T;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct __locale_t {
_unused: [u8; 0],
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _Bigint {
pub _next: *mut _Bigint,
pub _k: c_types::c_int,
pub _maxwds: c_types::c_int,
pub _sign: c_types::c_int,
pub _wds: c_types::c_int,
pub _x: [__ULong; 1usize],
}
impl Default for _Bigint {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct __tm {
pub __tm_sec: c_types::c_int,
pub __tm_min: c_types::c_int,
pub __tm_hour: c_types::c_int,
pub __tm_mday: c_types::c_int,
pub __tm_mon: c_types::c_int,
pub __tm_year: c_types::c_int,
pub __tm_wday: c_types::c_int,
pub __tm_yday: c_types::c_int,
pub __tm_isdst: c_types::c_int,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _on_exit_args {
pub _fnargs: [*mut c_types::c_void; 32usize],
pub _dso_handle: [*mut c_types::c_void; 32usize],
pub _fntypes: __ULong,
pub _is_cxa: __ULong,
}
impl Default for _on_exit_args {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _atexit {
pub _next: *mut _atexit,
pub _ind: c_types::c_int,
pub _fns: [::core::option::Option<unsafe extern "C" fn()>; 32usize],
pub _on_exit_args_ptr: *mut _on_exit_args,
}
impl Default for _atexit {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct __sbuf {
pub _base: *mut c_types::c_uchar,
pub _size: c_types::c_int,
}
impl Default for __sbuf {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct __sFILE_fake {
pub _p: *mut c_types::c_uchar,
pub _r: c_types::c_int,
pub _w: c_types::c_int,
pub _flags: c_types::c_short,
pub _file: c_types::c_short,
pub _bf: __sbuf,
pub _lbfsize: c_types::c_int,
pub _data: *mut _reent,
}
impl Default for __sFILE_fake {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
extern "C" {
pub fn __sinit(arg1: *mut _reent);
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct __sFILE {
pub _p: *mut c_types::c_uchar,
pub _r: c_types::c_int,
pub _w: c_types::c_int,
pub _flags: c_types::c_short,
pub _file: c_types::c_short,
pub _bf: __sbuf,
pub _lbfsize: c_types::c_int,
pub _data: *mut _reent,
pub _cookie: *mut c_types::c_void,
pub _read: ::core::option::Option<
unsafe extern "C" fn(
arg1: *mut _reent,
arg2: *mut c_types::c_void,
arg3: *mut c_types::c_char,
arg4: c_types::c_int,
) -> c_types::c_int,
>,
pub _write: ::core::option::Option<
unsafe extern "C" fn(
arg1: *mut _reent,
arg2: *mut c_types::c_void,
arg3: *const c_types::c_char,
arg4: c_types::c_int,
) -> c_types::c_int,
>,
pub _seek: ::core::option::Option<
unsafe extern "C" fn(
arg1: *mut _reent,
arg2: *mut c_types::c_void,
arg3: _fpos_t,
arg4: c_types::c_int,
) -> _fpos_t,
>,
pub _close: ::core::option::Option<
unsafe extern "C" fn(arg1: *mut _reent, arg2: *mut c_types::c_void) -> c_types::c_int,
>,
pub _ub: __sbuf,
pub _up: *mut c_types::c_uchar,
pub _ur: c_types::c_int,
pub _ubuf: [c_types::c_uchar; 3usize],
pub _nbuf: [c_types::c_uchar; 1usize],
pub _lb: __sbuf,
pub _blksize: c_types::c_int,
pub _offset: _off_t,
pub _lock: _flock_t,
pub _mbstate: _mbstate_t,
pub _flags2: c_types::c_int,
}
impl Default for __sFILE {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
pub type __FILE = __sFILE;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _glue {
pub _next: *mut _glue,
pub _niobs: c_types::c_int,
pub _iobs: *mut __FILE,
}
impl Default for _glue {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct _rand48 {
pub _seed: [c_types::c_ushort; 3usize],
pub _mult: [c_types::c_ushort; 3usize],
pub _add: c_types::c_ushort,
pub _rand_next: c_types::c_ulonglong,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _mprec {
pub _result: *mut _Bigint,
pub _result_k: c_types::c_int,
pub _p5s: *mut _Bigint,
pub _freelist: *mut *mut _Bigint,
}
impl Default for _mprec {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _misc_reent {
pub _strtok_last: *mut c_types::c_char,
pub _mblen_state: _mbstate_t,
pub _wctomb_state: _mbstate_t,
pub _mbtowc_state: _mbstate_t,
pub _l64a_buf: [c_types::c_char; 8usize],
pub _getdate_err: c_types::c_int,
pub _mbrlen_state: _mbstate_t,
pub _mbrtowc_state: _mbstate_t,
pub _mbsrtowcs_state: _mbstate_t,
pub _wcrtomb_state: _mbstate_t,
pub _wcsrtombs_state: _mbstate_t,
}
impl Default for _misc_reent {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _reent {
pub _errno: c_types::c_int,
pub _stdin: *mut __FILE,
pub _stdout: *mut __FILE,
pub _stderr: *mut __FILE,
pub _inc: c_types::c_int,
pub _emergency: *mut c_types::c_char,
pub __sdidinit: c_types::c_int,
pub _unspecified_locale_info: c_types::c_int,
pub _locale: *mut __locale_t,
pub _mp: *mut _mprec,
pub __cleanup: ::core::option::Option<unsafe extern "C" fn(arg1: *mut _reent)>,
pub _gamma_signgam: c_types::c_int,
pub _cvtlen: c_types::c_int,
pub _cvtbuf: *mut c_types::c_char,
pub _r48: *mut _rand48,
pub _localtime_buf: *mut __tm,
pub _asctime_buf: *mut c_types::c_char,
pub _sig_func: *mut ::core::option::Option<unsafe extern "C" fn(arg1: c_types::c_int)>,
pub _atexit: *mut _atexit,
pub _atexit0: _atexit,
pub __sglue: _glue,
pub __sf: *mut __FILE,
pub _misc: *mut _misc_reent,
pub _signal_buf: *mut c_types::c_char,
}
impl Default for _reent {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
extern "C" {
pub static __sf_fake_stdin: __sFILE_fake;
}
extern "C" {
pub static __sf_fake_stdout: __sFILE_fake;
}
extern "C" {
pub static __sf_fake_stderr: __sFILE_fake;
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct div_t {
pub quot: c_types::c_int,
pub rem: c_types::c_int,
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct ldiv_t {
pub quot: c_types::c_long,
pub rem: c_types::c_long,
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct lldiv_t {
pub quot: c_types::c_longlong,
pub rem: c_types::c_longlong,
}
pub type __compar_fn_t = ::core::option::Option<
unsafe extern "C" fn(
arg1: *const c_types::c_void,
arg2: *const c_types::c_void,
) -> c_types::c_int,
>;
extern "C" {
pub fn __locale_mb_cur_max() -> c_types::c_int;
}
extern "C" {
pub fn abort();
}
extern "C" {
pub fn abs(arg1: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn arc4random() -> __uint32_t;
}
extern "C" {
pub fn arc4random_uniform(arg1: __uint32_t) -> __uint32_t;
}
extern "C" {
pub fn arc4random_buf(arg1: *mut c_types::c_void, arg2: size_t);
}
extern "C" {
pub fn atexit(__func: ::core::option::Option<unsafe extern "C" fn()>) -> c_types::c_int;
}
extern "C" {
pub fn atof(__nptr: *const c_types::c_char) -> f64;
}
extern "C" {
pub fn atoff(__nptr: *const c_types::c_char) -> f32;
}
extern "C" {
pub fn atoi(__nptr: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn _atoi_r(arg1: *mut _reent, __nptr: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn atol(__nptr: *const c_types::c_char) -> c_types::c_long;
}
extern "C" {
pub fn _atol_r(arg1: *mut _reent, __nptr: *const c_types::c_char) -> c_types::c_long;
}
extern "C" {
pub fn bsearch(
__key: *const c_types::c_void,
__base: *const c_types::c_void,
__nmemb: size_t,
__size: size_t,
_compar: __compar_fn_t,
) -> *mut c_types::c_void;
}
extern "C" {
pub fn calloc(arg1: c_types::c_uint, arg2: c_types::c_uint) -> *mut c_types::c_void;
}
extern "C" {
pub fn div(__numer: c_types::c_int, __denom: c_types::c_int) -> div_t;
}
extern "C" {
pub fn exit(__status: c_types::c_int);
}
extern "C" {
pub fn free(arg1: *mut c_types::c_void);
}
extern "C" {
pub fn getenv(__string: *const c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn _getenv_r(arg1: *mut _reent, __string: *const c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn _findenv(
arg1: *const c_types::c_char,
arg2: *mut c_types::c_int,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn _findenv_r(
arg1: *mut _reent,
arg2: *const c_types::c_char,
arg3: *mut c_types::c_int,
) -> *mut c_types::c_char;
}
extern "C" {
pub static mut suboptarg: *mut c_types::c_char;
}
extern "C" {
pub fn getsubopt(
arg1: *mut *mut c_types::c_char,
arg2: *const *mut c_types::c_char,
arg3: *mut *mut c_types::c_char,
) -> c_types::c_int;
}
extern "C" {
pub fn labs(arg1: c_types::c_long) -> c_types::c_long;
}
extern "C" {
pub fn ldiv(__numer: c_types::c_long, __denom: c_types::c_long) -> ldiv_t;
}
extern "C" {
pub fn malloc(arg1: c_types::c_uint) -> *mut c_types::c_void;
}
extern "C" {
pub fn mblen(arg1: *const c_types::c_char, arg2: size_t) -> c_types::c_int;
}
extern "C" {
pub fn _mblen_r(
arg1: *mut _reent,
arg2: *const c_types::c_char,
arg3: size_t,
arg4: *mut _mbstate_t,
) -> c_types::c_int;
}
extern "C" {
pub fn mbtowc(arg1: *mut wchar_t, arg2: *const c_types::c_char, arg3: size_t)
-> c_types::c_int;
}
extern "C" {
pub fn _mbtowc_r(
arg1: *mut _reent,
arg2: *mut wchar_t,
arg3: *const c_types::c_char,
arg4: size_t,
arg5: *mut _mbstate_t,
) -> c_types::c_int;
}
extern "C" {
pub fn wctomb(arg1: *mut c_types::c_char, arg2: wchar_t) -> c_types::c_int;
}
extern "C" {
pub fn _wctomb_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: wchar_t,
arg4: *mut _mbstate_t,
) -> c_types::c_int;
}
extern "C" {
pub fn mbstowcs(arg1: *mut wchar_t, arg2: *const c_types::c_char, arg3: size_t) -> size_t;
}
extern "C" {
pub fn _mbstowcs_r(
arg1: *mut _reent,
arg2: *mut wchar_t,
arg3: *const c_types::c_char,
arg4: size_t,
arg5: *mut _mbstate_t,
) -> size_t;
}
extern "C" {
pub fn wcstombs(arg1: *mut c_types::c_char, arg2: *const wchar_t, arg3: size_t) -> size_t;
}
extern "C" {
pub fn _wcstombs_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: *const wchar_t,
arg4: size_t,
arg5: *mut _mbstate_t,
) -> size_t;
}
extern "C" {
pub fn mkdtemp(arg1: *mut c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn mkstemp(arg1: *mut c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn mkstemps(arg1: *mut c_types::c_char, arg2: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn mktemp(arg1: *mut c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn _mkdtemp_r(arg1: *mut _reent, arg2: *mut c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn _mkostemp_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: c_types::c_int,
) -> c_types::c_int;
}
extern "C" {
pub fn _mkostemps_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: c_types::c_int,
arg4: c_types::c_int,
) -> c_types::c_int;
}
extern "C" {
pub fn _mkstemp_r(arg1: *mut _reent, arg2: *mut c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn _mkstemps_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: c_types::c_int,
) -> c_types::c_int;
}
extern "C" {
pub fn _mktemp_r(arg1: *mut _reent, arg2: *mut c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn qsort(
__base: *mut c_types::c_void,
__nmemb: size_t,
__size: size_t,
_compar: __compar_fn_t,
);
}
extern "C" {
pub fn rand() -> c_types::c_int;
}
extern "C" {
pub fn realloc(arg1: *mut c_types::c_void, arg2: c_types::c_uint) -> *mut c_types::c_void;
}
extern "C" {
pub fn reallocarray(
arg1: *mut c_types::c_void,
arg2: size_t,
arg3: size_t,
) -> *mut c_types::c_void;
}
extern "C" {
pub fn reallocf(arg1: *mut c_types::c_void, arg2: size_t) -> *mut c_types::c_void;
}
extern "C" {
pub fn realpath(
path: *const c_types::c_char,
resolved_path: *mut c_types::c_char,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn rpmatch(response: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn srand(__seed: c_types::c_uint);
}
extern "C" {
pub fn strtod(__n: *const c_types::c_char, __end_PTR: *mut *mut c_types::c_char) -> f64;
}
extern "C" {
pub fn _strtod_r(
arg1: *mut _reent,
__n: *const c_types::c_char,
__end_PTR: *mut *mut c_types::c_char,
) -> f64;
}
extern "C" {
pub fn strtof(__n: *const c_types::c_char, __end_PTR: *mut *mut c_types::c_char) -> f32;
}
extern "C" {
pub fn strtol(
__n: *const c_types::c_char,
__end_PTR: *mut *mut c_types::c_char,
__base: c_types::c_int,
) -> c_types::c_long;
}
extern "C" {
pub fn _strtol_r(
arg1: *mut _reent,
__n: *const c_types::c_char,
__end_PTR: *mut *mut c_types::c_char,
__base: c_types::c_int,
) -> c_types::c_long;
}
extern "C" {
pub fn strtoul(
__n: *const c_types::c_char,
__end_PTR: *mut *mut c_types::c_char,
__base: c_types::c_int,
) -> c_types::c_ulong;
}
extern "C" {
pub fn _strtoul_r(
arg1: *mut _reent,
__n: *const c_types::c_char,
__end_PTR: *mut *mut c_types::c_char,
__base: c_types::c_int,
) -> c_types::c_ulong;
}
extern "C" {
pub fn system(__string: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn a64l(__input: *const c_types::c_char) -> c_types::c_long;
}
extern "C" {
pub fn l64a(__input: c_types::c_long) -> *mut c_types::c_char;
}
extern "C" {
pub fn _l64a_r(arg1: *mut _reent, __input: c_types::c_long) -> *mut c_types::c_char;
}
extern "C" {
pub fn on_exit(
__func: ::core::option::Option<
unsafe extern "C" fn(arg1: c_types::c_int, arg2: *mut c_types::c_void),
>,
__arg: *mut c_types::c_void,
) -> c_types::c_int;
}
extern "C" {
pub fn _Exit(__status: c_types::c_int);
}
extern "C" {
pub fn putenv(__string: *mut c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn _putenv_r(arg1: *mut _reent, __string: *mut c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn _reallocf_r(
arg1: *mut _reent,
arg2: *mut c_types::c_void,
arg3: size_t,
) -> *mut c_types::c_void;
}
extern "C" {
pub fn setenv(
__string: *const c_types::c_char,
__value: *const c_types::c_char,
__overwrite: c_types::c_int,
) -> c_types::c_int;
}
extern "C" {
pub fn _setenv_r(
arg1: *mut _reent,
__string: *const c_types::c_char,
__value: *const c_types::c_char,
__overwrite: c_types::c_int,
) -> c_types::c_int;
}
extern "C" {
pub fn __itoa(
arg1: c_types::c_int,
arg2: *mut c_types::c_char,
arg3: c_types::c_int,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn __utoa(
arg1: c_types::c_uint,
arg2: *mut c_types::c_char,
arg3: c_types::c_int,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn itoa(
arg1: c_types::c_int,
arg2: *mut c_types::c_char,
arg3: c_types::c_int,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn utoa(
arg1: c_types::c_uint,
arg2: *mut c_types::c_char,
arg3: c_types::c_int,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn rand_r(__seed: *mut c_types::c_uint) -> c_types::c_int;
}
extern "C" {
pub fn drand48() -> f64;
}
extern "C" {
pub fn _drand48_r(arg1: *mut _reent) -> f64;
}
extern "C" {
pub fn erand48(arg1: *mut c_types::c_ushort) -> f64;
}
extern "C" {
pub fn _erand48_r(arg1: *mut _reent, arg2: *mut c_types::c_ushort) -> f64;
}
extern "C" {
pub fn jrand48(arg1: *mut c_types::c_ushort) -> c_types::c_long;
}
extern "C" {
pub fn _jrand48_r(arg1: *mut _reent, arg2: *mut c_types::c_ushort) -> c_types::c_long;
}
extern "C" {
pub fn lcong48(arg1: *mut c_types::c_ushort);
}
extern "C" {
pub fn _lcong48_r(arg1: *mut _reent, arg2: *mut c_types::c_ushort);
}
extern "C" {
pub fn lrand48() -> c_types::c_long;
}
extern "C" {
pub fn _lrand48_r(arg1: *mut _reent) -> c_types::c_long;
}
extern "C" {
pub fn mrand48() -> c_types::c_long;
}
extern "C" {
pub fn _mrand48_r(arg1: *mut _reent) -> c_types::c_long;
}
extern "C" {
pub fn nrand48(arg1: *mut c_types::c_ushort) -> c_types::c_long;
}
extern "C" {
pub fn _nrand48_r(arg1: *mut _reent, arg2: *mut c_types::c_ushort) -> c_types::c_long;
}
extern "C" {
pub fn seed48(arg1: *mut c_types::c_ushort) -> *mut c_types::c_ushort;
}
extern "C" {
pub fn _seed48_r(arg1: *mut _reent, arg2: *mut c_types::c_ushort) -> *mut c_types::c_ushort;
}
extern "C" {
pub fn srand48(arg1: c_types::c_long);
}
extern "C" {
pub fn _srand48_r(arg1: *mut _reent, arg2: c_types::c_long);
}
extern "C" {
pub fn initstate(
arg1: c_types::c_uint,
arg2: *mut c_types::c_char,
arg3: size_t,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn random() -> c_types::c_long;
}
extern "C" {
pub fn setstate(arg1: *mut c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn srandom(arg1: c_types::c_uint);
}
extern "C" {
pub fn atoll(__nptr: *const c_types::c_char) -> c_types::c_longlong;
}
extern "C" {
pub fn _atoll_r(arg1: *mut _reent, __nptr: *const c_types::c_char) -> c_types::c_longlong;
}
extern "C" {
pub fn llabs(arg1: c_types::c_longlong) -> c_types::c_longlong;
}
extern "C" {
pub fn lldiv(__numer: c_types::c_longlong, __denom: c_types::c_longlong) -> lldiv_t;
}
extern "C" {
pub fn strtoll(
__n: *const c_types::c_char,
__end_PTR: *mut *mut c_types::c_char,
__base: c_types::c_int,
) -> c_types::c_longlong;
}
extern "C" {
pub fn _strtoll_r(
arg1: *mut _reent,
__n: *const c_types::c_char,
__end_PTR: *mut *mut c_types::c_char,
__base: c_types::c_int,
) -> c_types::c_longlong;
}
extern "C" {
pub fn strtoull(
__n: *const c_types::c_char,
__end_PTR: *mut *mut c_types::c_char,
__base: c_types::c_int,
) -> c_types::c_ulonglong;
}
extern "C" {
pub fn _strtoull_r(
arg1: *mut _reent,
__n: *const c_types::c_char,
__end_PTR: *mut *mut c_types::c_char,
__base: c_types::c_int,
) -> c_types::c_ulonglong;
}
extern "C" {
pub fn cfree(arg1: *mut c_types::c_void);
}
extern "C" {
pub fn unsetenv(__string: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn _unsetenv_r(arg1: *mut _reent, __string: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn posix_memalign(
arg1: *mut *mut c_types::c_void,
arg2: size_t,
arg3: size_t,
) -> c_types::c_int;
}
extern "C" {
pub fn _dtoa_r(
arg1: *mut _reent,
arg2: f64,
arg3: c_types::c_int,
arg4: c_types::c_int,
arg5: *mut c_types::c_int,
arg6: *mut c_types::c_int,
arg7: *mut *mut c_types::c_char,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn _malloc_r(arg1: *mut _reent, arg2: size_t) -> *mut c_types::c_void;
}
extern "C" {
pub fn _calloc_r(arg1: *mut _reent, arg2: size_t, arg3: size_t) -> *mut c_types::c_void;
}
extern "C" {
pub fn _free_r(arg1: *mut _reent, arg2: *mut c_types::c_void);
}
extern "C" {
pub fn _realloc_r(
arg1: *mut _reent,
arg2: *mut c_types::c_void,
arg3: size_t,
) -> *mut c_types::c_void;
}
extern "C" {
pub fn _mstats_r(arg1: *mut _reent, arg2: *mut c_types::c_char);
}
extern "C" {
pub fn _system_r(arg1: *mut _reent, arg2: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn __eprintf(
arg1: *const c_types::c_char,
arg2: *const c_types::c_char,
arg3: c_types::c_uint,
arg4: *const c_types::c_char,
);
}
extern "C" {
#[link_name = "\u{1}__bsd_qsort_r"]
pub fn qsort_r(
__base: *mut c_types::c_void,
__nmemb: size_t,
__size: size_t,
__thunk: *mut c_types::c_void,
_compar: ::core::option::Option<
unsafe extern "C" fn(
arg1: *mut c_types::c_void,
arg2: *const c_types::c_void,
arg3: *const c_types::c_void,
) -> c_types::c_int,
>,
);
}
extern "C" {
pub fn aligned_alloc(arg1: c_types::c_uint, arg2: c_types::c_uint) -> *mut c_types::c_void;
}
extern "C" {
pub fn at_quick_exit(arg1: ::core::option::Option<unsafe extern "C" fn()>) -> c_types::c_int;
}
extern "C" {
pub fn quick_exit(arg1: c_types::c_int);
}
extern "C" {
pub fn __assert(
arg1: *const c_types::c_char,
arg2: c_types::c_int,
arg3: *const c_types::c_char,
);
}
extern "C" {
pub fn __assert_func(
arg1: *const c_types::c_char,
arg2: c_types::c_int,
arg3: *const c_types::c_char,
arg4: *const c_types::c_char,
);
}
extern "C" {
pub static mut _global_impure_ptr: *mut _reent;
}
extern "C" {
pub fn _reclaim_reent(arg1: *mut _reent);
}
extern "C" {
pub fn __getreent() -> *mut _reent;
}
extern "C" {
pub fn _cleanup_r(r: *mut _reent);
}
pub type u_int8_t = __uint8_t;
pub type u_int16_t = __uint16_t;
pub type u_int32_t = __uint32_t;
pub type u_int64_t = __uint64_t;
pub type register_t = __intptr_t;
pub type __sigset_t = c_types::c_ulong;
pub type suseconds_t = __suseconds_t;
pub type time_t = c_types::c_long;
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct timeval {
pub tv_sec: time_t,
pub tv_usec: suseconds_t,
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct timespec {
pub tv_sec: time_t,
pub tv_nsec: c_types::c_long,
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct itimerspec {
pub it_interval: timespec,
pub it_value: timespec,
}
pub type sigset_t = __sigset_t;
pub type fd_mask = c_types::c_ulong;
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct _types_fd_set {
pub fds_bits: [fd_mask; 2usize],
}
extern "C" {
pub fn select(
__n: c_types::c_int,
__readfds: *mut _types_fd_set,
__writefds: *mut _types_fd_set,
__exceptfds: *mut _types_fd_set,
__timeout: *mut timeval,
) -> c_types::c_int;
}
extern "C" {
pub fn pselect(
__n: c_types::c_int,
__readfds: *mut _types_fd_set,
__writefds: *mut _types_fd_set,
__exceptfds: *mut _types_fd_set,
__timeout: *const timespec,
__set: *const sigset_t,
) -> c_types::c_int;
}
pub type in_addr_t = __uint32_t;
pub type in_port_t = __uint16_t;
pub type u_register_t = __uintptr_t;
pub type u_char = c_types::c_uchar;
pub type u_short = c_types::c_ushort;
pub type u_int = c_types::c_uint;
pub type u_long = c_types::c_ulong;
pub type ushort = c_types::c_ushort;
pub type uint = c_types::c_uint;
pub type ulong = c_types::c_ulong;
pub type blkcnt_t = __blkcnt_t;
pub type blksize_t = __blksize_t;
pub type clock_t = c_types::c_ulong;
pub type daddr_t = c_types::c_long;
pub type caddr_t = *mut c_types::c_char;
pub type fsblkcnt_t = __fsblkcnt_t;
pub type fsfilcnt_t = __fsfilcnt_t;
pub type id_t = __id_t;
pub type ino_t = __ino_t;
pub type off_t = __off_t;
pub type dev_t = __dev_t;
pub type uid_t = __uid_t;
pub type gid_t = __gid_t;
pub type pid_t = __pid_t;
pub type key_t = __key_t;
pub type ssize_t = _ssize_t;
pub type mode_t = __mode_t;
pub type nlink_t = __nlink_t;
pub type clockid_t = __clockid_t;
pub type timer_t = __timer_t;
pub type useconds_t = __useconds_t;
pub type sbintime_t = __int64_t;
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct sched_param {
pub sched_priority: c_types::c_int,
}
extern "C" {
pub fn sched_yield() -> c_types::c_int;
}
pub type pthread_t = __uint32_t;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct pthread_attr_t {
pub is_initialized: c_types::c_int,
pub stackaddr: *mut c_types::c_void,
pub stacksize: c_types::c_int,
pub contentionscope: c_types::c_int,
pub inheritsched: c_types::c_int,
pub schedpolicy: c_types::c_int,
pub schedparam: sched_param,
pub detachstate: c_types::c_int,
}
impl Default for pthread_attr_t {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
pub type pthread_mutex_t = __uint32_t;
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct pthread_mutexattr_t {
pub is_initialized: c_types::c_int,
pub type_: c_types::c_int,
pub recursive: c_types::c_int,
}
pub type pthread_cond_t = __uint32_t;
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct pthread_condattr_t {
pub is_initialized: c_types::c_int,
pub clock: clock_t,
}
pub type pthread_key_t = __uint32_t;
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct pthread_once_t {
pub is_initialized: c_types::c_int,
pub init_executed: c_types::c_int,
}
pub type FILE = __FILE;
pub type fpos_t = _fpos_t;
extern "C" {
pub fn ctermid(arg1: *mut c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn tmpfile() -> *mut FILE;
}
extern "C" {
pub fn tmpnam(arg1: *mut c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn tempnam(
arg1: *const c_types::c_char,
arg2: *const c_types::c_char,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn fclose(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn fflush(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn freopen(
arg1: *const c_types::c_char,
arg2: *const c_types::c_char,
arg3: *mut FILE,
) -> *mut FILE;
}
extern "C" {
pub fn setbuf(arg1: *mut FILE, arg2: *mut c_types::c_char);
}
extern "C" {
pub fn setvbuf(
arg1: *mut FILE,
arg2: *mut c_types::c_char,
arg3: c_types::c_int,
arg4: size_t,
) -> c_types::c_int;
}
extern "C" {
pub fn fprintf(arg1: *mut FILE, arg2: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn fscanf(arg1: *mut FILE, arg2: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn printf(arg1: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn scanf(arg1: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn sscanf(
arg1: *const c_types::c_char,
arg2: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn fgetc(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn fgets(
arg1: *mut c_types::c_char,
arg2: c_types::c_int,
arg3: *mut FILE,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn fputc(arg1: c_types::c_int, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn fputs(arg1: *const c_types::c_char, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn getc(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn getchar() -> c_types::c_int;
}
extern "C" {
pub fn gets(arg1: *mut c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn putc(arg1: c_types::c_int, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn putchar(arg1: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn puts(arg1: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn ungetc(arg1: c_types::c_int, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn fread(
arg1: *mut c_types::c_void,
_size: c_types::c_uint,
_n: c_types::c_uint,
arg2: *mut FILE,
) -> c_types::c_uint;
}
extern "C" {
pub fn fwrite(
arg1: *const c_types::c_void,
_size: c_types::c_uint,
_n: c_types::c_uint,
arg2: *mut FILE,
) -> c_types::c_uint;
}
extern "C" {
pub fn fgetpos(arg1: *mut FILE, arg2: *mut fpos_t) -> c_types::c_int;
}
extern "C" {
pub fn fseek(arg1: *mut FILE, arg2: c_types::c_long, arg3: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn fsetpos(arg1: *mut FILE, arg2: *const fpos_t) -> c_types::c_int;
}
extern "C" {
pub fn ftell(arg1: *mut FILE) -> c_types::c_long;
}
extern "C" {
pub fn rewind(arg1: *mut FILE);
}
extern "C" {
pub fn clearerr(arg1: *mut FILE);
}
extern "C" {
pub fn feof(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn ferror(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn perror(arg1: *const c_types::c_char);
}
extern "C" {
pub fn fopen(_name: *const c_types::c_char, _type: *const c_types::c_char) -> *mut FILE;
}
extern "C" {
pub fn sprintf(arg1: *mut c_types::c_char, arg2: *const c_types::c_char, ...)
-> c_types::c_int;
}
extern "C" {
pub fn remove(arg1: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn rename(arg1: *const c_types::c_char, arg2: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn fseeko(arg1: *mut FILE, arg2: off_t, arg3: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn ftello(arg1: *mut FILE) -> off_t;
}
extern "C" {
pub fn snprintf(
arg1: *mut c_types::c_char,
arg2: c_types::c_uint,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn asiprintf(
arg1: *mut *mut c_types::c_char,
arg2: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn asniprintf(
arg1: *mut c_types::c_char,
arg2: *mut size_t,
arg3: *const c_types::c_char,
...
) -> *mut c_types::c_char;
}
extern "C" {
pub fn asnprintf(
arg1: *mut c_types::c_char,
arg2: *mut size_t,
arg3: *const c_types::c_char,
...
) -> *mut c_types::c_char;
}
extern "C" {
pub fn diprintf(arg1: c_types::c_int, arg2: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn fiprintf(arg1: *mut FILE, arg2: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn fiscanf(arg1: *mut FILE, arg2: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn iprintf(arg1: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn iscanf(arg1: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn siprintf(
arg1: *mut c_types::c_char,
arg2: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn siscanf(
arg1: *const c_types::c_char,
arg2: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn sniprintf(
arg1: *mut c_types::c_char,
arg2: size_t,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn fdopen(arg1: c_types::c_int, arg2: *const c_types::c_char) -> *mut FILE;
}
extern "C" {
pub fn fileno(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn pclose(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn popen(arg1: *const c_types::c_char, arg2: *const c_types::c_char) -> *mut FILE;
}
extern "C" {
pub fn setbuffer(arg1: *mut FILE, arg2: *mut c_types::c_char, arg3: c_types::c_int);
}
extern "C" {
pub fn setlinebuf(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn getw(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn putw(arg1: c_types::c_int, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn getc_unlocked(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn getchar_unlocked() -> c_types::c_int;
}
extern "C" {
pub fn flockfile(arg1: *mut FILE);
}
extern "C" {
pub fn ftrylockfile(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn funlockfile(arg1: *mut FILE);
}
extern "C" {
pub fn putc_unlocked(arg1: c_types::c_int, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn putchar_unlocked(arg1: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn dprintf(arg1: c_types::c_int, arg2: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn fmemopen(
arg1: *mut c_types::c_void,
arg2: size_t,
arg3: *const c_types::c_char,
) -> *mut FILE;
}
extern "C" {
pub fn open_memstream(arg1: *mut *mut c_types::c_char, arg2: *mut size_t) -> *mut FILE;
}
extern "C" {
pub fn renameat(
arg1: c_types::c_int,
arg2: *const c_types::c_char,
arg3: c_types::c_int,
arg4: *const c_types::c_char,
) -> c_types::c_int;
}
extern "C" {
pub fn _asiprintf_r(
arg1: *mut _reent,
arg2: *mut *mut c_types::c_char,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _asniprintf_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: *mut size_t,
arg4: *const c_types::c_char,
...
) -> *mut c_types::c_char;
}
extern "C" {
pub fn _asnprintf_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: *mut size_t,
arg4: *const c_types::c_char,
...
) -> *mut c_types::c_char;
}
extern "C" {
pub fn _asprintf_r(
arg1: *mut _reent,
arg2: *mut *mut c_types::c_char,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _diprintf_r(
arg1: *mut _reent,
arg2: c_types::c_int,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _dprintf_r(
arg1: *mut _reent,
arg2: c_types::c_int,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _fclose_r(arg1: *mut _reent, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn _fcloseall_r(arg1: *mut _reent) -> c_types::c_int;
}
extern "C" {
pub fn _fdopen_r(
arg1: *mut _reent,
arg2: c_types::c_int,
arg3: *const c_types::c_char,
) -> *mut FILE;
}
extern "C" {
pub fn _fflush_r(arg1: *mut _reent, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn _fgetc_r(arg1: *mut _reent, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn _fgetc_unlocked_r(arg1: *mut _reent, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn _fgets_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: c_types::c_int,
arg4: *mut FILE,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn _fgets_unlocked_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: c_types::c_int,
arg4: *mut FILE,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn _fgetpos_r(arg1: *mut _reent, arg2: *mut FILE, arg3: *mut fpos_t) -> c_types::c_int;
}
extern "C" {
pub fn _fsetpos_r(arg1: *mut _reent, arg2: *mut FILE, arg3: *const fpos_t) -> c_types::c_int;
}
extern "C" {
pub fn _fiprintf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _fiscanf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _fmemopen_r(
arg1: *mut _reent,
arg2: *mut c_types::c_void,
arg3: size_t,
arg4: *const c_types::c_char,
) -> *mut FILE;
}
extern "C" {
pub fn _fopen_r(
arg1: *mut _reent,
arg2: *const c_types::c_char,
arg3: *const c_types::c_char,
) -> *mut FILE;
}
extern "C" {
pub fn _freopen_r(
arg1: *mut _reent,
arg2: *const c_types::c_char,
arg3: *const c_types::c_char,
arg4: *mut FILE,
) -> *mut FILE;
}
extern "C" {
pub fn _fprintf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _fpurge_r(arg1: *mut _reent, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn _fputc_r(arg1: *mut _reent, arg2: c_types::c_int, arg3: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn _fputc_unlocked_r(
arg1: *mut _reent,
arg2: c_types::c_int,
arg3: *mut FILE,
) -> c_types::c_int;
}
extern "C" {
pub fn _fputs_r(
arg1: *mut _reent,
arg2: *const c_types::c_char,
arg3: *mut FILE,
) -> c_types::c_int;
}
extern "C" {
pub fn _fputs_unlocked_r(
arg1: *mut _reent,
arg2: *const c_types::c_char,
arg3: *mut FILE,
) -> c_types::c_int;
}
extern "C" {
pub fn _fread_r(
arg1: *mut _reent,
arg2: *mut c_types::c_void,
_size: size_t,
_n: size_t,
arg3: *mut FILE,
) -> size_t;
}
extern "C" {
pub fn _fread_unlocked_r(
arg1: *mut _reent,
arg2: *mut c_types::c_void,
_size: size_t,
_n: size_t,
arg3: *mut FILE,
) -> size_t;
}
extern "C" {
pub fn _fscanf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _fseek_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: c_types::c_long,
arg4: c_types::c_int,
) -> c_types::c_int;
}
extern "C" {
pub fn _fseeko_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: _off_t,
arg4: c_types::c_int,
) -> c_types::c_int;
}
extern "C" {
pub fn _ftell_r(arg1: *mut _reent, arg2: *mut FILE) -> c_types::c_long;
}
extern "C" {
pub fn _ftello_r(arg1: *mut _reent, arg2: *mut FILE) -> _off_t;
}
extern "C" {
pub fn _rewind_r(arg1: *mut _reent, arg2: *mut FILE);
}
extern "C" {
pub fn _fwrite_r(
arg1: *mut _reent,
arg2: *const c_types::c_void,
_size: size_t,
_n: size_t,
arg3: *mut FILE,
) -> size_t;
}
extern "C" {
pub fn _fwrite_unlocked_r(
arg1: *mut _reent,
arg2: *const c_types::c_void,
_size: size_t,
_n: size_t,
arg3: *mut FILE,
) -> size_t;
}
extern "C" {
pub fn _getc_r(arg1: *mut _reent, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn _getc_unlocked_r(arg1: *mut _reent, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn _getchar_r(arg1: *mut _reent) -> c_types::c_int;
}
extern "C" {
pub fn _getchar_unlocked_r(arg1: *mut _reent) -> c_types::c_int;
}
extern "C" {
pub fn _gets_r(arg1: *mut _reent, arg2: *mut c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn _iprintf_r(arg1: *mut _reent, arg2: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn _iscanf_r(arg1: *mut _reent, arg2: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn _open_memstream_r(
arg1: *mut _reent,
arg2: *mut *mut c_types::c_char,
arg3: *mut size_t,
) -> *mut FILE;
}
extern "C" {
pub fn _perror_r(arg1: *mut _reent, arg2: *const c_types::c_char);
}
extern "C" {
pub fn _printf_r(arg1: *mut _reent, arg2: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn _putc_r(arg1: *mut _reent, arg2: c_types::c_int, arg3: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn _putc_unlocked_r(
arg1: *mut _reent,
arg2: c_types::c_int,
arg3: *mut FILE,
) -> c_types::c_int;
}
extern "C" {
pub fn _putchar_unlocked_r(arg1: *mut _reent, arg2: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn _putchar_r(arg1: *mut _reent, arg2: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn _puts_r(arg1: *mut _reent, arg2: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn _remove_r(arg1: *mut _reent, arg2: *const c_types::c_char) -> c_types::c_int;
}
extern "C" {
pub fn _rename_r(
arg1: *mut _reent,
_old: *const c_types::c_char,
_new: *const c_types::c_char,
) -> c_types::c_int;
}
extern "C" {
pub fn _scanf_r(arg1: *mut _reent, arg2: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
pub fn _siprintf_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _siscanf_r(
arg1: *mut _reent,
arg2: *const c_types::c_char,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _sniprintf_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: size_t,
arg4: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _snprintf_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: size_t,
arg4: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _sprintf_r(
arg1: *mut _reent,
arg2: *mut c_types::c_char,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _sscanf_r(
arg1: *mut _reent,
arg2: *const c_types::c_char,
arg3: *const c_types::c_char,
...
) -> c_types::c_int;
}
extern "C" {
pub fn _tempnam_r(
arg1: *mut _reent,
arg2: *const c_types::c_char,
arg3: *const c_types::c_char,
) -> *mut c_types::c_char;
}
extern "C" {
pub fn _tmpfile_r(arg1: *mut _reent) -> *mut FILE;
}
extern "C" {
pub fn _tmpnam_r(arg1: *mut _reent, arg2: *mut c_types::c_char) -> *mut c_types::c_char;
}
extern "C" {
pub fn _ungetc_r(arg1: *mut _reent, arg2: c_types::c_int, arg3: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn fpurge(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn __getdelim(
arg1: *mut *mut c_types::c_char,
arg2: *mut size_t,
arg3: c_types::c_int,
arg4: *mut FILE,
) -> ssize_t;
}
extern "C" {
pub fn __getline(
arg1: *mut *mut c_types::c_char,
arg2: *mut size_t,
arg3: *mut FILE,
) -> ssize_t;
}
extern "C" {
pub fn clearerr_unlocked(arg1: *mut FILE);
}
extern "C" {
pub fn feof_unlocked(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn ferror_unlocked(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn fileno_unlocked(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn fflush_unlocked(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn fgetc_unlocked(arg1: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn fputc_unlocked(arg1: c_types::c_int, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn fread_unlocked(
arg1: *mut c_types::c_void,
_size: size_t,
_n: size_t,
arg2: *mut FILE,
) -> size_t;
}
extern "C" {
pub fn fwrite_unlocked(
arg1: *const c_types::c_void,
_size: size_t,
_n: size_t,
arg2: *mut FILE,
) -> size_t;
}
extern "C" {
pub fn __srget_r(arg1: *mut _reent, arg2: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn __swbuf_r(arg1: *mut _reent, arg2: c_types::c_int, arg3: *mut FILE) -> c_types::c_int;
}
extern "C" {
pub fn funopen(
__cookie: *const c_types::c_void,
__readfn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut c_types::c_void,
__buf: *mut c_types::c_char,
__n: c_types::c_int,
) -> c_types::c_int,
>,
__writefn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut c_types::c_void,
__buf: *const c_types::c_char,
__n: c_types::c_int,
) -> c_types::c_int,
>,
__seekfn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut c_types::c_void,
__off: fpos_t,
__whence: c_types::c_int,
) -> fpos_t,
>,
__closefn: ::core::option::Option<
unsafe extern "C" fn(__cookie: *mut c_types::c_void) -> c_types::c_int,
>,
) -> *mut FILE;
}
extern "C" {
pub fn _funopen_r(
arg1: *mut _reent,
__cookie: *const c_types::c_void,
__readfn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut c_types::c_void,
__buf: *mut c_types::c_char,
__n: c_types::c_int,
) -> c_types::c_int,
>,
__writefn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut c_types::c_void,
__buf: *const c_types::c_char,
__n: c_types::c_int,
) -> c_types::c_int,
>,
__seekfn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut c_types::c_void,
__off: fpos_t,
__whence: c_types::c_int,
) -> fpos_t,
>,
__closefn: ::core::option::Option<
unsafe extern "C" fn(__cookie: *mut c_types::c_void) -> c_types::c_int,
>,
) -> *mut FILE;
}
pub type esp_err_t = c_types::c_int;
extern "C" {
#[doc = " @brief Returns string for esp_err_t error codes"]
#[doc = ""]
#[doc = " This function finds the error code in a pre-generated lookup-table and"]
#[doc = " returns its string representation."]
#[doc = ""]
#[doc = " The function is generated by the Python script"]
#[doc = " tools/gen_esp_err_to_name.py which should be run each time an esp_err_t"]
#[doc = " error is modified, created or removed from the IDF project."]
#[doc = ""]
#[doc = " @param code esp_err_t error code"]
#[doc = " @return string error message"]
pub fn esp_err_to_name(code: esp_err_t) -> *const c_types::c_char;
}
extern "C" {
#[doc = " @brief Returns string for esp_err_t and system error codes"]
#[doc = ""]
#[doc = " This function finds the error code in a pre-generated lookup-table of"]
#[doc = " esp_err_t errors and returns its string representation. If the error code"]
#[doc = " is not found then it is attempted to be found among system errors."]
#[doc = ""]
#[doc = " The function is generated by the Python script"]
#[doc = " tools/gen_esp_err_to_name.py which should be run each time an esp_err_t"]
#[doc = " error is modified, created or removed from the IDF project."]
#[doc = ""]
#[doc = " @param code esp_err_t error code"]
#[doc = " @param[out] buf buffer where the error message should be written"]
#[doc = " @param buflen Size of buffer buf. At most buflen bytes are written into the buf buffer (including the terminating null byte)."]
#[doc = " @return buf containing the string error message"]
pub fn esp_err_to_name_r(
code: esp_err_t,
buf: *mut c_types::c_char,
buflen: size_t,
) -> *const c_types::c_char;
}
extern "C" {
#[doc = " @cond"]
pub fn _esp_error_check_failed(
rc: esp_err_t,
file: *const c_types::c_char,
line: c_types::c_int,
function: *const c_types::c_char,
expression: *const c_types::c_char,
);
}
extern "C" {
#[doc = " @cond"]
pub fn _esp_error_check_failed_without_abort(
rc: esp_err_t,
file: *const c_types::c_char,
line: c_types::c_int,
function: *const c_types::c_char,
expression: *const c_types::c_char,
);
}
extern "C" {
#[doc = " Return full IDF version string, same as 'git describe' output."]
#[doc = ""]
#[doc = " @note If you are printing the ESP-IDF version in a log file or other information,"]
#[doc = " this function provides more information than using the numerical version macros."]
#[doc = " For example, numerical version macros don't differentiate between development,"]
#[doc = " pre-release and release versions, but the output of this function does."]
#[doc = ""]
#[doc = " @return constant string from IDF_VER"]
pub fn esp_get_idf_version() -> *const c_types::c_char;
}
pub const esp_mac_type_t_ESP_MAC_WIFI_STA: esp_mac_type_t = 0;
pub const esp_mac_type_t_ESP_MAC_WIFI_SOFTAP: esp_mac_type_t = 1;
pub const esp_mac_type_t_ESP_MAC_BT: esp_mac_type_t = 2;
pub const esp_mac_type_t_ESP_MAC_ETH: esp_mac_type_t = 3;
pub const esp_mac_type_t_ESP_MAC_IEEE802154: esp_mac_type_t = 4;
pub type esp_mac_type_t = c_types::c_uint;
extern "C" {
#[doc = " @brief Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or"]
#[doc = " external storage e.g. flash and EEPROM."]
#[doc = ""]
#[doc = " Base MAC address is used to generate the MAC addresses used by network interfaces."]
#[doc = ""]
#[doc = " If using a custom base MAC address, call this API before initializing any network interfaces."]
#[doc = " Refer to the ESP-IDF Programming Guide for details about how the Base MAC is used."]
#[doc = ""]
#[doc = " @note Base MAC must be a unicast MAC (least significant bit of first byte must be zero)."]
#[doc = ""]
#[doc = " @note If not using a valid OUI, set the \"locally administered\" bit"]
#[doc = " (bit value 0x02 in the first byte) to avoid collisions."]
#[doc = ""]
#[doc = " @param mac base MAC address, length: 6 bytes/8 bytes."]
#[doc = " length: 6 bytes for MAC-48"]
#[doc = " 8 bytes for EUI-64(used for IEEE 802.15.4)"]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
#[doc = " ESP_ERR_INVALID_ARG If mac is NULL or is not a unicast MAC"]
pub fn esp_base_mac_addr_set(mac: *const u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Return base MAC address which is set using esp_base_mac_addr_set."]
#[doc = ""]
#[doc = " @note If no custom Base MAC has been set, this returns the pre-programmed Espressif base MAC address."]
#[doc = ""]
#[doc = " @param mac base MAC address, length: 6 bytes/8 bytes."]
#[doc = " length: 6 bytes for MAC-48"]
#[doc = " 8 bytes for EUI-64(used for IEEE 802.15.4)"]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
#[doc = " ESP_ERR_INVALID_ARG mac is NULL"]
#[doc = " ESP_ERR_INVALID_MAC base MAC address has not been set"]
pub fn esp_base_mac_addr_get(mac: *mut u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Return base MAC address which was previously written to BLK3 of EFUSE."]
#[doc = ""]
#[doc = " Base MAC address is used to generate the MAC addresses used by the networking interfaces."]
#[doc = " This API returns the custom base MAC address which was previously written to EFUSE BLK3 in"]
#[doc = " a specified format."]
#[doc = ""]
#[doc = " Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also"]
#[doc = " possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details."]
#[doc = ""]
#[doc = " @note This function is currently only supported on ESP32."]
#[doc = ""]
#[doc = " @param mac base MAC address, length: 6 bytes/8 bytes."]
#[doc = " length: 6 bytes for MAC-48"]
#[doc = " 8 bytes for EUI-64(used for IEEE 802.15.4)"]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
#[doc = " ESP_ERR_INVALID_ARG mac is NULL"]
#[doc = " ESP_ERR_INVALID_MAC CUSTOM_MAC address has not been set, all zeros (for esp32-xx)"]
#[doc = " ESP_ERR_INVALID_VERSION An invalid MAC version field was read from BLK3 of EFUSE (for esp32)"]
#[doc = " ESP_ERR_INVALID_CRC An invalid MAC CRC was read from BLK3 of EFUSE (for esp32)"]
pub fn esp_efuse_mac_get_custom(mac: *mut u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Return base MAC address which is factory-programmed by Espressif in EFUSE."]
#[doc = ""]
#[doc = " @param mac base MAC address, length: 6 bytes/8 bytes."]
#[doc = " length: 6 bytes for MAC-48"]
#[doc = " 8 bytes for EUI-64(used for IEEE 802.15.4)"]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
#[doc = " ESP_ERR_INVALID_ARG mac is NULL"]
pub fn esp_efuse_mac_get_default(mac: *mut u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Read base MAC address and set MAC address of the interface."]
#[doc = ""]
#[doc = " This function first get base MAC address using esp_base_mac_addr_get()."]
#[doc = " Then calculates the MAC address of the specific interface requested,"]
#[doc = " refer to ESP-IDF Programming Guide for the algorithm."]
#[doc = ""]
#[doc = " @param mac base MAC address, length: 6 bytes/8 bytes."]
#[doc = " length: 6 bytes for MAC-48"]
#[doc = " 8 bytes for EUI-64(used for IEEE 802.15.4)"]
#[doc = " @param type Type of MAC address to return"]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
pub fn esp_read_mac(mac: *mut u8, type_: esp_mac_type_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Derive local MAC address from universal MAC address."]
#[doc = ""]
#[doc = " This function copies a universal MAC address and then sets the \"locally"]
#[doc = " administered\" bit (bit 0x2) in the first octet, creating a locally"]
#[doc = " administered MAC address."]
#[doc = ""]
#[doc = " If the universal MAC address argument is already a locally administered MAC"]
#[doc = " address, then the first octet is XORed with 0x4 in order to create a different"]
#[doc = " locally administered MAC address."]
#[doc = ""]
#[doc = " @param local_mac base MAC address, length: 6 bytes/8 bytes."]
#[doc = " length: 6 bytes for MAC-48"]
#[doc = " 8 bytes for EUI-64(used for IEEE 802.15.4)"]
#[doc = " @param universal_mac Source universal MAC address, length: 6 bytes."]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
pub fn esp_derive_local_mac(local_mac: *mut u8, universal_mac: *const u8) -> esp_err_t;
}
#[doc = "!< ESP32"]
pub const esp_chip_model_t_CHIP_ESP32: esp_chip_model_t = 1;
#[doc = "!< ESP32-S2"]
pub const esp_chip_model_t_CHIP_ESP32S2: esp_chip_model_t = 2;
#[doc = "!< ESP32-S3"]
pub const esp_chip_model_t_CHIP_ESP32S3: esp_chip_model_t = 9;
#[doc = "!< ESP32-C3"]
pub const esp_chip_model_t_CHIP_ESP32C3: esp_chip_model_t = 5;
#[doc = "!< ESP32-H2"]
pub const esp_chip_model_t_CHIP_ESP32H2: esp_chip_model_t = 6;
#[doc = " @brief Chip models"]
pub type esp_chip_model_t = c_types::c_uint;
#[doc = " @brief The structure represents information about the chip"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct esp_chip_info_t {
#[doc = "!< chip model, one of esp_chip_model_t"]
pub model: esp_chip_model_t,
#[doc = "!< bit mask of CHIP_FEATURE_x feature flags"]
pub features: u32,
#[doc = "!< number of CPU cores"]
pub cores: u8,
#[doc = "!< chip revision number"]
pub revision: u8,
}
impl Default for esp_chip_info_t {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
extern "C" {
#[doc = " @brief Fill an esp_chip_info_t structure with information about the chip"]
#[doc = " @param[out] out_info structure to be filled"]
pub fn esp_chip_info(out_info: *mut esp_chip_info_t);
}
extern "C" {
#[doc = " @brief Get one random 32-bit word from hardware RNG"]
#[doc = ""]
#[doc = " If Wi-Fi or Bluetooth are enabled, this function returns true random numbers. In other"]
#[doc = " situations, if true random numbers are required then consult the ESP-IDF Programming"]
#[doc = " Guide \"Random Number Generation\" section for necessary prerequisites."]
#[doc = ""]
#[doc = " This function automatically busy-waits to ensure enough external entropy has been"]
#[doc = " introduced into the hardware RNG state, before returning a new random number. This delay"]
#[doc = " is very short (always less than 100 CPU cycles)."]
#[doc = ""]
#[doc = " @return Random value between 0 and UINT32_MAX"]
pub fn esp_random() -> u32;
}
extern "C" {
#[doc = " @brief Fill a buffer with random bytes from hardware RNG"]
#[doc = ""]
#[doc = " @note This function is implemented via calls to esp_random(), so the same"]
#[doc = " constraints apply."]
#[doc = ""]
#[doc = " @param buf Pointer to buffer to fill with random numbers."]
#[doc = " @param len Length of buffer in bytes"]
pub fn esp_fill_random(buf: *mut c_types::c_void, len: size_t);
}
#[doc = "!< Reset reason can not be determined"]
pub const esp_reset_reason_t_ESP_RST_UNKNOWN: esp_reset_reason_t = 0;
#[doc = "!< Reset due to power-on event"]
pub const esp_reset_reason_t_ESP_RST_POWERON: esp_reset_reason_t = 1;
#[doc = "!< Reset by external pin (not applicable for ESP32)"]
pub const esp_reset_reason_t_ESP_RST_EXT: esp_reset_reason_t = 2;
#[doc = "!< Software reset via esp_restart"]
pub const esp_reset_reason_t_ESP_RST_SW: esp_reset_reason_t = 3;
#[doc = "!< Software reset due to exception/panic"]
pub const esp_reset_reason_t_ESP_RST_PANIC: esp_reset_reason_t = 4;
#[doc = "!< Reset (software or hardware) due to interrupt watchdog"]
pub const esp_reset_reason_t_ESP_RST_INT_WDT: esp_reset_reason_t = 5;
#[doc = "!< Reset due to task watchdog"]
pub const esp_reset_reason_t_ESP_RST_TASK_WDT: esp_reset_reason_t = 6;
#[doc = "!< Reset due to other watchdogs"]
pub const esp_reset_reason_t_ESP_RST_WDT: esp_reset_reason_t = 7;
#[doc = "!< Reset after exiting deep sleep mode"]
pub const esp_reset_reason_t_ESP_RST_DEEPSLEEP: esp_reset_reason_t = 8;
#[doc = "!< Brownout reset (software or hardware)"]
pub const esp_reset_reason_t_ESP_RST_BROWNOUT: esp_reset_reason_t = 9;
#[doc = "!< Reset over SDIO"]
pub const esp_reset_reason_t_ESP_RST_SDIO: esp_reset_reason_t = 10;
#[doc = " @brief Reset reasons"]
pub type esp_reset_reason_t = c_types::c_uint;
#[doc = " Shutdown handler type"]
pub type shutdown_handler_t = ::core::option::Option<unsafe extern "C" fn()>;
extern "C" {
#[doc = " @brief Register shutdown handler"]
#[doc = ""]
#[doc = " This function allows you to register a handler that gets invoked before"]
#[doc = " the application is restarted using esp_restart function."]
#[doc = " @param handle function to execute on restart"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if the handler has already been registered"]
#[doc = " - ESP_ERR_NO_MEM if no more shutdown handler slots are available"]
pub fn esp_register_shutdown_handler(handle: shutdown_handler_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Unregister shutdown handler"]
#[doc = ""]
#[doc = " This function allows you to unregister a handler which was previously"]
#[doc = " registered using esp_register_shutdown_handler function."]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if the given handler hasn't been registered before"]
pub fn esp_unregister_shutdown_handler(handle: shutdown_handler_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Restart PRO and APP CPUs."]
#[doc = ""]
#[doc = " This function can be called both from PRO and APP CPUs."]
#[doc = " After successful restart, CPU reset reason will be SW_CPU_RESET."]
#[doc = " Peripherals (except for WiFi, BT, UART0, SPI1, and legacy timers) are not reset."]
#[doc = " This function does not return."]
pub fn esp_restart();
}
extern "C" {
#[doc = " @brief Get reason of last reset"]
#[doc = " @return See description of esp_reset_reason_t for explanation of each value."]
pub fn esp_reset_reason() -> esp_reset_reason_t;
}
extern "C" {
#[doc = " @brief Get the size of available heap."]
#[doc = ""]
#[doc = " Note that the returned value may be larger than the maximum contiguous block"]
#[doc = " which can be allocated."]
#[doc = ""]
#[doc = " @return Available heap size, in bytes."]
pub fn esp_get_free_heap_size() -> u32;
}
extern "C" {
#[doc = " @brief Get the size of available internal heap."]
#[doc = ""]
#[doc = " Note that the returned value may be larger than the maximum contiguous block"]
#[doc = " which can be allocated."]
#[doc = ""]
#[doc = " @return Available internal heap size, in bytes."]
pub fn esp_get_free_internal_heap_size() -> u32;
}
extern "C" {
#[doc = " @brief Get the minimum heap that has ever been available"]
#[doc = ""]
#[doc = " @return Minimum free heap ever available"]
pub fn esp_get_minimum_free_heap_size() -> u32;
}
extern "C" {
#[doc = " @brief Trigger a software abort"]
#[doc = ""]
#[doc = " @param details Details that will be displayed during panic handling."]
pub fn esp_system_abort(details: *const c_types::c_char);
}
pub const soc_reset_reason_t_RESET_REASON_CHIP_POWER_ON: soc_reset_reason_t = 1;
pub const soc_reset_reason_t_RESET_REASON_CHIP_BROWN_OUT: soc_reset_reason_t = 1;
pub const soc_reset_reason_t_RESET_REASON_CHIP_SUPER_WDT: soc_reset_reason_t = 1;
pub const soc_reset_reason_t_RESET_REASON_CORE_SW: soc_reset_reason_t = 3;
pub const soc_reset_reason_t_RESET_REASON_CORE_DEEP_SLEEP: soc_reset_reason_t = 5;
pub const soc_reset_reason_t_RESET_REASON_CORE_MWDT0: soc_reset_reason_t = 7;
pub const soc_reset_reason_t_RESET_REASON_CORE_MWDT1: soc_reset_reason_t = 8;
pub const soc_reset_reason_t_RESET_REASON_CORE_RTC_WDT: soc_reset_reason_t = 9;
pub const soc_reset_reason_t_RESET_REASON_CPU0_MWDT0: soc_reset_reason_t = 11;
pub const soc_reset_reason_t_RESET_REASON_CPU1_MWDT0: soc_reset_reason_t = 11;
pub const soc_reset_reason_t_RESET_REASON_CPU0_SW: soc_reset_reason_t = 12;
pub const soc_reset_reason_t_RESET_REASON_CPU1_SW: soc_reset_reason_t = 12;
pub const soc_reset_reason_t_RESET_REASON_CPU0_RTC_WDT: soc_reset_reason_t = 13;
pub const soc_reset_reason_t_RESET_REASON_CPU1_RTC_WDT: soc_reset_reason_t = 13;
pub const soc_reset_reason_t_RESET_REASON_SYS_BROWN_OUT: soc_reset_reason_t = 15;
pub const soc_reset_reason_t_RESET_REASON_SYS_RTC_WDT: soc_reset_reason_t = 16;
pub const soc_reset_reason_t_RESET_REASON_CPU0_MWDT1: soc_reset_reason_t = 17;
pub const soc_reset_reason_t_RESET_REASON_CPU1_MWDT1: soc_reset_reason_t = 17;
pub const soc_reset_reason_t_RESET_REASON_SYS_SUPER_WDT: soc_reset_reason_t = 18;
pub const soc_reset_reason_t_RESET_REASON_SYS_CLK_GLITCH: soc_reset_reason_t = 19;
pub const soc_reset_reason_t_RESET_REASON_CORE_EFUSE_CRC: soc_reset_reason_t = 20;
pub const soc_reset_reason_t_RESET_REASON_CORE_USB_UART: soc_reset_reason_t = 21;
pub const soc_reset_reason_t_RESET_REASON_CORE_USB_JTAG: soc_reset_reason_t = 22;
pub const soc_reset_reason_t_RESET_REASON_CORE_PWR_GLITCH: soc_reset_reason_t = 23;
#[doc = " @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}"]
#[doc = " @note refer to TRM: <Reset and Clock> chapter"]
pub type soc_reset_reason_t = c_types::c_uint;
extern "C" {
#[doc = " @brief Print formated string to console device"]
#[doc = " @note float and long long data are not supported!"]
#[doc = ""]
#[doc = " @param fmt Format string"]
#[doc = " @param ... Additional arguments, depending on the format string"]
#[doc = " @return int: Total number of characters written on success; A negative number on failure."]
pub fn esp_rom_printf(fmt: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
#[doc = " @brief Pauses execution for us microseconds"]
#[doc = ""]
#[doc = " @param us Number of microseconds to pause"]
pub fn esp_rom_delay_us(us: u32);
}
extern "C" {
#[doc = " @brief esp_rom_printf can print message to different channels simultaneously."]
#[doc = " This function can help install the low level putc function for esp_rom_printf."]
#[doc = ""]
#[doc = " @param channel Channel number (startting from 1)"]
#[doc = " @param putc Function pointer to the putc implementation. Set NULL can disconnect esp_rom_printf with putc."]
pub fn esp_rom_install_channel_putc(
channel: c_types::c_int,
putc: ::core::option::Option<unsafe extern "C" fn(c: c_types::c_char)>,
);
}
extern "C" {
#[doc = " @brief Install UART1 as the default console channel, equivalent to `esp_rom_install_channel_putc(1, esp_rom_uart_putc)`"]
pub fn esp_rom_install_uart_printf();
}
extern "C" {
#[doc = " @brief Get reset reason of CPU"]
#[doc = ""]
#[doc = " @param cpu_no CPU number"]
#[doc = " @return Reset reason code (see in soc/reset_reasons.h)"]
pub fn esp_rom_get_reset_reason(cpu_no: c_types::c_int) -> soc_reset_reason_t;
}
#[doc = "< return successful in ets"]
pub const ETS_STATUS_ETS_OK: ETS_STATUS = 0;
#[doc = "< return failed in ets"]
pub const ETS_STATUS_ETS_FAILED: ETS_STATUS = 1;
#[doc = " @addtogroup ets_apis"]
#[doc = " @{"]
pub type ETS_STATUS = c_types::c_uint;
#[doc = " @addtogroup ets_apis"]
#[doc = " @{"]
pub use self::ETS_STATUS as ets_status_t;
pub type ETSSignal = u32;
pub type ETSParam = u32;
pub type ETSEvent = ETSEventTag;
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct ETSEventTag {
#[doc = "< Event signal, in same task, different Event with different signal"]
pub sig: ETSSignal,
#[doc = "< Event parameter, sometimes without usage, then will be set as 0"]
pub par: ETSParam,
}
pub type ETSTask = ::core::option::Option<unsafe extern "C" fn(e: *mut ETSEvent)>;
pub type ets_idle_cb_t = ::core::option::Option<unsafe extern "C" fn(arg: *mut c_types::c_void)>;
extern "C" {
#[doc = " @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it."]
#[doc = ""]
#[doc = " @param none"]
#[doc = ""]
#[doc = " @return none"]
pub fn ets_run();
}
extern "C" {
#[doc = " @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep."]
#[doc = ""]
#[doc = " @param ets_idle_cb_t func : The callback function."]
#[doc = ""]
#[doc = " @param void *arg : Argument of the callback."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_set_idle_cb(func: ets_idle_cb_t, arg: *mut c_types::c_void);
}
extern "C" {
#[doc = " @brief Init a task with processer, priority, queue to receive Event, queue length."]
#[doc = ""]
#[doc = " @param ETSTask task : The task processer."]
#[doc = ""]
#[doc = " @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task."]
#[doc = ""]
#[doc = " @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used."]
#[doc = ""]
#[doc = " @param uint8_t qlen : Queue length."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_task(task: ETSTask, prio: u8, queue: *mut ETSEvent, qlen: u8);
}
extern "C" {
#[doc = " @brief Post an event to an Task."]
#[doc = ""]
#[doc = " @param uint8_t prio : Priority of the Task."]
#[doc = ""]
#[doc = " @param ETSSignal sig : Event signal."]
#[doc = ""]
#[doc = " @param ETSParam par : Event parameter"]
#[doc = ""]
#[doc = " @return ETS_OK : post successful"]
#[doc = " @return ETS_FAILED : post failed"]
pub fn ets_post(prio: u8, sig: ETSSignal, par: ETSParam) -> ETS_STATUS;
}
extern "C" {
#[doc = " @addtogroup ets_apis"]
#[doc = " @{"]
pub static exc_cause_table: [*const c_types::c_char; 40usize];
}
extern "C" {
#[doc = " @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed."]
#[doc = " When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL."]
#[doc = ""]
#[doc = " @param uint32_t start : the PRO Entry code address value in uint32_t"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_set_user_start(start: u32);
}
extern "C" {
#[doc = " @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code."]
#[doc = " When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run."]
#[doc = ""]
#[doc = " @param uint32_t callback : the Startup code address value in uint32_t"]
#[doc = ""]
#[doc = " @return None : post successful"]
pub fn ets_set_startup_callback(callback: u32);
}
extern "C" {
#[doc = " @brief Set App cpu Entry code, code can be called in PRO CPU."]
#[doc = " When APP booting is completed, APP CPU will call the Entry code if not NULL."]
#[doc = ""]
#[doc = " @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_set_appcpu_boot_addr(start: u32);
}
extern "C" {
#[doc = " @brief Printf the strings to uart or other devices, similar with printf, simple than printf."]
#[doc = " Can not print float point data format, or longlong data format."]
#[doc = " So we maybe only use this in ROM."]
#[doc = ""]
#[doc = " @param const char *fmt : See printf."]
#[doc = ""]
#[doc = " @param ... : See printf."]
#[doc = ""]
#[doc = " @return int : the length printed to the output device."]
pub fn ets_printf(fmt: *const c_types::c_char, ...) -> c_types::c_int;
}
extern "C" {
#[doc = " @brief Set the uart channel of ets_printf(uart_tx_one_char)."]
#[doc = " ROM will set it base on the efuse and gpio setting, however, this can be changed after booting."]
#[doc = ""]
#[doc = " @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_set_printf_channel(uart_no: u8);
}
extern "C" {
#[doc = " @brief Get the uart channel of ets_printf(uart_tx_one_char)."]
#[doc = ""]
#[doc = " @return uint8_t uart channel used by ets_printf(uart_tx_one_char)."]
pub fn ets_get_printf_channel() -> u8;
}
extern "C" {
#[doc = " @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function."]
#[doc = " Can not print float point data format, or longlong data format"]
#[doc = ""]
#[doc = " @param char c : char to output."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_write_char_uart(c: c_types::c_char);
}
extern "C" {
#[doc = " @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput."]
#[doc = " To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode."]
#[doc = ""]
#[doc = " @param void (*)(char) p: Output function to install."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_install_putc1(p: ::core::option::Option<unsafe extern "C" fn(c: c_types::c_char)>);
}
extern "C" {
#[doc = " @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput."]
#[doc = " To install putc2, which is defaulted installed as NULL."]
#[doc = ""]
#[doc = " @param void (*)(char) p: Output function to install."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_install_putc2(p: ::core::option::Option<unsafe extern "C" fn(c: c_types::c_char)>);
}
extern "C" {
#[doc = " @brief Install putc1 as ets_write_char_uart."]
#[doc = " In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_install_uart_printf();
}
#[doc = " @addtogroup ets_timer_apis"]
#[doc = " @{"]
pub type ETSTimerFunc =
::core::option::Option<unsafe extern "C" fn(timer_arg: *mut c_types::c_void)>;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _ETSTIMER_ {
#[doc = "< timer linker"]
pub timer_next: *mut _ETSTIMER_,
#[doc = "< abstruct time when timer expire"]
pub timer_expire: u32,
#[doc = "< timer period, 0 means timer is not periodic repeated"]
pub timer_period: u32,
#[doc = "< timer handler"]
pub timer_func: ETSTimerFunc,
#[doc = "< timer handler argument"]
pub timer_arg: *mut c_types::c_void,
}
impl Default for _ETSTIMER_ {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
pub type ETSTimer = _ETSTIMER_;
extern "C" {
#[doc = " @brief Init ets timer, this timer range is 640 us to 429496 ms"]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_init();
}
extern "C" {
#[doc = " @brief In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_deinit();
}
extern "C" {
#[doc = " @brief Arm an ets timer, this timer range is 640 us to 429496 ms."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param ETSTimer *timer : Timer struct pointer."]
#[doc = ""]
#[doc = " @param uint32_t tmout : Timer value in ms, range is 1 to 429496."]
#[doc = ""]
#[doc = " @param bool repeat : Timer is periodic repeated."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_arm(timer: *mut ETSTimer, tmout: u32, repeat: bool);
}
extern "C" {
#[doc = " @brief Arm an ets timer, this timer range is 640 us to 429496 ms."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param ETSTimer *timer : Timer struct pointer."]
#[doc = ""]
#[doc = " @param uint32_t tmout : Timer value in us, range is 1 to 429496729."]
#[doc = ""]
#[doc = " @param bool repeat : Timer is periodic repeated."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_arm_us(ptimer: *mut ETSTimer, us: u32, repeat: bool);
}
extern "C" {
#[doc = " @brief Disarm an ets timer."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param ETSTimer *timer : Timer struct pointer."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_disarm(timer: *mut ETSTimer);
}
extern "C" {
#[doc = " @brief Set timer callback and argument."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param ETSTimer *timer : Timer struct pointer."]
#[doc = ""]
#[doc = " @param ETSTimerFunc *pfunction : Timer callback."]
#[doc = ""]
#[doc = " @param void *parg : Timer callback argument."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_setfn(
ptimer: *mut ETSTimer,
pfunction: ETSTimerFunc,
parg: *mut c_types::c_void,
);
}
extern "C" {
#[doc = " @brief Unset timer callback and argument to NULL."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param ETSTimer *timer : Timer struct pointer."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_done(ptimer: *mut ETSTimer);
}
extern "C" {
#[doc = " @brief CPU do while loop for some time."]
#[doc = " In FreeRTOS task, please call FreeRTOS apis."]
#[doc = ""]
#[doc = " @param uint32_t us : Delay time in us."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_delay_us(us: u32);
}
extern "C" {
#[doc = " @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate."]
#[doc = " Call this function when CPU frequency is changed."]
#[doc = ""]
#[doc = " @param uint32_t ticks_per_us : CPU ticks per us."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_update_cpu_frequency(ticks_per_us: u32);
}
extern "C" {
#[doc = " @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate."]
#[doc = ""]
#[doc = " @note This function only sets the tick rate for the current CPU. It is located in ROM,"]
#[doc = " so the deep sleep stub can use it even if IRAM is not initialized yet."]
#[doc = ""]
#[doc = " @param uint32_t ticks_per_us : CPU ticks per us."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_update_cpu_frequency_rom(ticks_per_us: u32);
}
extern "C" {
#[doc = " @brief Get the real CPU ticks per us to the ets."]
#[doc = " This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : CPU ticks per us record in ets."]
pub fn ets_get_cpu_frequency() -> u32;
}
extern "C" {
#[doc = " @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : if stored in efuse(not 0)"]
#[doc = " clock = ets_efuse_get_xtal_freq() * 1000000;"]
#[doc = " else if analog_8M in efuse"]
#[doc = " clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock();"]
#[doc = " else clock = 40M."]
pub fn ets_get_xtal_freq() -> u32;
}
extern "C" {
#[doc = " @brief Get the apb divisor. The xtal frequency gets divided"]
#[doc = " by this value to generate the APB clock."]
#[doc = " When any types of reset happens, the default value is 2."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : 1 or 2."]
pub fn ets_get_xtal_div() -> u32;
}
extern "C" {
#[doc = " @brief Modifies the apb divisor. The xtal frequency gets divided by this to"]
#[doc = " generate the APB clock."]
#[doc = ""]
#[doc = " @note The xtal frequency divisor is 2 by default as the glitch detector"]
#[doc = " doesn't properly stop glitches when it is 1. Please do not set the"]
#[doc = " divisor to 1 before the PLL is active without being aware that you"]
#[doc = " may be introducing a security risk."]
#[doc = ""]
#[doc = " @param div Divisor. 1 = xtal freq, 2 = 1/2th xtal freq."]
pub fn ets_set_xtal_div(div: c_types::c_int);
}
extern "C" {
#[doc = " @brief Get apb_freq value, If value not stored in RTC_STORE5, than store."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register."]
#[doc = " clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;"]
#[doc = " else store ets_get_detected_xtal_freq() in."]
pub fn ets_get_apb_freq() -> u32;
}
#[doc = " @addtogroup ets_intr_apis"]
#[doc = " @{"]
pub type ets_isr_t = ::core::option::Option<unsafe extern "C" fn(arg1: *mut c_types::c_void)>;
extern "C" {
#[doc = " @brief Attach a interrupt handler to a CPU interrupt number."]
#[doc = " This function equals to _xtos_set_interrupt_handler_arg(i, func, arg)."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param int i : CPU interrupt number."]
#[doc = ""]
#[doc = " @param ets_isr_t func : Interrupt handler."]
#[doc = ""]
#[doc = " @param void *arg : argument of the handler."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_isr_attach(i: c_types::c_int, func: ets_isr_t, arg: *mut c_types::c_void);
}
extern "C" {
#[doc = " @brief Mask the interrupts which show in mask bits."]
#[doc = " This function equals to _xtos_ints_off(mask)."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param uint32_t mask : BIT(i) means mask CPU interrupt number i."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_isr_mask(mask: u32);
}
extern "C" {
#[doc = " @brief Unmask the interrupts which show in mask bits."]
#[doc = " This function equals to _xtos_ints_on(mask)."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param uint32_t mask : BIT(i) means mask CPU interrupt number i."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_isr_unmask(unmask: u32);
}
extern "C" {
#[doc = " @brief Lock the interrupt to level 2."]
#[doc = " This function direct set the CPU registers."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_intr_lock();
}
extern "C" {
#[doc = " @brief Unlock the interrupt to level 0."]
#[doc = " This function direct set the CPU registers."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_intr_unlock();
}
extern "C" {
#[doc = " @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt)."]
#[doc = " This function direct set the CPU registers."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_waiti0();
}
extern "C" {
#[doc = " @brief Attach an CPU interrupt to a hardware source."]
#[doc = " We have 4 steps to use an interrupt:"]
#[doc = " 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);"]
#[doc = " 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);"]
#[doc = " 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);"]
#[doc = " 4.Enable interrupt in the module."]
#[doc = ""]
#[doc = " @param int cpu_no : The CPU which the interrupt number belongs."]
#[doc = ""]
#[doc = " @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table."]
#[doc = ""]
#[doc = " @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table."]
#[doc = ""]
#[doc = " @return None"]
pub fn intr_matrix_set(cpu_no: c_types::c_int, model_num: u32, intr_num: u32);
}
pub const STATUS_OK: STATUS = 0;
pub const STATUS_FAIL: STATUS = 1;
pub const STATUS_PENDING: STATUS = 2;
pub const STATUS_BUSY: STATUS = 3;
pub const STATUS_CANCEL: STATUS = 4;
pub type STATUS = c_types::c_uint;
#[doc = "< No log output"]
pub const esp_log_level_t_ESP_LOG_NONE: esp_log_level_t = 0;
#[doc = "< Critical errors, software module can not recover on its own"]
pub const esp_log_level_t_ESP_LOG_ERROR: esp_log_level_t = 1;
#[doc = "< Error conditions from which recovery measures have been taken"]
pub const esp_log_level_t_ESP_LOG_WARN: esp_log_level_t = 2;
#[doc = "< Information messages which describe normal flow of events"]
pub const esp_log_level_t_ESP_LOG_INFO: esp_log_level_t = 3;
#[doc = "< Extra information which is not necessary for normal use (values, pointers, sizes, etc)."]
pub const esp_log_level_t_ESP_LOG_DEBUG: esp_log_level_t = 4;
#[doc = "< Bigger chunks of debugging information, or frequent messages which can potentially flood the output."]
pub const esp_log_level_t_ESP_LOG_VERBOSE: esp_log_level_t = 5;
#[doc = " @brief Log level"]
#[doc = ""]
pub type esp_log_level_t = c_types::c_uint;
pub type vprintf_like_t = ::core::option::Option<
unsafe extern "C" fn(arg1: *const c_types::c_char, arg2: va_list) -> c_types::c_int,
>;
extern "C" {
#[doc = " @brief Default log level"]
#[doc = ""]
#[doc = " This is used by the definition of ESP_EARLY_LOGx macros. It is not"]
#[doc = " recommended to set this directly, call esp_log_level_set(\"*\", level)"]
#[doc = " instead."]
pub static mut esp_log_default_level: esp_log_level_t;
}
extern "C" {
#[doc = " @brief Set log level for given tag"]
#[doc = ""]
#[doc = " If logging for given component has already been enabled, changes previous setting."]
#[doc = ""]
#[doc = " Note that this function can not raise log level above the level set using"]
#[doc = " CONFIG_LOG_MAXIMUM_LEVEL setting in menuconfig."]
#[doc = ""]
#[doc = " To raise log level above the default one for a given file, define"]
#[doc = " LOG_LOCAL_LEVEL to one of the ESP_LOG_* values, before including"]
#[doc = " esp_log.h in this file."]
#[doc = ""]
#[doc = " @param tag Tag of the log entries to enable. Must be a non-NULL zero terminated string."]
#[doc = " Value \"*\" resets log level for all tags to the given value."]
#[doc = ""]
#[doc = " @param level Selects log level to enable. Only logs at this and lower verbosity"]
#[doc = " levels will be shown."]
pub fn esp_log_level_set(tag: *const c_types::c_char, level: esp_log_level_t);
}
extern "C" {
#[doc = " @brief Get log level for given tag, can be used to avoid expensive log statements"]
#[doc = ""]
#[doc = " @param tag Tag of the log to query current level. Must be a non-NULL zero terminated"]
#[doc = " string."]
#[doc = ""]
#[doc = " @return The current log level for the given tag"]
pub fn esp_log_level_get(tag: *const c_types::c_char) -> esp_log_level_t;
}
extern "C" {
#[doc = " @brief Set function used to output log entries"]
#[doc = ""]
#[doc = " By default, log output goes to UART0. This function can be used to redirect log"]
#[doc = " output to some other destination, such as file or network. Returns the original"]
#[doc = " log handler, which may be necessary to return output to the previous destination."]
#[doc = ""]
#[doc = " @note Please note that function callback here must be re-entrant as it can be"]
#[doc = " invoked in parallel from multiple thread context."]
#[doc = ""]
#[doc = " @param func new Function used for output. Must have same signature as vprintf."]
#[doc = ""]
#[doc = " @return func old Function used for output."]
pub fn esp_log_set_vprintf(func: vprintf_like_t) -> vprintf_like_t;
}
extern "C" {
#[doc = " @brief Function which returns timestamp to be used in log output"]
#[doc = ""]
#[doc = " This function is used in expansion of ESP_LOGx macros."]
#[doc = " In the 2nd stage bootloader, and at early application startup stage"]
#[doc = " this function uses CPU cycle counter as time source. Later when"]
#[doc = " FreeRTOS scheduler start running, it switches to FreeRTOS tick count."]
#[doc = ""]
#[doc = " For now, we ignore millisecond counter overflow."]
#[doc = ""]
#[doc = " @return timestamp, in milliseconds"]
pub fn esp_log_timestamp() -> u32;
}
extern "C" {
#[doc = " @brief Function which returns system timestamp to be used in log output"]
#[doc = ""]
#[doc = " This function is used in expansion of ESP_LOGx macros to print"]
#[doc = " the system time as \"HH:MM:SS.sss\". The system time is initialized to"]
#[doc = " 0 on startup, this can be set to the correct time with an SNTP sync,"]
#[doc = " or manually with standard POSIX time functions."]
#[doc = ""]
#[doc = " Currently this will not get used in logging from binary blobs"]
#[doc = " (i.e WiFi & Bluetooth libraries), these will still print the RTOS tick time."]
#[doc = ""]
#[doc = " @return timestamp, in \"HH:MM:SS.sss\""]
pub fn esp_log_system_timestamp() -> *mut c_types::c_char;
}
extern "C" {
#[doc = " @brief Function which returns timestamp to be used in log output"]
#[doc = ""]
#[doc = " This function uses HW cycle counter and does not depend on OS,"]
#[doc = " so it can be safely used after application crash."]
#[doc = ""]
#[doc = " @return timestamp, in milliseconds"]
pub fn esp_log_early_timestamp() -> u32;
}
extern "C" {
#[doc = " @brief Write message into the log"]
#[doc = ""]
#[doc = " This function is not intended to be used directly. Instead, use one of"]
#[doc = " ESP_LOGE, ESP_LOGW, ESP_LOGI, ESP_LOGD, ESP_LOGV macros."]
#[doc = ""]
#[doc = " This function or these macros should not be used from an interrupt."]
pub fn esp_log_write(
level: esp_log_level_t,
tag: *const c_types::c_char,
format: *const c_types::c_char,
...
);
}
extern "C" {
pub fn esp_log_buffer_hex_internal(
tag: *const c_types::c_char,
buffer: *const c_types::c_void,
buff_len: u16,
level: esp_log_level_t,
);
}
extern "C" {
pub fn esp_log_buffer_char_internal(
tag: *const c_types::c_char,
buffer: *const c_types::c_void,
buff_len: u16,
level: esp_log_level_t,
);
}
extern "C" {
pub fn esp_log_buffer_hexdump_internal(
tag: *const c_types::c_char,
buffer: *const c_types::c_void,
buff_len: u16,
log_level: esp_log_level_t,
);
}
pub const watchpoint_trigger_t_WATCHPOINT_TRIGGER_ON_RO: watchpoint_trigger_t = 0;
pub const watchpoint_trigger_t_WATCHPOINT_TRIGGER_ON_WO: watchpoint_trigger_t = 1;
pub const watchpoint_trigger_t_WATCHPOINT_TRIGGER_ON_RW: watchpoint_trigger_t = 2;
pub type watchpoint_trigger_t = c_types::c_uint;
extern "C" {
pub static Xthal_rev_no: c_types::c_uint;
}
extern "C" {
pub fn xthal_save_extra(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_restore_extra(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_save_cpregs(base: *mut c_types::c_void, arg1: c_types::c_int);
}
extern "C" {
pub fn xthal_restore_cpregs(base: *mut c_types::c_void, arg1: c_types::c_int);
}
extern "C" {
pub fn xthal_save_cp0(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_save_cp1(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_save_cp2(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_save_cp3(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_save_cp4(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_save_cp5(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_save_cp6(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_save_cp7(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_restore_cp0(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_restore_cp1(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_restore_cp2(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_restore_cp3(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_restore_cp4(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_restore_cp5(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_restore_cp6(base: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_restore_cp7(base: *mut c_types::c_void);
}
extern "C" {
pub static mut Xthal_cpregs_save_fn: [*mut c_types::c_void; 8usize];
}
extern "C" {
pub static mut Xthal_cpregs_restore_fn: [*mut c_types::c_void; 8usize];
}
extern "C" {
pub static mut Xthal_cpregs_save_nw_fn: [*mut c_types::c_void; 8usize];
}
extern "C" {
pub static mut Xthal_cpregs_restore_nw_fn: [*mut c_types::c_void; 8usize];
}
extern "C" {
pub static Xthal_extra_size: c_types::c_uint;
}
extern "C" {
pub static Xthal_extra_align: c_types::c_uint;
}
extern "C" {
pub static Xthal_cpregs_size: [c_types::c_uint; 8usize];
}
extern "C" {
pub static Xthal_cpregs_align: [c_types::c_uint; 8usize];
}
extern "C" {
pub static Xthal_all_extra_size: c_types::c_uint;
}
extern "C" {
pub static Xthal_all_extra_align: c_types::c_uint;
}
extern "C" {
pub static Xthal_cp_names: [*const c_types::c_char; 8usize];
}
extern "C" {
pub fn xthal_init_mem_extra(arg1: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_init_mem_cp(arg1: *mut c_types::c_void, arg2: c_types::c_int);
}
extern "C" {
pub static Xthal_num_coprocessors: c_types::c_uint;
}
extern "C" {
pub static Xthal_cp_num: c_types::c_uchar;
}
extern "C" {
pub static Xthal_cp_max: c_types::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask: c_types::c_uint;
}
extern "C" {
pub static Xthal_num_aregs: c_types::c_uint;
}
extern "C" {
pub static Xthal_num_aregs_log2: c_types::c_uchar;
}
extern "C" {
pub static Xthal_icache_linewidth: c_types::c_uchar;
}
extern "C" {
pub static Xthal_dcache_linewidth: c_types::c_uchar;
}
extern "C" {
pub static Xthal_icache_linesize: c_types::c_ushort;
}
extern "C" {
pub static Xthal_dcache_linesize: c_types::c_ushort;
}
extern "C" {
pub static Xthal_icache_size: c_types::c_uint;
}
extern "C" {
pub static Xthal_dcache_size: c_types::c_uint;
}
extern "C" {
pub static Xthal_dcache_is_writeback: c_types::c_uchar;
}
extern "C" {
pub fn xthal_icache_region_invalidate(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_dcache_region_invalidate(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_dcache_region_writeback(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_dcache_region_writeback_inv(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_icache_line_invalidate(addr: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_dcache_line_invalidate(addr: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_dcache_line_writeback(addr: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_dcache_line_writeback_inv(addr: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_icache_sync();
}
extern "C" {
pub fn xthal_dcache_sync();
}
extern "C" {
pub fn xthal_icache_get_ways() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_icache_set_ways(ways: c_types::c_uint);
}
extern "C" {
pub fn xthal_dcache_get_ways() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_dcache_set_ways(ways: c_types::c_uint);
}
extern "C" {
pub fn xthal_cache_coherence_on();
}
extern "C" {
pub fn xthal_cache_coherence_off();
}
extern "C" {
pub fn xthal_cache_coherence_optin();
}
extern "C" {
pub fn xthal_cache_coherence_optout();
}
extern "C" {
pub fn xthal_get_cache_prefetch() -> c_types::c_int;
}
extern "C" {
pub fn xthal_set_cache_prefetch(arg1: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn xthal_set_cache_prefetch_long(arg1: c_types::c_ulonglong) -> c_types::c_int;
}
extern "C" {
pub static Xthal_debug_configured: c_types::c_int;
}
extern "C" {
pub fn xthal_set_soft_break(addr: *mut c_types::c_void) -> c_types::c_uint;
}
extern "C" {
pub fn xthal_remove_soft_break(addr: *mut c_types::c_void, arg1: c_types::c_uint);
}
extern "C" {
pub fn xthal_disassemble(
instr_buf: *mut c_types::c_uchar,
tgt_addr: *mut c_types::c_void,
buffer: *mut c_types::c_char,
buflen: c_types::c_uint,
options: c_types::c_uint,
) -> c_types::c_int;
}
extern "C" {
pub fn xthal_disassemble_size(instr_buf: *mut c_types::c_uchar) -> c_types::c_int;
}
extern "C" {
pub fn xthal_memcpy(
dst: *mut c_types::c_void,
src: *const c_types::c_void,
len: c_types::c_uint,
) -> *mut c_types::c_void;
}
extern "C" {
pub fn xthal_bcopy(
src: *const c_types::c_void,
dst: *mut c_types::c_void,
len: c_types::c_uint,
) -> *mut c_types::c_void;
}
extern "C" {
pub fn xthal_compare_and_set(
addr: *mut c_types::c_int,
test_val: c_types::c_int,
compare_val: c_types::c_int,
) -> c_types::c_int;
}
extern "C" {
pub static Xthal_release_major: c_types::c_uint;
}
extern "C" {
pub static Xthal_release_minor: c_types::c_uint;
}
extern "C" {
pub static Xthal_release_name: *const c_types::c_char;
}
extern "C" {
pub static Xthal_release_internal: *const c_types::c_char;
}
extern "C" {
pub static Xthal_memory_order: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_windowed: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_density: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_booleans: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_loops: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_nsa: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_minmax: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_sext: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_clamps: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_mac16: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_mul16: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_fp: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_speculation: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_threadptr: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_pif: c_types::c_uchar;
}
extern "C" {
pub static Xthal_num_writebuffer_entries: c_types::c_ushort;
}
extern "C" {
pub static Xthal_build_unique_id: c_types::c_uint;
}
extern "C" {
pub static Xthal_hw_configid0: c_types::c_uint;
}
extern "C" {
pub static Xthal_hw_configid1: c_types::c_uint;
}
extern "C" {
pub static Xthal_hw_release_major: c_types::c_uint;
}
extern "C" {
pub static Xthal_hw_release_minor: c_types::c_uint;
}
extern "C" {
pub static Xthal_hw_release_name: *const c_types::c_char;
}
extern "C" {
pub static Xthal_hw_release_internal: *const c_types::c_char;
}
extern "C" {
pub fn xthal_clear_regcached_code();
}
extern "C" {
pub fn xthal_window_spill();
}
extern "C" {
pub fn xthal_validate_cp(arg1: c_types::c_int);
}
extern "C" {
pub fn xthal_invalidate_cp(arg1: c_types::c_int);
}
extern "C" {
pub fn xthal_set_cpenable(arg1: c_types::c_uint);
}
extern "C" {
pub fn xthal_get_cpenable() -> c_types::c_uint;
}
extern "C" {
pub static Xthal_num_intlevels: c_types::c_uchar;
}
extern "C" {
pub static Xthal_num_interrupts: c_types::c_uchar;
}
extern "C" {
pub static Xthal_excm_level: c_types::c_uchar;
}
extern "C" {
pub static Xthal_intlevel_mask: [c_types::c_uint; 16usize];
}
extern "C" {
pub static Xthal_intlevel_andbelow_mask: [c_types::c_uint; 16usize];
}
extern "C" {
pub static Xthal_intlevel: [c_types::c_uchar; 32usize];
}
extern "C" {
pub static Xthal_inttype: [c_types::c_uchar; 32usize];
}
extern "C" {
pub static Xthal_inttype_mask: [c_types::c_uint; 11usize];
}
extern "C" {
pub static Xthal_timer_interrupt: [c_types::c_int; 4usize];
}
extern "C" {
pub fn xthal_get_intenable() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_set_intenable(arg1: c_types::c_uint);
}
extern "C" {
pub fn xthal_get_interrupt() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_set_intset(arg1: c_types::c_uint);
}
extern "C" {
pub fn xthal_set_intclear(arg1: c_types::c_uint);
}
extern "C" {
pub static Xthal_num_ibreak: c_types::c_int;
}
extern "C" {
pub static Xthal_num_dbreak: c_types::c_int;
}
extern "C" {
pub static Xthal_have_ccount: c_types::c_uchar;
}
extern "C" {
pub static Xthal_num_ccompare: c_types::c_uchar;
}
extern "C" {
pub fn xthal_get_ccount() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_set_ccompare(arg1: c_types::c_int, arg2: c_types::c_uint);
}
extern "C" {
pub fn xthal_get_ccompare(arg1: c_types::c_int) -> c_types::c_uint;
}
extern "C" {
pub static Xthal_have_prid: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_exceptions: c_types::c_uchar;
}
extern "C" {
pub static Xthal_xea_version: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_interrupts: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_highlevel_interrupts: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_nmi: c_types::c_uchar;
}
extern "C" {
pub fn xthal_get_prid() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_vpri_to_intlevel(vpri: c_types::c_uint) -> c_types::c_uint;
}
extern "C" {
pub fn xthal_intlevel_to_vpri(intlevel: c_types::c_uint) -> c_types::c_uint;
}
extern "C" {
pub fn xthal_int_enable(arg1: c_types::c_uint) -> c_types::c_uint;
}
extern "C" {
pub fn xthal_int_disable(arg1: c_types::c_uint) -> c_types::c_uint;
}
extern "C" {
pub fn xthal_set_int_vpri(intnum: c_types::c_int, vpri: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn xthal_get_int_vpri(intnum: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn xthal_set_vpri_locklevel(intlevel: c_types::c_uint);
}
extern "C" {
pub fn xthal_get_vpri_locklevel() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_set_vpri(vpri: c_types::c_uint) -> c_types::c_uint;
}
extern "C" {
pub fn xthal_get_vpri() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_set_vpri_intlevel(intlevel: c_types::c_uint) -> c_types::c_uint;
}
extern "C" {
pub fn xthal_set_vpri_lock() -> c_types::c_uint;
}
pub type XtHalVoidFunc = ::core::option::Option<unsafe extern "C" fn()>;
extern "C" {
pub static mut Xthal_tram_pending: c_types::c_uint;
}
extern "C" {
pub static mut Xthal_tram_enabled: c_types::c_uint;
}
extern "C" {
pub static mut Xthal_tram_sync: c_types::c_uint;
}
extern "C" {
pub fn xthal_tram_pending_to_service() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_tram_done(serviced_mask: c_types::c_uint);
}
extern "C" {
pub fn xthal_tram_set_sync(intnum: c_types::c_int, sync: c_types::c_int) -> c_types::c_int;
}
extern "C" {
pub fn xthal_set_tram_trigger_func(trigger_fn: XtHalVoidFunc) -> XtHalVoidFunc;
}
extern "C" {
pub static Xthal_num_instrom: c_types::c_uchar;
}
extern "C" {
pub static Xthal_num_instram: c_types::c_uchar;
}
extern "C" {
pub static Xthal_num_datarom: c_types::c_uchar;
}
extern "C" {
pub static Xthal_num_dataram: c_types::c_uchar;
}
extern "C" {
pub static Xthal_num_xlmi: c_types::c_uchar;
}
extern "C" {
pub static mut Xthal_instrom_vaddr: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_instrom_paddr: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_instrom_size: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_instram_vaddr: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_instram_paddr: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_instram_size: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_datarom_vaddr: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_datarom_paddr: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_datarom_size: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_dataram_vaddr: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_dataram_paddr: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_dataram_size: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_xlmi_vaddr: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_xlmi_paddr: [c_types::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_xlmi_size: [c_types::c_uint; 0usize];
}
extern "C" {
pub static Xthal_icache_setwidth: c_types::c_uchar;
}
extern "C" {
pub static Xthal_dcache_setwidth: c_types::c_uchar;
}
extern "C" {
pub static Xthal_icache_ways: c_types::c_uint;
}
extern "C" {
pub static Xthal_dcache_ways: c_types::c_uint;
}
extern "C" {
pub static Xthal_icache_line_lockable: c_types::c_uchar;
}
extern "C" {
pub static Xthal_dcache_line_lockable: c_types::c_uchar;
}
extern "C" {
pub fn xthal_get_cacheattr() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_get_icacheattr() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_get_dcacheattr() -> c_types::c_uint;
}
extern "C" {
pub fn xthal_set_cacheattr(arg1: c_types::c_uint);
}
extern "C" {
pub fn xthal_set_icacheattr(arg1: c_types::c_uint);
}
extern "C" {
pub fn xthal_set_dcacheattr(arg1: c_types::c_uint);
}
extern "C" {
pub fn xthal_set_region_attribute(
addr: *mut c_types::c_void,
size: c_types::c_uint,
cattr: c_types::c_uint,
flags: c_types::c_uint,
) -> c_types::c_int;
}
extern "C" {
pub fn xthal_icache_enable();
}
extern "C" {
pub fn xthal_dcache_enable();
}
extern "C" {
pub fn xthal_icache_disable();
}
extern "C" {
pub fn xthal_dcache_disable();
}
extern "C" {
pub fn xthal_icache_all_invalidate();
}
extern "C" {
pub fn xthal_dcache_all_invalidate();
}
extern "C" {
pub fn xthal_dcache_all_writeback();
}
extern "C" {
pub fn xthal_dcache_all_writeback_inv();
}
extern "C" {
pub fn xthal_icache_all_unlock();
}
extern "C" {
pub fn xthal_dcache_all_unlock();
}
extern "C" {
pub fn xthal_icache_region_lock(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_dcache_region_lock(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_icache_region_unlock(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_dcache_region_unlock(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_icache_hugerange_invalidate(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_icache_hugerange_unlock(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_dcache_hugerange_invalidate(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_dcache_hugerange_unlock(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_dcache_hugerange_writeback(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_dcache_hugerange_writeback_inv(addr: *mut c_types::c_void, size: c_types::c_uint);
}
extern "C" {
pub fn xthal_icache_line_lock(addr: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_dcache_line_lock(addr: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_icache_line_unlock(addr: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_dcache_line_unlock(addr: *mut c_types::c_void);
}
extern "C" {
pub fn xthal_memep_inject_error(
addr: *mut c_types::c_void,
size: c_types::c_int,
flags: c_types::c_int,
);
}
extern "C" {
pub static Xthal_have_spanning_way: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_identity_map: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_mimic_cacheattr: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_xlt_cacheattr: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_cacheattr: c_types::c_uchar;
}
extern "C" {
pub static Xthal_have_tlbs: c_types::c_uchar;
}
extern "C" {
pub static Xthal_mmu_asid_bits: c_types::c_uchar;
}
extern "C" {
pub static Xthal_mmu_asid_kernel: c_types::c_uchar;
}
extern "C" {
pub static Xthal_mmu_rings: c_types::c_uchar;
}
extern "C" {
pub static Xthal_mmu_ring_bits: c_types::c_uchar;
}
extern "C" {
pub static Xthal_mmu_sr_bits: c_types::c_uchar;
}
extern "C" {
pub static Xthal_mmu_ca_bits: c_types::c_uchar;
}
extern "C" {
pub static Xthal_mmu_max_pte_page_size: c_types::c_uint;
}
extern "C" {
pub static Xthal_mmu_min_pte_page_size: c_types::c_uint;
}
extern "C" {
pub static Xthal_itlb_way_bits: c_types::c_uchar;
}
extern "C" {
pub static Xthal_itlb_ways: c_types::c_uchar;
}
extern "C" {
pub static Xthal_itlb_arf_ways: c_types::c_uchar;
}
extern "C" {
pub static Xthal_dtlb_way_bits: c_types::c_uchar;
}
extern "C" {
pub static Xthal_dtlb_ways: c_types::c_uchar;
}
extern "C" {
pub static Xthal_dtlb_arf_ways: c_types::c_uchar;
}
extern "C" {
pub fn xthal_static_v2p(vaddr: c_types::c_uint, paddrp: *mut c_types::c_uint)
-> c_types::c_int;
}
extern "C" {
pub fn xthal_static_p2v(
paddr: c_types::c_uint,
vaddrp: *mut c_types::c_uint,
cached: c_types::c_uint,
) -> c_types::c_int;
}
extern "C" {
pub fn xthal_set_region_translation(
vaddr: *mut c_types::c_void,
paddr: *mut c_types::c_void,
size: c_types::c_uint,
cache_atr: c_types::c_uint,
flags: c_types::c_uint,
) -> c_types::c_int;
}
extern "C" {
pub fn xthal_v2p(
arg1: *mut c_types::c_void,
arg2: *mut *mut c_types::c_void,
arg3: *mut c_types::c_uint,
arg4: *mut c_types::c_uint,
) -> c_types::c_int;
}
extern "C" {
pub fn xthal_invalidate_region(addr: *mut c_types::c_void) -> c_types::c_int;
}
extern "C" {
pub fn xthal_set_region_translation_raw(
vaddr: *mut c_types::c_void,
paddr: *mut c_types::c_void,
cattr: c_types::c_uint,
) -> c_types::c_int;
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct xthal_MPU_entry {
pub as_: u32,
pub at: u32,
}
extern "C" {
pub static mut Xthal_mpu_bgmap: [xthal_MPU_entry; 0usize];
}
extern "C" {
pub fn xthal_is_kernel_readable(accessRights: u32) -> i32;
}
extern "C" {
pub fn xthal_is_kernel_writeable(accessRights: u32) -> i32;
}
extern "C" {
pub fn xthal_is_kernel_executable(accessRights: u32) -> i32;
}
extern "C" {
pub fn xthal_is_user_readable(accessRights: u32) -> i32;
}
extern "C" {
pub fn xthal_is_user_writeable(accessRights: u32) -> i32;
}
extern "C" {
pub fn xthal_is_user_executable(accessRights: u32) -> i32;
}
extern "C" {
pub fn xthal_encode_memory_type(x: u32) -> c_types::c_int;
}
extern "C" {
pub fn xthal_is_cacheable(memoryType: u32) -> i32;
}
extern "C" {
pub fn xthal_is_writeback(memoryType: u32) -> i32;
}
extern "C" {
pub fn xthal_is_device(memoryType: u32) -> i32;
}
extern "C" {
pub fn xthal_read_map(entries: *mut xthal_MPU_entry) -> i32;
}
extern "C" {
pub fn xthal_write_map(entries: *const xthal_MPU_entry, n: u32);
}
extern "C" {
pub fn xthal_check_map(entries: *const xthal_MPU_entry, n: u32) -> c_types::c_int;
}
extern "C" {
pub fn xthal_get_entry_for_address(
vaddr: *mut c_types::c_void,
infgmap: *mut i32,
) -> xthal_MPU_entry;
}
extern "C" {
pub fn xthal_calc_cacheadrdis(e: *const xthal_MPU_entry, n: u32) -> u32;
}
extern "C" {
pub fn xthal_mpu_set_region_attribute(
vaddr: *mut c_types::c_void,
size: size_t,
accessRights: i32,
memoryType: i32,
flags: u32,
) -> c_types::c_int;
}
extern "C" {
pub fn xthal_read_background_map(entries: *mut xthal_MPU_entry) -> i32;
}
extern "C" {
pub static Xthal_cp_id_FPU: c_types::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_FPU: c_types::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP1_IDENT: c_types::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP1_IDENT: c_types::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP2_IDENT: c_types::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP2_IDENT: c_types::c_uint;
}
extern "C" {
pub static Xthal_cp_id_cop_ai: c_types::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_cop_ai: c_types::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP4_IDENT: c_types::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP4_IDENT: c_types::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP5_IDENT: c_types::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP5_IDENT: c_types::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP6_IDENT: c_types::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP6_IDENT: c_types::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP7_IDENT: c_types::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP7_IDENT: c_types::c_uint;
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct KernelFrame {
pub pc: c_types::c_long,
pub ps: c_types::c_long,
pub areg: [c_types::c_long; 4usize],
pub sar: c_types::c_long,
pub lcount: c_types::c_long,
pub lbeg: c_types::c_long,
pub lend: c_types::c_long,
pub acclo: c_types::c_long,
pub acchi: c_types::c_long,
pub mr: [c_types::c_long; 4usize],
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct UserFrame {
pub pc: c_types::c_long,
pub ps: c_types::c_long,
pub sar: c_types::c_long,
pub vpri: c_types::c_long,
pub a2: c_types::c_long,
pub a3: c_types::c_long,
pub a4: c_types::c_long,
pub a5: c_types::c_long,
pub exccause: c_types::c_long,
pub lcount: c_types::c_long,
pub lbeg: c_types::c_long,
pub lend: c_types::c_long,
pub acclo: c_types::c_long,
pub acchi: c_types::c_long,
pub mr: [c_types::c_long; 4usize],
pub pad: [c_types::c_long; 2usize],
}
#[repr(C)]
#[repr(align(16))]
#[derive(Debug, Copy, Clone)]
pub struct XtosCoreState {
pub signature: c_types::c_long,
pub restore_label: c_types::c_long,
pub aftersave_label: c_types::c_long,
pub areg: [c_types::c_long; 64usize],
pub caller_regs: [c_types::c_long; 16usize],
pub caller_regs_saved: c_types::c_long,
pub windowbase: c_types::c_long,
pub windowstart: c_types::c_long,
pub sar: c_types::c_long,
pub epc1: c_types::c_long,
pub ps: c_types::c_long,
pub excsave1: c_types::c_long,
pub depc: c_types::c_long,
pub epc: [c_types::c_long; 6usize],
pub eps: [c_types::c_long; 6usize],
pub excsave: [c_types::c_long; 6usize],
pub lcount: c_types::c_long,
pub lbeg: c_types::c_long,
pub lend: c_types::c_long,
pub vecbase: c_types::c_long,
pub atomctl: c_types::c_long,
pub memctl: c_types::c_long,
pub ccount: c_types::c_long,
pub ccompare: [c_types::c_long; 3usize],
pub intenable: c_types::c_long,
pub interrupt: c_types::c_long,
pub icount: c_types::c_long,
pub icountlevel: c_types::c_long,
pub debugcause: c_types::c_long,
pub dbreakc: [c_types::c_long; 2usize],
pub dbreaka: [c_types::c_long; 2usize],
pub ibreaka: [c_types::c_long; 2usize],
pub ibreakenable: c_types::c_long,
pub misc: [c_types::c_long; 4usize],
pub cpenable: c_types::c_long,
pub tlbs: [c_types::c_long; 16usize],
pub ncp: [c_types::c_char; 36usize],
pub cp0: [c_types::c_char; 72usize],
pub __bindgen_padding_0: [u8; 4usize],
pub cp3: [c_types::c_char; 208usize],
}
impl Default for XtosCoreState {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
pub type _xtos_handler_func = ::core::option::Option<unsafe extern "C" fn()>;
pub type _xtos_handler = _xtos_handler_func;
extern "C" {
pub fn _xtos_ints_off(mask: c_types::c_uint) -> c_types::c_uint;
}
extern "C" {
pub fn _xtos_ints_on(mask: c_types::c_uint) -> c_types::c_uint;
}
extern "C" {
pub fn _xtos_set_intlevel(intlevel: c_types::c_int) -> c_types::c_uint;
}
extern "C" {
pub fn _xtos_set_min_intlevel(intlevel: c_types::c_int) -> c_types::c_uint;
}
extern "C" {
pub fn _xtos_restore_intlevel(restoreval: c_types::c_uint) -> c_types::c_uint;
}
extern "C" {
pub fn _xtos_restore_just_intlevel(restoreval: c_types::c_uint) -> c_types::c_uint;
}
extern "C" {
pub fn _xtos_set_interrupt_handler(n: c_types::c_int, f: _xtos_handler) -> _xtos_handler;
}
extern "C" {
pub fn _xtos_set_interrupt_handler_arg(
n: c_types::c_int,
f: _xtos_handler,
arg: *mut c_types::c_void,
) -> _xtos_handler;
}
extern "C" {
pub fn _xtos_set_exception_handler(n: c_types::c_int, f: _xtos_handler) -> _xtos_handler;
}
extern "C" {
pub fn _xtos_memep_initrams();
}
extern "C" {
pub fn _xtos_memep_enable(flags: c_types::c_int);
}
extern "C" {
pub fn _xtos_dispatch_level1_interrupts();
}
extern "C" {
pub fn _xtos_dispatch_level2_interrupts();
}
extern "C" {
pub fn _xtos_dispatch_level3_interrupts();
}
extern "C" {
pub fn _xtos_dispatch_level4_interrupts();
}
extern "C" {
pub fn _xtos_dispatch_level5_interrupts();
}
extern "C" {
pub fn _xtos_dispatch_level6_interrupts();
}
extern "C" {
pub fn _xtos_read_ints() -> c_types::c_uint;
}
extern "C" {
pub fn _xtos_clear_ints(mask: c_types::c_uint);
}
extern "C" {
pub fn _xtos_core_shutoff(flags: c_types::c_uint) -> c_types::c_int;
}
extern "C" {
pub fn _xtos_core_save(
flags: c_types::c_uint,
savearea: *mut XtosCoreState,
code: *mut c_types::c_void,
) -> c_types::c_int;
}
extern "C" {
pub fn _xtos_core_restore(retvalue: c_types::c_uint, savearea: *mut XtosCoreState);
}
extern "C" {
pub fn _xtos_timer_0_delta(cycles: c_types::c_int);
}
extern "C" {
pub fn _xtos_timer_1_delta(cycles: c_types::c_int);
}
extern "C" {
pub fn _xtos_timer_2_delta(cycles: c_types::c_int);
}
extern "C" {
#[doc = " Set and enable breakpoint at an instruction address."]
#[doc = ""]
#[doc = " @note Overwrites previously set breakpoint with same breakpoint ID."]
#[doc = ""]
#[doc = " @param id breakpoint to set [0..SOC_CPU_BREAKPOINTS_NUM - 1]"]
#[doc = " @param addr address to set a breakpoint on"]
pub fn cpu_hal_set_breakpoint(id: c_types::c_int, addr: *const c_types::c_void);
}
extern "C" {
#[doc = " Clear and disable breakpoint."]
#[doc = ""]
#[doc = " @param id breakpoint to clear [0..SOC_CPU_BREAKPOINTS_NUM - 1]"]
pub fn cpu_hal_clear_breakpoint(id: c_types::c_int);
}
extern "C" {
#[doc = " Set and enable a watchpoint, specifying the memory range and trigger operation."]
#[doc = ""]
#[doc = " @param id watchpoint to set [0..SOC_CPU_WATCHPOINTS_NUM - 1]"]
#[doc = " @param addr starting address"]
#[doc = " @param size number of bytes from starting address to watch"]
#[doc = " @param trigger operation on specified memory range that triggers the watchpoint (read, write, read/write)"]
pub fn cpu_hal_set_watchpoint(
id: c_types::c_int,
addr: *const c_types::c_void,
size: size_t,
trigger: watchpoint_trigger_t,
);
}
extern "C" {
#[doc = " Clear and disable watchpoint."]
#[doc = ""]
#[doc = " @param id watchpoint to clear [0..SOC_CPU_WATCHPOINTS_NUM - 1]"]
pub fn cpu_hal_clear_watchpoint(id: c_types::c_int);
}
extern "C" {
#[doc = " Set exception vector table base address."]
#[doc = ""]
#[doc = " @param base address to move the exception vector table to"]
pub fn cpu_hal_set_vecbase(base: *const c_types::c_void);
}
pub type esp_cpu_ccount_t = u32;
extern "C" {
#[doc = " @brief Stall CPU using RTC controller"]
#[doc = " @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)"]
pub fn esp_cpu_stall(cpu_id: c_types::c_int);
}
extern "C" {
#[doc = " @brief Un-stall CPU using RTC controller"]
#[doc = " @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)"]
pub fn esp_cpu_unstall(cpu_id: c_types::c_int);
}
extern "C" {
#[doc = " @brief Reset CPU using RTC controller"]
#[doc = " @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)"]
pub fn esp_cpu_reset(cpu_id: c_types::c_int);
}
extern "C" {
#[doc = " @brief Returns true if a JTAG debugger is attached to CPU"]
#[doc = " OCD (on chip debug) port."]
#[doc = ""]
#[doc = " @note If \"Make exception and panic handlers JTAG/OCD aware\""]
#[doc = " is disabled, this function always returns false."]
pub fn esp_cpu_in_ocd_debug_mode() -> bool;
}
extern "C" {
#[doc = " @brief Set a watchpoint to break/panic when a certain memory range is accessed."]
#[doc = ""]
#[doc = " @param no Watchpoint number. On the ESP32, this can be 0 or 1."]
#[doc = " @param adr Base address to watch"]
#[doc = " @param size Size of the region, starting at the base address, to watch. Must"]
#[doc = " be one of 2^n, with n in [0..6]."]
#[doc = " @param flags One of ESP_WATCHPOINT_* flags"]
#[doc = ""]
#[doc = " @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise"]
#[doc = ""]
#[doc = " @warning The ESP32 watchpoint hardware watches a region of bytes by effectively"]
#[doc = " masking away the lower n bits for a region with size 2^n. If adr does"]
#[doc = " not have zero for these lower n bits, you may not be watching the"]
#[doc = " region you intended."]
pub fn esp_cpu_set_watchpoint(
no: c_types::c_int,
adr: *mut c_types::c_void,
size: c_types::c_int,
flags: c_types::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Clear a watchpoint"]
#[doc = ""]
#[doc = " @param no Watchpoint to clear"]
#[doc = ""]
pub fn esp_cpu_clear_watchpoint(no: c_types::c_int);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct esp_backtrace_frame_t {
pub pc: u32,
pub sp: u32,
pub next_pc: u32,
pub exc_frame: *const c_types::c_void,
}
impl Default for esp_backtrace_frame_t {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
extern "C" {
#[doc = " @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function"]
#[doc = " address. Do nothing otherwise."]
#[doc = " @param fn Pointer to the target breakpoint position"]
pub fn esp_set_breakpoint_if_jtag(fn_: *mut c_types::c_void);
}
extern "C" {
#[doc = " Get the first frame of the current stack's backtrace"]
#[doc = ""]
#[doc = " Given the following function call flow (B -> A -> X -> esp_backtrace_get_start),"]
#[doc = " this function will do the following."]
#[doc = " - Flush CPU registers and window frames onto the current stack"]
#[doc = " - Return PC and SP of function A (i.e. start of the stack's backtrace)"]
#[doc = " - Return PC of function B (i.e. next_pc)"]
#[doc = ""]
#[doc = " @note This function is implemented in assembly"]
#[doc = ""]
#[doc = " @param[out] pc PC of the first frame in the backtrace"]
#[doc = " @param[out] sp SP of the first frame in the backtrace"]
#[doc = " @param[out] next_pc PC of the first frame's caller"]
pub fn esp_backtrace_get_start(pc: *mut u32, sp: *mut u32, next_pc: *mut u32);
}
extern "C" {
#[doc = " Get the next frame on a stack for backtracing"]
#[doc = ""]
#[doc = " Given a stack frame(i), this function will obtain the next stack frame(i-1)"]
#[doc = " on the same call stack (i.e. the caller of frame(i)). This function is meant to be"]
#[doc = " called iteratively when doing a backtrace."]
#[doc = ""]
#[doc = " Entry Conditions: Frame structure containing valid SP and next_pc"]
#[doc = " Exit Conditions:"]
#[doc = " - Frame structure updated with SP and PC of frame(i-1). next_pc now points to frame(i-2)."]
#[doc = " - If a next_pc of 0 is returned, it indicates that frame(i-1) is last frame on the stack"]
#[doc = ""]
#[doc = " @param[inout] frame Pointer to frame structure"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - True if the SP and PC of the next frame(i-1) are sane"]
#[doc = " - False otherwise"]
pub fn esp_backtrace_get_next_frame(frame: *mut esp_backtrace_frame_t) -> bool;
}
extern "C" {
#[doc = " @brief Print the backtrace from specified frame."]
#[doc = ""]
#[doc = " @param depth The maximum number of stack frames to print (should be > 0)"]
#[doc = " @param frame Starting frame to print from"]
#[doc = " @param panic Indicator if backtrace print is during a system panic"]
#[doc = ""]
#[doc = " @note On the ESP32, users must call esp_backtrace_get_start() first to flush the stack."]
#[doc = " @note If a esp_backtrace_frame_t* frame is obtained though a call to esp_backtrace_get_start()"]
#[doc = " from some example function func_a(), then frame is only valid within the frame/scope of func_a()."]
#[doc = " Users should not attempt to pass/use frame other frames within the same stack of different stacks."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Backtrace successfully printed to completion or to depth limit"]
#[doc = " - ESP_FAIL Backtrace is corrupted"]
pub fn esp_backtrace_print_from_frame(
depth: c_types::c_int,
frame: *const esp_backtrace_frame_t,
panic: bool,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Print the backtrace of the current stack"]
#[doc = ""]
#[doc = " @param depth The maximum number of stack frames to print (should be > 0)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Backtrace successfully printed to completion or to depth limit"]
#[doc = " - ESP_FAIL Backtrace is corrupted"]
pub fn esp_backtrace_print(depth: c_types::c_int) -> esp_err_t;
}
#[doc = "< Touch pad channel 0 is GPIO4(ESP32)"]
pub const touch_pad_t_TOUCH_PAD_NUM0: touch_pad_t = 0;
#[doc = "< Touch pad channel 1 is GPIO0(ESP32) / GPIO1(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM1: touch_pad_t = 1;
#[doc = "< Touch pad channel 2 is GPIO2(ESP32) / GPIO2(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM2: touch_pad_t = 2;
#[doc = "< Touch pad channel 3 is GPIO15(ESP32) / GPIO3(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM3: touch_pad_t = 3;
#[doc = "< Touch pad channel 4 is GPIO13(ESP32) / GPIO4(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM4: touch_pad_t = 4;
#[doc = "< Touch pad channel 5 is GPIO12(ESP32) / GPIO5(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM5: touch_pad_t = 5;
#[doc = "< Touch pad channel 6 is GPIO14(ESP32) / GPIO6(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM6: touch_pad_t = 6;
#[doc = "< Touch pad channel 7 is GPIO27(ESP32) / GPIO7(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM7: touch_pad_t = 7;
#[doc = "< Touch pad channel 8 is GPIO33(ESP32) / GPIO8(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM8: touch_pad_t = 8;
#[doc = "< Touch pad channel 9 is GPIO32(ESP32) / GPIO9(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM9: touch_pad_t = 9;
#[doc = "< Touch channel 10 is GPIO10(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM10: touch_pad_t = 10;
#[doc = "< Touch channel 11 is GPIO11(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM11: touch_pad_t = 11;
#[doc = "< Touch channel 12 is GPIO12(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM12: touch_pad_t = 12;
#[doc = "< Touch channel 13 is GPIO13(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM13: touch_pad_t = 13;
#[doc = "< Touch channel 14 is GPIO14(ESP32-S2)"]
pub const touch_pad_t_TOUCH_PAD_NUM14: touch_pad_t = 14;
pub const touch_pad_t_TOUCH_PAD_MAX: touch_pad_t = 15;
#[doc = " Touch pad channel"]
pub type touch_pad_t = c_types::c_uint;
#[doc = "<Touch sensor high reference voltage, no change"]
pub const touch_high_volt_t_TOUCH_HVOLT_KEEP: touch_high_volt_t = -1;
#[doc = "<Touch sensor high reference voltage, 2.4V"]
pub const touch_high_volt_t_TOUCH_HVOLT_2V4: touch_high_volt_t = 0;
#[doc = "<Touch sensor high reference voltage, 2.5V"]
pub const touch_high_volt_t_TOUCH_HVOLT_2V5: touch_high_volt_t = 1;
#[doc = "<Touch sensor high reference voltage, 2.6V"]
pub const touch_high_volt_t_TOUCH_HVOLT_2V6: touch_high_volt_t = 2;
#[doc = "<Touch sensor high reference voltage, 2.7V"]
pub const touch_high_volt_t_TOUCH_HVOLT_2V7: touch_high_volt_t = 3;
pub const touch_high_volt_t_TOUCH_HVOLT_MAX: touch_high_volt_t = 4;
#[doc = " Touch sensor high reference voltage"]
pub type touch_high_volt_t = c_types::c_int;
#[doc = "<Touch sensor low reference voltage, no change"]
pub const touch_low_volt_t_TOUCH_LVOLT_KEEP: touch_low_volt_t = -1;
#[doc = "<Touch sensor low reference voltage, 0.5V"]
pub const touch_low_volt_t_TOUCH_LVOLT_0V5: touch_low_volt_t = 0;
#[doc = "<Touch sensor low reference voltage, 0.6V"]
pub const touch_low_volt_t_TOUCH_LVOLT_0V6: touch_low_volt_t = 1;
#[doc = "<Touch sensor low reference voltage, 0.7V"]
pub const touch_low_volt_t_TOUCH_LVOLT_0V7: touch_low_volt_t = 2;
#[doc = "<Touch sensor low reference voltage, 0.8V"]
pub const touch_low_volt_t_TOUCH_LVOLT_0V8: touch_low_volt_t = 3;
pub const touch_low_volt_t_TOUCH_LVOLT_MAX: touch_low_volt_t = 4;
#[doc = " Touch sensor low reference voltage"]
pub type touch_low_volt_t = c_types::c_int;
#[doc = "<Touch sensor high reference voltage attenuation, no change"]
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_KEEP: touch_volt_atten_t = -1;
#[doc = "<Touch sensor high reference voltage attenuation, 1.5V attenuation"]
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_1V5: touch_volt_atten_t = 0;
#[doc = "<Touch sensor high reference voltage attenuation, 1.0V attenuation"]
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_1V: touch_volt_atten_t = 1;
#[doc = "<Touch sensor high reference voltage attenuation, 0.5V attenuation"]
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_0V5: touch_volt_atten_t = 2;
#[doc = "<Touch sensor high reference voltage attenuation, 0V attenuation"]
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_0V: touch_volt_atten_t = 3;
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_MAX: touch_volt_atten_t = 4;
#[doc = " Touch sensor high reference voltage attenuation"]
pub type touch_volt_atten_t = c_types::c_int;
#[doc = "<Touch sensor charge / discharge speed, always zero"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_0: touch_cnt_slope_t = 0;
#[doc = "<Touch sensor charge / discharge speed, slowest"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_1: touch_cnt_slope_t = 1;
#[doc = "<Touch sensor charge / discharge speed"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_2: touch_cnt_slope_t = 2;
#[doc = "<Touch sensor charge / discharge speed"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_3: touch_cnt_slope_t = 3;
#[doc = "<Touch sensor charge / discharge speed"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_4: touch_cnt_slope_t = 4;
#[doc = "<Touch sensor charge / discharge speed"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_5: touch_cnt_slope_t = 5;
#[doc = "<Touch sensor charge / discharge speed"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_6: touch_cnt_slope_t = 6;
#[doc = "<Touch sensor charge / discharge speed, fast"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_7: touch_cnt_slope_t = 7;
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_MAX: touch_cnt_slope_t = 8;
#[doc = " Touch sensor charge/discharge speed"]
pub type touch_cnt_slope_t = c_types::c_uint;
#[doc = "<Initial level of charging voltage, low level"]
pub const touch_tie_opt_t_TOUCH_PAD_TIE_OPT_LOW: touch_tie_opt_t = 0;
#[doc = "<Initial level of charging voltage, high level"]
pub const touch_tie_opt_t_TOUCH_PAD_TIE_OPT_HIGH: touch_tie_opt_t = 1;
pub const touch_tie_opt_t_TOUCH_PAD_TIE_OPT_MAX: touch_tie_opt_t = 2;
#[doc = " Touch sensor initial charge level"]
pub type touch_tie_opt_t = c_types::c_uint;
#[doc = "<To start touch FSM by timer"]
pub const touch_fsm_mode_t_TOUCH_FSM_MODE_TIMER: touch_fsm_mode_t = 0;
#[doc = "<To start touch FSM by software trigger"]
pub const touch_fsm_mode_t_TOUCH_FSM_MODE_SW: touch_fsm_mode_t = 1;
pub const touch_fsm_mode_t_TOUCH_FSM_MODE_MAX: touch_fsm_mode_t = 2;
#[doc = " Touch sensor FSM mode"]
pub type touch_fsm_mode_t = c_types::c_uint;
#[doc = "<Touch interrupt will happen if counter value is less than threshold."]
pub const touch_trigger_mode_t_TOUCH_TRIGGER_BELOW: touch_trigger_mode_t = 0;
#[doc = "<Touch interrupt will happen if counter value is larger than threshold."]
pub const touch_trigger_mode_t_TOUCH_TRIGGER_ABOVE: touch_trigger_mode_t = 1;
pub const touch_trigger_mode_t_TOUCH_TRIGGER_MAX: touch_trigger_mode_t = 2;
#[doc = " ESP32 Only"]
pub type touch_trigger_mode_t = c_types::c_uint;
#[doc = "< wakeup interrupt is generated if both SET1 and SET2 are \"touched\""]
pub const touch_trigger_src_t_TOUCH_TRIGGER_SOURCE_BOTH: touch_trigger_src_t = 0;
#[doc = "< wakeup interrupt is generated if SET1 is \"touched\""]
pub const touch_trigger_src_t_TOUCH_TRIGGER_SOURCE_SET1: touch_trigger_src_t = 1;
pub const touch_trigger_src_t_TOUCH_TRIGGER_SOURCE_MAX: touch_trigger_src_t = 2;
pub type touch_trigger_src_t = c_types::c_uint;
#[doc = "<Measurement done for one of the enabled channels."]
pub const touch_pad_intr_mask_t_TOUCH_PAD_INTR_MASK_DONE: touch_pad_intr_mask_t = 1;
#[doc = "<Active for one of the enabled channels."]
pub const touch_pad_intr_mask_t_TOUCH_PAD_INTR_MASK_ACTIVE: touch_pad_intr_mask_t = 2;
#[doc = "<Inactive for one of the enabled channels."]
pub const touch_pad_intr_mask_t_TOUCH_PAD_INTR_MASK_INACTIVE: touch_pad_intr_mask_t = 4;
#[doc = "<Measurement done for all the enabled channels."]
pub const touch_pad_intr_mask_t_TOUCH_PAD_INTR_MASK_SCAN_DONE: touch_pad_intr_mask_t = 8;
#[doc = "<Timeout for one of the enabled channels."]
pub const touch_pad_intr_mask_t_TOUCH_PAD_INTR_MASK_TIMEOUT: touch_pad_intr_mask_t = 16;
#[doc = "<For proximity sensor, when the number of measurements reaches the set count of measurements, an interrupt will be generated."]
pub const touch_pad_intr_mask_t_TOUCH_PAD_INTR_MASK_PROXI_MEAS_DONE: touch_pad_intr_mask_t = 32;
pub const touch_pad_intr_mask_t_TOUCH_PAD_INTR_MASK_MAX: touch_pad_intr_mask_t = 33;
pub type touch_pad_intr_mask_t = c_types::c_uint;
#[doc = "<Denoise range is 12bit"]
pub const touch_pad_denoise_grade_t_TOUCH_PAD_DENOISE_BIT12: touch_pad_denoise_grade_t = 0;
#[doc = "<Denoise range is 10bit"]
pub const touch_pad_denoise_grade_t_TOUCH_PAD_DENOISE_BIT10: touch_pad_denoise_grade_t = 1;
#[doc = "<Denoise range is 8bit"]
pub const touch_pad_denoise_grade_t_TOUCH_PAD_DENOISE_BIT8: touch_pad_denoise_grade_t = 2;
#[doc = "<Denoise range is 4bit"]
pub const touch_pad_denoise_grade_t_TOUCH_PAD_DENOISE_BIT4: touch_pad_denoise_grade_t = 3;
pub const touch_pad_denoise_grade_t_TOUCH_PAD_DENOISE_MAX: touch_pad_denoise_grade_t = 4;
pub type touch_pad_denoise_grade_t = c_types::c_uint;
#[doc = "<Denoise channel internal reference capacitance is 5pf"]
pub const touch_pad_denoise_cap_t_TOUCH_PAD_DENOISE_CAP_L0: touch_pad_denoise_cap_t = 0;
#[doc = "<Denoise channel internal reference capacitance is 6.4pf"]
pub const touch_pad_denoise_cap_t_TOUCH_PAD_DENOISE_CAP_L1: touch_pad_denoise_cap_t = 1;
#[doc = "<Denoise channel internal reference capacitance is 7.8pf"]
pub const touch_pad_denoise_cap_t_TOUCH_PAD_DENOISE_CAP_L2: touch_pad_denoise_cap_t = 2;
#[doc = "<Denoise channel internal reference capacitance is 9.2pf"]
pub const touch_pad_denoise_cap_t_TOUCH_PAD_DENOISE_CAP_L3: touch_pad_denoise_cap_t = 3;
#[doc = "<Denoise channel internal reference capacitance is 10.6pf"]
pub const touch_pad_denoise_cap_t_TOUCH_PAD_DENOISE_CAP_L4: touch_pad_denoise_cap_t = 4;
#[doc = "<Denoise channel internal reference capacitance is 12.0pf"]
pub const touch_pad_denoise_cap_t_TOUCH_PAD_DENOISE_CAP_L5: touch_pad_denoise_cap_t = 5;
#[doc = "<Denoise channel internal reference capacitance is 13.4pf"]
pub const touch_pad_denoise_cap_t_TOUCH_PAD_DENOISE_CAP_L6: touch_pad_denoise_cap_t = 6;
#[doc = "<Denoise channel internal reference capacitance is 14.8pf"]
pub const touch_pad_denoise_cap_t_TOUCH_PAD_DENOISE_CAP_L7: touch_pad_denoise_cap_t = 7;
pub const touch_pad_denoise_cap_t_TOUCH_PAD_DENOISE_CAP_MAX: touch_pad_denoise_cap_t = 8;
pub type touch_pad_denoise_cap_t = c_types::c_uint;
#[doc = " Touch sensor denoise configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct touch_pad_denoise {
#[doc = "<Select denoise range of denoise channel."]
#[doc = "Determined by measuring the noise amplitude of the denoise channel."]
pub grade: touch_pad_denoise_grade_t,
#[doc = "<Select internal reference capacitance of denoise channel."]
#[doc = "Ensure that the denoise readings are closest to the readings of the channel being measured."]
#[doc = "Use `touch_pad_denoise_read_data` to get the reading of denoise channel."]
#[doc = "The equivalent capacitance of the shielded channel can be calculated"]
#[doc = "from the reading of denoise channel."]
pub cap_level: touch_pad_denoise_cap_t,
}
impl Default for touch_pad_denoise {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[doc = " Touch sensor denoise configuration"]
pub type touch_pad_denoise_t = touch_pad_denoise;
#[doc = "<The max equivalent capacitance in shield channel is 40pf"]
pub const touch_pad_shield_driver_t_TOUCH_PAD_SHIELD_DRV_L0: touch_pad_shield_driver_t = 0;
#[doc = "<The max equivalent capacitance in shield channel is 80pf"]
pub const touch_pad_shield_driver_t_TOUCH_PAD_SHIELD_DRV_L1: touch_pad_shield_driver_t = 1;
#[doc = "<The max equivalent capacitance in shield channel is 120pf"]
pub const touch_pad_shield_driver_t_TOUCH_PAD_SHIELD_DRV_L2: touch_pad_shield_driver_t = 2;
#[doc = "<The max equivalent capacitance in shield channel is 160pf"]
pub const touch_pad_shield_driver_t_TOUCH_PAD_SHIELD_DRV_L3: touch_pad_shield_driver_t = 3;
#[doc = "<The max equivalent capacitance in shield channel is 200pf"]
pub const touch_pad_shield_driver_t_TOUCH_PAD_SHIELD_DRV_L4: touch_pad_shield_driver_t = 4;
#[doc = "<The max equivalent capacitance in shield channel is 240pf"]
pub const touch_pad_shield_driver_t_TOUCH_PAD_SHIELD_DRV_L5: touch_pad_shield_driver_t = 5;
#[doc = "<The max equivalent capacitance in shield channel is 280pf"]
pub const touch_pad_shield_driver_t_TOUCH_PAD_SHIELD_DRV_L6: touch_pad_shield_driver_t = 6;
#[doc = "<The max equivalent capacitance in shield channel is 320pf"]
pub const touch_pad_shield_driver_t_TOUCH_PAD_SHIELD_DRV_L7: touch_pad_shield_driver_t = 7;
pub const touch_pad_shield_driver_t_TOUCH_PAD_SHIELD_DRV_MAX: touch_pad_shield_driver_t = 8;
#[doc = " Touch sensor shield channel drive capability level"]
pub type touch_pad_shield_driver_t = c_types::c_uint;
#[doc = " Touch sensor waterproof configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct touch_pad_waterproof {
#[doc = "<Waterproof. Select touch channel use for guard pad."]
#[doc = "Guard pad is used to detect the large area of water covering the touch panel."]
pub guard_ring_pad: touch_pad_t,
#[doc = "<Waterproof. Shield channel drive capability configuration."]
#[doc = "Shield pad is used to shield the influence of water droplets covering the touch panel."]
#[doc = "When the waterproof function is enabled, Touch14 is set as shield channel by default."]
#[doc = "The larger the parasitic capacitance on the shielding channel, the higher the drive capability needs to be set."]
#[doc = "The equivalent capacitance of the shield channel can be estimated through the reading value of the denoise channel(Touch0)."]
pub shield_driver: touch_pad_shield_driver_t,
}
impl Default for touch_pad_waterproof {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[doc = " Touch sensor waterproof configuration"]
pub type touch_pad_waterproof_t = touch_pad_waterproof;
#[doc = "<Idle status of touch channel is high resistance state"]
pub const touch_pad_conn_type_t_TOUCH_PAD_CONN_HIGHZ: touch_pad_conn_type_t = 0;
#[doc = "<Idle status of touch channel is ground connection"]
pub const touch_pad_conn_type_t_TOUCH_PAD_CONN_GND: touch_pad_conn_type_t = 1;
pub const touch_pad_conn_type_t_TOUCH_PAD_CONN_MAX: touch_pad_conn_type_t = 2;
#[doc = " Touch channel idle state configuration"]
pub type touch_pad_conn_type_t = c_types::c_uint;
#[doc = "<The filter mode is first-order IIR filter. The coefficient is 4."]
pub const touch_filter_mode_t_TOUCH_PAD_FILTER_IIR_4: touch_filter_mode_t = 0;
#[doc = "<The filter mode is first-order IIR filter. The coefficient is 8."]
pub const touch_filter_mode_t_TOUCH_PAD_FILTER_IIR_8: touch_filter_mode_t = 1;
#[doc = "<The filter mode is first-order IIR filter. The coefficient is 16 (Typical value)."]
pub const touch_filter_mode_t_TOUCH_PAD_FILTER_IIR_16: touch_filter_mode_t = 2;
#[doc = "<The filter mode is first-order IIR filter. The coefficient is 32."]
pub const touch_filter_mode_t_TOUCH_PAD_FILTER_IIR_32: touch_filter_mode_t = 3;
#[doc = "<The filter mode is first-order IIR filter. The coefficient is 64."]
pub const touch_filter_mode_t_TOUCH_PAD_FILTER_IIR_64: touch_filter_mode_t = 4;
#[doc = "<The filter mode is first-order IIR filter. The coefficient is 128."]
pub const touch_filter_mode_t_TOUCH_PAD_FILTER_IIR_128: touch_filter_mode_t = 5;
#[doc = "<The filter mode is first-order IIR filter. The coefficient is 256."]
pub const touch_filter_mode_t_TOUCH_PAD_FILTER_IIR_256: touch_filter_mode_t = 6;
#[doc = "<The filter mode is jitter filter"]
pub const touch_filter_mode_t_TOUCH_PAD_FILTER_JITTER: touch_filter_mode_t = 7;
pub const touch_filter_mode_t_TOUCH_PAD_FILTER_MAX: touch_filter_mode_t = 8;
#[doc = " @brief Touch channel IIR filter coefficient configuration."]
#[doc = " @note On ESP32S2. There is an error in the IIR calculation. The magnitude of the error is twice the filter coefficient."]
#[doc = " So please select a smaller filter coefficient on the basis of meeting the filtering requirements."]
#[doc = " Recommended filter coefficient selection `IIR_16`."]
pub type touch_filter_mode_t = c_types::c_uint;
#[doc = "<No filtering of raw data."]
pub const touch_smooth_mode_t_TOUCH_PAD_SMOOTH_OFF: touch_smooth_mode_t = 0;
#[doc = "<Filter the raw data. The coefficient is 2 (Typical value)."]
pub const touch_smooth_mode_t_TOUCH_PAD_SMOOTH_IIR_2: touch_smooth_mode_t = 1;
#[doc = "<Filter the raw data. The coefficient is 4."]
pub const touch_smooth_mode_t_TOUCH_PAD_SMOOTH_IIR_4: touch_smooth_mode_t = 2;
#[doc = "<Filter the raw data. The coefficient is 8."]
pub const touch_smooth_mode_t_TOUCH_PAD_SMOOTH_IIR_8: touch_smooth_mode_t = 3;
pub const touch_smooth_mode_t_TOUCH_PAD_SMOOTH_MAX: touch_smooth_mode_t = 4;
#[doc = " @brief Level of filter applied on the original data against large noise interference."]
#[doc = " @note On ESP32S2. There is an error in the IIR calculation. The magnitude of the error is twice the filter coefficient."]
#[doc = " So please select a smaller filter coefficient on the basis of meeting the filtering requirements."]
#[doc = " Recommended filter coefficient selection `IIR_2`."]
pub type touch_smooth_mode_t = c_types::c_uint;
#[doc = " Touch sensor filter configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct touch_filter_config {
#[doc = "<Set filter mode. The input of the filter is the raw value of touch reading,"]
#[doc = "and the output of the filter is involved in the judgment of the touch state."]
pub mode: touch_filter_mode_t,
#[doc = "<Set debounce count, such as `n`. If the measured values continue to exceed"]
#[doc = "the threshold for `n+1` times, the touch sensor state changes."]
#[doc = "Range: 0 ~ 7"]
pub debounce_cnt: u32,
#[doc = "<Noise threshold coefficient. Higher = More noise resistance."]
#[doc = "The actual noise should be less than (noise coefficient * touch threshold)."]
#[doc = "Range: 0 ~ 3. The coefficient is 0: 4/8; 1: 3/8; 2: 2/8; 3: 1;"]
pub noise_thr: u32,
#[doc = "<Set jitter filter step size. Range: 0 ~ 15"]
pub jitter_step: u32,
#[doc = "<Level of filter applied on the original data against large noise interference."]
pub smh_lvl: touch_smooth_mode_t,
}
impl Default for touch_filter_config {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[doc = " Touch sensor filter configuration"]
pub type touch_filter_config_t = touch_filter_config;
#[doc = " Touch sensor channel sleep configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct touch_pad_sleep_channel_t {
#[doc = "<Set touch channel number for sleep pad."]
#[doc = "Only one touch sensor channel is supported in deep sleep mode."]
#[doc = "If clear the sleep channel, point this pad to `TOUCH_PAD_NUM0`"]
pub touch_num: touch_pad_t,
#[doc = "<enable proximity function for sleep pad"]
pub en_proximity: bool,
}
impl Default for touch_pad_sleep_channel_t {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct gpio_dev_s {
pub bt_select: u32,
pub out: u32,
pub out_w1ts: u32,
pub out_w1tc: u32,
pub out1: gpio_dev_s__bindgen_ty_1,
pub out1_w1ts: gpio_dev_s__bindgen_ty_2,
pub out1_w1tc: gpio_dev_s__bindgen_ty_3,
pub sdio_select: gpio_dev_s__bindgen_ty_4,
pub enable: u32,
pub enable_w1ts: u32,
pub enable_w1tc: u32,
pub enable1: gpio_dev_s__bindgen_ty_5,
pub enable1_w1ts: gpio_dev_s__bindgen_ty_6,
pub enable1_w1tc: gpio_dev_s__bindgen_ty_7,
pub strap: gpio_dev_s__bindgen_ty_8,
pub in_: u32,
pub in1: gpio_dev_s__bindgen_ty_9,
pub status: u32,
pub status_w1ts: u32,
pub status_w1tc: u32,
pub status1: gpio_dev_s__bindgen_ty_10,
pub status1_w1ts: gpio_dev_s__bindgen_ty_11,
pub status1_w1tc: gpio_dev_s__bindgen_ty_12,
pub pcpu_int: u32,
pub pcpu_nmi_int: u32,
pub cpusdio_int: u32,
pub pcpu_int1: gpio_dev_s__bindgen_ty_13,
pub pcpu_nmi_int1: gpio_dev_s__bindgen_ty_14,
pub cpusdio_int1: gpio_dev_s__bindgen_ty_15,
pub pin: [gpio_dev_s__bindgen_ty_16; 54usize],
pub status_next: u32,
pub status_next1: gpio_dev_s__bindgen_ty_17,
pub func_in_sel_cfg: [gpio_dev_s__bindgen_ty_18; 256usize],
pub func_out_sel_cfg: [gpio_dev_s__bindgen_ty_19; 54usize],
pub clock_gate: gpio_dev_s__bindgen_ty_20,
pub reserved_630: u32,
pub reserved_634: u32,
pub reserved_638: u32,
pub reserved_63c: u32,
pub reserved_640: u32,
pub reserved_644: u32,
pub reserved_648: u32,
pub reserved_64c: u32,
pub reserved_650: u32,
pub reserved_654: u32,
pub reserved_658: u32,
pub reserved_65c: u32,
pub reserved_660: u32,
pub reserved_664: u32,
pub reserved_668: u32,
pub reserved_66c: u32,
pub reserved_670: u32,
pub reserved_674: u32,
pub reserved_678: u32,
pub reserved_67c: u32,
pub reserved_680: u32,
pub reserved_684: u32,
pub reserved_688: u32,
pub reserved_68c: u32,
pub reserved_690: u32,
pub reserved_694: u32,
pub reserved_698: u32,
pub reserved_69c: u32,
pub reserved_6a0: u32,
pub reserved_6a4: u32,
pub reserved_6a8: u32,
pub reserved_6ac: u32,
pub reserved_6b0: u32,
pub reserved_6b4: u32,
pub reserved_6b8: u32,
pub reserved_6bc: u32,
pub reserved_6c0: u32,
pub reserved_6c4: u32,
pub reserved_6c8: u32,
pub reserved_6cc: u32,
pub reserved_6d0: u32,
pub reserved_6d4: u32,
pub reserved_6d8: u32,
pub reserved_6dc: u32,
pub reserved_6e0: u32,
pub reserved_6e4: u32,
pub reserved_6e8: u32,
pub reserved_6ec: u32,
pub reserved_6f0: u32,
pub reserved_6f4: u32,
pub reserved_6f8: u32,
pub date: gpio_dev_s__bindgen_ty_21,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_1 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_1__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_1 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_2 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_2__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_2__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_2__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_2 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_3 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_3__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_3__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_3__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_3 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_4 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_4__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_4__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_4__bindgen_ty_1 {
#[inline]
pub fn sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(sel: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let sel: u32 = unsafe { ::core::mem::transmute(sel) };
sel as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_4 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_5 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_5__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_5__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_5__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_5 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_6 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_6__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_6__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_6__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_6 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_7 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_7__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_7__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_7__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_7 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_8 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_8__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_8__bindgen_ty_1 {
pub _bitfield_align_1: [u16; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_8__bindgen_ty_1 {
#[inline]
pub fn strapping(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_strapping(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn reserved16(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_reserved16(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(strapping: u32, reserved16: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let strapping: u32 = unsafe { ::core::mem::transmute(strapping) };
strapping as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let reserved16: u32 = unsafe { ::core::mem::transmute(reserved16) };
reserved16 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_8 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_9 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_9__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_9__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_9__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_9 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_10 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_10__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_10__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_10__bindgen_ty_1 {
#[inline]
pub fn intr_st(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_intr_st(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr_st: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let intr_st: u32 = unsafe { ::core::mem::transmute(intr_st) };
intr_st as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_10 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_11 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_11__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_11__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_11__bindgen_ty_1 {
#[inline]
pub fn intr_st(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_intr_st(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr_st: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let intr_st: u32 = unsafe { ::core::mem::transmute(intr_st) };
intr_st as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_11 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_12 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_12__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_12__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_12__bindgen_ty_1 {
#[inline]
pub fn intr_st(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_intr_st(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr_st: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let intr_st: u32 = unsafe { ::core::mem::transmute(intr_st) };
intr_st as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_12 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_13 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_13__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_13__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_13__bindgen_ty_1 {
#[inline]
pub fn intr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_intr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let intr: u32 = unsafe { ::core::mem::transmute(intr) };
intr as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_13 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_14 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_14__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_14__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_14__bindgen_ty_1 {
#[inline]
pub fn intr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_intr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let intr: u32 = unsafe { ::core::mem::transmute(intr) };
intr as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_14 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_15 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_15__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_15__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_15__bindgen_ty_1 {
#[inline]
pub fn intr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_intr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr: u32, reserved22: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let intr: u32 = unsafe { ::core::mem::transmute(intr) };
intr as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_15 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_16 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_16__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_16__bindgen_ty_1 {
pub _bitfield_align_1: [u16; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_16__bindgen_ty_1 {
#[inline]
pub fn sync2_bypass(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 2u8) as u32) }
}
#[inline]
pub fn set_sync2_bypass(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 2u8, val as u64)
}
}
#[inline]
pub fn pad_driver(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_pad_driver(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn sync1_bypass(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 2u8) as u32) }
}
#[inline]
pub fn set_sync1_bypass(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 2u8, val as u64)
}
}
#[inline]
pub fn reserved5(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 2u8) as u32) }
}
#[inline]
pub fn set_reserved5(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 2u8, val as u64)
}
}
#[inline]
pub fn int_type(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 3u8) as u32) }
}
#[inline]
pub fn set_int_type(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 3u8, val as u64)
}
}
#[inline]
pub fn wakeup_enable(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_wakeup_enable(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn config(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 2u8) as u32) }
}
#[inline]
pub fn set_config(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 2u8, val as u64)
}
}
#[inline]
pub fn int_ena(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 5u8) as u32) }
}
#[inline]
pub fn set_int_ena(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 5u8, val as u64)
}
}
#[inline]
pub fn reserved18(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 14u8) as u32) }
}
#[inline]
pub fn set_reserved18(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 14u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
sync2_bypass: u32,
pad_driver: u32,
sync1_bypass: u32,
reserved5: u32,
int_type: u32,
wakeup_enable: u32,
config: u32,
int_ena: u32,
reserved18: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 2u8, {
let sync2_bypass: u32 = unsafe { ::core::mem::transmute(sync2_bypass) };
sync2_bypass as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let pad_driver: u32 = unsafe { ::core::mem::transmute(pad_driver) };
pad_driver as u64
});
__bindgen_bitfield_unit.set(3usize, 2u8, {
let sync1_bypass: u32 = unsafe { ::core::mem::transmute(sync1_bypass) };
sync1_bypass as u64
});
__bindgen_bitfield_unit.set(5usize, 2u8, {
let reserved5: u32 = unsafe { ::core::mem::transmute(reserved5) };
reserved5 as u64
});
__bindgen_bitfield_unit.set(7usize, 3u8, {
let int_type: u32 = unsafe { ::core::mem::transmute(int_type) };
int_type as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let wakeup_enable: u32 = unsafe { ::core::mem::transmute(wakeup_enable) };
wakeup_enable as u64
});
__bindgen_bitfield_unit.set(11usize, 2u8, {
let config: u32 = unsafe { ::core::mem::transmute(config) };
config as u64
});
__bindgen_bitfield_unit.set(13usize, 5u8, {
let int_ena: u32 = unsafe { ::core::mem::transmute(int_ena) };
int_ena as u64
});
__bindgen_bitfield_unit.set(18usize, 14u8, {
let reserved18: u32 = unsafe { ::core::mem::transmute(reserved18) };
reserved18 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_16 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_17 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_17__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_17__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_17__bindgen_ty_1 {
#[inline]
pub fn intr_st_next(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 22u8) as u32) }
}
#[inline]
pub fn set_intr_st_next(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 22u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
intr_st_next: u32,
reserved22: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 22u8, {
let intr_st_next: u32 = unsafe { ::core::mem::transmute(intr_st_next) };
intr_st_next as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_17 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_18 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_18__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_18__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_18__bindgen_ty_1 {
#[inline]
pub fn func_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 6u8) as u32) }
}
#[inline]
pub fn set_func_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 6u8, val as u64)
}
}
#[inline]
pub fn sig_in_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_sig_in_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn sig_in_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_sig_in_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
func_sel: u32,
sig_in_inv: u32,
sig_in_sel: u32,
reserved8: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 6u8, {
let func_sel: u32 = unsafe { ::core::mem::transmute(func_sel) };
func_sel as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let sig_in_inv: u32 = unsafe { ::core::mem::transmute(sig_in_inv) };
sig_in_inv as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let sig_in_sel: u32 = unsafe { ::core::mem::transmute(sig_in_sel) };
sig_in_sel as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_18 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_19 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_19__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_19__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_19__bindgen_ty_1 {
#[inline]
pub fn func_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 9u8) as u32) }
}
#[inline]
pub fn set_func_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 9u8, val as u64)
}
}
#[inline]
pub fn inv_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_inv_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn oen_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_oen_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn oen_inv_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_oen_inv_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved12(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 20u8) as u32) }
}
#[inline]
pub fn set_reserved12(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 20u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
func_sel: u32,
inv_sel: u32,
oen_sel: u32,
oen_inv_sel: u32,
reserved12: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 9u8, {
let func_sel: u32 = unsafe { ::core::mem::transmute(func_sel) };
func_sel as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let inv_sel: u32 = unsafe { ::core::mem::transmute(inv_sel) };
inv_sel as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let oen_sel: u32 = unsafe { ::core::mem::transmute(oen_sel) };
oen_sel as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let oen_inv_sel: u32 = unsafe { ::core::mem::transmute(oen_inv_sel) };
oen_inv_sel as u64
});
__bindgen_bitfield_unit.set(12usize, 20u8, {
let reserved12: u32 = unsafe { ::core::mem::transmute(reserved12) };
reserved12 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_19 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_20 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_20__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_20__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_20__bindgen_ty_1 {
#[inline]
pub fn clk_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_clk_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 31u8) as u32) }
}
#[inline]
pub fn set_reserved1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 31u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(clk_en: u32, reserved1: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let clk_en: u32 = unsafe { ::core::mem::transmute(clk_en) };
clk_en as u64
});
__bindgen_bitfield_unit.set(1usize, 31u8, {
let reserved1: u32 = unsafe { ::core::mem::transmute(reserved1) };
reserved1 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_20 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union gpio_dev_s__bindgen_ty_21 {
pub __bindgen_anon_1: gpio_dev_s__bindgen_ty_21__bindgen_ty_1,
pub val: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Default, Copy, Clone)]
pub struct gpio_dev_s__bindgen_ty_21__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl gpio_dev_s__bindgen_ty_21__bindgen_ty_1 {
#[inline]
pub fn date(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 28u8) as u32) }
}
#[inline]
pub fn set_date(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 28u8, val as u64)
}
}
#[inline]
pub fn reserved28(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved28(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(date: u32, reserved28: u32) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 28u8, {
let date: u32 = unsafe { ::core::mem::transmute(date) };
date as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let reserved28: u32 = unsafe { ::core::mem::transmute(reserved28) };
reserved28 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for gpio_dev_s__bindgen_ty_21 {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
impl Default for gpio_dev_s {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
pub type gpio_dev_t = gpio_dev_s;
extern "C" {
pub static mut GPIO: gpio_dev_t;
}
extern "C" {
pub static GPIO_PIN_MUX_REG: [u32; 49usize];
}
extern "C" {
pub static GPIO_HOLD_MASK: [u32; 49usize];
}
pub const gpio_port_t_GPIO_PORT_0: gpio_port_t = 0;
pub const gpio_port_t_GPIO_PORT_MAX: gpio_port_t = 1;
pub type gpio_port_t = c_types::c_uint;
#[doc = "< Use to signal not connected to S/W"]
pub const gpio_num_t_GPIO_NUM_NC: gpio_num_t = -1;
#[doc = "< GPIO0, input and output"]
pub const gpio_num_t_GPIO_NUM_0: gpio_num_t = 0;
#[doc = "< GPIO1, input and output"]
pub const gpio_num_t_GPIO_NUM_1: gpio_num_t = 1;
#[doc = "< GPIO2, input and output"]
pub const gpio_num_t_GPIO_NUM_2: gpio_num_t = 2;
#[doc = "< GPIO3, input and output"]
pub const gpio_num_t_GPIO_NUM_3: gpio_num_t = 3;
#[doc = "< GPIO4, input and output"]
pub const gpio_num_t_GPIO_NUM_4: gpio_num_t = 4;
#[doc = "< GPIO5, input and output"]
pub const gpio_num_t_GPIO_NUM_5: gpio_num_t = 5;
#[doc = "< GPIO6, input and output"]
pub const gpio_num_t_GPIO_NUM_6: gpio_num_t = 6;
#[doc = "< GPIO7, input and output"]
pub const gpio_num_t_GPIO_NUM_7: gpio_num_t = 7;
#[doc = "< GPIO8, input and output"]
pub const gpio_num_t_GPIO_NUM_8: gpio_num_t = 8;
#[doc = "< GPIO9, input and output"]
pub const gpio_num_t_GPIO_NUM_9: gpio_num_t = 9;
#[doc = "< GPIO10, input and output"]
pub const gpio_num_t_GPIO_NUM_10: gpio_num_t = 10;
#[doc = "< GPIO11, input and output"]
pub const gpio_num_t_GPIO_NUM_11: gpio_num_t = 11;
#[doc = "< GPIO12, input and output"]
pub const gpio_num_t_GPIO_NUM_12: gpio_num_t = 12;
#[doc = "< GPIO13, input and output"]
pub const gpio_num_t_GPIO_NUM_13: gpio_num_t = 13;
#[doc = "< GPIO14, input and output"]
pub const gpio_num_t_GPIO_NUM_14: gpio_num_t = 14;
#[doc = "< GPIO15, input and output"]
pub const gpio_num_t_GPIO_NUM_15: gpio_num_t = 15;
#[doc = "< GPIO16, input and output"]
pub const gpio_num_t_GPIO_NUM_16: gpio_num_t = 16;
#[doc = "< GPIO17, input and output"]
pub const gpio_num_t_GPIO_NUM_17: gpio_num_t = 17;
#[doc = "< GPIO18, input and output"]
pub const gpio_num_t_GPIO_NUM_18: gpio_num_t = 18;
#[doc = "< GPIO19, input and output"]
pub const gpio_num_t_GPIO_NUM_19: gpio_num_t = 19;
#[doc = "< GPIO20, input and output"]
pub const gpio_num_t_GPIO_NUM_20: gpio_num_t = 20;
#[doc = "< GPIO21, input and output"]
pub const gpio_num_t_GPIO_NUM_21: gpio_num_t = 21;
#[doc = "< GPIO26, input and output"]
pub const gpio_num_t_GPIO_NUM_26: gpio_num_t = 26;
#[doc = "< GPIO27, input and output"]
pub const gpio_num_t_GPIO_NUM_27: gpio_num_t = 27;
#[doc = "< GPIO28, input and output"]
pub const gpio_num_t_GPIO_NUM_28: gpio_num_t = 28;
#[doc = "< GPIO29, input and output"]
pub const gpio_num_t_GPIO_NUM_29: gpio_num_t = 29;
#[doc = "< GPIO30, input and output"]
pub const gpio_num_t_GPIO_NUM_30: gpio_num_t = 30;
#[doc = "< GPIO31, input and output"]
pub const gpio_num_t_GPIO_NUM_31: gpio_num_t = 31;
#[doc = "< GPIO32, input and output"]
pub const gpio_num_t_GPIO_NUM_32: gpio_num_t = 32;
#[doc = "< GPIO33, input and output"]
pub const gpio_num_t_GPIO_NUM_33: gpio_num_t = 33;
#[doc = "< GPIO34, input and output"]
pub const gpio_num_t_GPIO_NUM_34: gpio_num_t = 34;
#[doc = "< GPIO35, input and output"]
pub const gpio_num_t_GPIO_NUM_35: gpio_num_t = 35;
#[doc = "< GPIO36, input and output"]
pub const gpio_num_t_GPIO_NUM_36: gpio_num_t = 36;
#[doc = "< GPIO37, input and output"]
pub const gpio_num_t_GPIO_NUM_37: gpio_num_t = 37;
#[doc = "< GPIO38, input and output"]
pub const gpio_num_t_GPIO_NUM_38: gpio_num_t = 38;
#[doc = "< GPIO39, input and output"]
pub const gpio_num_t_GPIO_NUM_39: gpio_num_t = 39;
#[doc = "< GPIO40, input and output"]
pub const gpio_num_t_GPIO_NUM_40: gpio_num_t = 40;
#[doc = "< GPIO41, input and output"]
pub const gpio_num_t_GPIO_NUM_41: gpio_num_t = 41;
#[doc = "< GPIO42, input and output"]
pub const gpio_num_t_GPIO_NUM_42: gpio_num_t = 42;
#[doc = "< GPIO43, input and output"]
pub const gpio_num_t_GPIO_NUM_43: gpio_num_t = 43;
#[doc = "< GPIO44, input and output"]
pub const gpio_num_t_GPIO_NUM_44: gpio_num_t = 44;
#[doc = "< GPIO45, input and output"]
pub const gpio_num_t_GPIO_NUM_45: gpio_num_t = 45;
#[doc = "< GPIO46, input and output"]
pub const gpio_num_t_GPIO_NUM_46: gpio_num_t = 46;
#[doc = "< GPIO47, input and output"]
pub const gpio_num_t_GPIO_NUM_47: gpio_num_t = 47;
#[doc = "< GPIO48, input and output"]
pub const gpio_num_t_GPIO_NUM_48: gpio_num_t = 48;
pub const gpio_num_t_GPIO_NUM_MAX: gpio_num_t = 49;
pub type gpio_num_t = c_types::c_int;
#[doc = "< Disable GPIO interrupt"]
pub const gpio_int_type_t_GPIO_INTR_DISABLE: gpio_int_type_t = 0;
#[doc = "< GPIO interrupt type : rising edge"]
pub const gpio_int_type_t_GPIO_INTR_POSEDGE: gpio_int_type_t = 1;
#[doc = "< GPIO interrupt type : falling edge"]
pub const gpio_int_type_t_GPIO_INTR_NEGEDGE: gpio_int_type_t = 2;
#[doc = "< GPIO interrupt type : both rising and falling edge"]
pub const gpio_int_type_t_GPIO_INTR_ANYEDGE: gpio_int_type_t = 3;
#[doc = "< GPIO interrupt type : input low level trigger"]
pub const gpio_int_type_t_GPIO_INTR_LOW_LEVEL: gpio_int_type_t = 4;
#[doc = "< GPIO interrupt type : input high level trigger"]
pub const gpio_int_type_t_GPIO_INTR_HIGH_LEVEL: gpio_int_type_t = 5;
pub const gpio_int_type_t_GPIO_INTR_MAX: gpio_int_type_t = 6;
pub type gpio_int_type_t = c_types::c_uint;
#[doc = "< GPIO mode : disable input and output"]
pub const gpio_mode_t_GPIO_MODE_DISABLE: gpio_mode_t = 0;
#[doc = "< GPIO mode : input only"]
pub const gpio_mode_t_GPIO_MODE_INPUT: gpio_mode_t = 1;
#[doc = "< GPIO mode : output only mode"]
pub const gpio_mode_t_GPIO_MODE_OUTPUT: gpio_mode_t = 2;
#[doc = "< GPIO mode : output only with open-drain mode"]
pub const gpio_mode_t_GPIO_MODE_OUTPUT_OD: gpio_mode_t = 6;
#[doc = "< GPIO mode : output and input with open-drain mode"]
pub const gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD: gpio_mode_t = 7;
#[doc = "< GPIO mode : output and input mode"]
pub const gpio_mode_t_GPIO_MODE_INPUT_OUTPUT: gpio_mode_t = 3;
#[doc = " @endcond"]
pub type gpio_mode_t = c_types::c_uint;
#[doc = "< Disable GPIO pull-up resistor"]
pub const gpio_pullup_t_GPIO_PULLUP_DISABLE: gpio_pullup_t = 0;
#[doc = "< Enable GPIO pull-up resistor"]
pub const gpio_pullup_t_GPIO_PULLUP_ENABLE: gpio_pullup_t = 1;
pub type gpio_pullup_t = c_types::c_uint;
#[doc = "< Disable GPIO pull-down resistor"]
pub const gpio_pulldown_t_GPIO_PULLDOWN_DISABLE: gpio_pulldown_t = 0;
#[doc = "< Enable GPIO pull-down resistor"]
pub const gpio_pulldown_t_GPIO_PULLDOWN_ENABLE: gpio_pulldown_t = 1;
pub type gpio_pulldown_t = c_types::c_uint;
#[doc = " @brief Configuration parameters of GPIO pad for gpio_config function"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct gpio_config_t {
#[doc = "< GPIO pin: set with bit mask, each bit maps to a GPIO"]
pub pin_bit_mask: u64,
#[doc = "< GPIO mode: set input/output mode"]
pub mode: gpio_mode_t,
#[doc = "< GPIO pull-up"]
pub pull_up_en: gpio_pullup_t,
#[doc = "< GPIO pull-down"]
pub pull_down_en: gpio_pulldown_t,
#[doc = "< GPIO interrupt type"]
pub intr_type: gpio_int_type_t,
}
impl Default for gpio_config_t {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
#[doc = "< Pad pull up"]
pub const gpio_pull_mode_t_GPIO_PULLUP_ONLY: gpio_pull_mode_t = 0;
#[doc = "< Pad pull down"]
pub const gpio_pull_mode_t_GPIO_PULLDOWN_ONLY: gpio_pull_mode_t = 1;
#[doc = "< Pad pull up + pull down"]
pub const gpio_pull_mode_t_GPIO_PULLUP_PULLDOWN: gpio_pull_mode_t = 2;
#[doc = "< Pad floating"]
pub const gpio_pull_mode_t_GPIO_FLOATING: gpio_pull_mode_t = 3;
pub type gpio_pull_mode_t = c_types::c_uint;
#[doc = "< Pad drive capability: weak"]
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_0: gpio_drive_cap_t = 0;
#[doc = "< Pad drive capability: stronger"]
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_1: gpio_drive_cap_t = 1;
#[doc = "< Pad drive capability: medium"]
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_2: gpio_drive_cap_t = 2;
#[doc = "< Pad drive capability: medium"]
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_DEFAULT: gpio_drive_cap_t = 2;
#[doc = "< Pad drive capability: strongest"]
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_3: gpio_drive_cap_t = 3;
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_MAX: gpio_drive_cap_t = 4;
pub type gpio_drive_cap_t = c_types::c_uint;
pub type gpio_isr_t = ::core::option::Option<unsafe extern "C" fn(arg1: *mut c_types::c_void)>;
#[doc = "!< Wake the chip when all selected GPIOs go low"]
pub const esp_sleep_ext1_wakeup_mode_t_ESP_EXT1_WAKEUP_ALL_LOW: esp_sleep_ext1_wakeup_mode_t = 0;
#[doc = "!< Wake the chip when any of the selected GPIOs go high"]
pub const esp_sleep_ext1_wakeup_mode_t_ESP_EXT1_WAKEUP_ANY_HIGH: esp_sleep_ext1_wakeup_mode_t = 1;
#[doc = " @brief Logic function used for EXT1 wakeup mode."]
pub type esp_sleep_ext1_wakeup_mode_t = c_types::c_uint;
#[doc = "!< RTC IO, sensors and ULP co-processor"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_RTC_PERIPH: esp_sleep_pd_domain_t = 0;
#[doc = "!< RTC slow memory"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_RTC_SLOW_MEM: esp_sleep_pd_domain_t = 1;
#[doc = "!< RTC fast memory"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_RTC_FAST_MEM: esp_sleep_pd_domain_t = 2;
#[doc = "!< XTAL oscillator"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_XTAL: esp_sleep_pd_domain_t = 3;
#[doc = "!< CPU core"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_CPU: esp_sleep_pd_domain_t = 4;
#[doc = "!< Internal 8M oscillator"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_RTC8M: esp_sleep_pd_domain_t = 5;
#[doc = "!< VDD_SDIO"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_VDDSDIO: esp_sleep_pd_domain_t = 6;
#[doc = "!< Number of domains"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_MAX: esp_sleep_pd_domain_t = 7;
#[doc = " @brief Power domains which can be powered down in sleep mode"]
pub type esp_sleep_pd_domain_t = c_types::c_uint;
#[doc = "!< Power down the power domain in sleep mode"]
pub const esp_sleep_pd_option_t_ESP_PD_OPTION_OFF: esp_sleep_pd_option_t = 0;
#[doc = "!< Keep power domain enabled during sleep mode"]
pub const esp_sleep_pd_option_t_ESP_PD_OPTION_ON: esp_sleep_pd_option_t = 1;
#[doc = "!< Keep power domain enabled in sleep mode, if it is needed by one of the wakeup options. Otherwise power it down."]
pub const esp_sleep_pd_option_t_ESP_PD_OPTION_AUTO: esp_sleep_pd_option_t = 2;
#[doc = " @brief Power down options"]
pub type esp_sleep_pd_option_t = c_types::c_uint;
#[doc = "!< In case of deep sleep, reset was not caused by exit from deep sleep"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_UNDEFINED: esp_sleep_source_t = 0;
#[doc = "!< Not a wakeup cause, used to disable all wakeup sources with esp_sleep_disable_wakeup_source"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_ALL: esp_sleep_source_t = 1;
#[doc = "!< Wakeup caused by external signal using RTC_IO"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_EXT0: esp_sleep_source_t = 2;
#[doc = "!< Wakeup caused by external signal using RTC_CNTL"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_EXT1: esp_sleep_source_t = 3;
#[doc = "!< Wakeup caused by timer"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_TIMER: esp_sleep_source_t = 4;
#[doc = "!< Wakeup caused by touchpad"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_TOUCHPAD: esp_sleep_source_t = 5;
#[doc = "!< Wakeup caused by ULP program"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_ULP: esp_sleep_source_t = 6;
#[doc = "!< Wakeup caused by GPIO (light sleep only on ESP32, S2 and S3)"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_GPIO: esp_sleep_source_t = 7;
#[doc = "!< Wakeup caused by UART (light sleep only)"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_UART: esp_sleep_source_t = 8;
#[doc = "!< Wakeup caused by WIFI (light sleep only)"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_WIFI: esp_sleep_source_t = 9;
#[doc = "!< Wakeup caused by COCPU int"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_COCPU: esp_sleep_source_t = 10;
#[doc = "!< Wakeup caused by COCPU crash"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG: esp_sleep_source_t = 11;
#[doc = "!< Wakeup caused by BT (light sleep only)"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_BT: esp_sleep_source_t = 12;
#[doc = " @brief Sleep wakeup cause"]
pub type esp_sleep_source_t = c_types::c_uint;
#[doc = " @brief Sleep wakeup cause"]
pub use self::esp_sleep_source_t as esp_sleep_wakeup_cause_t;
extern "C" {
#[doc = " @brief Disable wakeup source"]
#[doc = ""]
#[doc = " This function is used to deactivate wake up trigger for source"]
#[doc = " defined as parameter of the function."]
#[doc = ""]
#[doc = " @note This function does not modify wake up configuration in RTC."]
#[doc = " It will be performed in esp_sleep_start function."]
#[doc = ""]
#[doc = " See docs/sleep-modes.rst for details."]
#[doc = ""]
#[doc = " @param source - number of source to disable of type esp_sleep_source_t"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if trigger was not active"]
pub fn esp_sleep_disable_wakeup_source(source: esp_sleep_source_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup by ULP coprocessor"]
#[doc = " @note In revisions 0 and 1 of the ESP32, ULP wakeup source"]
#[doc = " cannot be used when RTC_PERIPH power domain is forced"]
#[doc = " to be powered on (ESP_PD_OPTION_ON) or when"]
#[doc = " ext0 wakeup source is used."]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled."]
#[doc = " - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict"]
pub fn esp_sleep_enable_ulp_wakeup() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup by timer"]
#[doc = " @param time_in_us time before wakeup, in microseconds"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if value is out of range (TBD)"]
pub fn esp_sleep_enable_timer_wakeup(time_in_us: u64) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup by touch sensor"]
#[doc = ""]
#[doc = " @note In revisions 0 and 1 of the ESP32, touch wakeup source"]
#[doc = " can not be used when RTC_PERIPH power domain is forced"]
#[doc = " to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup"]
#[doc = " source is used."]
#[doc = ""]
#[doc = " @note The FSM mode of the touch button should be configured"]
#[doc = " as the timer trigger mode."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled."]
#[doc = " - ESP_ERR_INVALID_STATE if wakeup triggers conflict"]
pub fn esp_sleep_enable_touchpad_wakeup() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get the touch pad which caused wakeup"]
#[doc = ""]
#[doc = " If wakeup was caused by another source, this function will return TOUCH_PAD_MAX;"]
#[doc = ""]
#[doc = " @return touch pad which caused wakeup"]
pub fn esp_sleep_get_touchpad_wakeup_status() -> touch_pad_t;
}
extern "C" {
#[doc = " @brief Returns true if a GPIO number is valid for use as wakeup source."]
#[doc = ""]
#[doc = " @note For SoCs with RTC IO capability, this can be any valid RTC IO input pin."]
#[doc = ""]
#[doc = " @param gpio_num Number of the GPIO to test for wakeup source capability"]
#[doc = ""]
#[doc = " @return True if this GPIO number will be accepted as a sleep wakeup source."]
pub fn esp_sleep_is_valid_wakeup_gpio(gpio_num: gpio_num_t) -> bool;
}
extern "C" {
#[doc = " @brief Enable wakeup using a pin"]
#[doc = ""]
#[doc = " This function uses external wakeup feature of RTC_IO peripheral."]
#[doc = " It will work only if RTC peripherals are kept on during sleep."]
#[doc = ""]
#[doc = " This feature can monitor any pin which is an RTC IO. Once the pin transitions"]
#[doc = " into the state given by level argument, the chip will be woken up."]
#[doc = ""]
#[doc = " @note This function does not modify pin configuration. The pin is"]
#[doc = " configured in esp_sleep_start, immediately before entering sleep mode."]
#[doc = ""]
#[doc = " @note In revisions 0 and 1 of the ESP32, ext0 wakeup source"]
#[doc = " can not be used together with touch or ULP wakeup sources."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number used as wakeup source. Only GPIOs which are have RTC"]
#[doc = " functionality can be used: 0,2,4,12-15,25-27,32-39."]
#[doc = " @param level input level which will trigger wakeup (0=low, 1=high)"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if the selected GPIO is not an RTC GPIO,"]
#[doc = " or the mode is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if wakeup triggers conflict"]
pub fn esp_sleep_enable_ext0_wakeup(gpio_num: gpio_num_t, level: c_types::c_int) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup using multiple pins"]
#[doc = ""]
#[doc = " This function uses external wakeup feature of RTC controller."]
#[doc = " It will work even if RTC peripherals are shut down during sleep."]
#[doc = ""]
#[doc = " This feature can monitor any number of pins which are in RTC IOs."]
#[doc = " Once any of the selected pins goes into the state given by mode argument,"]
#[doc = " the chip will be woken up."]
#[doc = ""]
#[doc = " @note This function does not modify pin configuration. The pins are"]
#[doc = " configured in esp_sleep_start, immediately before"]
#[doc = " entering sleep mode."]
#[doc = ""]
#[doc = " @note internal pullups and pulldowns don't work when RTC peripherals are"]
#[doc = " shut down. In this case, external resistors need to be added."]
#[doc = " Alternatively, RTC peripherals (and pullups/pulldowns) may be"]
#[doc = " kept enabled using esp_sleep_pd_config function."]
#[doc = ""]
#[doc = " @param mask bit mask of GPIO numbers which will cause wakeup. Only GPIOs"]
#[doc = " which are have RTC functionality can be used in this bit map:"]
#[doc = " 0,2,4,12-15,25-27,32-39."]
#[doc = " @param mode select logic function used to determine wakeup condition:"]
#[doc = " - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low"]
#[doc = " - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO,"]
#[doc = " or mode is invalid"]
pub fn esp_sleep_enable_ext1_wakeup(mask: u64, mode: esp_sleep_ext1_wakeup_mode_t)
-> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup from light sleep using GPIOs"]
#[doc = ""]
#[doc = " Each GPIO supports wakeup function, which can be triggered on either low level"]
#[doc = " or high level. Unlike EXT0 and EXT1 wakeup sources, this method can be used"]
#[doc = " both for all IOs: RTC IOs and digital IOs. It can only be used to wakeup from"]
#[doc = " light sleep though."]
#[doc = ""]
#[doc = " To enable wakeup, first call gpio_wakeup_enable, specifying gpio number and"]
#[doc = " wakeup level, for each GPIO which is used for wakeup."]
#[doc = " Then call this function to enable wakeup feature."]
#[doc = ""]
#[doc = " @note In revisions 0 and 1 of the ESP32, GPIO wakeup source"]
#[doc = " can not be used together with touch or ULP wakeup sources."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if wakeup triggers conflict"]
pub fn esp_sleep_enable_gpio_wakeup() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup from light sleep using UART"]
#[doc = ""]
#[doc = " Use uart_set_wakeup_threshold function to configure UART wakeup threshold."]
#[doc = ""]
#[doc = " Wakeup from light sleep takes some time, so not every character sent"]
#[doc = " to the UART can be received by the application."]
#[doc = ""]
#[doc = " @note ESP32 does not support wakeup from UART2."]
#[doc = ""]
#[doc = " @param uart_num UART port to wake up from"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if wakeup from given UART is not supported"]
pub fn esp_sleep_enable_uart_wakeup(uart_num: c_types::c_int) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup by WiFi MAC"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn esp_sleep_enable_wifi_wakeup() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable wakeup by WiFi MAC"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn esp_sleep_disable_wifi_wakeup() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get the bit mask of GPIOs which caused wakeup (ext1)"]
#[doc = ""]
#[doc = " If wakeup was caused by another source, this function will return 0."]
#[doc = ""]
#[doc = " @return bit mask, if GPIOn caused wakeup, BIT(n) will be set"]
pub fn esp_sleep_get_ext1_wakeup_status() -> u64;
}
extern "C" {
#[doc = " @brief Set power down mode for an RTC power domain in sleep mode"]
#[doc = ""]
#[doc = " If not set set using this API, all power domains default to ESP_PD_OPTION_AUTO."]
#[doc = ""]
#[doc = " @param domain power domain to configure"]
#[doc = " @param option power down option (ESP_PD_OPTION_OFF, ESP_PD_OPTION_ON, or ESP_PD_OPTION_AUTO)"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if either of the arguments is out of range"]
pub fn esp_sleep_pd_config(
domain: esp_sleep_pd_domain_t,
option: esp_sleep_pd_option_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enter deep sleep with the configured wakeup options"]
#[doc = ""]
#[doc = " This function does not return."]
pub fn esp_deep_sleep_start();
}
extern "C" {
#[doc = " @brief Enter light sleep with the configured wakeup options"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success (returned after wakeup)"]
#[doc = " - ESP_ERR_INVALID_STATE if WiFi or BT is not stopped"]
pub fn esp_light_sleep_start() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enter deep-sleep mode"]
#[doc = ""]
#[doc = " The device will automatically wake up after the deep-sleep time"]
#[doc = " Upon waking up, the device calls deep sleep wake stub, and then proceeds"]
#[doc = " to load application."]
#[doc = ""]
#[doc = " Call to this function is equivalent to a call to esp_deep_sleep_enable_timer_wakeup"]
#[doc = " followed by a call to esp_deep_sleep_start."]
#[doc = ""]
#[doc = " esp_deep_sleep does not shut down WiFi, BT, and higher level protocol"]
#[doc = " connections gracefully."]
#[doc = " Make sure relevant WiFi and BT stack functions are called to close any"]
#[doc = " connections and deinitialize the peripherals. These include:"]
#[doc = " - esp_bluedroid_disable"]
#[doc = " - esp_bt_controller_disable"]
#[doc = " - esp_wifi_stop"]
#[doc = ""]
#[doc = " This function does not return."]
#[doc = ""]
#[doc = " @note The device will wake up immediately if the deep-sleep time is set to 0"]
#[doc = ""]
#[doc = " @param time_in_us deep-sleep time, unit: microsecond"]
pub fn esp_deep_sleep(time_in_us: u64);
}
extern "C" {
#[doc = " @brief Get the wakeup source which caused wakeup from sleep"]
#[doc = ""]
#[doc = " @return cause of wake up from last sleep (deep sleep or light sleep)"]
pub fn esp_sleep_get_wakeup_cause() -> esp_sleep_wakeup_cause_t;
}
extern "C" {
#[doc = " @brief Default stub to run on wake from deep sleep."]
#[doc = ""]
#[doc = " Allows for executing code immediately on wake from sleep, before"]
#[doc = " the software bootloader or ESP-IDF app has started up."]
#[doc = ""]
#[doc = " This function is weak-linked, so you can implement your own version"]
#[doc = " to run code immediately when the chip wakes from"]
#[doc = " sleep."]
#[doc = ""]
#[doc = " See docs/deep-sleep-stub.rst for details."]
pub fn esp_wake_deep_sleep();
}
#[doc = " @brief Function type for stub to run on wake from sleep."]
#[doc = ""]
pub type esp_deep_sleep_wake_stub_fn_t = ::core::option::Option<unsafe extern "C" fn()>;
extern "C" {
#[doc = " @brief Install a new stub at runtime to run on wake from deep sleep"]
#[doc = ""]
#[doc = " If implementing esp_wake_deep_sleep() then it is not necessary to"]
#[doc = " call this function."]
#[doc = ""]
#[doc = " However, it is possible to call this function to substitute a"]
#[doc = " different deep sleep stub. Any function used as a deep sleep stub"]
#[doc = " must be marked RTC_IRAM_ATTR, and must obey the same rules given"]
#[doc = " for esp_wake_deep_sleep()."]
pub fn esp_set_deep_sleep_wake_stub(new_stub: esp_deep_sleep_wake_stub_fn_t);
}
extern "C" {
#[doc = " @brief Get current wake from deep sleep stub"]
#[doc = " @return Return current wake from deep sleep stub, or NULL if"]
#[doc = " no stub is installed."]
pub fn esp_get_deep_sleep_wake_stub() -> esp_deep_sleep_wake_stub_fn_t;
}
extern "C" {
#[doc = " @brief The default esp-idf-provided esp_wake_deep_sleep() stub."]
#[doc = ""]
#[doc = " See docs/deep-sleep-stub.rst for details."]
pub fn esp_default_wake_deep_sleep();
}
extern "C" {
#[doc = " @brief Disable logging from the ROM code after deep sleep."]
#[doc = ""]
#[doc = " Using LSB of RTC_STORE4."]
pub fn esp_deep_sleep_disable_rom_logging();
}
extern "C" {
#[doc = " @brief CPU Power down low-level initialize"]
#[doc = ""]
#[doc = " @param enable enable or disable CPU power down during light sleep"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_NO_MEM not enough retention memory"]
pub fn esp_sleep_cpu_pd_low_init(enable: bool) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Configure to isolate all GPIO pins in sleep state"]
pub fn esp_sleep_config_gpio_isolate();
}
extern "C" {
#[doc = " @brief Enable or disable GPIO pins status switching between slept status and waked status."]
#[doc = " @param enable decide whether to switch status or not"]
pub fn esp_sleep_enable_gpio_switch(enable: bool);
}
extern "C" {
#[doc = " This function is defined to provide a deprecation warning whenever"]
#[doc = " XT_CLOCK_FREQ macro is used."]
#[doc = " Update the code to use esp_clk_cpu_freq function instead."]
#[doc = " @return current CPU clock frequency, in Hz"]
pub fn xt_clock_freq() -> c_types::c_int;
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct XtExcFrame {
pub exit: c_types::c_long,
pub pc: c_types::c_long,
pub ps: c_types::c_long,
pub a0: c_types::c_long,
pub a1: c_types::c_long,
pub a2: c_types::c_long,
pub a3: c_types::c_long,
pub a4: c_types::c_long,
pub a5: c_types::c_long,
pub a6: c_types::c_long,
pub a7: c_types::c_long,
pub a8: c_types::c_long,
pub a9: c_types::c_long,
pub a10: c_types::c_long,
pub a11: c_types::c_long,
pub a12: c_types::c_long,
pub a13: c_types::c_long,
pub a14: c_types::c_long,
pub a15: c_types::c_long,
pub sar: c_types::c_long,
pub exccause: c_types::c_long,
pub excvaddr: c_types::c_long,
pub lbeg: c_types::c_long,
pub lend: c_types::c_long,
pub lcount: c_types::c_long,
pub tmp0: c_types::c_long,
pub tmp1: c_types::c_long,
pub tmp2: c_types::c_long,
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct XtSolFrame {
pub exit: c_types::c_long,
pub pc: c_types::c_long,
pub ps: c_types::c_long,
pub threadptr: c_types::c_long,
pub a0: c_types::c_long,
pub a1: c_types::c_long,
pub a2: c_types::c_long,
pub a3: c_types::c_long,
}
pub type TaskFunction_t = ::core::option::Option<unsafe extern "C" fn(arg1: *mut c_types::c_void)>;
extern "C" {
#[doc = " @brief Configure CPU to disable access to invalid memory regions"]
#[doc = ""]
pub fn esp_cpu_configure_region_protection();
}
extern "C" {
pub fn compare_and_set_extram(addr: *mut u32, compare: u32, set: *mut u32);
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct spinlock_t {
pub owner: u32,
pub count: u32,
}
extern "C" {
#[doc = " Initialize the crosscore interrupt system for this CPU."]
#[doc = " This needs to be called once on every CPU that is used"]
#[doc = " by FreeRTOS."]
#[doc = ""]
#[doc = " If multicore FreeRTOS support is enabled, this will be"]
#[doc = " called automatically by the startup code and should not"]
#[doc = " be called manually."]
pub fn esp_crosscore_int_init();
}
extern "C" {
#[doc = " Send an interrupt to a CPU indicating it should yield its"]
#[doc = " currently running task in favour of a higher-priority task"]
#[doc = " that presumably just woke up."]
#[doc = ""]
#[doc = " This is used internally by FreeRTOS in multicore mode"]
#[doc = " and should not be called by the user."]
#[doc = ""]
#[doc = " @param core_id Core that should do the yielding"]
pub fn esp_crosscore_int_send_yield(core_id: c_types::c_int);
}
extern "C" {
#[doc = " Send an interrupt to a CPU indicating it should update its"]
#[doc = " CCOMPARE1 value due to a frequency switch."]
#[doc = ""]
#[doc = " This is used internally when dynamic frequency switching is"]
#[doc = " enabled, and should not be called from application code."]
#[doc = ""]
#[doc = " @param core_id Core that should update its CCOMPARE1 value"]
pub fn esp_crosscore_int_send_freq_switch(core_id: c_types::c_int);
}
extern "C" {
#[doc = " Send an interrupt to a CPU indicating it should print its current backtrace"]
#[doc = ""]
#[doc = " This is use internally by the Task Watchdog to dump the backtrace of the"]
#[doc = " opposite core and should not be called from application code."]
#[doc = ""]
#[doc = " @param core_id Core that should print its backtrace"]
pub fn esp_crosscore_int_send_print_backtrace(core_id: c_types::c_int);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct esp_timer {
_unused: [u8; 0],
}
#[doc = " @brief Opaque type representing a single esp_timer"]
pub type esp_timer_handle_t = *mut esp_timer;
#[doc = " @brief Timer callback function type"]
#[doc = " @param arg pointer to opaque user-specific data"]
pub type esp_timer_cb_t = ::core::option::Option<unsafe extern "C" fn(arg: *mut c_types::c_void)>;
#[doc = "!< Callback is called from timer task"]
pub const esp_timer_dispatch_t_ESP_TIMER_TASK: esp_timer_dispatch_t = 0;
#[doc = "!< Count of the methods for dispatching timer callback"]
pub const esp_timer_dispatch_t_ESP_TIMER_MAX: esp_timer_dispatch_t = 1;
#[doc = " @brief Method for dispatching timer callback"]
pub type esp_timer_dispatch_t = c_types::c_uint;
#[doc = " @brief Timer configuration passed to esp_timer_create"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct esp_timer_create_args_t {
#[doc = "!< Function to call when timer expires"]
pub callback: esp_timer_cb_t,
#[doc = "!< Argument to pass to the callback"]
pub arg: *mut c_types::c_void,
#[doc = "!< Call the callback from task or from ISR"]
pub dispatch_method: esp_timer_dispatch_t,
#[doc = "!< Timer name, used in esp_timer_dump function"]
pub name: *const c_types::c_char,
#[doc = "!< Skip unhandled events for periodic timers"]
pub skip_unhandled_events: bool,
}
impl Default for esp_timer_create_args_t {
fn default() -> Self {
let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
unsafe {
::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
s.assume_init()
}
}
}
extern "C" {
#[doc = " @brief Minimal initialization of esp_timer"]
#[doc = ""]
#[doc = " @note This function is called from startup code. Applications do not need"]
#[doc = " to call this function before using other esp_timer APIs."]
#[doc = ""]
#[doc = " This function can be called very early in startup process, after this call"]
#[doc = " only esp_timer_get_time function can be used."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn esp_timer_early_init() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Initialize esp_timer library"]
#[doc = ""]
#[doc = " @note This function is called from startup code. Applications do not need"]
#[doc = " to call this function before using other esp_timer APIs."]
#[doc = " Before calling this function, esp_timer_early_init must be called by the"]
#[doc = " startup code."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_NO_MEM if allocation has failed"]
#[doc = " - ESP_ERR_INVALID_STATE if already initialized"]
#[doc = " - other errors from interrupt allocator"]
pub fn esp_timer_init() -> esp_err_t;
}
extern "C" {
#[doc = " @brief De-initialize esp_timer library"]
#[doc = ""]
#[doc = " @note Normally this function should not be called from applications"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if not yet initialized"]
pub fn esp_timer_deinit() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Create an esp_timer instance"]
#[doc = ""]
#[doc = " @note When done using the timer, delete it with esp_timer_delete function."]
#[doc = ""]
#[doc = " @param create_args Pointer to a structure with timer creation arguments."]
#[doc = " Not saved by the library, can be allocated on the stack."]
#[doc = " @param[out] out_handle Output, pointer to esp_timer_handle_t variable which"]
#[doc = " will hold the created timer handle."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if some of the create_args are not valid"]
#[doc = " - ESP_ERR_INVALID_STATE if esp_timer library is not initialized yet"]
#[doc = " - ESP_ERR_NO_MEM if memory allocation fails"]
pub fn esp_timer_create(
create_args: *const esp_timer_create_args_t,
out_handle: *mut esp_timer_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start one-shot timer"]
#[doc = ""]
#[doc = " Timer should not be running when this function is called."]
#[doc = ""]
#[doc = " @param timer timer handle created using esp_timer_create"]
#[doc = " @param timeout_us timer timeout, in microseconds relative to the current moment"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if the handle is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if the timer is already running"]
pub fn esp_timer_start_once(timer: esp_timer_handle_t, timeout_us: u64) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start a periodic timer"]
#[doc = ""]
#[doc = " Timer should not be running when this function is called. This function will"]
#[doc = " start the timer which will trigger every 'period' microseconds."]
#[doc = ""]
#[doc = " @param timer timer handle created using esp_timer_create"]
#[doc = " @param period timer period, in microseconds"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if the handle is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if the timer is already running"]
pub fn esp_timer_start_periodic(timer: esp_timer_handle_t, period: u64) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Stop the timer"]
#[doc = ""]
#[doc = " This function stops the timer previously started using esp_timer_start_once"]
#[doc = " or esp_timer_start_periodic."]
#[doc = ""]
#[doc = " @param timer timer handle created using esp_timer_create"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if the timer is not running"]
pub fn esp_timer_stop(timer: esp_timer_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Delete an esp_timer instance"]
#[doc = ""]
#[doc = " The timer must be stopped before deleting. A one-shot timer which has expired"]
#[doc = " does not need to be stopped."]
#[doc = ""]
#[doc = " @param timer timer handle allocated using esp_timer_create"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if the timer is running"]
pub fn esp_timer_delete(timer: esp_timer_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get time in microseconds since boot"]
#[doc = " @return number of microseconds since underlying timer has been started"]
pub fn esp_timer_get_time() -> i64;
}
extern "C" {
#[doc = " @brief Get the timestamp when the next timeout is expected to occur"]
#[doc = " @return Timestamp of the nearest timer event, in microseconds."]
#[doc = " The timebase is the same as for the values returned by esp_timer_get_time."]
pub fn esp_timer_get_next_alarm() -> i64;
}
extern "C" {
#[doc = " @brief Get the timestamp when the next timeout is expected to occur skipping those which have skip_unhandled_events flag"]
#[doc = " @return Timestamp of the nearest timer event, in microseconds."]
#[doc = " The timebase is the same as for the values returned by esp_timer_get_time."]
pub fn esp_timer_get_next_alarm_for_wake_up() -> i64;
}
extern "C" {
#[doc = " @brief Dump the list of timers to a stream"]
#[doc = ""]
#[doc = " If CONFIG_ESP_TIMER_PROFILING option is enabled, this prints the list of all"]
#[doc = " the existing timers. Otherwise, only the list active timers is printed."]
#[doc = ""]
#[doc = " The format is:"]
#[doc = ""]
#[doc = " name period alarm times_armed times_triggered total_callback_run_time"]
#[doc = ""]
#[doc = " where:"]
#[doc = ""]
#[doc = " name — timer name (if CONFIG_ESP_TIMER_PROFILING is defined), or timer pointer"]
#[doc = " period — period of timer, in microseconds, or 0 for one-shot timer"]
#[doc = " alarm - time of the next alarm, in microseconds since boot, or 0 if the timer"]
#[doc = " is not started"]
#[doc = ""]
#[doc = " The following fields are printed if CONFIG_ESP_TIMER_PROFILING is defined:"]
#[doc = ""]
#[doc = " times_armed — number of times the timer was armed via esp_timer_start_X"]
#[doc = " times_triggered - number of times the callback was called"]
#[doc = " total_callback_run_time - total time taken by callback to execute, across all calls"]
#[doc = ""]
#[doc = " @param stream stream (such as stdout) to dump the information to"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_NO_MEM if can not allocate temporary buffer for the output"]
pub fn esp_timer_dump(stream: *mut FILE) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Returns status of a timer, active or not"]
#[doc = ""]
#[doc = " This function is used to identify if the timer is still active or not."]
#[doc = ""]
#[doc = " @param timer timer handle created using esp_timer_create"]
#[doc = " @return"]
#[doc = " - 1 if timer is still active"]
#[doc = " - 0 if timer is not active."]
pub fn esp_timer_is_active(timer: esp_timer_handle_t) -> bool;
}
extern "C" {
pub fn esp_newlib_time_init();
}
extern "C" {
#[doc = " Replacement for newlib's _REENT_INIT_PTR and __sinit."]
#[doc = ""]
#[doc = " Called from startup code and FreeRTOS, not intended to be called from"]
#[doc = " application code."]
pub fn esp_reent_init(r: *mut _reent);
}
extern "C" {
#[doc = " Clean up some of lazily allocated buffers in REENT structures."]
pub fn esp_reent_cleanup();
}
extern "C" {
#[doc = " Function which sets up newlib in ROM for use with ESP-IDF"]
#[doc = ""]
#[doc = " Includes defining the syscall table, setting up any common locks, etc."]
#[doc = ""]
#[doc = " Called from the startup code, not intended to be called from application"]
#[doc = " code."]
pub fn esp_newlib_init();
}
extern "C" {
pub fn esp_setup_syscall_table();
}
extern "C" {
#[doc = " Update current microsecond time from RTC"]
pub fn esp_set_time_from_rtc();
}
extern "C" {
pub fn esp_sync_counters_rtc_and_frc();
}
extern "C" {
#[doc = " Initialize newlib static locks"]
pub fn esp_newlib_locks_init();
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct multi_heap_info {
_unused: [u8; 0],
}
#[doc = " @brief Opaque handle to a registered heap"]
pub type multi_heap_handle_t = *mut multi_heap_info;
extern "C" {
#[doc = " @brief allocate a chunk of memory with specific alignment"]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param size size in bytes of memory chunk"]
#[doc = " @param alignment how the memory must be aligned"]
#[doc = ""]
#[doc = " @return pointer to the memory allocated, NULL on failure"]
pub fn multi_heap_aligned_alloc(
heap: multi_heap_handle_t,
size: size_t,
alignment: size_t,
) -> *mut c_types::c_void;
}
extern "C" {
#[doc = " @brief malloc() a buffer in a given heap"]
#[doc = ""]
#[doc = " Semantics are the same as standard malloc(), only the returned buffer will be allocated in the specified heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param size Size of desired buffer."]
#[doc = ""]
#[doc = " @return Pointer to new memory, or NULL if allocation fails."]
pub fn multi_heap_malloc(heap: multi_heap_handle_t, size: size_t) -> *mut c_types::c_void;
}
extern "C" {
#[doc = " @brief free() a buffer aligned in a given heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param p NULL, or a pointer previously returned from multi_heap_aligned_alloc() for the same heap."]
#[doc = " @note This function is deprecated, consider using multi_heap_free() instead"]
pub fn multi_heap_aligned_free(heap: multi_heap_handle_t, p: *mut c_types::c_void);
}
extern "C" {
#[doc = " @brief free() a buffer in a given heap."]
#[doc = ""]
#[doc = " Semantics are the same as standard free(), only the argument 'p' must be NULL or have been allocated in the specified heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param p NULL, or a pointer previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap."]
pub fn multi_heap_free(heap: multi_heap_handle_t, p: *mut c_types::c_void);
}
extern "C" {
#[doc = " @brief realloc() a buffer in a given heap."]
#[doc = ""]
#[doc = " Semantics are the same as standard realloc(), only the argument 'p' must be NULL or have been allocated in the specified heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param p NULL, or a pointer previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap."]
#[doc = " @param size Desired new size for buffer."]
#[doc = ""]
#[doc = " @return New buffer of 'size' containing contents of 'p', or NULL if reallocation failed."]
pub fn multi_heap_realloc(
heap: multi_heap_handle_t,
p: *mut c_types::c_void,
size: size_t,
) -> *mut c_types::c_void;
}
extern "C" {
#[doc = " @brief Return the size that a particular pointer was allocated with."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param p Pointer, must have been previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap."]
#[doc = ""]
#[doc = " @return Size of the memory allocated at this block. May be more than the original size argument, due"]
#[doc = " to padding and minimum block sizes."]
pub fn multi_heap_get_allocated_size(
heap: multi_heap_handle_t,
p: *mut c_types::c_void,
) -> size_t;
}
extern "C" {
#[doc = " @brief Register a new heap for use"]
#[doc = ""]
#[doc = " This function initialises a heap at the specified address, and returns a handle for future heap operations."]
#[doc = ""]
#[doc = " There is no equivalent function for deregistering a heap - if all blocks in the heap are free, you can immediately start using the memory for other purposes."]
#[doc = ""]
#[doc = " @param start Start address of the memory to use for a new heap."]
#[doc = " @param size Size (in bytes) of the new heap."]
#[doc = ""]
#[doc = " @return Handle of a new heap ready for use, or NULL if the heap region was too small to be initialised."]
pub fn multi_heap_register(start: *mut c_types::c_void, size: size_t) -> multi_heap_handle_t;
}
extern "C" {
#[doc = " @brief Associate a private lock pointer with a heap"]
#[doc = ""]
#[doc = " The lock argument is supplied to the MULTI_HEAP_LOCK() and MULTI_HEAP_UNLOCK() macros, defined in multi_heap_platform.h."]
#[doc = ""]
#[doc = " The lock in question must be recursive."]
#[doc = ""]
#[doc = " When the heap is first registered, the associated lock is NULL."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param lock Optional pointer to a locking structure to associate with this heap."]
pub fn multi_heap_set_lock(heap: multi_heap_handle_t, lock: *mut c_types::c_void);
}
extern "C" {
#[doc = " @brief Dump heap information to stdout"]
#[doc = ""]
#[doc = " For debugging purposes, this function dumps information about every block in the heap to stdout."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
pub fn multi_heap_dump(heap: multi_heap_handle_t);
}
extern "C" {
#[doc = " @brief Check heap integrity"]
#[doc = ""]
#[doc = " Walks the heap and checks all heap data structures are valid. If any errors are detected, an error-specific message"]
#[doc = " can be optionally printed to stderr. Print behaviour can be overriden at compile time by defining"]
#[doc = " MULTI_CHECK_FAIL_PRINTF in multi_heap_platform.h."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param print_errors If true, errors will be printed to stderr."]
#[doc = " @return true if heap is valid, false otherwise."]
pub fn multi_heap_check(heap: multi_heap_handle_t, print_errors: bool) -> bool;
}
extern "C" {
#[doc = " @brief Return free heap size"]
#[doc = ""]
#[doc = " Returns the number of bytes available in the heap."]
#[doc = ""]
#[doc = " Equivalent to the total_free_bytes member returned by multi_heap_get_heap_info()."]
#[doc = ""]
#[doc = " Note that the heap may be fragmented, so the actual maximum size for a single malloc() may be lower. To know this"]
#[doc = " size, see the largest_free_block member returned by multi_heap_get_heap_info()."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @return Number of free bytes."]
pub fn multi_heap_free_size(heap: multi_heap_handle_t) -> size_t;
}
extern "C" {
#[doc = " @brief Return the lifetime minimum free heap size"]
#[doc = ""]
#[doc = " Equivalent to the minimum_free_bytes member returned by multi_heap_get_info()."]
#[doc = ""]
#[doc = " Returns the lifetime \"low water mark\" of possible values returned from multi_free_heap_size(), for the specified"]
#[doc = " heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @return Number of free bytes."]
pub fn multi_heap_minimum_free_size(heap: multi_heap_handle_t) -> size_t;
}
#[doc = " @brief Structure to access heap metadata via multi_heap_get_info"]
#[repr(C)]
#[derive(Debug, Default, Copy, Clone)]
pub struct multi_heap_info_t {
#[doc = "< Total free bytes in the heap. Equivalent to multi_free_heap_size()."]
pub total_free_bytes: size_t,
#[doc = "< Total bytes allocated to data in the heap."]
pub total_allocated_bytes: size_t,
#[doc = "< Size of largest free block in the heap. This is the largest malloc-able size."]
pub largest_free_block: size_t,
#[doc = "< Lifetime minimum free heap size. Equivalent to multi_minimum_free_heap_size()."]
pub minimum_free_bytes: size_t,
#[doc = "< Number of (variable size) blocks allocated in the heap."]
pub allocated_blocks: size_t,
#[doc = "< Number of (variable size) free blocks in the heap."]
pub free_blocks: size_t,
#[doc = "< Total number of (variable size) blocks in the heap."]
pub total_blocks: size_t,
}
extern "C" {
#[doc = " @brief Return metadata about a given heap"]
#[doc = ""]
#[doc = " Fills a multi_heap_info_t structure with information about the specified heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param info Pointer to a structure to fill with heap metadata."]
pub fn multi_heap_get_info(heap: multi_heap_handle_t, info: *mut multi_heap_info_t);
}
#[doc = " @brief callback called when a allocation operation fails, if registered"]
#[doc = " @param size in bytes of failed allocation"]
#[doc = " @param caps capabillites requested of failed allocation"]
#[doc = " @param function_name function which generated the failure"]
pub type esp_alloc_failed_hook_t = ::core::option::Option<
unsafe extern "C" fn(size: size_t, caps: u32, function_name: *const c_types::c_char),
>;
extern "C" {
#[doc = " @brief registers a callback function to be invoked if a memory allocation operation fails"]
#[doc = " @param callback caller defined callback to be invoked"]
#[doc = " @return ESP_OK if callback was registered."]
pub fn heap_caps_register_failed_alloc_callback(callback: esp_alloc_failed_hook_t)
-> esp_err_t;
}
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