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plantuml mixed signal timing diagrams
@startuml
clock clk with period 1
binary "Enable" as EN
analog "Vcore" as VDD
@0
EN is low
VDD is 0
@1
VDD is 1.8
@3
EN is high
@10
EN is low
@11
VDD is 1.8
@20
VDD is 0.3
@enduml
@matt-chv
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matt-chv commented Apr 28, 2020

mixed_beta_20200428_interpolated

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